WO2018076599A1 - 一种动态比较器及其失调校准的方法、计算机存储介质 - Google Patents

一种动态比较器及其失调校准的方法、计算机存储介质 Download PDF

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Publication number
WO2018076599A1
WO2018076599A1 PCT/CN2017/077576 CN2017077576W WO2018076599A1 WO 2018076599 A1 WO2018076599 A1 WO 2018076599A1 CN 2017077576 W CN2017077576 W CN 2017077576W WO 2018076599 A1 WO2018076599 A1 WO 2018076599A1
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Prior art keywords
calibration
control switch
switch
input
comparison
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PCT/CN2017/077576
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English (en)
French (fr)
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李福乐
裴蕊寒
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深圳市中兴微电子技术有限公司
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Publication of WO2018076599A1 publication Critical patent/WO2018076599A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/1023—Offset correction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing

Definitions

  • the present invention relates to the field of communications, and in particular, to a dynamic comparator and a method for offset calibration thereof, and a computer storage medium.
  • the circuit design technology and performance optimization of the comparator are also very important.
  • the full-motion comparator is more and more widely used in high-performance, low-power A/D converter circuits due to its low power consumption, high speed, and compatibility with deep sub-micron processes.
  • the full-motion comparator also has the disadvantage of large offset, especially as the size of the CMOS process shrinks, the offset becomes more serious, and gradually becomes one of the main bottlenecks restricting the performance of the A/D converter.
  • the pros and cons of a calibration technique are measured primarily by the performance of the calibrated circuit, the increased area and power consumption due to calibration, and the calibration time.
  • the principle is to adjust the input tube threshold voltage by adjusting the load capacitance of the pre-amplified differential output to cancel the original offset voltage of the comparator.
  • the adjustment of the load capacitance can be achieved by configurable capacitor arrays CP and CN.
  • the configurable capacitor array consists of m capacitors connected in series with the switch. If the switch is turned on, the capacitor of the unit is incorporated into the load capacitor. Otherwise, the capacitor of the unit does not constitute a load.
  • the switch control signal comes from m-bit The output of the memory, the contents of which are obtained by a power-on calibration control circuit.
  • the value of m is determined by the offset voltage calibration range and calibration accuracy. Moreover, the larger the calibration range and the higher the accuracy, the larger the m required.
  • Figure 2 is another conventional dynamic comparator offset calibration circuit that works by calibrating the comparator offset by adjusting the current of the differential branch.
  • the calibration technique compensates for mismatch by adjusting the gate voltage difference of the auxiliary input differential pair of transistors M1 and M2.
  • the gate of the M1 tube is connected to a fixed voltage value
  • the gate of the M2 tube is connected to a voltage holding capacitor CH, the voltage of which is controlled by a calibration circuit.
  • the two input terminals of the comparator are shorted to the common mode signal, and the offset voltage of the circuit is amplified and compared with the output, thereby controlling the external control current source to extract or inject current from the capacitor CH.
  • the current source injects current into the CH
  • the gate voltage of M2 is increased and its discharge current is increased.
  • a mismatch in the auxiliary input tube current is used to compensate for the offset of the comparator itself.
  • the comparator offset can be reduced to a relatively small range.
  • the capacitance of the voltage holding capacitor CH is determined by the calibration accuracy of the comparator offset. The higher the calibration accuracy, the larger the CH value.
  • the shortcoming of the traditional calibration method is that it needs to increase the configurable capacitor array, memory and logic controller, and its area is proportional to the calibration range and calibration accuracy; the increased pre-amplifier circuit load capacitance will reduce the speed of the comparator. .
  • this method can be used permanently for a single calibration without refreshing and no additional power consumption.
  • the traditional calibration method 2 needs to increase the voltage holding capacitor CH, and its area is proportional to the calibration accuracy.
  • the adjustment of the auxiliary input gate voltage requires multiple cycle successive approximations to complete the calibration time; the calibration requires the participation of the entire comparator (including the dynamic preamplifier and subsequent latch circuits), which is more costly. . Therefore, there is a need for a dynamic comparator and its offset calibration technique that enables offset calibration with small area cost, short calibration time, and low power consumption.
  • embodiments of the present invention are directed to a dynamic comparator and a method for offset calibration thereof, and a computer storage medium, which can achieve small area cost, short calibration time, and low power consumption cost. Offset calibration.
  • An embodiment of the present invention provides a dynamic comparator, the dynamic comparator including: a latch and a preamplifier including a preamplifier circuit and a calibration auxiliary circuit;
  • the calibration auxiliary circuit includes a charge storage capacitor that stores an offset voltage, a charge and discharge switch, a common mode switch, a first calibration control switch, and a second calibration control switch;
  • a gate of the input differential NMOS transistor of the preamplifier circuit is respectively connected to a first end of the charge storage capacitor and a first end of the charge and discharge switch, and a second end of the charge storage capacitor is respectively associated with the a first end of the mode switch is connected to an input end of the dynamic comparator, a second end of the common mode switch is connected to an input common mode voltage power supply of the preamplifier circuit, and a second end of the charge and discharge switch is connected To the output of the preamplifier;
  • a drain of the input differential NMOS transistor is connected to a first end of the first calibration control switch
  • a source of the input differential NMOS transistor is connected to a first end of the second calibration control switch
  • An output of the preamplifier is coupled to an input stage of the latch.
  • the turning on and off of the first calibration control switch is controlled by a calibration trigger clock signal, and the second calibration control switch is turned on and off by inverting the calibration trigger clock signal.
  • Control wherein the first calibration control switch is a PMOS transistor and the second calibration control switch is an NMOS transistor.
  • the second end of the charge storage capacitor is connected to the first end of the differential input switch of the preamplifier circuit, and the second end of the differential input switch is connected to the input end of the dynamic comparator;
  • the differential input switch is in an off state in an offset calibration state and a conducting state in a comparison state.
  • the second end of the first calibration control switch is coupled to the first end of the first comparison control switch of the preamplifier circuit, wherein the second end of the first comparison control switch is Calibration voltage supply connection;
  • a first end of the second calibration control switch is coupled to a first end of the second comparison control switch of the preamplifier circuit, and a second end of the second calibration control switch is respectively associated with the second comparison control switch The second end is connected to the ground of the preamplifier circuit.
  • the turning on and off of the first comparison control switch is controlled by comparing a trigger clock signal, and the turning on and off of the second comparison control switch is performed by inverting the comparison trigger clock signal Control is performed; wherein the first comparison control switch is a PMOS transistor, and the second comparison control switch is an NMOS transistor.
  • the on and off of the charge and discharge switch is controlled by a signal obtained by performing a comparison between a control signal obtained by inverting a control signal of the common mode switch and a voltage signal of the output terminal.
  • the embodiment of the invention further provides a method for offset calibration of a dynamic comparator, which can be applied to the dynamic comparator described above, the method comprising:
  • the first calibration control switch is turned on, and the second calibration control switch, the common mode switch, and the charge and discharge switch are respectively turned off, and the calibration voltage power supply of the preamplifier circuit is turned to
  • the input differential NMOS transistor charges a voltage value of a drain of the input differential NMOS transistor to a calibration voltage
  • the first calibration control switch is turned off, and the second calibration control switch, the common mode switch and the charge and discharge switch are respectively turned on, and the drain voltage of the input differential NMOS transistor is via the input difference
  • the NMOS transistor performs a common mode discharge, charges the charge storage capacitor, and stores the offset charge in the charge storage capacitor.
  • the method further includes:
  • the first calibration control switch and the charge and discharge switch are respectively turned off, and the second calibration control switch and the common mode switch are respectively turned on, and the drain voltage of the input differential NMOS transistor is via the input differential NMOS
  • the tube performs a common mode discharge and stops charging the charge storage capacitor.
  • the method further includes:
  • the first calibration control switch is turned on, and the common mode switch, the charge and discharge switch, and the second calibration control switch are respectively turned off, and the differential input of the input of the dynamic comparator is amplified. And superimposing an offset voltage corresponding to the offset charge stored in the charge storage capacitor to obtain an equivalent voltage, and the equivalent voltage is amplified by the preamplifier circuit and amplified by the latch to obtain a match.
  • the comparison result of the differential amplified signal is described.
  • the method further includes:
  • the first calibration control switch is turned on and on by calibrating the trigger clock signal, and the second calibration control switch is turned off and on by inverting the calibration trigger clock signal; wherein the first calibration The control switch is a PMOS transistor, and the second calibration control switch is an NMOS transistor.
  • the method further includes:
  • the differential input switch When in the offset calibration state, the differential input switch is turned off; wherein the first end of the differential input switch is coupled to the second end of the charge storage capacitor, and the second end of the differential input switch is compared to the dynamic The input of the device is connected.
  • the method further includes:
  • a second end of the first calibration control switch is connected to a first end of the first comparison control switch, and a second end of the first comparison control switch is connected to the calibration voltage power source;
  • a first end of the second calibration control switch is coupled to a first end of the second comparison control switch, and a second end of the second calibration control switch is respectively coupled to a second end of the second comparison control switch
  • the ground terminal of the preamplifier circuit is connected.
  • the method further includes:
  • the control signal obtained by inverting the control signal of the common mode switch and the voltage signal of the output terminal are controlled to turn on and off the charge and discharge switch.
  • Embodiments of the present invention provide a computer storage medium storing computer executable instructions.
  • the computer executable instructions are configured to perform the method of offset calibration of the dynamic comparator described above.
  • the dynamic comparator and the offset calibration method thereof eliminate offset by storing the offset voltage of the dynamic comparator on the series capacitor of the input end of the dynamic comparator, and do not require a large amount of memory and control lines, and only cost
  • the power consumption of the preamplifier does not need to wait for the calibration convergence time, which not only effectively reduces the offset of the dynamic preamplifier, improves the conversion precision of the comparator, but also has the advantages of small area cost, low power consumption cost and fast calibration speed.
  • FIG. 1 is a schematic structural diagram of a conventional dynamic comparator offset calibration circuit 1;
  • FIG. 2 is a schematic structural diagram of a conventional dynamic comparator offset calibration circuit 2;
  • FIG. 3 is a schematic structural diagram of a dynamic comparator according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic diagram showing the working principle of a dynamic comparator according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic structural diagram of a circuit of a preamplifier and a latch of a dynamic comparator according to Embodiment 1 of the present invention
  • FIG. 6 is a schematic structural diagram of a control circuit of a charge and discharge switch according to Embodiment 1 of the present invention.
  • FIG. 7 is a schematic flowchart diagram of a method for dynamic comparator offset calibration according to Embodiment 2 of the present invention.
  • FIG. 8 is a schematic circuit diagram of an offset charge storage process of a dynamic comparator according to Embodiment 3 of the present invention.
  • FIG. 9 is a schematic circuit diagram of a comparison process of a dynamic comparator according to Embodiment 3 of the present invention.
  • FIG. 10 is a timing diagram of a dynamic comparator according to Embodiment 3 of the present invention.
  • charge storage capacitor, Ch charge and discharge switch, K2; common mode switch, F2; first calibration control switch, K11; second calibration control switch, K12; first input differential NMOS transistor, M1; Input differential NMOS transistor, M2; differential input switch, F1; first comparison control switch F1K1; second comparison control switch F1K2.
  • a first embodiment of the present invention provides a dynamic comparator.
  • the dynamic comparator includes: a latch and a preamplifier including a preamplifier circuit and a calibration auxiliary circuit;
  • the calibration auxiliary circuit includes a storage offset voltage a charge storage capacitor Ch, a charge and discharge switch K2, a common mode switch F2, a first calibration control switch K11, and a second calibration control switch K12;
  • the gate of the input differential NMOS transistor of the preamplifier circuit and the charge storage capacitor Ch respectively The first end is connected to the first end of the charge and discharge switch K2, and the second end of the charge storage capacitor Ch is respectively connected to the first end of the common mode switch F2 and the input end of the dynamic comparator, and the second end of the common mode switch F2 Connected to the input common mode voltage power supply V CM of the preamplifier circuit, the second end of the charge and discharge switch K2 is connected to the output end of the preamplifier; the drain of the input differential NMOS transistor and the first calibration control A first end
  • a completely symmetrical circuit composed of the first input differential NMOS transistor M1 and the second input differential NMOS transistor M2, the drain of the first input differential NMOS transistor and the drain of the second input differential NMOS transistor
  • the voltage at the output is connected to the input stage of the latch.
  • a charge storage capacitor Ch, a charge and discharge switch K2, and a common mode switch F2 are connected to the gate, the drain and the source of the first input differential NMOS transistor M1 and the second input differential NMOS transistor M2, respectively.
  • the first calibration control switch is turned on and off by a calibration trigger clock signal
  • the second calibration control switch is turned on and off by inverting the calibration trigger clock signal. Control is performed; wherein the first calibration control switch is a PMOS transistor and the second calibration control switch is an NMOS transistor.
  • the calibration trigger clock signal is CLK K1
  • the first calibration control switch K11 and the second calibration control switch K12 are simultaneously controlled by CLK K1
  • the states of the first calibration control switch K11 and the second calibration control switch K12 are opposite, specifically
  • the low level control of CLK K1 controls the first calibration control switch K11 to be turned on, the second calibration control switch K12 is turned off; the high level of CLK K1 controls the first calibration control switch K11 to be off, and the second calibration control switch K12 Turn on.
  • the first calibration control switch is a PMOS transistor and the second calibration control switch is an NMOS transistor
  • the first end of the first calibration control switch is a source
  • the second end of the first calibration switch is a drain
  • the second calibration The first end of the control switch is a source
  • the second end of the second calibration control switch is a drain
  • the calibration trigger clock signal CLK K1 low level controls the first calibration control switch K11 to be turned on, and the second calibration control switch K12 is turned off.
  • the calibration trigger clock signal CLK K1 is calibrated.
  • the low-level phase control node P, the node N is charged to the voltage V DD of the calibration voltage supply;
  • the high-level phase control node P and the node N of the calibration trigger clock signal CLK K1 are common-mode via the input differential pair tube (M1, M2) Discharge at this time.
  • M1, M2 input differential pair tube
  • the charge storage capacitor Ch corresponding to the node P and the node N tracks and stores the voltages (Vp and Vn) of the node P and the node N.
  • the node P and the node N are the output terminals of the preventive device, and are connected to the input stage of the latch.
  • the circuit structure of the preamplifier circuit of the dynamic comparator provided by the embodiment of the present invention is as shown in FIG. 5, and the circuit structure of the latch is as shown in FIG. 6, wherein the output node P(V P ) and the node of the preamplifier circuit are N(V N ) is respectively connected to the input stages V IP and V IN of the latch, so that the output signal of the preamplifier circuit is used as an input signal of the latch, and the latch is performed according to the amplified voltage signal of the preamplifier circuit.
  • the amplification decision is made by comparing the dynamic comparator with the differential signal input from the differential input terminals V IP , V IN of the preamplifier circuit.
  • the preamplification circuit further includes a differential input switch F1 and a first comparison control switch F1K1 and a second comparison control switch F1K2.
  • the second end of the charge storage capacitor Ch is connected to the first end of the differential input switch F1 of the preamplifier circuit, and the second end of the differential input switch F1 is connected to the input end of the dynamic comparator;
  • the differential input switch is in an off state in an offset calibration state and a conducting state in a comparison state.
  • the input end of the preamplifier circuit includes V IP and V IN .
  • the second end of the first calibration control switch K11 is coupled to the first end of the first comparison control switch F1K1 of the preamplifier circuit, wherein the second end of the first comparison control switch F1K1 is Calibrating the voltage source connection;
  • the first end of the second calibration control switch K12 is coupled to the first end of the second comparison control switch F1K2 of the preamplifier circuit, and the second end of the second calibration control switch K12 is respectively compared to the second comparison control
  • the second end of the switch F1K2 is connected to the ground of the preamplifier circuit.
  • the voltage of the calibration voltage source VDD is V DD .
  • the first comparison control switch F1K1 is turned on and off by comparing the trigger clock signal
  • the second comparison control switch F1K2 is turned on and off by inverting the comparison trigger clock signal. Control is performed; wherein the first comparison control switch F1K1 is a PMOS transistor, and the second comparison control switch F1K2 is an NMOS transistor.
  • the first comparison control switch is a PMOS transistor and the second comparison control switch is an NMOS transistor
  • the first end of the first comparison control switch is a source
  • the second end of the first comparison switch is a drain
  • the second comparison The first end of the quasi-control switch is a source
  • the second end of the second comparison control switch is a drain.
  • the comparison trigger clock signal is CLK F1K
  • the first comparison control switch F1K1 and the second comparison control switch F1K2 are simultaneously controlled by CLK F1K , and the states of the first comparison control switch F1K1 and the second comparison control switch F1K2 are opposite, specifically
  • the low level control of CLK F1K controls the first comparison control switch F1K1 to be turned on, the second comparison control switch F1K2 is turned off; the high level of CLK F1K controls the first comparison control switch F1K1 to be off, and the second comparison control switch F1K2 Turn on.
  • the on and off of the charge and discharge switch K2 is obtained by performing an AND operation between a control signal obtained by inverting a control signal of the common mode switch F2 and a voltage signal at the output end.
  • the signal is controlled. Therefore, the gate-controlled common mode switch K2 of the voltage Vp of the node P and the voltage Vn of the node N and the control signal of the charge and discharge switch F2 is a high level or a low level, wherein the control signal CLK F1 of F2 is K2 A small delay of the control signal CLK K2 .
  • the charge and discharge switch K2 needs to be turned off in time.
  • the calibration technique adds a discharge and charge operation to the output node of the preamplifier circuit during the comparator reset phase by calibrating the change from the low level to the high level of the clock K1, and at two points of the node P and the node N. The storage of the offset charge is completed during the discharge process.
  • the dynamic comparator provided by the embodiment of the invention adds a first calibration control switch F11 and a second calibration control switch F12 in the pre-amplification circuit, and turns on and off through the first calibration control switch F11 and the second calibration control switch F12.
  • the clock signal CLK K1 changes from low level to high level, and adds a discharge and charge operation to the output node of the preamplifier circuit, and discharges at two points of node P and node N. The storage of the offset charge in the charge storage capacitor is completed.
  • the dynamic storage capacitor Ch including the storage offset voltage, the charge and discharge switch K2, the common mode switch F2, the first calibration control switch K11, and the second calibration control switch K12 are added to the preamplifier circuit.
  • the offset voltage of the comparator is stored in the series capacitor Ch at the input to eliminate the offset. It does not require a large amount of memory and control lines. It only takes the power consumption of the preamplifier, and does not need to wait for the calibration convergence time, which not only effectively reduces the offset of the dynamic preamplifier.
  • the conversion accuracy of the comparator is improved, and the advantages of small area cost, low power consumption, and fast calibration speed are obtained.
  • the dynamic comparator provided by the embodiment of the present invention does not require a large amount of memory and control lines, and the size and output of the offset charge storage capacitor Ch
  • the parasitic capacitance of the MOS transistor is related. Because the input MOS transistor of the circuit is small in size, the charge storage capacitor Ch is relatively small and the area cost is small; the dynamic comparator stores the offset voltage before each normal comparison, and the process only costs
  • the power consumption of the preamplifier does not require the participation of the subsequent latch circuit, and the power consumption is low; the principle is simple and easy to implement, and the calibration is completed in an instant, without the time required for gradual convergence, and the system can be powered up without a special calibration process.
  • the calibration time is short.
  • the dynamic comparator offset calibration technique proposed by the present invention has comprehensive advantages in terms of area, power consumption and calibration time.
  • the dynamic comparator offset calibration method provided by the embodiment of the present invention is described in conjunction with the dynamic comparator shown in FIG. 3 to FIG. 6. As shown in FIG. 7, the method includes:
  • the first calibration control switch is turned off, and the second calibration control switch, the common mode switch, and the charge and discharge switch are respectively turned on, and a drain voltage of the input differential NMOS transistor is The differential NMOS transistor is input for common mode discharge, and the charge storage capacitor is charged, and the storage of the offset charge is performed in the charge storage capacitor.
  • the first calibration control switch and the charge and discharge switch are respectively turned off, and the second calibration control switch and the common mode switch are respectively turned on, and the drain of the input differential NMOS transistor is turned on. Voltage is common mode discharge via the input differential NMOS transistor and stops charging The storage capacitor is charged.
  • the first calibration control switch is turned on, and the common mode switch, the charge and discharge switch, and the second calibration control switch are respectively turned off, and the differential amplification signal input by the input terminal is
  • the offset voltage corresponding to the offset charge stored in the charge storage capacitor is superposed to obtain an equivalent voltage
  • the equivalent voltage is amplified by the preamplifier circuit and amplified by the latch to obtain the difference Amplify the comparison result of the signal.
  • the first calibration control switch is turned on and turned on by calibrating the trigger clock signal, and the second calibration control switch is turned off and turned on by inverting the calibration trigger clock signal; wherein, the A calibration control switch is a PMOS transistor and the second calibration control switch is an NMOS transistor.
  • the differential input switch When in the offset calibration state, the differential input switch is turned off; wherein the first end of the differential input switch is coupled to the second end of the charge storage capacitor, and the second end of the differential input switch is preamplified The inputs of the circuit are connected.
  • the dynamic comparator When the first comparison control switch of the preamplifier circuit is turned on, and the second comparison control switch of the preamplifier circuit is turned off, the dynamic comparator is in an offset calibration state; wherein the first calibration a second end of the control switch is coupled to the first end of the first comparison control switch, a second end of the first comparison control switch is coupled to the calibration voltage supply; a first end of the second calibration control switch Connected to the first end of the second comparison control switch, the second end of the second calibration control switch is respectively connected to the second end of the second comparison control switch and the ground end of the preamplifier circuit.
  • the control signal obtained by inverting the control signal of the common mode switch and the voltage signal of the output terminal are controlled to be turned on and off by the signal obtained after the operation.
  • the input differential pair transistors M1 and M2, the first comparison control switch F1K1, the second comparison control switch F1K2, and the differential input switch F1 constitute a normal preamplifier circuit of the comparator, and the input of the preamplifier circuit
  • the charge storage capacitor Ch in series, the first calibration control switch K11, the second calibration control switch K12, the charge and discharge switch K2, and the common mode switch F2 constitute a calibration auxiliary circuit of the comparator.
  • the comparator is divided into two stages: offset storage (offset calibration state) and normal comparison (comparison state). Specifically, the charge storage process of the offset storage phase is shown in Figure 8(a) and Figure 8(b), and the normal comparison phase.
  • the differential voltage comparison process is shown in Fig. 9(a) and Fig. 9(b).
  • the comparison trigger clock signal CLK F1K and the calibration trigger clock signal CLK K1 are low, the first comparison control switch F1K1 and the first calibration control switch F11 (PMOS tube) put the preamplifier
  • the output node (node P, node N) is precharged to the calibration voltage V DD at the same time, while the latch output node out is reset to ground, and the tail current tubes of the preamplifier and the latch are turned off.
  • the AND gate control K2 of Vp/Vn and switch F2 is high level or low level, and K1 is a small delay of K2, as shown in FIG. 6.
  • the comparator is controlled by the comparison trigger clock CLK F1K to enter the normal comparison phase, as shown.
  • the comparator equivalent input is the voltage value after the input signal and the offset voltage are superimposed.
  • CLK F1K when CLK F1K is low, the comparator is reset.
  • the preamplifier when CLK F1K is high, the preamplifier amplifies the input differential signal and triggers the latch to output a comparison result by positive feedback.
  • the circuit of the dynamic comparator offset calibration technique of the embodiment of the present invention is divided into five working states:
  • the first calibration control switch F11 and the second calibration control switch F12 may be implemented by a MOS tube.
  • the form of the specific switch of the common mode switch F2 and the charge and discharge switch K2 is not limited in the embodiment of the present invention.
  • Embodiments of the present invention provide a computer storage medium storing computer executable instructions configured to perform offset calibration of the dynamic comparator.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • the offset is cancelled by storing the offset voltage of the dynamic comparator on the series capacitor of the input end of the dynamic comparator, and a large amount of memory and control lines are not required, and only the power consumption of the preamplifier is required, and there is no need to wait for the calibration to converge.
  • Time not only effectively reduces the offset of the dynamic preamplifier, improves the conversion accuracy of the comparator, but also has the advantages of small area cost, low power consumption and fast calibration speed.

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Abstract

本发明实施例公开了一种动态比较器及其失调校准的方法、计算机存储介质，该动态比较器包括：锁存器和包括预放大电路和校准辅助电路的预放大器；所述校准辅助电路包括存储失调电压的电荷存储电容、充放电开关、共模开关、第一校准控制开关和第二校准控制开关；通过在动态比较器的输入端串联电荷存储电容，并通过充放电开关、共模开关、第一校准控制开关和第二校准控制开关的控制进行失调校准。

Description

一种动态比较器及其失调校准的方法、计算机存储介质 技术领域
本发明涉及通信领域，尤其涉及一种动态比较器及其失调校准的方法、计算机存储介质。
背景技术
随着现代数字系统数据处理速度的不断提升，高性能的A/D转换器成为一种必然的发展趋势。作为A/D转换器的基本模块之一，比较器的电路设计技术和性能优化也非常重要。其中，全动态比较器由于其低功耗、高速、与深亚微米工艺更好兼容的特点，在高性能、低功耗A/D转换器电路中得到越来越多的应用。然而，全动态比较器也具有失调较大的缺点，特别是随着CMOS工艺尺寸的缩小，失调会变得更加严重，逐渐成为制约A/D转换器性能的主要瓶颈之一。为了降低全动态比较器的失调，可以采用大尺寸的集成元件，但这会增加面积和负载，另一种方法是采用失调校准技术，通过对失调的测量和调整抵消，可以以比较小的比较器面积，实现较高的比较精度。全动态比较器失调校准通常需要在校准辅助电路和校准逻辑的支持下工作，并需要一定的校准时间和附加功耗。
一种校准技术的优劣，主要通过校准后电路的性能、因校准而增加的面积和功耗、以及校准时间来综合衡量。
图1是一种传统的动态比较器失调校准电路，其原理是通过调整预放大差分输出端的负载电容来调整输入管阈值电压以抵消比较器原有的失调电压。负载电容的调节可通过可配置电容阵列CP和CN来实现。可配置电容阵列由m个电容与开关串联的单元构成，如果开关接通，则该单元的电容并入负载电容，否则，该单元的电容不构成负载。通常，开关控制信号来自m-bit 存储器的输出，存储器的内容通过一个上电校准控制电路来获得。这里m的值由失调电压校准范围和校准精度来确定。而且，校准范围越大，精度越高，则所需的m就越大。
图2是另一种传统的动态比较器失调校准电路，其工作原理是通过调整差分支路的电流来校准比较器失调。在电路实现上，该校准技术通过调整辅助输入差分对管M1和M2的栅极电压差来补偿失配。M1管的栅极接固定电压值，M2管的栅极连接电压保持电容CH，其电压由校准电路来控制。当电路处于校准模式时，比较器两输入端短接共模信号，电路的失调电压被放大并比较输出，从而来控制外控电流源从电容CH抽取或者注入电流。如果电流源向CH注入电流，那么会增加M2的栅极电压，增大其放电电流。辅助输入管电流的不匹配被用来补偿比较器本身的失调。通过多个周期的比较与补偿，可以将比较器失调减小到一个比较小的范围。这里电压保持电容CH的容值由比较器失调的校准精度决定，校准精度越高，CH的容值越大。
可以明显看出，传统校准方法一的缺点是需要增加可配置电容阵列、存储器和逻辑控制器，其面积与校准范围和校准精度均成正比；增加的预放大电路负载电容会降低比较器的速度。但是此方法单次校准即可永久使用，无需刷新，无额外的功耗。传统校准方法二需要增加电压保持电容CH，其面积和校准精度成正比。另外，辅助输入管栅极电压的调整需要多个周期逐次逼近来完成，增加了校准时间；校准需要整个比较器(包括动态预放大器和后续的锁存器电路)的参与，功耗代价较大。因此，亟需一种动态比较器及其失调校准的技术方案，能够实现面积代价小、校准时间短和功耗代价低的失调校准。
发明内容
有鉴于此，本发明实施例希望提供一种动态比较器及其失调校准的方法、计算机存储介质，能够实现面积代价小、校准时间短和功耗代价低的 失调校准。
本发明实施例的技术方案是这样实现的：
本发明实施例提供一种动态比较器，所述动态比较器包括：锁存器和包括预放大电路和校准辅助电路的预放大器；
所述校准辅助电路包括存储失调电压的电荷存储电容、充放电开关、共模开关、第一校准控制开关和第二校准控制开关；
所述预放大电路的输入差分NMOS管的栅极分别与所述电荷存储电容的第一端和所述充放电开关的第一端连接，所述电荷存储电容的第二端分别与所述共模开关的第一端和所述动态比较器的输入端连接，所述共模开关的第二端与所述预放大电路的输入共模电压电源连接，所述充放电开关的第二端连接至所述预放大器的输出端；
所述输入差分NMOS管的漏极与所述第一校准控制开关的第一端连接；
所述输入差分NMOS管的源极与所述第二校准控制开关的第一端连接；
所述预放大器的输出端与所述锁存器的输入级连接。
在上述方案中，所述第一校准控制开关的导通和关断通过校准触发时钟信号进行控制，所述第二校准控制开关的导通和关断通过对所述校准触发时钟信号取反进行控制；其中，所述第一校准控制开关为PMOS管，所述第二校准控制开关为NMOS管。
在上述方案中，所述电荷存储电容的第二端与所述预放大电路的差分输入开关的第一端连接，所述差分输入开关的第二端与所述动态比较器的输入端连接；其中，所述差分输入开关在失调校准状态为关断状态且在比较状态为导通状态。
在上述方案中，所述第一校准控制开关的第二端与所述预放大电路的第一比较控制开关的第一端连接，其中，所述第一比较控制开关的第二端与所述校准电压电源连接；
所述第二校准控制开关的第一端与所述预放大电路的第二比较控制开关的第一端连接，所述第二校准控制开关的第二端分别与所述第二比较控制开关的第二端和所述预放大电路的接地端连接。
在上述方案中，所述第一比较控制开关的导通和关断通过比较触发时钟信号进行控制，所述第二比较控制开关的导通和关断通过对所述比较触发时钟信号的取反进行控制；其中，所述第一比较控制开关为PMOS管，所述第二比较控制开关为NMOS管。
在上述方案中，所述充放电开关的导通和关断通过将所述共模开关的控制信号取反后得到的控制信号和所述输出端的电压信号进行与运算得到的信号进行控制。
本发明实施例还提供一种动态比较器的失调校准的方法，可以应用于上述动态比较器，所述方法包括：
在失调校准状态，置所述第一校准控制开关导通，分别置所述第二校准控制开关、所述共模开关和所述充放电开关关断，所述预放大电路的校准电压电源向所述输入差分NMOS管充电使所述输入差分NMOS管的漏极的电压值达到校准电压；
置所述第一校准控制开关关断，分别置所述第二校准控制开关、所述共模开关和所述充放电开关导通，所述输入差分NMOS管的漏极电压经由所述输入差分NMOS管进行共模放电，向所述电荷存储电容充电，在所述电荷存储电容中进行失调电荷的存储。
在上述方案中，所述方法还包括：
分别置所述第一校准控制开关和充放电开关关断，分别置所述第二校准控制开关和所述共模开关导通，所述输入差分NMOS管的漏极电压经由所述输入差分NMOS管进行共模放电并停止向所述电荷存储电容充电。
在上述方案中，所述方法还包括：
在比较状态，置所述第一校准控制开关导通，分别置所述共模开关、所述充放电开关、所述第二校准控制开关关断，将动态比较器的输入端输入的差分放大信号和所述电荷存储电容中存储的失调电荷对应的失调电压进行叠加后得到等效电压，将所述等效电压经过所述预放大电路的放大和所述锁存器的放大判决得到对所述差分放大信号的比较结果。
在上述方案中，所述方法还包括：
通过校准触发时钟信号置所述第一校准控制开关导通和导通，通过对所述校准触发时钟信号取反置所述第二校准控制开关关断和导通；其中，所述第一校准控制开关为PMOS管，所述第二校准控制开关为NMOS管。
在上述方案中，所述方法还包括：
当在失调校准状态，置差分输入开关关断；其中，所述差分输入开关的第一端与所述电荷存储电容的第二端连接，所述差分输入开关的第二端与所述动态比较器的输入端连接。
在上述方案中，所述方法还包括：
当置所述预放大电路的第一比较控制开关导通，并置所述预放大电路的第二比较控制开关关断时，所述动态比较器处于失调校准状态；其中，
所述第一校准控制开关的第二端与所述第一比较控制开关的第一端连接，所述第一比较控制开关的第二端与所述校准电压电源连接；
所述第二校准控制开关的第一端与所述第二比较控制开关的第一端连接，所述第二校准控制开关的第二端分别与所述第二比较控制开关的第二端和所述预放大电路的接地端连接。
在上述方案中，所述方法还包括：
通过将所述共模开关的控制信号取反后得到的控制信号和所述输出端的电压信号进行与运算后得到的信号控制所述充放电开关的导通和关断。
本发明实施例提供一种计算机存储介质，存储有计算机可执行指令， 该计算机可执行指令配置为执行上述动态比较器的失调校准的方法。
本发明实施例的所述动态比较器及其失调校准方法，通过把动态比较器的失调电压存储在动态比较器的输入端的串联电容上来消除失调，不需要大量的存储器与控制线，仅需花费预放大器的功耗，无需等待校准收敛时间，不仅有效降低了动态预放大器的失调，提高了比较器的转换精度，而且具有面积代价小、功耗代价小和校准速度快的优势。
附图说明
图1传统的动态比较器失调校准电路一的结构示意图；
图2传统的动态比较器失调校准电路二的结构示意图；
图3为本发明实施例一提供的一种动态比较器的结构示意图；
图4为本发明实施例一提供动态比较器的工作原理图；
图5为本发明实施例一提供的动态比较器的预放大器和锁存器的电路结构示意图；
图6为本发明实施例一供的充放电开关的控制电路的结构示意图；
图7为本发明实施例二提供的动态比较器失调校准的方法的流程示意图；
图8为本发明实施例三提供的动态比较器的失调电荷存储过程的电路示意图；
图9为本发明实施例三提供的动态比较器的比较过程的电路示意图；
图10为本发明实施例三提供的动态比较器的时序图；
附图标记说明：电荷存储电容，Ch；充放电开关，K2；共模开关，F2；第一校准控制开关，K11；第二校准控制开关，K12；第一输入差分NMOS管，M1；第二输入差分NMOS管，M2；差分输入开关，F1；第一比较控制开关F1K1；第二比较控制开关F1K2。
具体实施方式
下面结合附图对技术方案的实施作进一步的详细描述。
实施例一
本发明实施例一提供一种动态比较器，如图3所示，所述动态比较器包括：锁存器和包括预放大电路和校准辅助电路的预放大器；所述校准辅助电路包括存储失调电压的电荷存储电容Ch、充放电开关K2、共模开关F2、第一校准控制开关K11和第二校准控制开关K12；所述预放大电路的输入差分NMOS管的栅极分别与电荷存储电容Ch的第一端和充放电开关K2的第一端连接，电荷存储电容Ch的第二端分别与共模开关F2的第一端和所述动态比较器的输入端连接，共模开关F2的第二端与所述预放大电路的输入共模电压电源VCM连接，充放电开关K2的第二端连接至所述预放大器的输出端；所述输入差分NMOS管的漏极与所述第一校准控制开关的第一端连接；所述输入差分NMOS管的源极与所述第二校准控制开关的第一端连接；所述预放大器的输出端与所述锁存器的输入级连接。其中，在预放大电路中，包括由第一输入差分NMOS管M1和第二输入差分NMOS管M2构成的完全对称的电路，第一输入差分NMOS管的漏极和第二输入差分NMOS管的漏极为预放大器的输出端，输出端的电压与锁存器的输入级连接。如图3所示，分别在第一输入差分NMOS管M1和第二输入差分NMOS管M2的栅极、漏极、源极上连接有包括电荷存储电容Ch、充放电开关K2、共模开关F2、第一校准控制开关K11和第二校准控制开关K12的校准辅助电路。通过在预放大器中增加校准辅助电路，在每一个周期内，动态比较器均进行失调存储和正常比较。
如图3所示，所述第一校准控制开关的导通和关断通过校准触发时钟信号进行控制，所述第二校准控制开关的导通和关断通过对所述校准触发时钟信号取反进行控制；其中，所述第一校准控制开关为PMOS管，所述 第二校准控制开关为NMOS管。这里，当校准触发时钟信号为CLKK1时，通过CLKK1同时控制第一校准控制开关K11和第二校准控制开关K12，并且第一校准控制开关K11和第二校准控制开关K12的状态相反，具体的，CLKK1的低电平控制第一校准控制开关K11导通，第二校准控制开关K12关断；CLKK1的高电平控制第一校准控制开关K11为关断，第二校准控制开关K12导通。
其中，当第一校准控制开关为PMOS管，第二校准控制开关为NMOS管时，第一校准控制开关的第一端为源极，第一校准开关的第二端为漏极，第二校准控制开关的第一端为源极，第二校准控制开关的第二端为漏极。
这里，校准触发时钟信号CLKK1低电平控制第一校准控制开关K11为导通，第二校准控制开关K12为关断，在失调存储阶段，如图4所示，校准触发时钟信号CLKK1的低电平相控制节点P、节点N充电到校准电压电源的电压VDD；校准触发时钟信号CLKK1的高电平相控制节点P、节点N经由输入差分对管(M1，M2)进行共模放电此时。在输入差分对管进行共模放电过程中，电路的失配影响节点P和N的放电速度。节点P和节点N对应的电荷存储电容Ch跟踪并存储节点P和节点N的电压(Vp和Vn)。其中，节点P、节点N为预防大器的输出端，与锁存器的输入级连接，。
本发明实施例提供的动态比较器的预放大电路的电路结构如图5所示，锁存器的电路结构如图6所示，其中，预放大电路的输出端节点P(VP)、节点N(VN)分别与锁存器的输入级VIP、VIN连接，从而，将预放大电路的输出信号作为锁存器的输入信号，锁存器根据预放大电路放大后的电压信号进行放大判决，对动态比较器从预放大电路的差分输入端VIP、VIN输入的差分信号进行比较。
这里，预放大电路还包括差分输入开关F1和第一比较控制开关F1K1和第二比较控制开关F1K2。
如图5所示，电荷存储电容Ch的第二端与所述预放大电路的差分输入开关F1的第一端连接，差分输入开关F1的第二端与所述动态比较器的输入端连接；其中，所述差分输入开关在失调校准状态为关断状态且在比较状态为导通状态。其中，预放大电路的输入端包括VIP和VIN。
如图5所示，第一校准控制开关K11的第二端与所述预放大电路的第一比较控制开关F1K1的第一端连接，其中，第一比较控制开关F1K1的第二端与所述校准电压电源连接；第二校准控制开关K12的第一端与所述预放大电路的第二比较控制开关F1K2的第一端连接，第二校准控制开关K12的第二端分别与第二比较控制开关F1K2的第二端和所述预放大电路的接地端连接。其中，校准电压电源VDD的电压为VDD。
在本发明实施例中，第一比较控制开关F1K1的导通和关断通过比较触发时钟信号进行控制，第二比较控制开关F1K2的导通和关断通过对所述比较触发时钟信号的取反进行控制；其中，第一比较控制开关F1K1为PMOS管，第二比较控制开关F1K2为NMOS管。其中，当第一比较控制开关为PMOS管，第二比较控制开关为NMOS管时，第一比较控制开关的第一端为源极，第一比较开关的第二端为漏极，第二比较准控制开关的第一端为源极，第二比较控制开关的第二端为漏极。
这里，当比较触发时钟信号为CLKF1K时，通过CLKF1K同时控制第一比较控制开关F1K1和第二比较控制开关F1K2，并且第一比较控制开关F1K1和第二比较控制开关F1K2的状态相反，具体的，CLKF1K的低电平控制第一比较控制开关F1K1导通，第二比较控制开关F1K2关断；CLKF1K的高电平控制第一比较控制开关F1K1为关断，第二比较控制开关F1K2导通。
在本发明实施例中，如图7所示，充放电开关K2的导通和关断通过将共模开关F2的控制信号取反后得到的控制信号和所述输出端的电压信号进 行与运算得到的信号进行控制。从而，由节点P的电压Vp/节点N的电压Vn与充放电开关F2的控制信号的与门控制共模开关K2为高电平或低电平，其中，F2的控制信号CLKF1为K2的控制信号CLKK2的一小段延时。
在实际应用中，为确保预放大电路的输入差分NMOS管在接下来的比较时间内正常工作在饱和区，需要控制节点P和节点N对应的电荷存储电容Ch中存储的Vp和Vn。当节点P、节点N的电压下降到某一个电压范围时，充放电开关K2需要及时关断。该校准技术在比较器复位阶段，通过校准时钟K1的从低电平到高电平的变化，对预放大电路的输出节点增加了一次放电和充电的操作，并在节点P、节点N两点放电过程中来完成失调电荷的存储。
本发明实施例提供的动态比较器，在预放大电路中增加第一校准控制开关F11和第二校准控制开关F12，通过第一校准控制开关F11和第二校准控制开关F12的导通与关断，在其控制信号校准触发时钟信号CLKK1从低电平到高电平的变化对，对预放大电路的输出节点增加了一次放电和充电的操作，并在节点P、节点N两点放电过程中来完成在电荷存储电容中的失调电荷的存储。
在本发明实施例中，通过在预放大电路上增加包括存储失调电压的电荷存储电容Ch、充放电开关K2、共模开关F2、第一校准控制开关K11和第二校准控制开关K12，把动态比较器的失调电压存储在输入端的串联电容Ch上来消除失调，不需要大量的存储器与控制线，仅需花费预放大器的功耗，无需等待校准收敛时间，不仅有效降低了动态预放大器的失调，提高了比较器的转换精度，而且具有面积代价小、功耗代价小和校准速度快的优势。
相比于传统的动态比较器失调校准技术，本发明实施例提供的动态比较器不需要大量的存储器与控制线，并且失调电荷存储电容Ch的大小与输 入MOS管的寄生电容有关，由于电路的输入MOS管尺寸小，电荷存储电容Ch比较小，面积代价小；动态比较器在每次正常比较前先进行失调电压的存储，而该过程仅需花费预放大器的功耗，不需要后续锁存器电路参与，功耗代价低；原理简单易实现，且校准在瞬间完成，无需逐渐收敛所花费的时间，系统无需专门校准过程即可上电工作，校准时间短。本发明所提出的动态比较器失调校准技术与传统失调校准技术相比，在面积、功耗和校准时间三个方面具有综合优势。
实施例二
在发明实施例中，结合图3至图6所示的动态比较器对本发明实施例提供的动态比较器失调校准的方法进行描述，如图7所示，所述方法包括：
S701、在失调校准状态，置所述第一校准控制开关导通，分别置所述第二校准控制开关、所述共模开关和所述充放电开关关断，所述预放大电路的校准电压电源向所述输入差分NMOS管充电使所述输入差分NMOS管的漏极的电压值达到校准电压；
S702、置所述第一校准控制开关关断，分别置所述第二校准控制开关、所述共模开关和所述充放电开关导通，所述输入差分NMOS管的漏极电压经由所述输入差分NMOS管进行共模放电，向所述电荷存储电容充电，在所述电荷存储电容中进行失调电荷的存储。
其中，在S701中，完成了一次预放大电路的输出节点的放电操作；在S702中，完成了一次预放大电路的输出节点的充电操作，从而由预放大电路的输出节点向电荷存储电容充电，在所述电荷存储电容中进行失调电荷的存储。
在本发明实施例中，分别置所述第一校准控制开关和充放电开关关断，分别置所述第二校准控制开关和所述共模开关导通，所述输入差分NMOS管的漏极电压经由所述输入差分NMOS管进行共模放电并停止向所述电荷 存储电容充电。
在比较状态，置所述第一校准控制开关导通，分别置所述共模开关、所述充放电开关、所述第二校准控制开关关断，将所述输入端输入的差分放大信号和所述电荷存储电容中存储的失调电荷对应的失调电压进行叠加后得到等效电压，将所述等效电压经过所述预放大电路的放大和所述锁存器的放大判决得到对所述差分放大信号的比较结果。
其中，通过校准触发时钟信号置所述第一校准控制开关导通和导通，通过对所述校准触发时钟信号取反置所述第二校准控制开关关断和导通；其中，所述第一校准控制开关为PMOS管，所述第二校准控制开关为NMOS管。
当在失调校准状态，置差分输入开关关断；其中，所述差分输入开关的第一端与所述电荷存储电容的第二端连接，所述差分输入开关的第二端与所述预放大电路的输入端连接。
当置所述预放大电路的第一比较控制开关导通，并置所述预放大电路的第二比较控制开关关断时，所述动态比较器处于失调校准状态；其中，所述第一校准控制开关的第二端与所述第一比较控制开关的第一端连接，所述第一比较控制开关的第二端与所述校准电压电源连接；所述第二校准控制开关的第一端与所述第二比较控制开关的第一端连接，所述第二校准控制开关的第二端分别与所述第二比较控制开关的第二端和所述预放大电路的接地端连接。其中，通过将所述共模开关的控制信号取反后得到的控制信号和所述输出端的电压信号进行与运算后得到的信号控制所述充放电开关的导通和关断。
实施例三
在本实施例中，结合图8(a)、图8(b)、图9(a)、图9(b)对本发明实施例提供的图3-图6所示的动态比较器的失调校准方法进行说明。
需要说明的是，在预放大器部分，输入差分对管M1和M2、第一比较控制开关F1K1、第二比较控制开关F1K2和差分输入开关F1构成比较器的正常预放大电路，预放大电路的输入端串联的电荷存储电容Ch、第一校准控制开关K11、第二校准控制开关K12、充放电开关K2和共模开关F2构成比较器的校准辅助电路。比较器分为失调存储(失调校准状态)和正常比较(比较状态)两个阶段，具体的，失调存储阶段的电荷存储过程如图8(a)、图8(b)所示，正常比较阶段的差分电压比较过程如图9(a)、图9(b)所示。
在失调存储阶段，如图8(a)所示，比较触发时钟信号CLKF1K和校准触发时钟信号CLKK1为低，第一比较控制开关F1K1和第一校准控制开关F11(PMOS管)把预放大器的输出节点(节点P、节点N)两点预充电至校准电压VDD，同时锁存器输出节点out复位到地，预放大器和锁存器的尾电流管都关断。如图8(b)所示当节点P、节点N的共模电压的上升触发CLKK1变为高电平后，预放大器的尾电流管导通，预放大器输出节点节点P、节点N两点开始共模放电，电路的失配效应导致放电速度不同。当节点P、节点N节点共模电压的下降触发K2的下降沿，失调电压被储存到对应的输入串联电容Ch上，当CLKK1变为低电平后，比较器的失调存储阶段结束。另外，为确保预放大电路的输入差分对管(M1、M2)在接下来的比较时间内正常工作在饱和区，需要控制Ch存储的Vp和Vn。在电路实现上，由Vp/Vn与开关F2的与门控制K2为高电平或低电平，K1为K2的一小段延时，如图6所示。
接着，比较器由比较触发时钟CLKF1K控制进入正常比较阶段，所示。比较器等效输入是输入信号和失调电压叠加后的电压值。如图9(a)所示，当CLKF1K为低电平的时候，比较器复位。如图9(a)所示，当CLKF1K为高电平的时候，预放大器放大输入差分信号，并触发锁存器通过正反馈进 行放大判决后输出比较结果。
根据图10的时序图所示，本发明实施例的动态比较器失调校准技术的电路分为5个工作状态：
(1)校准触发时钟CLKK1和比较触发时钟CLKF1K为低、K2断开、F2断开和F12关断、F11导通的输入电容预充电状态；
(2)校准触发时钟CLKK1为高和比较触发时钟CLKF1K为低、K2导通、F2导通和F11导通，F12关断的校准电荷存储状态；
(3)校准触发时钟CLKK1为高、比较触发时钟CLKF1K为低、K2关断、F2导通和F11导通、F12断开的校准电荷停止存储状态；
(4)校准触发时钟CLKK1和比较触发时钟CLKF1K为低、K2断开、F2断开和F11导通、F12断开的比较器正常比较工作前的复位状态；以及
(5)校准触发时钟CLKK1为低和比较触发时钟CLKF1K为高、K2断开、F2断开和F11断开、F12闭合的比较器正常比较工作状态。
上述状态中，其中校准电荷停止存储状态和比较器正常工作前的复位状态几乎是同时的，时序图上F2的控制信号比K2的控制信号有一小段的延时。
在本发明实施例中，第一校准控制开关F11和第二校准控制开关F12可由MOS管实现，共模开关F2和充放电开关K2的具体开关的形式在本发明实施例中不进行任何限制。
本发明实施例提供一种计算机存储介质，存储有计算机可执行指令，该计算机可执行指令配置为执行上述动态比较器的失调校准的方法。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、 嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
采用本发明实施例，通过把动态比较器的失调电压存储在动态比较器的输入端的串联电容上来消除失调，不需要大量的存储器与控制线，仅需花费预放大器的功耗，无需等待校准收敛时间，不仅有效降低了动态预放大器的失调，提高了比较器的转换精度，而且具有面积代价小、功耗代价小和校准速度快的优势。

Claims (14)

  1. 一种动态比较器，所述动态比较器包括：锁存器和包括预放大电路和校准辅助电路的预放大器；
    所述校准辅助电路包括存储失调电压的电荷存储电容、充放电开关、共模开关、第一校准控制开关和第二校准控制开关；
    所述预放大电路的输入差分NMOS管的栅极分别与所述电荷存储电容的第一端和所述充放电开关的第一端连接，所述电荷存储电容的第二端分别与所述共模开关的第一端和所述动态比较器的输入端连接，所述共模开关的第二端与所述预放大电路的输入共模电压电源连接，所述充放电开关的第二端连接至所述预放大器的输出端；
    所述输入差分NMOS管的漏极与所述第一校准控制开关的第一端连接；
    所述输入差分NMOS管的源极与所述第二校准控制开关的第一端连接；
    所述预放大器的输出端与所述锁存器的输入级连接。
  2. 根据权利要求1所述的动态比较器，其中，所述第一校准控制开关的导通和关断通过校准触发时钟信号进行控制，所述第二校准控制开关的导通和关断通过对所述校准触发时钟信号取反进行控制；其中，所述第一校准控制开关为PMOS管，所述第二校准控制开关为NMOS管。
  3. 根据权利要求1所述的动态比较器，其中，所述电荷存储电容的第二端与所述预放大电路的差分输入开关的第一端连接，所述差分输入开关的第二端与所述动态比较器的输入端连接；其中，所述差分输入开关在失调校准状态为关断状态且在比较状态为导通状态。
  4. 根据权利要求1或2所述的动态比较器，其中，所述第一校准控制开关的第二端与所述预放大电路的第一比较控制开关的第一端连接，其中，所述第一比较控制开关的第二端与所述校准电压电源连接；
    所述第二校准控制开关的第一端与所述预放大电路的第二比较控制开 关的第一端连接，所述第二校准控制开关的第二端分别与所述第二比较控制开关的第二端和所述预放大电路的接地端连接。
  5. 根据权利要求4所述的动态比较器，其中，所述第一比较控制开关的导通和关断通过比较触发时钟信号进行控制，所述第二比较控制开关的导通和关断通过对所述比较触发时钟信号的取反进行控制；其中，所述第一比较控制开关为PMOS管，所述第二比较控制开关为NMOS管。
  6. 根据权利要求1所述的动态比较器，其中，所述充放电开关的导通和关断通过将所述共模开关的控制信号取反后得到的控制信号和所述输出端的电压信号进行与运算得到的信号进行控制。
  7. 一种动态比较器的失调校准的方法，所述方法包括：
    在失调校准状态，置所述第一校准控制开关导通，分别置所述第二校准控制开关、所述共模开关和所述充放电开关关断，所述预放大电路的校准电压电源向所述输入差分NMOS管充电使所述输入差分NMOS管的漏极的电压值达到校准电压；
    置所述第一校准控制开关关断，分别置所述第二校准控制开关、所述共模开关和所述充放电开关导通，所述输入差分NMOS管的漏极电压经由所述输入差分NMOS管进行共模放电，向所述电荷存储电容充电，在所述电荷存储电容中进行失调电荷的存储。
  8. 根据权利要求7所述的方法，其中，所述方法还包括：
    分别置所述第一校准控制开关和充放电开关关断，分别置所述第二校准控制开关和所述共模开关导通，所述输入差分NMOS管的漏极电压经由所述输入差分NMOS管进行共模放电并停止向所述电荷存储电容充电。
  9. 根据权利要求7所述的方法，其中，所述方法还包括：
    在比较状态，置所述第一校准控制开关导通，分别置所述共模开关、所述充放电开关、所述第二校准控制开关关断，将动态比较器的输入端输 入的差分放大信号和所述电荷存储电容中存储的失调电荷对应的失调电压进行叠加后得到等效电压，将所述等效电压经过所述预放大电路的放大和所述锁存器的放大判决得到对所述差分放大信号的比较结果。
  10. 根据权利要求7所述的方法，其中，所述方法还包括：
    通过校准触发时钟信号置所述第一校准控制开关导通和导通，通过对所述校准触发时钟信号取反置所述第二校准控制开关关断和导通；其中，所述第一校准控制开关为PMOS管，所述第二校准控制开关为NMOS管。
  11. 根据权利要求7所述的方法，其中，所述方法还包括：
    当在失调校准状态，置差分输入开关关断；其中，所述差分输入开关的第一端与所述电荷存储电容的第二端连接，所述差分输入开关的第二端与所述动态比较器的输入端连接。
  12. 根据权利要求7所述的方法，其中，所述方法还包括：
    当置所述预放大电路的第一比较控制开关导通，并置所述预放大电路的第二比较控制开关关断时，所述动态比较器处于失调校准状态；其中，
    所述第一校准控制开关的第二端与所述第一比较控制开关的第一端连接，所述第一比较控制开关的第二端与所述校准电压电源连接；
    所述第二校准控制开关的第一端与所述第二比较控制开关的第一端连接，所述第二校准控制开关的第二端分别与所述第二比较控制开关的第二端和所述预放大电路的接地端连接。
  13. 根据权利要求7所述的方法，其中，所述方法还包括：
    通过将所述共模开关的控制信号取反后得到的控制信号和所述输出端的电压信号进行与运算后得到的信号控制所述充放电开关的导通和关断。
  14. 一种计算机存储介质，存储有计算机可执行指令，该计算机可执行指令配置为执行上述权利要求7-13任一项所述的动态比较器的失调校准的方法。
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