WO2017101143A1 - 存储阵列、存储对象逻辑关系的存储芯片及方法 - Google Patents

存储阵列、存储对象逻辑关系的存储芯片及方法 Download PDF

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Publication number
WO2017101143A1
WO2017101143A1 PCT/CN2015/098732 CN2015098732W WO2017101143A1 WO 2017101143 A1 WO2017101143 A1 WO 2017101143A1 CN 2015098732 W CN2015098732 W CN 2015098732W WO 2017101143 A1 WO2017101143 A1 WO 2017101143A1
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Prior art keywords
lead line
logical relationship
storage
value
lead
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PCT/CN2015/098732
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English (en)
French (fr)
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宋三年
陈小刚
宋志棠
郭天琪
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中国科学院上海微系统与信息技术研究所
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Priority to US15/739,883 priority Critical patent/US10482955B2/en
Publication of WO2017101143A1 publication Critical patent/WO2017101143A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Definitions

  • the present invention relates to the field of semiconductor memory integrated circuits, and in particular, to a memory array, a memory chip and a method for storing object logical relationships.
  • the human brain processes a large amount of information every day through various means such as sight, hearing, touch, etc.
  • the ability in reasoning, recognition, association, prediction, etc. is unmatched by computer systems, but it is estimated that an adult's brain power consumption Only about 20W, and the speed of information transfer in the brain can only reach the order of milliseconds. How to get inspiration from the working mode of the human brain and improve the operation mode of the computer system to achieve high efficiency and low power consumption.
  • Neural network computing has formed a very mature and perfect theoretical system, imitating the parallel processing mechanism of brain neural network, forming a multi-input and multi-output system. Through the training of a large amount of data, the system has more and more accurate prediction ability.
  • This system was originally implemented in computer software. In order to improve the computational efficiency, more hardware systems use processors, FPGA (Field Programmable Gate Array) and other technologies to achieve hardware acceleration of the algorithm. Further, IBM has launched the Watson computer system project of artificial intelligence many years ago, leading the development of intelligent processing chips.
  • an object of the present invention is to provide a memory array and a memory chip and a method for storing object logical relationships, which are used to solve the problem of increasing storage requirements in the prior art.
  • the present invention provides a storage array, the storage array including at least:
  • the first lead line and the second lead line having the same number and respectively located in the row direction and the column direction, the first lead line and the second lead line are respectively numbered, and the first lead line and the second lead line of different numbers are respectively connected a storage unit, a controllable switch is respectively connected between the first lead line and the second lead line of the same number;
  • the memory unit includes a series-connected varistor type two-terminal device and a strobe diode, and the strobe diode is forwardly turned from the first lead line to the second lead line, and is reversed from the second lead line to the first lead line. ;
  • the controllable switch is switched between a two-way cutoff and a two-way conduction from the second lead to the first lead.
  • the varistor type two-terminal device can change between at least two resistance states under the action of an electrical pulse signal.
  • the varistor type two-terminal device changes between the highest resistance value and the lowest resistance value according to the intensity and waveform of the excitation electric signal under the action of the electric pulse signal, wherein the highest resistance value At least one order of magnitude higher than the minimum resistance.
  • the present invention further provides a memory chip that stores a logical relationship of an object, where the storage chip of the logical relationship of the storage object includes at least:
  • An interface module a control module, a driver module, a first decoder, a second decoder, and the foregoing storage array;
  • the interface module is used for inputting and outputting data
  • the control module is connected to the interface module, the driving module, and the first decoder, and obtains Input instructions and generate corresponding control signals;
  • the driving module is connected to the control module and the second decoder, and generates a write current, an erase current or a read current according to a control signal output by the control module;
  • the first decoder is connected to the control module and the first lead line of the storage array, and is controlled by the control module to strobe a corresponding first lead line;
  • the second decoder is connected to the driving module and the second lead line of the storage array, and is controlled by the control module to strobe a corresponding second lead line;
  • the storage array is respectively connected to the control module, the first decoder and the second decoder, and all controllable switches are turned off by the control module, and the first lead line is gated And a storage unit between the second lead line writes a logical relationship value; or is controlled by the control module to turn on all controllable switches, and read a logical relationship between the first lead line and the second lead line of the strobe value.
  • the gated first lead line represents a first object as a condition
  • the gated second lead line represents a second object as a result, the logical relationship value directly causing the second object to be established when the first object is established
  • the probability value, the first leader line and the second leader line of the same number correspond to the same object.
  • the present invention further provides a storage method for storing a logical relationship of a storage object.
  • the storage method of the logical relationship of the storage object uses the foregoing storage array, and at least includes the following steps:
  • Inputting information to be written including a first object, a second object, and logical relationship values of the first object and the second object;
  • the group of objects including a first object and a second object;
  • the readout resistance value is converted into a corresponding logical relationship value and output.
  • the first object is a condition
  • the second object is a result
  • the logical relationship value is a probability value that directly causes the second object to be established when the first object is established.
  • the written logical relationship value is overwritten by the original logical relationship value; or superimposed on the basis of the original logical relationship value, thereby enhancing the logical relationship between the first object and the second object.
  • the resistance value corresponding to the logical relationship value of the first object and the second object is directly read; if the first object passes the third object and If the second object has an indirect relationship, the sum of the resistance value corresponding to the logical relationship value of the first object and the third object and the resistance value corresponding to the logical relationship value of the third object and the second object are read; if the first object and the first object The two objects have a direct relationship and an indirect relationship through the third object, and the resistance value corresponding to the logical relationship value of the first object and the third object is read out and the resistance value corresponding to the logical relationship value of the third object and the second object is serially connected.
  • the resistance value obtained by connecting the resistance values corresponding to the logical relationship values of the first object and the second object in parallel.
  • the method for stroking the second lead line corresponding to the second object includes: grounding the second lead line corresponding to the second object, and hanging other second lead lines or other second lead lines A high level is applied to reverse turn off the gate diodes in the unselected memory cells.
  • the method of strobing the second lead line corresponding to the second object comprises: grounding the second lead line corresponding to the second object, and floating the other second lead lines.
  • the memory array of the present invention As described above, the memory array of the present invention, the memory chip and the method for storing the logical relationship of the object have the following beneficial effects:
  • the storage array and the storage chip logical relationship storage chip and method of the present invention adopt an electrically operable resistive memory array having the same number of two sets of lead lines perpendicular to each other, two mutually perpendicular and different numbers.
  • a memory cell is connected between the root lead wires, each memory cell is composed of an electrically operable varistor type two-terminal device and one strobe diode, and only one controllable switching device is used between two lead wires of the same vertical and the same number. connection.
  • Figure 1 shows a schematic diagram of a memory array of the present invention.
  • Figure 2 shows a schematic diagram of a memory unit of the present invention.
  • FIG. 3 is a schematic diagram showing a memory chip of a storage object logical relationship of the present invention.
  • FIG. 4 is a flow chart showing the write operation of the storage method of the logical relationship of the storage object of the present invention.
  • FIG. 5 is a flow chart showing the read operation of the memory chip of the storage object logical relationship of the present invention.
  • the present invention provides a storage array 1, which includes:
  • the first lead line and the second lead line have the same number and are respectively located in the row direction and the column direction, and the first lead line and the second lead line are respectively numbered.
  • the first lead line is in the row direction
  • the second lead line is in the column direction
  • the directions of the first lead line and the second lead line are interchangeable, not in this embodiment. Limited.
  • the first lead lines are named L0-Ln from top to bottom
  • the second lead lines are named C0-Cn from left to right, wherein the subscripts 0-n are numbers.
  • a storage unit 11 is connected between the first lead line and the second lead line of different numbers, and a controllable switch M is respectively connected between the first lead line and the second lead line of the same number.
  • the memory unit 11 includes a series-connected varistor type two-terminal device R and a strobe diode D, and the strobe diode D is forwardly guided from the first lead line to the second lead line.
  • the second lead line is reversely cut off toward the first lead line.
  • one end of the varistor type two-terminal device R is connected to the second lead line, the other end is connected to the negative pole of the strobe diode D, and the anode of the strobe diode D is connected to the first lead line.
  • the varistor type two-terminal device R includes a variable resistance material layer 112, an upper electrode 111 and a lower electrode 113 on the upper and lower surfaces of the variable resistance material layer 112, and an outer side. a layer of a silicon dioxide dielectric material (not shown); one end of the variable resistance type two-terminal device R is connected to the second lead line through the second through hole 118, and the other end is connected to the gate diode D; the upper electrode 111 and the material of the lower electrode 113 are materials having a low resistivity such as W or TiN, and the material of the variable resistance material layer 112 is one or alloy of Ge, Sb, Te, preferably, the variable The resistive material layer 112 is an alloy having a Ge, Sb, and Te composition ratio of 2:2:6.
  • the gate diode D includes a P pole 114 and an N pole 115, and a P pole 114 is connected to the lower electrode 113 of the varistor type two-terminal device R.
  • the N pole 115 is connected to the highly doped buried layer 116 and is connected to the first lead line through the first through hole 117.
  • the varistor type two-terminal device R can be switched between at least two resistance states under the action of an electrical pulse signal, such as a high resistance state and a low resistance state; or the varistor type two-terminal device R acts on an electrical pulse signal
  • the resistance value may vary between a highest resistance value and a minimum resistance value according to the intensity and waveform of the excitation electrical signal, wherein the highest resistance value is at least one order of magnitude higher than the lowest resistance value.
  • controllable switch M is switched between two states of bidirectional cutoff and one-way conduction from the second lead line to the first lead line, and the control end of each controllable switch M is connected to the same switch.
  • the control signal Ctl is turned off at the time of the write operation, and the controllable switches M are all turned on during the read operation.
  • the present invention further provides a storage chip storing a logical relationship of an object, where the storage chip logically includes at least an interface module 2, a control module 3, a driving module 4, and a first decoder 5. a second decoder 6, and the memory array 1.
  • the interface module 2 is used for input and output of data.
  • the interface module 2 serves as a channel for exchanging information between the storage chip and the external device, and any interface module in the prior art is applicable to the storage chip of the storage object logical relationship of the present invention.
  • the data input from the interface module 2 includes a first object a, a second object b, and a logical relationship value p of the first object a and the second object b.
  • the first object a is a condition
  • the second object b is a result.
  • the logical relationship value p is a probability value that directly causes the second object b to be established when the first object a is established.
  • control module 3 is connected to the interface module 2, the driving module 4, and the first decoder 5, and acquires an input command and generates a corresponding control signal.
  • control module 3 is bidirectionally connected to the interface module 2, the driving module 4, and the first decoder 5, and outputs various control signals to perform a write, read or erase operation after receiving an instruction.
  • the driving module 4 is connected to the control module 3 and the second decoder 6, and generates a write current, an erase current or a read current according to a control signal output by the control module 3.
  • the magnitude and pulse width of the write current can be generated by the control module 3 based on the strength of the written logical relationship value.
  • the first decoder 5 is connected to the control module 3 and the first lead line of the storage array 1, and is controlled by the control module 3 to strobe the first object a.
  • the first lead line is connected to the control module 3 and the first lead line of the storage array 1, and is controlled by the control module 3 to strobe the first object a.
  • the first lead line is connected to the control module 3 and the first lead line of the storage array 1, and is controlled by the control module 3 to strobe the first object a.
  • the second decoder 6 and the driving module 3 and the second of the storage array 1 are connected, and the second lead line corresponding to the second object b is strobed by the control of the control module 3.
  • the memory array 1 is connected to the control module 3, the first decoder 5, and the second decoder 6, respectively.
  • the memory array 1 is turned off by the control of the switch control signal Ctl output by the control module 3 to turn off all controllable switches and to store between the gated first and second lead lines.
  • the unit writes the logical relationship value p of the first object a and the second object b.
  • the memory array 1 is turned on by the control of the switch control signal Ctl outputted by the control module 3 to turn on all controllable switches, and read from the first lead line and the second lead line of the gate.
  • the logical relationship value p of an object a and the second object b is
  • the memory chip storing the logical relationship of the object further includes a clock module 7 and a power module 8 for respectively providing an operating clock and a power voltage.
  • the present invention further provides a storage method for storing a logical relationship of a storage object.
  • the storage method of the logical relationship of the storage object uses the storage array, and at least includes the following steps:
  • the write operation as shown in FIG. 4, specifically includes the following steps:
  • Step S11 input information to be written, including the first object a, the second object b, and the logical relationship value p of the first object a and the second object b.
  • the information ⁇ a, b, p ⁇ that needs to be written is given.
  • the first object a is represented by a number
  • the first object a represents a condition
  • the second object b is represented by a number
  • the second object b represents the result
  • the logical relationship value p of the first object a and the second object b represents a probability value that directly causes the second object b to be established when the first object a is established
  • the value range of p can be set to [0, 1 ]
  • 0 indicates that there is no relationship between the first object a and the second object b
  • the establishment of the first object a does not cause the second object b to be established at all
  • 1 indicates that the establishment of the first object a necessarily results in the second object b being established.
  • the definition of the numerical range of p can be set according to actual requirements, and is not limited to this embodiment.
  • the storage logic of the storage object logical relationship is used to store the logical relationship of the object, so that the information to be written is transmitted to the control module 3 through the interface module 2.
  • Step S12 Turn off the controllable switches in the storage array.
  • control module 3 outputs a switch control signal Ctl after receiving the information, and turns off all the controllable switches M in the storage array 1 between the first lead line and the second lead line of the same number. It is in a high resistance state.
  • Step S13 strobe the first lead line corresponding to the first object a, and strobe the second lead line corresponding to the second object b.
  • control module 3 controls the first decoder 5 and the second decoder 6 to strobe the corresponding first lead line and the second lead according to the numbers of the first object a and the second object b. line.
  • the method for strobing the second lead line corresponding to the second object b includes: grounding the second lead line corresponding to the second object b, and suspending the other second lead lines or applying a high level to the other second lead lines.
  • the gate diode D in the unselected memory cell 11 is reverse turned off.
  • Step S14 generating a write current corresponding to the logical relationship value p of the first object a and the second object b, and applying the write current to the storage between the gated first lead line and the second lead line On the unit.
  • the control module 3 controls the driving module 4 to generate a current corresponding to the logical relationship value p of the first object a and the second object b, and inputs the strobed through the gated first lead line.
  • the resistance value of the varistor type two-terminal device R changes due to a change in current.
  • the resistance of the varistor type two-terminal device R can be changed between at least two resistance states; or according to the strength and waveform of the excitation electrical signal, the resistance value can be between the highest resistance value and the lowest resistance value. a variation wherein the highest resistance is at least an order of magnitude higher than the lowest resistance.
  • the logical relationship value p corresponding to the first object a and the second object b has been written to the storage array 1.
  • the written logical relationship value is overwritten by the original logical relationship value; or superimposed on the basis of the original logical relationship value.
  • the superimposed manner is employed to enhance the logical relationship between the first object a and the second object b.
  • the read operation as shown in FIG. 5, specifically includes the following steps:
  • Step S21 Input an object group that needs to read out a relationship, and the object group includes a first object a and a second object b.
  • an object group ⁇ a, b ⁇ that needs to be read out is given.
  • the first object a is represented by a number
  • the first object a represents a condition
  • the second object b is represented by a number
  • the second object b stands for the result.
  • the storage logic of the storage object logical relationship is used to store the logical relationship of the object, so that the information of the object group that needs to read out the relationship is transmitted to the control module 3 through the interface module 2.
  • Step S22 All the controllable switches in the storage array are connected.
  • control module 3 outputs a switch control signal Ctl after receiving the information, and all the controllable switches M in the storage array 11 are all connected, and the first lead line and the second lead line of the same number are Low resistance state.
  • Step S23 strobing the first lead line corresponding to the first object a, and stroking the second object corresponding to the second object b Lead line.
  • control module 3 controls the first decoder 5 and the second decoder 6 to strobe the corresponding first lead line and the second lead according to the numbers of the first object a and the second object b. line.
  • the method for strobing the second lead line corresponding to the second object specifically includes: grounding the second lead line corresponding to the second object b, and floating the other second lead lines.
  • Step S24 generating a read voltage or current, and applying the read voltage or current to the gated first lead line and the second lead line, and reading the gated first lead line and the second lead line The resistance value between.
  • control module 3 controls the driving module 4 to generate a read voltage or current, and is applied to the gated first lead line and the second lead line, wherein the first lead line applies a high potential, and the second A low potential is applied to the lead line, and a current flowing through the first lead line and the second lead line is read to obtain a resistance value.
  • the resistance value r in the memory cell between the gated first lead line L1 and the second lead line Cn is smaller, and the smaller the resistance value r is, the higher the probability p that the second object b is established when the first object a is established.
  • the number of the first object a is 1, and the number of the second object b is n.
  • the number of the third object c is 0.
  • the probability that the third object c is directly established is p1
  • the probability that the second object b is directly established is p2
  • the current is selected.
  • the first lead line L1 is input. Since the first object a and the second object b are not directly related, the storage unit storing the logical relationship between the first object a and the second object b is in a high impedance state, and no current flows.
  • the first object a has a direct relationship with the third object c, so the current flows through the storage unit storing the logical relationship value of the first object a and the third object c, and since the controllable switches are turned on, the current is from the third
  • the second lead line C0 corresponding to the object c flows to the first lead line L0 corresponding to the third object c, and the third object c is converted from the result to the condition, and since the third object c has a direct relationship with the second object b,
  • the current flows through the storage third object c and the second object b
  • the storage unit of the logical relationship value is finally outputted from the gated second lead line Cn, and the resulting resistance value is the resistance value r1 and the third object c corresponding to the logical relationship value of the first object a and the third object c.
  • the r1+r2 must be greater than the single resistance values r1 and r2, that is, the probability that the second object b is established when the first object a is established is lower than the probability that the third object c is established when the first object a is established, and the third object c is established.
  • the total resistance of the current flowing through is the parallel connection of the two cases, that is, (r1+r2)//r
  • the resistance value finally read out must be smaller than any of the above two cases.
  • Step S25 Converting the read resistance value into a corresponding logical relationship value and outputting.
  • the sensed resistance value is output to the control circuit 3, the control circuit 3 outputs a corresponding logical relationship value according to the readout resistance value, and the logical relationship value is output by the interface circuit 2.
  • the relationship between the resistance value and the logical relationship value may be linear or non-linear, and may be specifically set according to the actual use occasion.
  • the storage array and the storage chip logical relationship storage chip and method of the present invention adopt an electrically operable resistive memory array having the same number of two sets of lead lines perpendicular to each other, two mutually perpendicular and different numbers.
  • a memory cell is connected between the root lead wires, each memory cell is composed of an electrically operable varistor type two-terminal device and one strobe diode, and only one controllable switching device is used between two lead wires of the same vertical and the same number. connection.
  • the present invention provides a memory array and a memory chip and method for storing object logical relationships.
  • the storage array includes: a first lead line and a second lead line having the same number and respectively located in a row direction and a column direction, where the first lead line and the second lead line are respectively numbered, the first lead line of different numbers and the second line
  • a storage unit is connected between the lead lines, and the first lead line and the second lead line of the same number are respectively connected
  • Connect a controllable switch is
  • the storage chip of the logical relationship of the storage object includes: an interface module; a control module that generates a control signal; a driving module that generates a write current, a wipe current or a read current according to the control signal; and a first decoding of the corresponding first lead line a second decoder that strobes the corresponding second leader; and a memory array for storing the logical relationship values.
  • the storage method of the storage object logical relationship includes: a write operation and a read operation.
  • the storage array and the storage chip logical relationship storage chip and method of the invention realize the storage of the logical relationship between the objects through a brand-new storage array; at the same time, when read, the controllable switch is transmitted between the same number of lead lines, The result is converted into a condition, which is a comprehensive indirect relationship factor, which can be used to simulate the brain intelligent application scenario and improve the amount of information in the storage array. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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Abstract

一种存储阵列（1）、存储对象逻辑关系的存储芯片及方法，存储阵列（1）包括：第一引出线（L0~Ln）和第二引出线（C0~Cn），不同编号的第一引出线（L0~Ln）和第二引出线（C0~Cn）之间分别连接一存储单元（11），相同编号的第一引出线（L0~Ln）和第二引出线（C0~Cn）之间分别连接一可控开关（M）。存储芯片包括：接口模块（2）；产生控制信号的控制模块（3）；产生写电流、擦电流或读电流的驱动模块（4）；选通第一引出线（L0~Ln）的第一译码器（5），选通第二引出线（C0~Cn）的第二译码器（6）；以及存储逻辑关系值的存储阵列（1）。存储方法包括：写入和读出操作。通过全新的存储阵列（1）实现对象间的逻辑关系的存储；同时在读出时，通过可控开关（M）在相同编号的引出线间传递，将结果转换为条件，以此综合间接关系因素，可用于仿脑智能应用场景，提高存储阵列（1）中的信息量。

Description

存储阵列、存储对象逻辑关系的存储芯片及方法 技术领域
本发明涉及半导体存储集成电路领域，特别是涉及一种存储阵列、存储对象逻辑关系的存储芯片及方法。
背景技术
经过数十年的发展，计算机存储体系已经形成了完善的层级结构，SRAM、DRAM、FLASH、EEPROM以及磁介质存储等技术根据性能的不同，在层级结构中占据了各自的地位，以保证计算核心能够在高速运行时有足够的数据使用。尽管各种存储介质的性能和存储原理千差万别，但其功能是一致的，那就是将数据存储到指定地址，并保证需要时可以原样读取出来使用。
随着存储需求的剧烈增长，CPU的处理能力也是随着摩尔定律稳步增强，数据中心的建设规模也是越来越大，从而导致能源使用逐渐成为数据中心最大的支出，另一方面，数据规模的扩大使得从数据中获取有用的信息变得越来越困难。在这一状况下，众多公司和研究人员把注意力集中到大脑的神经网络上。
人的大脑通过视觉、听觉、触觉等等多种途径每天处理大量的信息，在推理、识别、联想、预测等等方面的能力是计算机系统难以匹敌的，但据估算一个成年人的大脑功耗仅仅只有20W左右，而信息在大脑中的传递速度也仅能达到毫秒量级。如何从人类大脑的工作方式中获得启发，改善计算机体系的运行方式，以达到高效率低功耗运行的目的。
神经网络计算已经形成了一个非常成熟完善的理论体系，模仿大脑神经网络的并行处理机制，组成多输入多输出系统，通过大量数据的训练使得该系统有越来越准确的预测能力。这一系统起初是在计算机软件中实现，为了提高计算效率，更多的硬件系统利用处理器、FPGA(Field Programmable Gate Array，现场可编程门阵列)等技术实现算法的硬件加速。更进一步的，IBM公司已在多年前启动了人工智能的Watson电脑系统项目，引领了智能处理芯片领域的研发。
在仿脑或仿神经元网络方向上，存储技术的研究进展相比计算技术要慢得多，人脑记忆的原理与计算机的存储方式相去甚远。其中最根本的区别在于，人脑以对象及对象间的逻辑关系作为主要记忆的内容，而对图像、声音、文字等原 始信息数据的记忆能力是很弱的，也因此人脑的思考方式与计算机的计算方式有着巨大的差别。以相变存储技术为代表的新存储技术出现后，特别是新存储技术基于电阻存储，作为非易失存储技术，同时又支持高速的随机访问，敏锐的研究者已经开始试图利用这些新技术制造出更为接近人脑记忆的存储芯片，以期望实现在仿脑或人工智能领域的应用。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种存储阵列、存储对象逻辑关系的存储芯片及方法，用于解决现有技术中存储需求增长的问题。
为实现上述目的及其他相关目的，本发明提供一种存储阵列，所述存储阵列至少包括：
具有相同数量且分别位于行方向和列方向的第一引出线和第二引出线，第一引出线及第二引出线分别编号，不同编号的第一引出线和第二引出线之间分别连接一存储单元，相同编号的第一引出线和第二引出线之间分别连接一可控开关；其中，
所述存储单元包括串联的变阻型二端器件和选通二极管，所述选通二极管由第一引出线向第二引出线正向导通、由第二引出线向第一引出线反向截止；
所述可控开关在双向截止和由第二引出线向第一引出线单向导通的两种状态间切换。
优选地，所述变阻型二端器件在电脉冲信号作用下至少能在2种阻值状态间转变。
优选地，所述变阻型二端器件在电脉冲信号作用下，根据激励电信号的强度、波形不同，阻值可以在最高阻值和最低阻值之间变化，其中，所述最高阻值至少比所述最低阻值高一个数量级。
为实现上述目的及其他相关目的，本发明还提供一种存储对象逻辑关系的存储芯片，所述存储对象逻辑关系的存储芯片至少包括：
接口模块、控制模块、驱动模块、第一译码器、第二译码器、以及上述存储阵列；
所述接口模块用于数据的输入和输出；
所述控制模块与所述接口模块、所述驱动模块及所述第一译码器相连，获取 输入的指令并产生相应的控制信号；
所述驱动模块与所述控制模块及所述第二译码器相连，根据所述控制模块输出的控制信号产生写电流、擦电流或读电流；
所述第一译码器与所述控制模块及所述存储阵列的第一引出线相连，受所述控制模块的控制选通相应的第一引出线；
所述第二译码器与所述驱动模块及所述存储阵列的第二引出线相连，受所述控制模块的控制选通相应的第二引出线；
所述存储阵列分别连接所述控制模块、所述第一译码器以及所述第二译码器，受所述控制模块的控制关断所有可控开关，并向选通的第一引出线和第二引出线之间的存储单元写入逻辑关系值；或受所述控制模块的控制开启所有可控开关，并从选通的第一引出线和第二引出线之间读出逻辑关系值。
优选地，选通的第一引出线代表作为条件的第一对象，选通的第二引出线代表作为结果的第二对象，所述逻辑关系值为第一对象成立时直接导致第二对象成立的概率值，相同编号的第一引出线和第二引出线对应同一对象。
为实现上述目的及其他相关目的，本发明还提供一种存储对象逻辑关系的存储方法，所述存储对象逻辑关系的存储方法采用上述存储阵列，至少包括以下步骤：
写入操作：
输入需要写入的信息，包括第一对象，第二对象，以及第一对象和第二对象的逻辑关系值；
将存储阵列中的可控开关全部关断；
选通第一对象对应的第一引出线，选通第二对象对应的第二引出线；
产生与第一对象和第二对象的逻辑关系值相对应的写电流，并将所述写电流施加到被选通的第一引出线和第二引出线之间的存储单元上；
读出操作：
输入需要读出关系的对象组，所述对象组包括第一对象和第二对象；
将存储阵列中的可控开关全部连通；
选通第一对象对应的第一引出线，选通第二对象对应的第二引出线；
产生读电压或电流，并将所述读电压或电流施加到被选通的第一引出线和第二引出线上，读取被选通的第一引出线和第二引出线之间的电阻值；
将读出的电阻值转化为相应的逻辑关系值后输出。
优选地，所述第一对象为条件，所述第二对象为结果，所述逻辑关系值为第一对象成立时直接导致第二对象成立的概率值。
优选地，在写入操作中，写入的逻辑关系值将原逻辑关系值覆盖；或在原逻辑关系值的基础上叠加，以此增强第一对象与第二对象之间的逻辑关系。
优选地，在读出操作中，若第一对象与第二对象存在直接关系，则直接读出第一对象与第二对象的逻辑关系值对应的电阻值；若第一对象通过第三对象与第二对象存在间接关系，则读出第一对象与第三对象的逻辑关系值对应的电阻值和第三对象与第二对象的逻辑关系值对应的电阻值的和；若第一对象与第二对象既存在直接关系又通过第三对象存在间接关系，则读出第一对象与第三对象的逻辑关系值对应的电阻值和第三对象与第二对象的逻辑关系值对应的电阻值串联后与第一对象与第二对象的逻辑关系值对应的电阻值并联所得的电阻值。
优选地，在写入操作中，选通第二对象对应的第二引出线的方法包括：将第二对象对应的第二引出线接地，将其他第二引出线悬空或对其他第二引出线施加高电平以使未选中的存储单元中的选通二极管反向截止。
优选地，在读出操作中，选通第二对象对应的第二引出线的方法包括：将第二对象对应的第二引出线接地，将其他第二引出线悬空。
如上所述，本发明的存储阵列、存储对象逻辑关系的存储芯片及方法，具有以下有益效果：
本发明的存储阵列、存储对象逻辑关系的存储芯片及方法采用一种基于电可操作的阻变型存储阵列，该存储阵列具有相同数量且相互垂直的两组引出线，相互垂直且不同编号的两根引出线之间连接一个存储单元，每个存储单元由一个电可操作的变阻型二端器件和一个选通二极管构成，相互垂直且相同编号的两根引出线之间仅用一个可控开关器件连接。写入时，将所有的开关器件断开，使相同编号的引出线之间高阻，并对指定编号的两根引出线之间的单元施加电脉冲改变单元阻值；读出时，可将所有的开关器件连通，使相同编号的引出线之间低阻，在指定编号的两根引出线之间施加电信号读出电阻值。由于读出时，电流可通过开关器件在相同编号的引出线间传递，因此，若认为编号代表对象，而阻值表达两个对象间的关系的话，该芯片在读出时可以同时综合间接关系因素的贡献，可用于仿脑智能应用场景。
附图说明
图1显示为本发明的存储阵列的示意图。
图2显示为本发明的存储单元的示意图。
图3显示为本发明的存储对象逻辑关系的存储芯片的示意图。
图4显示为本发明的存储对象逻辑关系的存储方法的写入操作的流程示意图。
图5显示为本发明的存储对象逻辑关系的存储芯片的读出操作的流程示意图。
元件标号说明
1         存储阵列
11        存储单元
111       上电极
112       可变电阻材料层
113       下电极
114       P极
115       N极
116       高掺杂埋层
117       第一通孔
118       第二通孔
2         接口模块
3         控制模块
4         驱动模块
5         第一译码器
6         第二译码器
7         时钟模块
8         电源模块
S11～S14  步骤
S21～S25  步骤
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1～图5。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
如图1所示，本发明提供一种存储阵列1，所述存储阵列1包括：
具有相同数量且分别位于行方向和列方向的第一引出线和第二引出线，第一引出线及第二引出线分别编号。在本实施例中，所述第一引出线位于行方向，所述第二引出线位于列方向，所述第一引出线和所述第二引出线的方向可互换，不以本实施例为限。在本实施例中，将所述第一引出线从上到下依次命名为L0～Ln，将第二引出线从左到右依次命名为C0～Cn，其中下标0～n为编号。不同编号的第一引出线和第二引出线之间分别连接一存储单元11，相同编号的第一引出线和第二引出线之间分别连接一可控开关M。
具体地，如图1所示，所述存储单元11包括串联的变阻型二端器件R和选通二极管D，所述选通二极管D由第一引出线向第二引出线正向导通、由第二引出线向第一引出线反向截止。在本实施例中，所述变阻型二端器件R的一端连接第二引出线，另一端连接所述选通二极管D的负极，所述选通二极管D的正极连接第一引出线。如图2所示，更具体地，所述变阻型二端器件R包括可变电阻材料层112，位于所述可变电阻材料层112上下表面的上电极111和下电极113，以及外侧的二氧化硅介质材料层(图中未显示)；所述变阻型二端器件R的一端通过第二通孔118连接第二引出线，另一端连接所述选通二极管D；所述上电极111和所述下电极113的材料为W或TiN等电阻率较低的材料，所述可变电阻材料层112的材质为Ge、Sb、Te的一种或合金，优选地，所述可变电阻材料层112为Ge、Sb、Te组分比例为2:2:6的合金。所述选通二极管D包括P极114和N极115，其P极114与所述变阻型二端器件R的下电极113连接， N极115与高掺杂埋层116相连，通过第一通孔117与第一引出线连接。所述变阻型二端器件R在电脉冲信号作用下至少能在2种阻值状态间转变，例如高阻状态和低阻状态；或者所述变阻型二端器件R在电脉冲信号作用下，根据激励电信号的强度、波形不同，阻值可以在最高阻值和最低阻值之间变化，其中，所述最高阻值至少比所述最低阻值高一个数量级。
具体地，如图1所示，所述可控开关M在双向截止和由第二引出线向第一引出线单向导通的两种状态间切换，各可控开关M的控制端连接同一开关控制信号Ctl，在写入操作时各可控开关M全部关闭，在读出操作时各可控开关M全部打开。
如图3所示，本发明还提供一种存储对象逻辑关系的存储芯片，所述存储对象逻辑关系的存储芯片至少包括：接口模块2、控制模块3、驱动模块4、第一译码器5、第二译码器6、以及所述存储阵列1。
如图3所示，所述接口模块2用于数据的输入和输出。
具体地，所述接口模块2作为所述存储对象逻辑关系的存储芯片与外部设备交换信息的通道，现有技术中的任何接口模块均适用于本发明的存储对象逻辑关系的存储芯片。从所述接口模块2输入的数据包括第一对象a，第二对象b，以及第一对象a与第二对象b的逻辑关系值p。在本实施例中，所述第一对象a作为条件，所述第二对象b作为结果，所述逻辑关系值p为第一对象a成立时直接导致第二对象b成立的概率值。
如图3所示，所述控制模块3与所述接口模块2、所述驱动模块4及所述第一译码器5相连，获取输入的指令并产生相应的控制信号。
具体地，所述控制模块3与所述接口模块2、所述驱动模块4及所述第一译码器5双向连接，接受指令后输出各种控制信号以进行写、读或擦除操作。
如图3所示，所述驱动模块4与所述控制模块3及所述第二译码器6相连，根据所述控制模块3输出的控制信号产生写电流、擦电流或读电流。
具体地，写电流的幅值和脉宽可由所述控制模块3根据写入的逻辑关系值强度产生。
如图3所示，所述第一译码器5与所述控制模块3及所述存储阵列1的第一引出线相连，受所述控制模块3的控制选通第一对象a所对应的第一引出线。
如图3所示，所述第二译码器6与所述驱动模块3及所述存储阵列1的第二 引出线相连，受所述控制模块3的控制选通第二对象b所对应的第二引出线。
如图3所示，所述存储阵列1分别连接所述控制模块3、所述第一译码器5以及所述第二译码器6。在写入操作时，所述存储阵列1受所述控制模块3输出的开关控制信号Ctl的控制关断所有可控开关，并向选通的第一引出线和第二引出线之间的存储单元写入第一对象a与第二对象b的逻辑关系值p。在读出操作时，所述存储阵列1受所述控制模块3输出的开关控制信号Ctl的控制开启所有可控开关，并从选通的第一引出线和第二引出线之间读出第一对象a与第二对象b的逻辑关系值p。
如图3所示，所述存储对象逻辑关系的存储芯片还包括时钟模块7和电源模块8，分别用于提供工作时钟和电源电压。
如图3～图5所示，本发明还提供一种存储对象逻辑关系的存储方法，所述存储对象逻辑关系的存储方法采用所述存储阵列，至少包括以下步骤：
写入操作，如图4所示，具体包括以下步骤：
步骤S11：输入需要写入的信息，包括第一对象a，第二对象b，以及第一对象a和第二对象b的逻辑关系值p。
具体地，给出需要写入的信息{a,b,p}，在本实施例中，第一对象a以编号表示，第一对象a代表条件；第二对象b以编号表示，第二对象b代表结果；第一对象a和第二对象b的逻辑关系值p代表第一对象a成立时直接导致第二对象b成立的概率值；其中p的取值范围可设定为[0,1]，0表示第一对象a与第二对象b不存在任何关系，第一对象a的成立完全不会导致第二对象b成立，1表示第一对象a的成立必然导致第二对象b成立，数值越大成立的概率越高，在实际使用中，对于p的数值范围的定义可根据实际需求设定，不以本实施例为限。在本实施例中，采用所述存储对象逻辑关系的存储芯片实现对象逻辑关系的存储，因此通过所述接口模块2将需要写入的信息传输到所述控制模块3。
步骤S12：将存储阵列中的可控开关全部关断。
具体地，所述控制模块3接收到信息后输出一开关控制信号Ctl，将所述存储阵列1中的所有可控开关M全部关断，相同编号的第一引出线和第二引出线之间呈高阻状态。
步骤S13：选通第一对象a对应的第一引出线，选通第二对象b对应的第二引出线。
具体地，所述控制模块3根据第一对象a及第二对象b的编号控制所述第一译码器5及所述第二译码器6选通相应的第一引出线和第二引出线。选通第二对象b对应的第二引出线的方法具体包括：将第二对象b对应的第二引出线接地，将其他第二引出线悬空或对其他第二引出线施加高电平以使未选中的存储单元11中的选通二极管D反向截止。
步骤S14：产生与第一对象a和第二对象b的逻辑关系值p相对应的写电流，并将所述写电流施加到被选通的第一引出线和第二引出线之间的存储单元上。
具体地，所述控制模块3控制所述驱动模块4产生与第一对象a和第二对象b的逻辑关系值p相对应的电流，并通过被选通的第一引出线输入到被选通的第一引出线和第二引出线之间的存储单元11上，由于电流的变化，所述变阻型二端器件R上的阻值发生变化。具体地，所述变阻型二端器件R的阻值至少能在2种阻值状态间转变；或根据激励电信号的强度、波形不同，阻值可以在最高阻值和最低阻值之间变化，其中，所述最高阻值至少比所述最低阻值高一个数量级。
至此，第一对象a和第二对象b对应的逻辑关系值p已被写入所述存储阵列1。在写入操作中，写入的逻辑关系值将原逻辑关系值覆盖；或在原逻辑关系值的基础上叠加。在本实施例中，采用的叠加的方式以增强第一对象a与第二对象b之间的逻辑关系。
读出操作，如图5所示，具体包括以下步骤：
步骤S21：输入需要读出关系的对象组，所述对象组包括第一对象a和第二对象b。
具体地，给出需要读出关系的对象组{a,b}，在本实施例中，第一对象a以编号表示，第一对象a代表条件；第二对象b以编号表示，第二对象b代表结果。在本实施例中，采用所述存储对象逻辑关系的存储芯片实现对象逻辑关系的存储，因此通过所述接口模块2将需要读出关系的对象组的信息传输到所述控制模块3。
步骤S22：将存储阵列中的可控开关全部连通。
具体地，所述控制模块3接收到信息后输出一开关控制信号Ctl，将所述存储阵列11中的所有可控开关M全部连通，相同编号的第一引出线和第二引出线之间呈低阻状态。
步骤S23：选通第一对象a对应的第一引出线，选通第二对象b对应的第二 引出线。
具体地，所述控制模块3根据第一对象a及第二对象b的编号控制所述第一译码器5及所述第二译码器6选通相应的第一引出线和第二引出线。选通第二对象对应的第二引出线的方法具体包括：将第二对象b对应的第二引出线接地，将其他第二引出线悬空。
步骤S24：产生读电压或电流，并将所述读电压或电流施加到被选通的第一引出线和第二引出线上，读取被选通的第一引出线和第二引出线之间的电阻值。
具体地，所述控制模块3控制所述驱动模块4产生读电压或电流，并施加在被选通的第一引出线和第二引出线上，其中第一引出线上施加高电位，第二引出线上施加低电位，读取流经第一引出线和第二引出线的电流，以此获取电阻值。
更具体地，若第一对象a与第二对象b存在直接关系，如图1所示，在本实施例中，第一对象a的编号为1，第二对象b的编号为n，则电流从被选通的第一引出线L1输入，流经被选通的第一引出线L1与第二引出线Cn之间的存储单元后，从被选通的第二引出线Cn输出，直接读出被选通的第一引出线L1与第二引出线Cn之间的存储单元中的电阻值r，电阻值r越小，第一对象a成立时第二对象b成立的概率p越高。
更具体地，若第一对象通过第三对象与第二对象存在间接关系，如图1所示，在本实施例中，第一对象a的编号为1，第二对象b的编号为n，第三对象c的编号为0，第一对象a成立时直接导致第三对象c成立的概率为p1，第三对象c成立时直接导致第二对象b成立的概率为p2，则电流从被选通的第一引出线L1输入，由于第一对象a与第二对象b无直接关系，则存储第一对象a与第二对象b的逻辑关系值的存储单元呈高阻状态，没有电流流过，而第一对象a与第三对象c存在直接关系，因此电流流过存储第一对象a与第三对象c的逻辑关系值的存储单元，由于各可控开关开启，因此电流又从第三对象c对应的第二引出线C0流至第三对象c对应的第一引出线L0，将第三对象c从结果转化为条件，之后由于第三对象c与第二对象b存在直接关系，因此电流又流经存储第三对象c与第二对象b的逻辑关系值的存储单元，最后从被选通的第二引出线Cn输出，最终得到的电阻值为第一对象a与第三对象c的逻辑关系值对应的电阻值r1和第三对象c与第二对象b的逻辑关系值对应的电阻值r2的和。即使第一对象a与第二对象c不存在直接关系，也可通过间接关系推理获知两者的逻辑关系，其 中r1+r2必大于单一阻值r1和r2，即第一对象a成立则第二对象b成立的概率低于第一对象a成立则第三对象c成立的概率以及第三对象c成立则第二对象b成立的概率，且第一对象a成立则第三对象c成立的概率p1及第三对象c成立则第二对象b成立的概率p2越小，r1+r2越大，第一对象a成立则第二对象b成立的概率越小，符合逻辑思维。
更具体地，若第一对象a与第二对象b既存在直接关系也存在间接关系，则电流流经的总的电阻为上述两种情况获取电阻的并联，即(r1+r2)//r，则最终读出的电阻值必小于上述两种情况中任意一种，第一对象a成立则第二对象b成立的概率则增加，实现了第一对象a与第二对象b的逻辑关系的增强。
步骤S25：将读出的电阻值转化为相应的逻辑关系值后输出。
优选地，读出的电阻值被输出到所述控制电路3，所述控制电路3根据读出的电阻值输出相应的逻辑关系值，再藉由所述接口电路2将所述逻辑关系值输出。电阻值与逻辑关系值的关系可以是线性的，也可以是非线性的，可根据实际使用场合的不同做具体的设定。
至此，第一对象a和第二对象b对应的逻辑关系被读出。
本发明的存储阵列、存储对象逻辑关系的存储芯片及方法采用一种基于电可操作的阻变型存储阵列，该存储阵列具有相同数量且相互垂直的两组引出线，相互垂直且不同编号的两根引出线之间连接一个存储单元，每个存储单元由一个电可操作的变阻型二端器件和一个选通二极管构成，相互垂直且相同编号的两根引出线之间仅用一个可控开关器件连接。写入时，将所有的开关器件断开，使相同编号的引出线之间高阻，并对指定编号的两根引出线之间的单元施加电脉冲改变单元阻值；读出时，可将所有的开关器件连通，使相同编号的引出线之间低阻，在指定编号的两根引出线之间施加电信号读出电阻值。由于读出时，电流可通过开关器件在相同编号的引出线间传递，因此，若认为编号代表对象，而阻值表达两个对象间的关系的话，该芯片在读出时可以同时综合间接关系因素的贡献，可用于仿脑智能应用场景。
综上所述，本发明提供一种存储阵列、存储对象逻辑关系的存储芯片及方法。所述存储阵列包括：具有相同数量且分别位于行方向和列方向的第一引出线和第二引出线，第一引出线及第二引出线分别编号，不同编号的第一引出线和第二引出线之间分别连接一存储单元，相同编号的第一引出线和第二引出线之间分别连 接一可控开关。所述储对象逻辑关系的存储芯片包括：接口模块；产生控制信号的控制模块；根据控制信号产生写电流、擦电流或读电流的驱动模块；选通相应的第一引出线的第一译码器；选通相应的第二引出线的第二译码器；以及用于存储逻辑关系值的存储阵列。所述存储对象逻辑关系的存储方法包括：写入操作和读出操作。本发明的存储阵列、存储对象逻辑关系的存储芯片及方法通过全新的存储阵列，实现对象间的逻辑关系的存储；同时在读出时，通过可控开关在相同编号的引出线间传递，将结果转换为条件，以此综合间接关系因素，可用于仿脑智能应用场景，提高存储阵列中的信息量。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (11)

  1. 一种存储阵列，其特征在于，所述存储阵列至少包括：
    具有相同数量且分别位于行方向和列方向的第一引出线和第二引出线，第一引出线及第二引出线分别编号，不同编号的第一引出线和第二引出线之间分别连接一存储单元，相同编号的第一引出线和第二引出线之间分别连接一可控开关；其中，
    所述存储单元包括串联的变阻型二端器件和选通二极管，所述选通二极管由第一引出线向第二引出线正向导通、由第二引出线向第一引出线反向截止；
    所述可控开关在双向截止和由第二引出线向第一引出线单向导通的两种状态间切换。
  2. 根据权利要求1所述的存储阵列，其特征在于：所述变阻型二端器件在电脉冲信号作用下至少能在2种阻值状态间转变。
  3. 根据权利要求1所述的存储阵列，其特征在于：所述变阻型二端器件在电脉冲信号作用下，根据激励电信号的强度、波形不同，阻值可以在最高阻值和最低阻值之间变化，其中，所述最高阻值至少比所述最低阻值高一个数量级。
  4. 一种存储对象逻辑关系的存储芯片，其特征在于，所述存储对象逻辑关系的存储芯片至少包括：
    接口模块、控制模块、驱动模块、第一译码器、第二译码器、以及如权利要求1～3任意一项所述的存储阵列；
    所述接口模块用于数据的输入和输出；
    所述控制模块与所述接口模块、所述驱动模块及所述第一译码器相连，获取输入的指令并产生相应的控制信号；
    所述驱动模块与所述控制模块及所述第二译码器相连，根据所述控制模块输出的控制信号产生写电流、擦电流或读电流；
    所述第一译码器与所述控制模块及所述存储阵列的第一引出线相连，受所述控制模块的控制选通相应的第一引出线；
    所述第二译码器与所述驱动模块及所述存储阵列的第二引出线相连，受所述控制模块的控制选通相应第二引出线；
    所述存储阵列分别连接所述控制模块、所述第一译码器以及所述第二译码器，受所述控制模块的控制关断所有可控开关，并向选通的第一引出线和第二引出线之间的存储单元写入逻辑关系值；或受所述控制模块的控制开启所有可控开关，并从选通的第一引出线和第二引出线之间读出逻辑关系值。
  5. 根据权利要求4所述的存储对象逻辑关系的存储芯片，其特征在于：选通的第一引出线代表作为条件的第一对象，选通的第二引出线代表作为结果的第二对象，所述逻辑关系值为第一对象成立时直接导致第二对象成立的概率值，相同编号的第一引出线和第二引出线对应同一对象。
  6. 一种存储对象逻辑关系的存储方法，其特征在于，所述存储对象逻辑关系的存储方法采用如权利要求1～3任意一项所述的存储阵列，至少包括以下步骤：
    写入操作：
    输入需要写入的信息，包括第一对象，第二对象，以及第一对象和第二对象的逻辑关系值；
    将存储阵列中的可控开关全部关断；
    选通第一对象对应的第一引出线，选通第二对象对应的第二引出线；
    产生与第一对象和第二对象的逻辑关系值相对应的写电流，并将所述写电流施加到被选通的第一引出线和第二引出线之间的存储单元上；
    读出操作：
    输入需要读出关系的对象组，所述对象组包括第一对象和第二对象；
    将存储阵列中的可控开关全部连通；
    选通第一对象对应的第一引出线，选通第二对象对应的第二引出线；
    产生读电压或电流，并将所述读电压或电流施加到被选通的第一引出线和第二引出线上，读取被选通的第一引出线和第二引出线之间的电阻值；
    将读出的电阻值转化为相应的逻辑关系值后输出。
  7. 根据权利要求6所述的存储对象逻辑关系的存储方法，其特征在于：所述第一对象为条件，所述第二对象为结果，所述逻辑关系值为第一对象成立时直接导致第二对象成立的概率值。
  8. 根据权利要求6所述的存储对象逻辑关系的存储方法，其特征在于：在写入操作中，写入的逻辑关系值将原逻辑关系值覆盖；或在原逻辑关系值的基础上叠加，以此增强第一对象与第二对象之间的逻辑关系。
  9. 根据权利要求6所述的存储对象逻辑关系的存储方法，其特征在于：在读出操作中，若第一对象与第二对象存在直接关系，则直接读出第一对象与第二对象的逻辑关系值对应的电阻值；若第一对象通过第三对象与第二对象存在间接关系，则读出第一对象与第三对象的逻辑关系值对应的电阻值和第三对象与第二对象的逻辑关系值对应的电阻值的和；若第一对象与第二对象既存在直接关系又通过第三对象存在间接关系，则读出第一对象与第三对象的逻辑关系值对应的电阻值和第三对象与第二对象的逻辑关系值对应的电阻值串联后与第一对象与第二对象的逻辑关系值对应的电阻值并联所得的电阻值。
  10. 根据权利要求6所述的存储对象逻辑关系的存储方法，其特征在于：在写入操作中，选通第二对象对应的第二引出线的方法包括：将第二对象对应的第二引出线接地，将其他第二引出线悬空或对其他第二引出线施加高电平以使未选中的存储单元中的选通二极管反向截止。
  11. 根据权利要求6所述的存储对象逻辑关系的存储方法，其特征在于：在读出操作中，选通第二对象对应的第二引出线的方法包括：将第二对象对应的第二引出线接地，将其他第二引出线悬空。
PCT/CN2015/098732 2015-12-18 2015-12-24 存储阵列、存储对象逻辑关系的存储芯片及方法 WO2017101143A1 (zh)

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