WO2022073311A1 - 一种自参考存储结构和存算一体电路 - Google Patents

一种自参考存储结构和存算一体电路 Download PDF

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WO2022073311A1
WO2022073311A1 PCT/CN2021/070110 CN2021070110W WO2022073311A1 WO 2022073311 A1 WO2022073311 A1 WO 2022073311A1 CN 2021070110 W CN2021070110 W CN 2021070110W WO 2022073311 A1 WO2022073311 A1 WO 2022073311A1
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transistor
tunnel junction
magnetic tunnel
self
voltage
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PCT/CN2021/070110
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English (en)
French (fr)
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邢国忠
林淮
刘宇
张凯平
张康玮
吕杭炳
谢常青
刘琦
李泠
刘明
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中国科学院微电子研究所
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Priority to US18/247,446 priority Critical patent/US20240005974A1/en
Publication of WO2022073311A1 publication Critical patent/WO2022073311A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1655—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1693—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5607—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using magnetic storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type

Definitions

  • the present disclosure relates to the technical field of memory, and in particular, to a self-reference memory structure and a memory-computing integrated circuit.
  • the core storage unit of magnetic random access memory is a magnetic tunnel junction.
  • the magnetization reversal of the magnetic tunnel junction needs to add an external magnetic field, and the tunneling magneto-resistance of the magnetic tunnel junction is relatively low. Therefore, the existing memory is not only unfavorable for circuit integration. , and the writing process results in a large power consumption of the device and a low reading margin.
  • the purpose of the present disclosure is, at least in part, to provide a self-reference memory structure and a memory-computing integrated circuit that overcomes the above problems or at least partially solves the above problems.
  • a self-referential storage structure comprising:
  • three transistors including: a first transistor, a second transistor, and a third transistor;
  • Two magnetic tunnel junctions including: a first magnetic tunnel junction and a second magnetic tunnel junction;
  • the first magnetic tunnel junction is connected in series between the first transistor and the second transistor;
  • the second magnetic tunnel junction is connected in series between the second transistor and the third transistor; when the first transistor, the second transistor and the third transistor are turned on, the writing of one-bit binary information is realized.
  • the first magnetic tunnel junction and the second magnetic tunnel junction each include:
  • Bottom-up spin-orbit coupling layer ferromagnetic free layer, tunneling layer, ferromagnetic reference layer, top electrode;
  • the ferromagnetic free layer and the ferromagnetic reference layer are any one of the following vertically anisotropic magnetic materials:
  • CoFeB Co 2 FeAl, CO , CoFe, Fe 3 GeTe 2 and Ni 3 GeTe 2 .
  • it also includes:
  • word line first bit line, second bit line, read/write control line, source line;
  • the first gate of the first transistor and the third gate of the third transistor are both connected to the word line, and the second gate of the second transistor is connected to the read/write control line;
  • Both the first top electrode of the first magnetic tunnel junction and the second top electrode of the second magnetic tunnel junction are connected to the source line;
  • the first drain of the first transistor is connected to the first bit line, and the third drain of the third transistor is connected to the second bit line.
  • the class of the ferromagnetic free layer when current is injected into the spin-orbit coupling layers of the first magnetic tunnel junction and the second magnetic tunnel junction through the word line, the class of the ferromagnetic free layer is controlled
  • the ratio of the field torque to the damping-like torque satisfies the first preset condition, so as to achieve deterministic magnetization reversal without the action of an external auxiliary magnetic field, so that the resistance states of the first magnetic tunnel junction and the second magnetic tunnel junction are deterministically generated switch.
  • the antisymmetric exchange interaction coefficient between the spin-orbit coupling layer and the ferromagnetic free layer is adjusted so that the antisymmetric exchange interaction coefficient satisfies 0.2 ⁇ 0.3 mJ/m 2 ;
  • the ratio between the field-like torque and the damping-like torque of the ferromagnetic free layer is controlled.
  • the ratio satisfies the second preset condition, deterministic magnetization reversal without the action of an external auxiliary magnetic field is realized, so that the resistance states of the first magnetic tunnel junction and the second magnetic tunnel junction are deterministically switched.
  • initialization is performed, including:
  • the resistance state is the opposite resistance state.
  • the spin-orbit torque causes the first magnetic tunnel junction to form a second resistance state, and the second magnetic tunnel junction to form a first resistance state;
  • a high level is applied to the word line, and a write current pulse is injected, so that the first magnetic tunnel junction and the second magnetic tunnel junction are turned over, that is, data is written.
  • an integrated circuit of storage and calculation comprising:
  • the storage unit includes a plurality of parallel self-reference storage structures, and the storage unit generates a voltage difference between the induced voltage and the reference voltage under the action of the current;
  • the asymmetric sense amplifier includes two transistors of different sizes
  • the voltage generating circuit is connected between the storage unit and the asymmetrical sense amplifier, and is used for inputting the voltage difference between the induced voltage and the reference voltage into the asymmetrical sense amplifier to realize data reading and logical operation functions.
  • when performing a data read operation it includes:
  • the power supply generating circuit applies a power supply voltage, so that the storage unit outputs the voltage difference, and the voltage difference is input to the asymmetrical sense amplifier, based on the difference between the two transistors of different sizes in the asymmetrical sense amplifier.
  • the difference in the discharge rate causes the two inverse output ends of the asymmetric sense amplifier to generate complementary outputs, thereby realizing the read data.
  • the The asymmetrical sense amplifier outputs the result of the logic operation.
  • One or more technical solutions provided in the present disclosure include: three transistors, including: a first transistor, a second transistor, and a third transistor; two magnetic tunnel junctions, including: a first magnetic tunnel junction, a second magnetic tunnel junction tunnel junction; the first magnetic tunnel junction is connected in series between the first transistor and the second transistor; the second magnetic tunnel junction is connected in series between the second transistor and the third transistor; in When the first transistor, the second transistor, and the third transistor are turned on, the writing of one-bit binary information is realized. When data storage is realized, one-bit binary writing only needs to be applied by applying a unidirectional current. During the process, the delay is low, the power consumption is low, and the reading margin is high, so as to achieve high-precision and reliable reading.
  • One or more technical solutions provided in the present disclosure include: a storage unit, an asymmetrical sense amplifier, and a voltage generation circuit, the storage unit includes a plurality of parallel self-reference storage structures, and the storage unit functions in the voltage generation circuit The voltage difference between the induced voltage and the reference voltage is generated, and the asymmetrical sense amplifier includes two transistors with different sizes. The two branches of the voltage generating circuit generate currents respectively, and pass through the two magnetic tunnel junctions to achieve a voltage difference with high read margin.
  • the architecture adopts a self-reference storage structure, which increases the voltage difference output by the storage unit, realizes a high read margin, and increases read reliability and operation performance.
  • FIG. 1 is a schematic diagram of a self-referencing memory structure according to one or more embodiments of the present disclosure
  • FIG. 2 is a schematic structural diagram of a magnetic tunnel junction according to one or more embodiments of the present disclosure
  • 3a is a schematic diagram of the change of material magnetization with time when the ratio of field-like torque and damping-like torque is independently adjusted according to one or more embodiments of the present disclosure
  • 3b shows the magnetization of the material when the ratio of the field-like torque and the damping-like torque is simultaneously controlled when the antisymmetric exchange interaction strength between the ferromagnetic free layer and the spin-orbit coupling layer is controlled according to one or more embodiments of the present disclosure.
  • FIG. 4 is a layout design structural diagram of a self-reference storage structure according to one or more embodiments of the present disclosure
  • FIG. 5 is a schematic diagram illustrating the magnetization inversion characteristics of the ferromagnetic free layer when a current pulse is applied to the self-reference memory structure according to one or more embodiments of the present disclosure
  • FIG. 6 is a schematic diagram of an integrated circuit of storage and computing according to one or more embodiments of the present disclosure
  • FIG. 7a and 7b are schematic diagrams showing the comparison of the read results using the conventional 2T1M and the self-reference storage structure in the present disclosure according to one or more embodiments of the present disclosure;
  • 7c is a schematic diagram illustrating the comparison of circuit read delay, power consumption and read margin under different TMR conditions according to one or more embodiments of the present disclosure
  • FIG. 8 is an internal structural diagram of an asymmetric sense amplifier according to one or more embodiments of the present disclosure.
  • FIG. 9 is a schematic diagram of a conversion circuit that will realize the exchange of different logic operations according to one or more embodiments of the present disclosure.
  • 10a and 10b are diagrams of read voltage distributions under simulated process fluctuations according to one or more embodiments of the present disclosure
  • FIG. 11 is a circuit diagram formed by a memory array structure and a peripheral circuit configuration according to one or more embodiments of the present disclosure.
  • a self-referential memory structure including: three transistors, including: a first transistor T1 , a second transistor T2 , and a third transistor T3 ; two magnetic tunnel junctions , including: a first magnetic tunnel junction MTJ0, a second magnetic tunnel junction MTJ1; the first magnetic tunnel junction MTJ0 is connected in series between the first transistor T1 and the second transistor T2; the word line WL; Between the two transistors T2 and the third transistor T3; the first gate of the first transistor T1 and the third gate of the third transistor T3 are connected to the word line WL; when the first transistor T1, the second transistor T2, and the third transistor are turned on When the transistor T3 is used, the writing of one-bit binary information is realized.
  • the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 both include:
  • CoFeB Co 2 FeAl, CO , CoFe, Fe 3 GeTe 2 and Ni 3 GeTe 2 .
  • the ferromagnetic free layer 202 and the ferromagnetic reference layer 204 have easy magnetization directions perpendicular to the plane. In turn, it is beneficial to the miniaturization of the device size and the rapid magnetization inversion.
  • the self-reference storage structure further includes: word line WL, first bit line BL1, second bit line BL2, read/write control line R/W Ctrl, and source line Source Line.
  • the first gate of the first transistor T1 and the third gate of the third transistor T3 are both connected to the word line WL, and the second gate of the second transistor T2 is connected to the read/write control line R/W Ctrl;
  • the first top electrode of a magnetic tunnel junction MTJ0 and the second top electrode of the second magnetic tunnel junction MJT1 are both connected to the source line Source Line;
  • the first drain of the first transistor T1 is connected to the first bit line BL1, the first The third drain of the three transistor T3 is connected to the second bit line BL2.
  • the first magnetic tunnel junction MTJ0 is connected in series between the first transistor T1 and the second transistor T2, and the second magnetic tunnel junction MTJ1 is connected in series between the second transistor T2 and the third transistor T3, specifically:
  • the spin-orbit coupling layer (SOC Layer) 201 of the first magnetic tunnel junction MTJ0 is connected to the source of the first transistor T1, and the other end is connected to the drain (or source) of the second transistor T2.
  • the second magnetic tunnel One end of the spin-orbit coupling layer (SOC Layer) 201 of the junction MTJ1 is connected to the source electrode of the third transistor T3, and the other end is connected to the source electrode (or drain electrode) of the second transistor T2.
  • the current injected when the ferromagnetic free layer 202 has a spin-orbit torque effect, the ratio of the field-like torque to the damping-like torque of the ferromagnetic free layer 202 changes.
  • ( ⁇ FL / ⁇ DL ) satisfies the first preset condition, deterministic magnetization inversion without the assistance of an external magnetic field can be realized, so that the resistance states of the first magnetic tunnel junction and the second magnetic tunnel junction can be switched deterministically.
  • the first preset condition is that ⁇ FL / ⁇ DL ⁇ 2.
  • the field-like torque and the like-like torque of the ferromagnetic free layer 202 are controlled by regulating Changes in the ratio of damping torque ( ⁇ FL / ⁇ DL ) to obtain an image of material magnetization m z versus time.
  • CoFeB, Co 2 FeAl, CO For any one of CoFe, Fe 3 GeTe 2 and Ni 3 GeTe 2 , when ⁇ FL / ⁇ DL ⁇ 2, the material magnetization m z oscillates on one side of the initial magnetization direction and fails to complete the deterministic flip; when ⁇ FL / ⁇ DL ⁇ 2, the magnetization direction m z passes through the plane position from the initial direction, and at the falling edge of the current pulse, it gradually relaxes to a state opposite to the initial position, thereby realizing a rapid flip without an external magnetic field, and then The data writing is controlled by adjusting the ratio of ⁇ FL / ⁇ DL .
  • the above-mentioned magnetization inversion means that the magnetization directions of the ferromagnetic free layer and the ferromagnetic reference layer in the magnetic tunnel junction are parallel or anti-parallel.
  • the antisymmetric exchange interaction (Dzyaloshinskii-Moriya interaction) coefficient between the spin-orbit coupling layer 201 and the ferromagnetic free layer 202 in the two magnetic tunnel junctions
  • the ratio of the field-like torque and the damping-like torque ( ⁇ FL / ⁇ DL ) of the ferromagnetic free layer 202 is adjusted, and the two work together to achieve rapid flipping without an external magnetic field.
  • the DM interaction coefficient is made to satisfy 0.2-0.3 mJ/m 2 ; and current is injected into the spin-orbit coupling layers 201 of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 through the word line WL, and the field-like torque and
  • the ratio of the damping-like torque satisfies the second preset condition, the deterministic magnetization reversal without the action of the external auxiliary magnetic field is realized, so that the resistance states of the first magnetic tunnel junction and the second magnetic tunnel junction are deterministically switched.
  • the antisymmetric exchange interaction coefficient between the spin-orbit coupling layer and the ferromagnetic free layer is adjusted, specifically by adjusting the thickness of the spin-orbit coupling layer, or the spin-orbit coupling layer and the ferromagnetic free layer. stress distribution between free layers, roughness or interface electronic band structure.
  • the first magnetic tunnel junction and the second magnetic tunnel junction form different resistance states by any of the above-mentioned methods to achieve deterministic magnetization inversion, thereby realizing a single bit Writing of binary information.
  • the magnetic tunnel junction forms a low resistance state, representing binary information "0".
  • the magnetization direction of the reference layer is antiparallel
  • the high resistance state formed by the magnetic tunnel junction represents binary information "1".
  • the memory cell Before the first data writing, the memory cell needs to be initialized, including: turning on the first transistor T1 and the third transistor T3, turning off the second transistor T2 and the source line, and applying a gate voltage to the word line WL to The first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 pass current, so that the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are both under the effect of spin transfer torque (STT) generated by the initialization current
  • STT spin transfer torque
  • the first magnetic tunnel junction is formed into a first resistance state
  • the second magnetic tunnel junction is formed into a second resistance state
  • the first resistance state and the second resistance state are opposite resistance states.
  • the first transistor T1 and the third transistor T3 are turned on by applying a gate voltage to the word line WL, and at this time, the read/write control line (R/W Ctrl) is at a low voltage level, the source line SL and the second transistor T2 are both turned off, the first bit line BL1 connected to the first drain of the first transistor T1 is at a high level, and the second bit line BL1 connected to the third drain of the third transistor T3 Line BL2 is at a low level.
  • the current flows through the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1, thereby generating a spin transfer torque (STT) effect, so that the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 form opposite resistance states, namely MTJ0 is "1", MTJ1 is "0”; or MTJ0 is "0", MTJ1 is "1", depending on the magnetization direction of the ferromagnetic reference layer.
  • STT spin transfer torque
  • the second transistor T2 when the read/write control line (R/W Ctrl) is at a high level, the second transistor T2 is turned on, when current flows through the smaller resistance (ie, the magnetic resistance state is "0" Tunnel junction) corresponding to the spin-orbit coupling layer 201 of the magnetic tunnel junction, a spin current is generated under the spin-orbit coupling effect (STT), so a torque effect is generated on the ferromagnetic material of the ferromagnetic free layer.
  • STT spin-orbit coupling effect
  • the first magnetic tunnel junction MTJ0 and the second The magnetization direction m z of the ferromagnetic free layer in the magnetic tunnel junction MTJ1 is simultaneously reversed to the opposite resistance state to the initialized resistance state, at this time, data writing is realized.
  • FIG. 4 it is the design layout of the self-reference storage structure.
  • a high level is applied to the word line WL, and the magnetization inversion is realized in the magnetic tunnel junction under the action of the write current pulse.
  • the word line WL is set to a high level, and a current pulse with a very short rise time (10ps) is applied in the spin-orbit coupling layer of the magnetic tunnel junction, so as to achieve magnetization reversal without external auxiliary magnetic field. .
  • a current pulse with a very short rise time (10ps) is applied in the spin-orbit coupling layer of the magnetic tunnel junction, so as to achieve magnetization reversal without external auxiliary magnetic field.
  • the current pulse is injected again, and the flip process will be repeated. This process realizes the reverse magnetization flip process, thereby making the magnetization flip tunable.
  • the process of realizing the rapid magnetization inversion during the data writing process greatly improves the response speed of the device, and realizes the characteristics of low time delay and low power consumption.
  • One or more technical solutions are provided in the present disclosure, including: three transistors, including: a first transistor, a second transistor, and a third transistor; two magnetic tunnel junctions, including: a first magnetic tunnel junction, a second magnetic tunnel junction; the first magnetic tunnel junction is connected in series between the first transistor and the second transistor; the second magnetic tunnel junction is connected in series between the second transistor and the third transistor, and is turned on
  • the first transistor, the second transistor, and the third transistor are used, the writing of one-bit binary information is realized.
  • the writing of one-bit binary information is realized.
  • the device is in the process of data writing. Low latency, low power consumption, and high read margin enable high-accuracy and reliable reading.
  • a storage-calculation integrated circuit including: a storage unit 601 , an asymmetrical sense amplifier 602 and a voltage generating circuit 603 .
  • the storage unit 601 includes a plurality of parallel self-reference storage structures, and under the action of the current, the storage unit generates a voltage difference between the induced voltage and the reference voltage.
  • the asymmetric sense amplifier 602 includes two transistors of different sizes.
  • the voltage generating circuit 603 is connected between the storage unit 601 and the asymmetrical sense amplifier 602, and is used for inputting the voltage difference between the induced voltage and the reference voltage into the asymmetrical sense amplifier 602, so as to achieve a high read margin data reading and logic operation functions.
  • the voltage generating circuit 603 When performing a data read operation, the voltage generating circuit 603 applies a power supply voltage, so that the storage unit 601 generates a voltage difference between the induced voltage and the reference voltage, and the voltage difference is input to the asymmetrical sense amplifier 602, based on two of the asymmetrical sense amplifiers Due to the difference in the discharge rates of transistors with different sizes, the two inverting output terminals of the asymmetric sense amplifier 602 generate complementary outputs to realize the read data.
  • V L V dd -V clamp /R mtj ⁇ R load
  • V R V dd -(V clamp /R ap +V clamp /R p )/2 ⁇ R load
  • V clamp is a clamping voltage applied to the sensing path where the resistance of the first magnetic tunnel junction MTJ0 is located and the reference path where the second magnetic tunnel junction MTJ1 is located, to ensure that the two paths have the same voltage drop.
  • VL is the induced voltage
  • VR is the reference voltage.
  • R p is the resistance when the magnetization directions of the ferromagnetic free layer and the ferromagnetic reference layer are parallel
  • R ap is the resistance when the magnetization directions of the ferromagnetic free layer and the ferromagnetic reference layer are antiparallel.
  • V access and word line WL By controlling V access and word line WL, it is used to select any set of self-referencing memory structures.
  • the two inverting output terminals of the asymmetric sense amplifier PCSA are precharged to V dd in the initial stage, and after the read enable signal is pulled high, the voltage generated by the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 is generated.
  • the gate control voltage turns on the transistor to discharge, and the difference of the discharge rate will produce the result of the complementary output, that is, through the V out and /V out output, the read operation is realized.
  • the corresponding delay is 120ps faster than when the TMR is 50%, the corresponding delay is 287ps.
  • the reference voltage VR is used as the gate voltage of the transistor T2 '.
  • the reference voltage is used as the gate voltage of the transistor T1 ' .
  • the conversion circuit shown in the figure the conversion circuit is set between the output terminals of the induced voltage and the reference voltage and the asymmetrical sense amplifier, and the corresponding transistor is turned on when the OR or AND operation is realized to realize the control of the asymmetrical sense amplifiers T1' and T2' Swap of grid voltage.
  • FIG. 10a and FIG. 10b the voltage distributions read under simulated process fluctuations.
  • Fig. 10a corresponds to the induced voltage VL1 and the reference voltage VR1 corresponding to one storage result
  • Fig. 10b corresponds to the induced voltage VL2 and the reference voltage VR2 corresponding to another storage result.
  • the integrated memory-computing circuit can be applied in large-scale array applications, including multiple horizontal memory cells, multiple column-oriented memory cells, column decoding (RD), row decoding (CD), read/write Control line (R/D Ctrl), source line (SL Driver) and asymmetric sense amplifier (PCSA) and reference voltage generation circuit.
  • RD column decoding
  • CD row decoding
  • R/D Ctrl read/write Control line
  • S Driver source line
  • PCSA asymmetric sense amplifier
  • a plurality of horizontal memory cells and a plurality of column memory cells can be extended in the XY direction, and the column decoding (RD) and the row decoding (CD) are used to control the gating of the memory cells.
  • the read/write control line (R/D Ctrl) and the source line (SL Driver) control the read and write of the memory cell.
  • the combination of an asymmetrical sense amplifier (PCSA) and a reference voltage generation circuit is used to realize the read and in-memory operations of the memory cell array.
  • the reference voltage generation circuit includes a storage unit and a voltage generation circuit, and the memory operation is based on the storage unit, the voltage generation circuit and the asymmetrical sense amplifier to realize the integration of storage and calculation.
  • One or more technical solutions provided in the present disclosure include: a storage unit, an asymmetrical sense amplifier, and a voltage generating circuit, the storage unit includes a plurality of parallel self-reference storage structures, and the storage unit, under the action of a current, A voltage difference is generated, the asymmetrical sense amplifier includes two transistors with different sizes, the voltage generation circuit is connected between the storage unit and the asymmetrical sense amplifier, and is used to input the voltage difference into the asymmetrical sense amplifier to achieve high readout
  • the read data and logical operation functions of the margin use the constructed self-reference storage structure to increase the voltage difference output by the storage unit, thereby realizing a high read margin and increasing the read and operation performance.

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  • Computer Hardware Design (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

提供一种自参考存储结构及存算一体电路，所述自参考存储结构包括：三个晶体管，包括：第一晶体管T1、第二晶体管T2、第三晶体管T3；两个磁隧道结，包括：第一磁隧道结MTJ0、第二磁隧道结MTJ1；第一磁隧道结MTJ0串联于第一晶体管T1与第二晶体管T2之间；第二磁隧道结MTJ1串联于第二晶体管T2与第三晶体管T3之间；在开启第一晶体管T1、第二晶体管T2、第三晶体管T3时，实现一位二进制信息的写入；在实现数据存储时，只需要施加单向电流即可实现一位二进制的写入。

Description

一种自参考存储结构和存算一体电路
相关申请的交叉引用
本申请要求于2020年10月10日提交、申请号为202011077197.0且名称为“一种自参考存储结构以及存算一体电路”的中国专利申请的优先权，其全部内容通过引用合并于此。
技术领域
本公开内容涉及存储器技术领域，尤其涉及一种自参考存储结构和存算一体电路。
背景技术
磁性随机存储器(MRAM)的核心存储单元为磁隧道结，对该磁隧道结的磁化翻转需要添加外加磁场，且磁隧道结隧穿磁电阻比较低，因此，现有的存储器不仅不利于电路集成，而且，写入过程造成器件功耗较大，读取裕度低。
因此，如何获得低功耗低时延以及高读取裕度的存储器是目前亟待解决的技术问题。
发明内容
本公开内容的目的至少部分在于，提供了一种克服上述问题或者至少部分地解决上述问题的自参考存储结构和存算一体电路。
在本公开的一个方面，提供了一种自参考存储结构，包括：
三个晶体管，包括：第一晶体管、第二晶体管、第三晶体管；
两个磁隧道结，包括：第一磁隧道结、第二磁隧道结；
所述第一磁隧道结串联于所述第一晶体管与所述第二晶体管之间；
所述第二磁隧道结串联于所述第二晶体管与所述第三晶体管之间；在所述第一晶体管、第二晶体管、第三晶体管导通时，实现一位二进制信息的写入。
在一些实施方式中，所述第一磁隧道结和所述第二磁隧道结均包括：
由下至上的自旋轨道耦合层、铁磁自由层、隧穿层、铁磁参考层、顶电极；
其中，所述铁磁自由层与所述铁磁参考层均为如下任意一种垂直各项 异性的磁性材料：
CoFeB、Co 2FeAl、C O、CoFe、Fe 3GeTe 2和Ni 3GeTe 2。
在一些实施方式中，还包括：
字线、第一位线、第二位线、读/写控制线、源极线；
所述第一晶体管的第一栅极和第三晶体管的第三栅极均连接所述字线，所述第二晶体管的第二栅极与所述读/写控制线连接；
所述第一磁隧道结的第一顶电极与所述第二磁隧道结的第二顶电极均与所述源极线连接；
所述第一晶体管的第一漏极连接所述第一位线，所述第三晶体管的第三漏极连接所述第二位线。
在一些实施方式中，在通过所述字线对所述第一磁隧道结和所述第二磁隧道结的所述自旋轨道耦合层注入电流时，以控制所述铁磁自由层的类场力矩和类阻尼力矩之比满足第一预设条件，实现无外加辅助磁场作用下的确定性磁化翻转，以使所述第一磁隧道结和所述第二磁隧道结阻态发生确定性切换。
在一些实施方式中，在通过对所述自旋轨道耦合层与所述铁磁自由层之间的反对称交换作用系数进行调整，以使得所述反对称交换作用系数满足0.2～0.3mJ/m 2；且
通过所述字线对所述第一磁隧道结和所述第二磁隧道结的所述自旋轨道耦合层注入电流时，以控制所述铁磁自由层的类场力矩和类阻尼力矩之比满足第二预设条件时，实现无外加辅助磁场作用下的确定性磁化翻转，以使所述第一磁隧道结和所述第二磁隧道结的阻态发生确定性切换。
在一些实施方式中，在执行写操作之前，进行初始化，包括：
开启所述第一晶体管和所述第三晶体管，关闭所述第二晶体管以及所述源极线，通过对所述字线施加栅压，注入初始化电流，使得所述第一磁隧道结和所述第二磁隧道结均产生自旋转移矩效应，以使第一磁隧道结形成第一阻态，第二磁隧道结形成第二阻态，且所述第一阻态与所述第二阻态为相反阻态。
在一些实施方式中，在执行写操作时，包括：
开启所述第一晶体管、所述第二晶体管、所述第三晶体管，控制所述读/写控制线处于高电平，使得所述第一磁隧道结和所述第二磁隧道结均产生自旋轨道力矩的作用，使得所述第一磁隧道结形成第二阻态，所述第二磁隧道结形成第一阻态；
在所述字线上施加高电平，注入写电流脉冲，使得所述第一磁隧道结 和所述第二磁隧道结实现翻转，即数据的写入。
在本公开的另一个方面，提供了一种存算一体电路，包括：
存储单元、非对称灵敏放大器以及电压产生电路；
所述存储单元包括多个并联的自参考存储结构，所述存储单元在电流的作用下，产生感应电压和参考电压的电压差；
所述非对称灵敏放大器包括两个尺寸不同的晶体管；
所述电压产生电路连接于所述存储单元与所述非对称灵敏放大器之间，用于将所述感应电压与所述参考电压的电压差输入所述非对称灵敏放大器中，以实现数据读取以及逻辑运算功能。
在一些实施方式中，在执行数据读操作时，包括：
所述电源产生电路施加电源电压，使得所述存储单元输出所述电压差，所述电压差输入所述非对称灵敏放大器，基于所述非对称灵敏放大器中的所述两个尺寸不同的晶体管的放电速率的差异，使得所述非对称灵敏放大器的两个反向输出端产生互补输出的结果，实现读数据。
在一些实施方式中，在执行逻辑运算时，包括：
通过导通所述存储单元中的任意两个自参考存储结构，基于所述任意两个自参考存储结构的存储状态，以及所述非对称灵敏放大器中的两个尺寸不同的晶体管，使得所述非对称灵敏放大器输出逻辑运算结果。
本公开内容中提供的一个或多个技术方案，包括：三个晶体管，包括：第一晶体管、第二晶体管、第三晶体管；两个磁隧道结，包括：第一磁隧道结、第二磁隧道结；所述第一磁隧道结串联于所述第一晶体管与所述第二晶体管之间；所述第二磁隧道结串联于所述第二晶体管与所述第三晶体管之间；在开启第一晶体管、第二晶体管、第三晶体管时，实现一位二进制信息的写入，在实现数据存储时，只需要施加单向电流即可实现一位二进制的写入，器件在数据写入过程中延时低、功耗小，且读取裕度高，从而实现高精度可靠读取。
本公开内容中提供的一个或多个技术方案，包括：存储单元、非对称灵敏放大器以及电压产生电路，该存储单元包括多个并联的自参考存储结构，所述存储单元在电压产生电路的作用下，产生感应电压与参考电压的电压差，该非对称灵敏放大器包括两个尺寸不同的晶体管。该电压产生电路的两个支路分别产生电流，通过两个磁隧道结，以实现高读取裕度的电压差，读数据产生的电压差输入非对称灵敏放大器中，实现逻辑运算功能。该架构采用自参考存储结构，将该存储单元输出的电压差拉大，实现了高读取裕度，增加了读取可靠性以及运算性能。
附图说明
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本公开内容的限制。而且在整个附图中，用相同的参考图形表示相同的部件。在附图中：
图1为依据本公开一个或多个实施方式的自参考存储结构的示意图；
图2为依据本公开一个或多个实施方式的磁隧道结的结构示意图；
图3a为依据本公开一个或多个实施方式的单独调控类场力矩和类阻尼力矩之比时，材料磁化随时间变化的示意图；
图3b为依据本公开一个或多个实施方式的在调控铁磁自由层与自旋轨道耦合层之间的反对称交换作用强度时，同时调控类场力矩和类阻尼力矩之比时，材料磁化随时间变化的示意图；
图4为依据本公开一个或多个实施方式的自参考存储结构的版图设计结构图；
图5为依据本公开一个或多个实施方式的在对自参考存储结构通入电流脉冲时，铁磁自由层磁化翻转特性示意图；
图6为依据本公开一个或多个实施方式的存算一体电路的示意图；
图7a、图7b为依据本公开一个或多个实施方式的采用传统2T1M与本公开中采用自参考存储结构的读取结果对比示意图；
图7c为依据本公开一个或多个实施方式的对比不同TMR情况下，电路读取延时、功耗以及读取裕度的对比示意图；
图8为依据本公开一个或多个实施方式的非对称灵敏放大器的内部结构图；
图9为依据本公开一个或多个实施方式的将实现不同逻辑操作调换的转换电路示意图；
图10a、图10b为依据本公开一个或多个实施方式的模拟工艺波动情况下读取电压分布情况图；
图11为依据本公开一个或多个实施方式的存储器阵列结构与外围电路配置形成的电路图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而 不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
根据本公开的一个方面，提供了一种自参考存储结构，如图1所示，包括：三个晶体管，包括：第一晶体管T1、第二晶体管T2、第三晶体管T3；两个磁隧道结，包括：第一磁隧道结MTJ0、第二磁隧道结MTJ1；第一磁隧道结MTJ0串联于第一晶体管T1与第二晶体管T2之间；字线WL；第二磁隧道MTJ1结串联于第二晶体管T2与第三晶体管T3之间；第一晶体管T1的第一栅极与第三晶体管T3的第三栅极均连接字线WL；在开启第一晶体管T1、第二晶体管T2、第三晶体管T3时，实现一位二进制信息的写入。
其中，如图2所示，该第一磁隧道结MTJ0和第二磁隧道结MTJ1均包括：
由下至上的自旋轨道耦合层(SOC Layer)201、铁磁自由层(FL)202、隧穿层203、铁磁参考层(RL)204、顶电极205；其中，铁磁自由层202与所述铁磁参考层204均为如下任意一种垂直各项异性的磁性材料：
CoFeB、Co 2FeAl、C O、CoFe、Fe 3GeTe 2和Ni 3GeTe 2。
该铁磁自由层202与铁磁参考层204具有垂直于面内的易磁化方向。进而有利于器件尺寸的微缩以及快速磁化翻转。
如图1所示，该自参考存储结构还包括：字线WL、第一位线BL1、第二位线BL2、读/写控制线R/W Ctrl、源极线Source Line。
第一晶体管T1的第一栅极和第三晶体管T3的第三栅极均连接字线WL，该第二晶体管T2的第二栅极与该读/写控制线R/W Ctrl连接；该第一磁隧道结MTJ0的第一顶电极与第二磁隧道结MJT1的第二顶电极均与该源极线Source Line连接；该第一晶体管T1的第一漏极连接第一位线BL1，第三晶体管T3的第三漏极连接第二位线BL2。
该第一磁隧道结MTJ0串联于第一晶体管T1与第二晶体管T2之间，第二磁隧道结MTJ1串联于第二晶体管T2与第三晶体管T3之间，具体为：
该第一磁隧道结MTJ0的自旋轨道耦合层(SOC Layer)201的一端连接第一晶体管T1的源极，另一端与第二晶体管T2的漏极(或源极)连接，第二磁隧道结MTJ1的自旋轨道耦合层(SOC Layer)201的一端连接第三晶体管T3的源极，另一端连接第二晶体管T2的源极(或漏极)连接。
在对该第一磁隧道结MTJ0和第二磁隧道结MTJ1通入电流，以实现无外加辅助磁场作用下确定性磁化翻转时，具体采用如下两种方式实现。
在一些实施方式中，在对该字线WL施加电流脉冲时，由于该第一磁隧道结MTJ0和第二磁隧道结MTJ1中的自旋轨道耦合层201具有自旋轨道耦 合效应，在注入电流时，会对该铁磁自由层202产生自旋轨道力矩的作用，使得该铁磁自由层202的类场力矩和类阻尼力矩之比发生变化，而在该类场力矩与类阻尼力矩之比(λ FL/λ DL)满足第一预设条件时，能够实现无外加磁场辅助下的确定性磁化翻转，以使第一磁隧道结和第二磁隧道结的阻态发生确定性切换。
该第一预设条件为，λ FL/λ DL≥2。
具体如图3a所示，在对该字线WL施加密度J＝1.2×10 12A/cm 2，脉宽为0.5ns的开关电流脉冲时，通过调控铁磁自由层202的类场力矩和类阻尼力矩之比(λ FL/λ DL)的变化，得到材料磁化m z随时间变化的图像，对于本公开内容所采用的垂直各项异性的铁磁材料，CoFeB、Co 2FeAl、C O、CoFe、Fe 3GeTe 2和Ni 3GeTe 2中的任意一种，在λ FL/λ DL＜2时，材料磁化m z，位于初始磁化方向一侧震荡，未能完成确定性翻转；当λ FL/λ DL≥2，该磁化方向m z由初始方向穿过平面位置，在该电流脉冲的下降沿，逐步驰豫到与初始位置相反的状态，进而实现了无外加磁场下的快速翻转，进而实现了通过调控λ FL/λ DL的比值控制数据的写入。
上述的磁化翻转是指磁隧道结中的铁磁自由层与铁磁参考层的磁化方向平行或者反平行。
在一些实施方式中，如图3b所示，首先，通过对两个磁隧道结中的自旋轨道耦合层201与铁磁自由层202之间的反对称交换作用(Dzyaloshinskii-Moriya相互作用)系数进行调整，同时，对铁磁自由层202的类场力矩和类阻尼力矩之比(λ FL/λ DL)进行调整，两者共同作用实现无外加磁场下的快速翻转。
其中，使得DM相互作用系数满足0.2～0.3mJ/m 2；且通过字线WL对第一磁隧道结MTJ0和第二磁隧道结MTJ1的自旋轨道耦合层201注入电流，在类场力矩和类阻尼力矩之比满足第二预设条件时，实现无外加辅助磁场作用下的确定性磁化翻转，以使第一磁隧道结和第二磁隧道结的阻态发生确定性切换。
在一些实施方式中，通过该字线WL施加密度J＝1.2×10 12A/cm 2，脉宽为0.5ns的开关电流脉冲时，同时，调制DM相互作用系数D＝0.2mJ/m 2，由此可以得到，无外加磁场下的快速翻转时所需的λ FL/λ DL比值为0.02、0.1和0.14。该方案中所需的λ FL/λ DL比值相较于图3a中的方案(λ FL/λ DL≥2)大大降低。更加方便调控。因此，上述该第二预设条件为λ FL/λ DL＝0.02，λ FL/λ D＝0.1，λ FL/λ DL＝0.14。
其中，对自旋轨道耦合层与所述铁磁自由层之间的反对称交换作用系 数进行调整，具体是通过调节该自旋轨道耦合层的厚度，或者该自旋轨道耦合层与该铁磁自由层之间的应力分布、粗糙度或界面电子能带结构来实现。
在对字线置高电平，存储单元通入电流时，通过上述任意一种实现确定性磁化翻转的方式，使得第一磁隧道结和第二磁隧道结形成不同的阻态，实现一位二进制信息的写入。
其中，在磁隧道结的铁磁自由层与铁磁参考层的磁化方向平行时，该磁隧道结形成低阻态，代表二进制信息“0”，在磁隧道结的铁磁自由层与铁磁参考层的磁化方向反平行时，该磁隧道结形成的高阻态，代表二进制信息“1”。
在首次数据写入之前，存储单元需要进行初始化，包括：开启该第一晶体管T1和第三晶体管T3，关闭该第二晶体管T2以及源极线，通过对该字线WL施加栅压，以对该第一磁隧道结MTJ0和第二磁隧道结MTJ1通入电流，使得该第一磁隧道结MTJ0与该第二磁隧道结MTJ1，均在初始化电流产生的自旋转移矩效应(STT)作用下，使第一磁隧道结形成第一阻态、第二磁隧道结形成第二阻态，且第一阻态与第二阻态为相反阻态。
在一些实施方式中，该初始化过程中，通过对该字线WL外加栅压，开启该第一晶体管T1和第三晶体管T3，此时，读/写控制线(R/W Ctrl)处于低电平，源极线SL和第二晶体管T2均关断，第一晶体管T1的第一漏极连接的第一位线BL1处于高电平，第三晶体管T3的第三漏极连接的第二位线BL2处于低电平。电流流经该第一磁隧道结MTJ0和第二磁隧道结MTJ1，进而产生自旋转移矩效应(STT)，使得第一磁隧道结MTJ0和第二磁隧道结MTJ1形成相反阻态，即MTJ0为“1”，MTJ1为“0”；或者MTJ0为“0”，MTJ1为“1”，其取决于铁磁参考层磁化方向。
在执行数据写入时，控制该读/写控制线R/W Ctrl以及字线处于高电平，开启第一晶体管T1、第二晶体管T2、第三晶体管T3，使得第一磁隧道结MTJ0和第二磁隧道结MTJ1均产生自旋轨道力矩(SOT)的作用，使得第一磁隧道结MTJ0形成第二阻态，第二磁隧道结MTJ1形成第一阻态。
在一些实施方式中，在该读/写控制线(R/W Ctrl)处于高电平时，该第二晶体管T2导通，当电流流过该较小电阻(即阻态为“0”的磁隧道结)对应的磁隧道结的自旋轨道耦合层201时，在自旋轨道耦合效应(STT)下产生自旋流，因此对铁磁自由层的铁磁材料产生力矩作用，在铁磁自由层202的类场力矩和类阻尼力矩之比(λ FL/λ DL)满足预设条件(第一预设条件，或者第二预设条件)时，使得该第一磁隧道结MTJ0和第二磁隧道结MTJ1中的铁磁自由层的磁化方向m z同时翻转为与初始化的阻态的相反阻态，此时，实现 数据写入。
如图4所示，为该自参考存储结构的设计版图。
如图5所示，为字线WL上施加高电平，在写电流脉冲作用下，该磁隧道结中实现磁化翻转的图示。
在一些实施方式中，字线WL置于高电平，在磁隧道结的自旋轨道耦合层中施加上升沿时间极短(10ps)的电流脉冲，从而实现无外加辅助磁场作用下的磁化翻转。在磁化方向m z翻转之后再次注入该电流脉冲，会重复翻转过程，此过程实现了反向的磁化翻转过程，进而使得磁化翻转可调控。
由于，在电流脉冲注入时则会导致磁化方向m z的快速翻转，且翻转效果对电流的脉冲的宽度不敏感，因此，无需长时间保持电流，使得器件功耗减小。因此，在实现数据写入过程中实现快速磁化翻转的过程，使得器件的响应速度大大提高，实现了低时延、低功耗的特点。
本公开内容中提供一个或多个技术方案，包括：三个晶体管，包括：第一晶体管、第二晶体管、第三晶体管；两个磁隧道结，包括：第一磁隧道结、第二磁隧道结；所述第一磁隧道结串联于所述第一晶体管与所述第二晶体管之间；所述第二磁隧道结串联于所述第二晶体管与所述第三晶体管之间，在开启第一晶体管、第二晶体管、第三晶体管时，实现一位二进制信息的写入，在实现数据存储时，只需要施加单向电流即可实现一位二进制的写入，器件在数据写入过程中时延低，功耗较小，且读取裕度高，从而实现高精度可靠读取。
在本公开的另一个方面，提供了一种存算一体电路，如图6所示，包括：存储单元601、非对称灵敏放大器602以及电压产生电路603。
存储单元601包括多个并联的自参考存储结构，存储单元在电流的作用下，产生感应电压与参考电压的电压差。
该非对称灵敏放大器602包括两个尺寸不同的晶体管。
该电压产生电路603连接于存储单元601与非对称灵敏放大器602之间，用于将所述感应电压与所述参考电压的电压差输入该非对称灵敏放大器602中，以实现高读取裕度的数据读取以及逻辑运算功能。
以选通一组自参考存储结构为例，进行读取数据。
在执行数据读操作时，该电压产生电路603施加电源电压，使得存储单元601产生感应电压与参考电压的电压差，该电压差输入该非对称灵敏放大器602，基于非对称灵敏放大器中的两个尺寸不同的晶体管的放电速率的差异，非对称灵敏放大器602的两个反向输出端产生互补输出的结果，实现读数据。
具体地，通过对该电压产生电路603的电源端施加V dd，由于所选取的一组自参考存储结构中第一磁隧道结MTJ0的电阻和第二磁隧道结MTJ1的电阻之间存在电阻差，因此，流经该第一磁隧道结MTJ0的电阻和第二磁隧道结MTJ1的电阻的电流不同，因此，第一磁隧道结MTJ0的电阻和第二磁隧道结MTJ1的电阻所对应的路径的电流差转化为电压差，则有：
V L＝V dd-V clamp/R mtj×R load
V R＝V dd-(V clamp/R ap+V clamp/R p)/2×R load
V clamp是为该第一磁隧道结MTJ0的电阻所在的感应路径和第二磁隧道结MTJ1所在的参考路径上施加的钳位电压，用于确保这两个路径上具有相同的压降。V L为感应电压，V R为参考电压。
R p为铁磁自由层和铁磁参考层磁化方向平行时的电阻，R ap为铁磁自由层和铁磁参考层磁化方向反平行时的电阻。
通过对V access以及字线WL的控制，用于选择任意一组自参考存储结构。
该非对称灵敏放大器PCSA的两个反相输出端在初始阶段被预充电至V dd，将读使能信号拉高后，经过上述第一磁隧道结MTJ0和第二磁隧道结MTJ1所产生的栅控电压，开启晶体管进行放电，该放电速率的差异将产生互补输出的结果，即通过V out和/V out输出，实现了读操作。
将现有技术中采用的2T1R结构与本公开内容中采用的3T2MTJ结构的读取结果进行比较，如图7a、图7b所示，其中，虚线表示读取结果为“1”，实线表示读取结果为“0”。通过在300ps时，将V access置于高电平，将字线WL也置于高电平，使得输出的感应电压与参考电压作为该非对称灵敏放大器602的两个晶体管的栅极电压，用以控制这两个晶体管(T 1’和T 2’)的放电速率，由此，第一磁隧道结MTJ0所在的支路与第二磁隧道结MTJ1所在的支路的电压差值为读取裕度，由图7b所示，与图7a的相比，本公开内容中具有更大的读取裕度(如虚线框内所示)，因此，本公开内容的技术方案具有更高的读取可靠性。
如图7c所示，通过对比不同隧穿磁电阻比即TMR下，电路读取延(Latency)时、功耗(Power Consumption)以及读取裕度(Sensing Margin)，可以看出，TMR的大小与电路延迟成反比，TMR的大小与功耗也成反比，TMR的大小与读取裕度呈正比，因此，TMR越大，延迟越低、功耗越低，读取裕度也越大，更利于实际应用。
其中，在TMR达到250％时，对应的延迟为120ps快于在TMR为50％时，对应的延迟287ps。
如图8所示，将非对称灵敏放大器PCSA中的内部结构进行展示，并 选通任意两组自参考存储结构(A，A’和B，B’)。该非对称灵敏放大器PCSA包括不同尺寸的晶体管T 1’和T 2’，其中，晶体管T 1’的沟道长度L 1＝60nm，沟道宽度W 1＝120nm，晶体管T 2’的沟道长度L 2＝60nm，沟道宽度W 2＝180nm。
在对同列任意两个自参考存储结构进行选择，同时，对字线WL1和WL2进行选通，使得所选通的两个自参考存储结构存在四种存储状态，即“00”、“11”、“01”、“10”，对应三种电压输出状态V O，即，“V O”＝V 00、(V 01、V 10)、V 11。
基于对两个自参考存储结构存在的四种存储状态进行读取，基于读取结果以及该非对称灵敏放大器PCSA的原理，实现逻辑运算。
在实现AND运算时：
若感应电压V L作为晶体管T 1’的栅压，参考电压V R作为晶体管T 2’的栅压。
在“V O”＝V 00时，感应电压V L小于参考电压V R，因此，驱动晶体管T 1’的放电速度小于晶体管T 2’的放电速度，V out输出“0”。
在“V O”＝V 11时，感应电压V L大于参考电压V R，驱动晶体管T 1’的放电速度大于晶体管T 2’的放电速度，V out输出“1”。
在“V O”＝V 01或V 10时，感应电压V L等于参考电压V R，而由于晶体管T 1’的沟道宽度小于晶体管T 2’的沟道宽度，因此，晶体管T 1’的放电速度小于晶体管T 2’的放电速度，V out输出“0”。从而实现AND运算，则对应的/V out则实现NAND运算。
在实现OR运算时：
若感应电压作为晶体管T 2’的栅压，参考电压作为晶体管T 1’的栅压。
在“V O”＝V 00时，感应电压V L小于参考电压V R，因此，驱动晶体管T 2’的放电速度小于晶体管T 1’的放电速度，V out输出“0”。
在“V O”＝V 11时，感应电压V L大于参考电压V R，驱动晶体管T 2’的放电速度大于晶体管T 1’的放电速度，V out输出“1”。
在“V O”＝V 01或V 10时，感应电压V L等于参考电压V R，而由于晶体管T 2’的沟道宽度大于晶体管T 1’的沟道宽度，因此，晶体管T 2’的放电速度大于晶体管T 1’的放电速度，V out输出“1”。从而实现OR运算，则对应的/V out则实现NOR运算。
在输入晶体管T1’的感应电压V L大于输入晶体管T2’的参考电压V R时，晶体管T1’对应的导通电流越大，因此，对应的放电速率越快。
具体地，在实现感应电压V L与参考电压V R输入该非对称灵敏放大器中时，针对在AND运算和OR运算，需要将感应电压V L和参考电压V R方向 调换，具体通过图9所示的转换电路，在感应电压和参考电压的输出端与非对称灵敏放大器之间设置该转换电路，在实现OR或AND运算时开启对应的晶体管，实现对非对称灵敏放大器T1’以及T2’控制栅压的互换。
如图10a、图10b所示，为模拟工艺波动情况下读取的电压分布情况。其中，图10a对应一种存储结果对应的感应电压V L1与参考电压V R1，图10b对应另一种存储结果对应的感应电压V L2与参考电压V R2，通过改变工艺参数，模拟得到对应的感应电压(V L1、V L2)和参考电压(V R1、V R2)的值，根据该模拟结果，由图10a可以看出，感应电压V L1和参考电压V R1各自对应的支路的读取结果没有重叠，因此，保证了在工艺波动的情况下，数据读取的准确性。
如图11所示，该存算一体电路能够应用在大型阵列应用中，包括多个横向存储单元、多个列向存储单元、列译码(RD)、行译码(CD)、读/写控制线(R/D Ctrl)、源极线(SL Driver)和非对称灵敏放大器(PCSA)和参考电压生成电路。
其中，多个横向存储单元、多个列向存储单元可以在XY方向上扩展，列译码(RD)、行译码(CD)用于控制存储单元的选通。
读/写控制线(R/D Ctrl)、源极线(SL Driver)控制存储单元的读写。
非对称灵敏放大器(PCSA)和参考电压生成电路组合用于实现存储单元阵列的读取与存内运算。该参考电压生成电路包括存储单元和电压产生电路，该存内运算基于存储单元、电压产生电路以及非对称灵敏放大器实现存算一体。
本公开内容中提供的一个或多个技术方案，包括：存储单元、非对称灵敏放大器以及电压产生电路，该存储单元包括多个并联的自参考存储结构，所述存储单元在电流的作用下，产生电压差，该非对称灵敏放大器包括两个尺寸不同的晶体管，该电压产生电路连接于存储单元与非对称灵敏放大器之间，用于将电压差输入非对称灵敏放大器中，以实现高读取裕度的读数据以及逻辑运算功能，采用构造的自参考存储结构，将该存储单元输出的电压差拉大，实现了高读取裕度，增加了读取以及运算性能。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
显然，本领域的技术人员可以对本公开内容进行各种改动和变型而不 脱离本公开内容的精神和范围。这样，倘若本公开内容的这些修改和变型属于本公开内容权利要求及其等同技术的范围之内，则本公开内容也意图包含这些改动和变型在内。

Claims (10)

  1. 一种自参考存储结构，包括：
    三个晶体管，包括：第一晶体管、第二晶体管、第三晶体管；
    两个磁隧道结，包括：第一磁隧道结、第二磁隧道结；
    所述第一磁隧道结串联于所述第一晶体管与所述第二晶体管之间；
    所述第二磁隧道结串联于所述第二晶体管与所述第三晶体管之间；
    在控制所述第一晶体管、第二晶体管、第三晶体管导通时，实现一位二进制信息的写入。
  2. 如权利要求1所述的自参考存储结构，其中，所述第一磁隧道结和所述第二磁隧道结均包括：
    由下至上的自旋轨道耦合层、铁磁自由层、隧穿层、铁磁参考层、顶电极；
    其中，所述铁磁自由层与所述铁磁参考层均为如下任意一种垂直各项异性的磁性材料：
    CoFeB、Co 2FeAl、C O、CoFe、Fe 3GeTe 2和Ni 3GeTe 2。
  3. 如权利要求2所述的自参考存储结构，其中，还包括：
    字线、第一位线、第二位线、读/写控制线、源极线；
    所述第一晶体管的第一栅极和第三晶体管的第三栅极均连接所述字线，所述第二晶体管的第二栅极与所述读/写控制线连接；
    所述第一磁隧道结的第一顶电极与所述第二磁隧道结的第二顶电极均与所述源极线连接；
    所述第一晶体管的第一漏极连接所述第一位线，所述第三晶体管的第三漏极连接所述第二位线。
  4. 如权利要求3所述的自参考存储结构，其中，在通过所述字线对所述第一磁隧道结和所述第二磁隧道结的所述自旋轨道耦合层注入电流时，以控制所述铁磁自由层的类场力矩和类阻尼力矩之比满足第一预设条件，实现无外加辅助磁场作用下的确定性磁化翻转，使所述第一磁隧道结和所述第二磁隧道结的阻态发生确定性切换。
  5. 如权利要求3所述的自参考存储结构，其中，在通过对所述自旋轨道耦合层与所述铁磁自由层之间的反对称交换作用系数进行调整，以使得反对称交换作用系数满足0.2～0.3mJ/m 2；且
    通过所述字线对所述第一磁隧道结和所述第二磁隧道结的所述自旋轨道 耦合层注入电流时，以控制所述铁磁自由层的类场力矩和类阻尼力矩之比满足第二预设条件时，实现无外加辅助磁场作用下的确定性磁化翻转，使所述第一磁隧道结和所述第二磁隧道结的阻态发生确定性切换。
  6. 如权利要求3所述的自参考存储结构，其中，在执行写操作之前，进行初始化，包括：
    开启所述第一晶体管和所述第三晶体管，关闭所述第二晶体管以及所述源极线，通过对所述字线施加栅压，使得所述第一磁隧道结和所述第二磁隧道结均产生自旋转移矩效应，以使第一磁隧道结形成第一阻态，第二磁隧道结形成第二阻态，且所述第一阻态与所述第二阻态为相反阻态。
  7. 如权利要求6所述的自参考存储结构，其中，在执行写操作时，包括：
    开启所述第一晶体管、所述第二晶体管、所述第三晶体管，控制所述读/写控制线处于高电平，使得所述第一磁隧道结和所述第二磁隧道结，均产生自旋轨道力矩的作用，使得所述第一磁隧道结形成第二阻态，所述第二磁隧道结形成第一阻态；
    在所述字线上施加高电平，注入写电流脉冲，使得所述第一磁隧道结和所述第二磁隧道结实现翻转，即数据的写入。
  8. 一种存算一体电路，包括：
    存储单元、非对称灵敏放大器以及电压产生电路；
    所述存储单元包括多个并联的自参考存储结构，所述存储单元在电流的作用下，产生感应电压与参考电压的电压差；
    所述非对称灵敏放大器包括两个尺寸不同的晶体管；
    所述电压产生电路连接于所述存储单元与所述非对称灵敏放大器之间，用于将所述感应电压与所述参考电压的电压差输入所述非对称灵敏放大器中，以实现数据读取以及逻辑运算功能。
  9. 如权利要求8所述的存算一体电路，其中，
    在执行数据读操作时，包括：
    所述电源产生电路施加电源电压，使得所述存储单元输出所述电压差，所述电压差输入所述非对称灵敏放大器，基于所述非对称灵敏放大器中所述两个尺寸不同的晶体管放电速率的差异，使得所述非对称灵敏放大器的两个反向输出端产生互补输出的结果，实现读数据。
  10. 如权利要求8所述的存算一体电路，其中，
    在执行逻辑运算时，包括：
    通过导通所述存储单元中的任意两个自参考存储结构，基于所述任意两个自参考存储结构的存储状态，以及所述非对称灵敏放大器中的两个尺寸不 同的晶体管，使得所述非对称灵敏放大器输出逻辑运算结果。
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