WO2023060475A1 - 自旋电子器件、存储单元、存储阵列和读写电路 - Google Patents

自旋电子器件、存储单元、存储阵列和读写电路 Download PDF

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WO2023060475A1
WO2023060475A1 PCT/CN2021/123529 CN2021123529W WO2023060475A1 WO 2023060475 A1 WO2023060475 A1 WO 2023060475A1 CN 2021123529 W CN2021123529 W CN 2021123529W WO 2023060475 A1 WO2023060475 A1 WO 2023060475A1
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terminal
transistor
magnetic tunnel
read
bit line
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PCT/CN2021/123529
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English (en)
French (fr)
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邢国忠
王迪
刘龙
林淮
刘明
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中国科学院微电子研究所
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Priority to PCT/CN2021/123529 priority Critical patent/WO2023060475A1/zh
Priority to US18/251,699 priority patent/US20240013826A1/en
Publication of WO2023060475A1 publication Critical patent/WO2023060475A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1655—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1657—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/20—Spin-polarised current-controlled devices

Definitions

  • the disclosure belongs to the field of integrated circuits, and in particular relates to a spintronic device, a storage unit, a storage array and a read-write circuit.
  • the spin-orbit moment magnetic random access memory reverses the magnetization direction of the free layer through the vertical spin current induced by the current flowing through the heavy metal layer, and arranges them in parallel or antiparallel according to the magnetization directions of the free layer and the reference layer, respectively. A low-impedance and high-impedance state is achieved. At the same time, SOT-MRAM has the advantages of high speed and high durability, which provides the possibility for integrated storage and computing applications.
  • the main purpose of the present disclosure is to provide a spintronic device, a memory unit, a memory array and a read-write circuit without out-of-field flipping and high read-write margin.
  • the first aspect of the embodiments of the present disclosure provides a spintronic device, including:
  • each of the magnetic tunnel junctions includes a free layer, a tunneling layer, and a reference layer sequentially arranged from bottom to top, and each pair of magnetic tunnel junctions The magnetization directions of the reference layers of the two magnetic tunnel junctions are opposite;
  • a top electrode disposed on the reference layer of each magnetic tunnel junction.
  • the structure of each magnetic tunnel junction is a string structure.
  • each straight line side of the magnetic tunnel junction forms a preset angle with the axis of the spin-orbit coupling layer in the length direction.
  • the bottom electrode includes:
  • first end and the second end of the spin-orbit coupling layer are arranged opposite to each other.
  • the material of the spin-orbit coupling layer is a heavy metal material.
  • a second aspect of an embodiment of the present disclosure provides a storage unit, including:
  • the first transistor includes a first terminal, a second terminal and a third terminal, the first terminal of the first transistor is connected to one terminal of the bottom electrode, the second terminal of the first transistor is connected to the write word line, and the first transistor is connected to the writing word line.
  • the third end of a transistor is connected to the bit line, and the other end of the bottom electrode is connected to the source line;
  • the second transistor includes a first terminal, a second terminal and a third terminal, the first terminal of the second transistor is connected to a top electrode in the pair of magnetic tunnel junctions, and the second terminal of the second transistor is connected to reading the word line, the third terminal of the second transistor is connected to the bit line;
  • the third transistor includes a first terminal, a second terminal and a third terminal, the first terminal of the third transistor is connected to the other top electrode in the pair of magnetic tunnel junctions, the second terminal of the third transistor connected to the read word line, and the third terminal of the third transistor is connected to the inverted bit line.
  • the third aspect of the embodiments of the present disclosure provides a memory array, including: m write word lines, m read word lines, n source lines, and m rows and n columns of memory cells, the memory cells are the second embodiment of the present disclosure
  • m and n are both positive integers;
  • bit lines of each of the memory cells in the same column are connected to the same bit line, and the reverse bit lines of each of the memory cells in the same column are connected to the same reverse bit line;
  • the write word lines of each of the memory cells in the same row are connected to the same write word line, and the read word lines of each of the memory cells in the same column are connected to the same read word line.
  • the fourth aspect of the embodiments of the present disclosure provides a read-write circuit, including:
  • bit line decoder configured to provide bit line operating voltages to n said bit lines and n said inverse bit lines
  • a word line decoder configured to provide a word line operating voltage to the m write word lines and the m read word lines
  • a source line decoder configured to provide a bit line operating voltage and an induced current to the n source lines
  • the reading operation module is used to read the data stored in the storage array and perform logical operation on the data stored in the storage array.
  • the reading operation module includes:
  • the current-type sense amplifier includes an input end, a reference end and an output end, the input end of the current-type sense amplifier is connected to the bit line through the bit line decoder, and the reference end of the current-type sense amplifier is connected through the The bit line decoder is connected to the reverse bit line;
  • An adder comprising an input end and an output end, the input end of the adder is connected with the output end of the current-type sense amplifier;
  • a register connected to the output terminal of the adder.
  • the read-write circuit is used for a binarized neural network.
  • the spintronic device, memory unit, memory array, and read/write circuit provided by the present disclosure can, on the one hand, realize deterministic magnetization switching driven by a unipolar current pulse without an external magnetic field.
  • the magnetization directions of the reference layers of the two magnetic tunnel junctions of each pair of magnetic tunnel junctions are opposite, ensuring that the two magnetic tunnel junctions are always in the opposite resistance state, realizing self-referencing and improving the read margin.
  • the constructed memory array can realize matrix-vector multiplication operation in combination with external circuits.
  • FIG. 1 is a schematic structural diagram of a spintronic device provided by an embodiment of the present disclosure.
  • Fig. 2 is a top view of a spintronic device provided by an embodiment of the present disclosure.
  • FIG. 3 is a magnetization flip curve of a spintronic device provided by an embodiment of the present disclosure.
  • FIG. 4 is a synchronous flip curve of a unipolar pulse of a spintronic device provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a storage unit provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a storage array provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a read-write circuit provided by an embodiment of the present disclosure
  • FIG. 1 is a schematic structural diagram of a spintronic device provided by an embodiment of the present disclosure.
  • the spintronic device includes: bottom electrodes 101, 104, and a spin-orbit coupling layer 102 disposed on the bottom electrodes 101, 104.
  • At least one pair of magnetic tunnel junctions 103 is arranged on the spin-orbit coupling layer 102, and each magnetic tunnel junction 103 includes a free layer 1031, a tunneling layer 1032 and a reference layer 1033 arranged sequentially from bottom to top, and each pair of magnetic The magnetization direction of the reference layer 1033 of the tunnel junction 103 is opposite, and the top electrode 1034 is disposed on the reference layer 1033 of each magnetic tunnel junction 103 .
  • the materials of the reference layer 1033 and the free layer 1031 are one or more of ferromagnetic materials such as CoFeB and Co/Pt with perpendicular magnetic anisotropy.
  • the spin-orbit coupling layer 102 is composed of one or more of heavy metals such as Pt, Ta, and W.
  • the bottom electrodes 101, 104 and the top electrode 1034 are made of metals such as Ti/Au, Ti/Pt, Cr/Au, Ta/CuN and the like. More, the tunneling layer 1032 is made of MgO, Al 2 O 3 and so on.
  • FIG. 2 is a top view of a spintronic device provided by an embodiment of the present disclosure.
  • each magnetic tunnel junction 103 is a string structure.
  • the straight side of each magnetic tunnel junction 103 forms a preset angle with the axis of the spin-orbit coupling layer 102 in the length direction
  • the asymmetric shape of the magnetic tunnel junction 103 will induce a certain shape anisotropy, combined with the DM antisymmetric exchange effect, the field-free deterministic flipping of the magnetic tunnel junction 103 can be realized, and unipolar switching can be realized.
  • spin current in the vertical direction will be generated due to the spin Hall effect of the heavy metal or the Rashaba effect at the interface, so that the free layer 1031 of the magnetic tunnel junction 103 is turned over. Since the magnetization directions of the reference layers 1033 of the two magnetic tunnel junctions 103 are opposite, the two magnetic tunnel junctions 103 always store opposite resistance states.
  • the linear sides of the two magnetic tunnel junctions 103 in a pair of magnetic tunnel junctions form a preset angle with the axis of the spin-orbit coupling layer 102 in the longitudinal direction. They may be the same or complementary, which is not limited in the present disclosure.
  • FIG. 3 is a magnetization switching curve of a spintronic device provided by an embodiment of the present disclosure.
  • FIG. 4 is a synchronous flip curve of a spintronic device provided by an embodiment of the present disclosure.
  • the unipolar current pulse is easy to operate and simplifies the peripheral driving circuit.
  • FIG. 5 is a schematic diagram of a storage unit provided by an embodiment of the present disclosure.
  • the storage unit includes: a spintronic device 604 as shown in FIG. 1 ; a first transistor 601 including a first terminal, a second terminal and a third terminal, the first terminal of the first transistor is connected to the bottom electrode 101, and the first transistor The second terminal of 601 is connected to the write word line WWL, the third terminal of the first transistor 601 is connected to the bit line BL, and the bottom electrode 104 is connected to the source line SL; the second transistor 602 includes a first terminal, a second terminal and a third terminal, and The first end of the second transistor 602 is connected to a top electrode 1034 in a pair of magnetic tunnel junctions 103, the second end of the second transistor 102 is connected to the read word line RWL, and the third end of the second transistor 102 is connected to the bit line BL;
  • the transistor 603 includes a first terminal, a second terminal and a third terminal.
  • the first terminal of the third transistor 603 is connected to the other top electrode 1034 in the pair of magnetic tunnel junctions 103, and the second terminal of the third transistor 603 is connected to the read word line RWL, and the third terminal of the third transistor 603 is connected to the inverted bit line /BL.
  • 601 can be regarded as a write control transistor
  • 602 and 603 can be regarded as read control transistors
  • 604 is a spintronic device.
  • the write word line WWL is pulled low, so that the first transistor 601 is turned off, and the read word line RWL is pulled high, so that the second transistor 602 and the third transistor 603 are turned on, and the source line SL is grounded at the same time, so the current flows through The bit line BL and the reverse bit line /BL flow through a pair of magnetic tunnel junctions 103 .
  • the current on the bit line BL and the reverse bit line /BL flows into the current-type sense amplifier CSA to read the storage state of the spintronic device 604.
  • the write word line WWL is pulled high to turn on the first transistor 601 , the read word line RWL is pulled low, so that the second transistor 602 and the third transistor 603 are turned off, and the source line SL is grounded at the same time, the current between the bit line BL and the source line SL flows through the current path of the spin-orbit coupling layer 102, flipping
  • the magnetic tunnel junction 103 is in a resistive state to realize writing in the resistive state.
  • FIG. 6 is a schematic diagram of a memory array provided by an embodiment of the present disclosure.
  • the memory array includes: m write word lines, m read word lines, n source lines, and m rows and n columns of memory cells.
  • m and n are both positive integers; the bit lines of each storage unit located in the same column are connected to the same bit line, and the reverse bit lines of each storage unit located in the same column are connected to On the same reverse bit line; the write word lines of each memory cell in the same row are connected to the same write word line, and the read word lines of each memory cell in the same column are connected to the same read word line.
  • FIG. 7 is a schematic diagram of a read-write circuit provided by an embodiment of the present disclosure.
  • the read-write circuit includes:
  • bit line decoder configured to provide bit line operating voltages to n bit lines and n inverse bit lines
  • a word line decoder configured to provide a word line operating voltage to m write word lines and m read word lines;
  • a source line decoder configured to provide bit line operating voltages and induced currents to n source lines
  • the reading operation module is used for reading the data stored in the storage array and performing logic operation on the data stored in the storage array.
  • the high and low resistance states are respectively mapped to (+1, 0).
  • a multiplication result can be output and input to the adder and register; when the input of the current stage is low, no output, that is, the output is low.
  • the matrix-vector multiplication operation can be realized for the binary neural network.
  • the reading operation module includes: a current-type sense amplifier, an input end, a reference end and an output end, the input end of the current-type sense amplifier is connected to the bit line through a bit-line decoder, and the other part of the current-type sense amplifier
  • the reference end is connected to the anti-bit line through the bit line decoder
  • the adder includes an input end and an output end, and the input end of the adder is connected to the output end of the current-type sense amplifier
  • the register is connected to the output end of the adder .
  • the reference terminal of the current-mode sense amplifier is connected to the bit line through the bit-line decoder, and the input terminal of the current-mode sense amplifier is connected with the reverse bit line through the bit-line decoder. This disclosure does not limit this.
  • each functional module in each embodiment of the present disclosure may be integrated into one processing module, each module may exist separately physically, or two or more modules may be integrated into one module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules.
  • the integrated modules are realized in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the essence of the technical solution of the present invention or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of software products.

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Abstract

一种自旋电子器件、存储单元、存储阵列和读写电路，应用于集成技术领域，包括：底电极（101、104），自旋轨道耦合层（102），设置在所述底电极（101、104）上，至少一对磁性隧道结（103），设置在所述自旋轨道耦合层（102）上，每个所述磁性隧道结（103）包括由下而上依次设置的自由层（1031）、隧穿层（1032）和参考层（1033），每对所述磁性隧道结（103）的两个磁性隧道结的参考层（1033）磁化方向相反，顶电极（1034），设置在每个所述磁性隧道结（103）的参考层（1033）上。

Description

自旋电子器件、存储单元、存储阵列和读写电路 技术领域
本公开属于集成电路领域，具体涉及一种自旋电子器件、存储单元、存储阵列和读写电路。
背景技术
自旋轨道矩磁随机存储器(SOT-MRAM)通过电流流经重金属层所诱导的垂直方向的自旋流，翻转自由层的磁化方向，根据自由层和参考层磁化方向平行或反平行排列，分别实现低阻和高阻状态。同时，SOT-MRAM具有高速、高耐久性的优点，为存算一体应用提供了可能。然而，传统SOT-MRAM的翻转需要面内场辅助，不利于集成；并且磁性隧道结(MTJ)的隧穿磁电阻率(TMR)较低，一般只能达到100％-150％，这使得工艺波动会导致较大的误读概率。
发明内容
本公开的主要目的在于提供一种无场外翻转和高读写裕度的自旋电子器件、存储单元、存储阵列和读写电路。
为实现上述目的，本公开实施例第一方面提供一种自旋电子器件，包括：
底电极；
自旋轨道耦合层，设置在所述底电极上；
至少一对磁性隧道结，设置在所述自旋轨道耦合层上，每个所述磁性隧道结包括由下而上依次设置的自由层、隧穿层和参考层，每对所述磁性隧道结的两个磁性隧道结的参考层磁化方向相反；
顶电极，设置在每个所述磁性隧道结的参考层上。
在一实施例中，每个所述磁性隧道结的结构均为弦型结构。
在一实施例中，每个所述磁性隧道结的直线边与所述自旋轨道耦合层的长度方向的轴线形成预设夹角。
在一实施例中，所述底电极包括：
第一电极，与所述自旋轨道耦合层的第一端连接；
第二电极，与所述自旋轨道耦合层的第二端连接；
其中，所述自旋轨道耦合层的第一端和第二端相对设置。
在一实施例中，所述自旋轨道耦合层的材料为重金属材料。
本公开实施例第二方面提供一种存储单元，包括：
如第一方面所述的自旋电子器件；
第一晶体管，包括第一端、第二端和第三端，所述第一晶体管的第一端连接所述底电极的一端，所述第一晶体管的第二端连接写字线，所述第一晶体管的第三端连接位线，所述底电极的另一端连接源线；
第二晶体管，包括第一端、第二端和第三端，所述第二晶体管的第一端连接所述一对磁性隧道结中的一个顶电极，所述第二晶体管的第二端连接读字线，所述第二晶体管的第三端连接位线；
第三晶体管，包括第一端、第二端和第三端，所述第三晶体管的第一端连接所述一对磁性隧道结中的另一个顶电极，所述第三晶体管的第二端连接读字线，所述第三晶体管的第三端连接反位线。
本公开实施例第三方面提供了一种存储阵列，包括：m条写字线、m条读字线、n条源线和m行n列存储单元，所述存储单元为本公开实施例第二方面所述的存储单元，m和n均为正整数；
位于同一列的每个所述存储单元的位线连接在同一位线上，位于同一列的每个所述存储单元的反位线连接在同一反位线上；
位于同一行的每个所述存储单元的写字线连接在同一写字线上，位于同一列的每个所述存储单元的读字线连接在同一读字线上。
本公开实施例第四方面提供了一种读写电路，包括：
如本公开实施例第三方面所述的存储阵列；
位线译码器，用于向n条所述位线和n条所述反位线提供位线操作电压；
字线译码器，用于向m条所述写字线和m条所述读字线提供字线操作电压；
源线译码器，用于向n条所述源线提供位线操作电压和感应电流；
读取运算模块，用于读取所述存储阵列存储的数据，并对所述存储阵列存储的数据进行逻辑运算。
在一实施例中，所述读取运算模块包括：
电流型灵敏放大器，包括输入端、参考端和输出端，所述电流型灵敏放大器的输入端通过所述位线译码器与所述位线连接，所述电流型灵敏放大器的参考端通过所述位线译码器与所述反位线连接；
加法器，包括一个输入端和一个输出端，所述加法器的输入端与所述电流型灵敏放大器的输出端连接；
寄存器，与所述加法器的输出端连接。
在一实施例中，所述读写电路用于二值化神经网络。
从上述本公开实施例可知，本公开提供的自旋电子器件、存储单元、存储阵列和读写电路，一方面，可以实现单极性电流脉冲驱动无外磁场确定性磁化翻转。另一方面，每对磁性隧道结的两个磁性隧道结的参考层磁化方向相反，保证两磁性隧道结始终处于相反阻态，实现自参考，提升读取裕度。又一方面，构建的存储阵列结合外部电路，可以实现矩阵-向量乘法运算。
附图说明
图1为本公开一实施例提供的自旋电子器件的结构示意图。
图2为本公开一实施例提供的自旋电子器件的俯视图。
图3为本公开一实施例提供的自旋电子器件的磁化翻转曲线。
图4为本公开一实施例提供的自旋电子器件的单极性脉冲同步翻转曲线。
图5为本公开一实施例提供的存储单元的示意图。
图6为本公开一实施例提供的存储阵列的示意图。
图7为本公开一实施例提供的读写电路的示意图
具体实施方式
为使得本公开的公开目的、特征、优点能够更加的明显和易懂，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而非全部实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
请参阅图1，图1为本公开一实施例提供的自旋电子器件的结构示意图，该自旋电子器件包括：底电极101、104，自旋轨道耦合层102，设置在底电极101、104上，至少一对磁性隧道结103，设置在自旋轨道耦合层102上，每个磁性隧道结103包括由下而上依次设置的自由层1031、隧穿层1032和参考层1033，每对磁性隧道结103的参考层1033磁化方向相反，顶电极1034，设置在每个磁性隧道结103的参考层1033上。
在本公开一实施例中，参考层1033和自由层1031的材料为由具有垂直磁各向异性的CoFeB、Co/Pt等铁磁材料的一种或多种。自旋轨道耦合层102由Pt、Ta、W等重金属的一种或多种构成。底电极101、104和顶电极1034由Ti/Au、Ti/Pt、Cr/Au、Ta/CuN等金属构成。更多的，隧穿层1032由MgO、Al 2O 3等构成。
请参阅图2，图2为本公开一实施例提供的自旋电子器件的俯视图。
在本公开一实施例中，每个磁性隧道结103的结构均为弦型结构。 每个磁性隧道结103的直线边与自旋轨道耦合层102的长度方向的轴线形成预设夹角
Figure PCTCN2021123529-appb-000001
磁性隧道结103采用这种不对称的形状会诱导一定的形状各向异性，结合DM反对称交换作用，可以实现磁性隧道结103的无场确定性翻转，并且可以实现单极性切换。当电流流经自旋轨道耦合层102时，由于重金属的自旋霍尔效应或界面的Rashaba效应会产生垂直方向的自旋流，使磁性隧道结103的自由层1031翻转。由于两个磁性隧道结103的参考层1033的磁化方向相反，两个磁性隧道结103始终存储相反的阻态。
在本公开中，一对磁性隧道结中的两个磁性隧道结103的直线边与自旋轨道耦合层102的长度方向的轴线形成预设夹角
Figure PCTCN2021123529-appb-000002
可以相同或者互补，本公开对此不做限制。
请参阅图3，图3为本公开一实施例提供的自旋电子器件的磁化翻转曲线。设置一对磁性隧道结103的预设夹角
Figure PCTCN2021123529-appb-000003
依次为45°、60°和90°，沿x轴方向施加脉宽为0.5ns，密度为2×10 8A/cm 2的电流脉冲，实现了一对磁性隧道结103同步的无场确定性翻转。
请参阅图4，图4为本公开一实施例提供的自旋电子器件的单极性脉冲同步翻转曲线。设置一对磁性隧道结103的预设夹角
Figure PCTCN2021123529-appb-000004
为45°，沿x轴方向连续施加4个脉宽为0.5ns，密度为2×10 8A/cm 2的单极性电流脉冲，实现了两个磁性隧道结103同步的反复翻转。单极性电流脉冲易于操作，简化外围驱动电路。
请参阅图5，图5为本公开一实施例提供的存储单元的示意图。该存储单元包括：如图1所示的自旋电子器件604；第一晶体管601，包括第一端、第二端和第三端，第一晶体管的第一端连接底电极101，第一晶体管601的第二端连接写字线WWL，第一晶体管601的第三端连 接位线BL，底电极104连接源线SL；第二晶体管602，包括第一端、第二端和第三端，第二晶体管602的第一端连接一对磁性隧道结103中的一个顶电极1034，第二晶体管102的第二端连接读字线RWL，第二晶体管102的第三端连接位线BL；第三晶体管603，包括第一端、第二端和第三端，第三晶体管603的第一端连接一对磁性隧道结103中的另一个顶电极1034，第三晶体管603的第二端连接读字线RWL，第三晶体管603的第三端连接反位线/BL。
在本实施例中，601可视作写控制晶体管，602和603可视作读控制晶体管，604为自旋电子器件。当执行读取操作时，写字线WWL拉低，使第一晶体管601关断，读字线RWL拉高，使第二晶体管602和第三晶体管603导通，同时源线SL接地，于是电流经位线BL和反位线/BL流经一对磁性隧道结103。位线BL和反位线/BL上的电流流入电流型灵敏放大器CSA中，读出自旋电子器件604存储状态，当执行写入操作时，写字线WWL拉高，使第一晶体管601导通，读字线RWL拉低，使第二晶体管602和第三晶体管603关断，同时源线SL接地，位线BL和源线SL间的电流流经自旋轨道耦合层102的电流通路，翻转磁性隧道结103阻态，实现阻态的写入。
请参阅图6，图6为本公开一实施例提供的存储阵列的示意图，该存储阵列包括：m条写字线、m条读字线、n条源线和m行n列存储单元，存储单元为如图5所示的存储单元，m和n均为正整数；位于同一列的每个存储单元的位线连接在同一位线上，位于同一列的每个存储单元的反位线连接在同一反位线上；位于同一行的每个存储单元的写字线连接在同一写字线上，位于同一列的每个存储单元的读字线连接在同一读字线上。
请参阅图7，图7为本公开一实施例提供的读写电路的示意图，该读写电路包括：
如图6所示的存储阵列；
位线译码器，用于向n条位线和n条反位线提供位线操作电压；
字线译码器，用于向m条写字线和m条读字线提供字线操作电压；
源线译码器，用于向n条源线提供位线操作电压和感应电流；
读取运算模块，用于读取存储阵列存储的数据，并对存储阵列存储的数据进行逻辑运算。
在本实施例中，在算法层面，将高低阻态分别映射成(+1，0)。当前级输入为高电平时，根据位线BL和反位线/BL上电流的差异，可以输出一个乘法运算结果，并输入到加法器和寄存器中；当前级输入为低电平时，不会产生输出，即输出为低电平。经过一系列的乘加运算，可以实现矩阵-向量乘法运算，用于二值化神经网络。
在一实施例中，读取运算模块包括：电流型灵敏放大器，输入端、参考端和输出端，电流型灵敏放大器的输入端通过位线译码器与位线连接，电流型灵敏放大器的另参考端通过位线译码器与反位线连接；加法器，包括一个输入端和一个输出端，加法器的输入端与电流型灵敏放大器的输出端连接；寄存器，与加法器的输出端连接。
更多的，还可以是电流型灵敏放大器的参考端通过位线译码器与位线连接，电流型灵敏放大器的输入端通过位线译码器与反位线连接。本公开对此不做限制。
需要说明的是，在本公开各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现， 也可以采用软件功能模块的形式实现。
所述集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来。
需要说明的是，对于前述的各方法实施例，为了简便描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本发明并不受所描述的动作顺序的限制，因为依据本发明，某些步骤可以采用其它顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定都是本发明所必须的。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其它实施例的相关描述。
以上为对本发明所提供的一种自旋电子器件、存储单元、存储阵列和读写电路的描述，对于本领域的技术人员，依据本发明实施例的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本发明的限制。

Claims (10)

  1. 一种自旋电子器件，其特征在于，包括：
    底电极；
    自旋轨道耦合层，设置在所述底电极上；
    至少一对磁性隧道结，设置在所述自旋轨道耦合层上，每个所述磁性隧道结包括由下而上依次设置的自由层、隧穿层和参考层，每对所述磁性隧道结的两个磁性隧道结的参考层磁化方向相反；
    顶电极，设置在每个所述磁性隧道结的参考层上。
  2. 根据权利要求1所述的自旋电子器件，其特征在于，每个所述磁性隧道结的结构均为弦型结构。
  3. 根据权利要求2所述的自旋电子器件，其特征在于，每个所述磁性隧道结的直线边与所述自旋轨道耦合层的长度方向的轴线形成预设夹角。
  4. 根据权利要求1至3任意一项所述的自旋电子器件，其特征在于，所述底电极包括：
    第一电极，与所述自旋轨道耦合层的第一端连接；
    第二电极，与所述自旋轨道耦合层的第二端连接；
    其中，所述自旋轨道耦合层的第一端和第二端相对设置。
  5. 根据权利要求1至3任意一项所述的自旋电子器件，其特征在于，所述自旋轨道耦合层的材料为重金属材料。
  6. 一种存储单元，其特征在于，包括：
    如权利要求1至5任意一项所述的自旋电子器件；
    第一晶体管，包括第一端、第二端和第三端，所述第一晶体管的第 一端连接所述底电极，所述第一晶体管的第二端连接写字线，所述第一晶体管的第三端连接位线，所述底电极连接源线；
    第二晶体管，包括第一端、第二端和第三端，所述第二晶体管的第一端连接所述一对磁性隧道结中的一个顶电极，所述第二晶体管的第二端连接读字线，所述第二晶体管的第三端连接位线；
    第三晶体管，包括第一端、第二端和第三端，所述第三晶体管的第一端连接所述一对磁性隧道结中的另一个顶电极，所述第三晶体管的第二端连接读字线，所述第三晶体管的第三端连接反位线。
  7. 一种存储阵列，其特征在于，包括：m条写字线、m条读字线、n条源线和m行n列存储单元，所述存储单元为如权利要求6所述的存储单元，m和n均为正整数；
    位于同一列的每个所述存储单元的位线连接在同一位线上，位于同一列的每个所述存储单元的反位线连接在同一反位线上；
    位于同一行的每个所述存储单元的写字线连接在同一写字线上，位于同一列的每个所述存储单元的读字线连接在同一读字线上。
  8. 一种读写电路，其特征在于，包括：
    如权利要求7所述的存储阵列；
    位线译码器，用于向n条所述位线和n条所述反位线提供位线操作电压；
    字线译码器，用于向m条所述写字线和m条所述读字线提供字线操作电压；
    源线译码器，用于向n条所述源线提供位线操作电压和感应电流；
    读取运算模块，用于读取所述存储阵列存储的数据，并对所述存储阵列存储的数据进行逻辑运算。
  9. 根据权利要求8所述的读写电路，其特征在于，所述读取运算模块包括：
    电流型灵敏放大器，包括输入端、参考端和输出端，所述电流型灵敏放大器的输入端通过所述位线译码器与所述位线连接，所述电流型灵敏放大器的参考端通过所述位线译码器与所述反位线连接；
    加法器，包括一个输入端和一个输出端，所述加法器的输入端与所述电流型灵敏放大器的输出端连接；
    寄存器，与所述加法器的输出端连接。
  10. 根据权利要求8或9所述的读写电路，其特征在于，所述读写电路用于二值化神经网络。
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