WO2017092142A1 - 低温多晶硅tft基板的制作方法 - Google Patents

低温多晶硅tft基板的制作方法 Download PDF

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WO2017092142A1
WO2017092142A1 PCT/CN2015/099985 CN2015099985W WO2017092142A1 WO 2017092142 A1 WO2017092142 A1 WO 2017092142A1 CN 2015099985 W CN2015099985 W CN 2015099985W WO 2017092142 A1 WO2017092142 A1 WO 2017092142A1
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layer
gate
insulating layer
gate insulating
depositing
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French (fr)
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李松杉
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a low temperature polysilicon TFT substrate.
  • Liquid Crystal Display has many advantages such as thin body, power saving, no radiation, etc., and has been widely used, such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptop screens. Wait.
  • PDAs personal digital assistants
  • LCD Liquid Crystal Display
  • liquid crystal display devices which include a casing, a liquid crystal panel disposed in the casing, and a backlight module disposed in the casing.
  • the structure of the conventional liquid crystal panel is composed of a color filter substrate, a thin film transistor array substrate (TFT Array Substrate), and a liquid crystal layer (Liquid Crystal Layer) disposed between the two substrates.
  • TFT Array Substrate thin film transistor array substrate
  • Liquid Crystal Layer Liquid Crystal Layer
  • LTPS Low Temperature Poly-silicon
  • a-Si amorphous silicon
  • FIG. 1 is a cross-sectional structural diagram of a conventional low-temperature polysilicon TFT substrate.
  • the manufacturing method mainly includes the following steps: firstly depositing a buffer layer 200, an amorphous silicon (a-Si) layer, and an amorphous layer on the substrate 100.
  • the silicon layer is transformed into polysilicon (Poly-Si) by excimer laser annealing (ELA), then the polysilicon layer 300 is obtained by a yellow/etching process, and the mask is used twice on the polysilicon layer 300.
  • ELA excimer laser annealing
  • the polysilicon layer 300 is ion implanted by a yellow photoresist to obtain an N-type heavily doped (N+) region and an N-type lightly doped (N-) region, resulting in a lightly doped drain region (LDD);
  • the yellow light and the etching process obtain the gate insulating layer 400, the gate electrode 500, the interlayer insulating layer 600, and the source/drain electrodes 700, thereby finally obtaining a low-temperature polysilicon TFT substrate having the structure shown in FIG.
  • the method for fabricating the low-temperature polysilicon TFT substrate has certain disadvantages, that is, after the N-type heavily doped region and the N-type lightly doped region of the low-temperature polysilicon TFT substrate are defined, two ion implantations are required, and the manufacturing process is complicated and the manufacturing cost is low. high. Therefore, it is necessary to provide a method for fabricating a low-temperature polysilicon TFT substrate to solve the above problems.
  • the object of the present invention is to provide a method for fabricating a low-temperature polysilicon TFT substrate, which can reduce the primary ion implantation process, simplify the process flow, and reduce the production cost.
  • the present invention provides a method for fabricating a low temperature polysilicon TFT substrate, comprising the following steps:
  • Step 1 providing a substrate, depositing a buffer layer on the substrate;
  • Step 2 depositing an amorphous silicon layer on the buffer layer, dehydrogenating the amorphous silicon layer, converting it into a polysilicon layer by a crystallization process, and patterning the polysilicon layer to obtain island polysilicon Floor;
  • Step 3 coating a photoresist on the island-shaped polysilicon layer, exposing and developing the photoresist to form a photoresist layer; using the photoresist layer as a shielding layer, facing the island polysilicon layer Performing ion implantation to form an N-type heavily doped region on both sides of the island-shaped polysilicon layer and an undoped region between the two N-type heavily doped regions, and then peeling off the photoresist layer;
  • Step 4 depositing a first gate insulating layer on the island-shaped polysilicon layer, depositing a first metal layer on the first gate insulating layer, and patterning the first metal layer to obtain a corresponding a first gate above the undoped region, and a width of the first gate is smaller than a width of the undoped region;
  • Step 5 depositing a second gate insulating layer on the first gate insulating layer, the first gate, depositing a second metal layer on the second gate insulating layer, and bonding the second metal layer Performing a patterning process to obtain a second gate corresponding to the first gate, a width of the second gate is equal to a width of the undoped region, and both ends of the second gate are exceeded a distance between the two ends of the first gate, such that a region covered by the first gate and the second gate on the undoped region forms a channel region having a strong electric field, The regions on both sides of the undoped region that are only covered by the second gate form a low electric field region;
  • Step 6 depositing an interlayer insulating layer on the second gate insulating layer and the second gate; and forming the interlayer insulating layer, the first gate insulating layer, and the second gate insulating layer by a yellow light process Forming a via hole above the N-type heavily doped region on both sides of the island-shaped polysilicon layer;
  • Step 7 depositing a third metal layer on the interlayer insulating layer, patterning the third metal layer to obtain a source/drain, the source/drain via the via and the island
  • the N-type heavily doped regions on both sides of the polycrystalline silicon layer are in contact.
  • the substrate is a glass substrate;
  • the buffer layer is a composite layer of a silicon nitride layer and a silicon oxide layer;
  • the thickness of the silicon nitride layer is 40-100 nm;
  • the thickness of the silicon oxide layer It is 100 to 200 nm.
  • the amorphous silicon layer has a thickness of 40 to 60 nm; and the crystallization process is an excimer laser annealing treatment or a solid phase crystallization process.
  • the material of the first gate insulating layer and the second gate insulating layer is silicon nitride or silicon oxide; the material of the first gate and the second gate is molybdenum; and the interlayer insulating layer is nitrided a silicon layer, a silicon oxide layer, or a combination of both; the source/drain is a molybdenum/aluminum/molybdenum composite layer.
  • the distance between the two ends of the second gate exceeding the both ends of the first gate is 1 to 2 ⁇ m.
  • the present invention also provides another method for fabricating a low temperature polysilicon TFT substrate, comprising the following steps
  • Step 1 providing a substrate, depositing a buffer layer on the substrate;
  • Step 2 depositing a first metal layer on the buffer layer, and patterning the first metal layer to obtain a first gate; depositing a first gate insulating layer on the first gate;
  • Step 3 depositing an amorphous silicon layer on the first gate insulating layer, performing dehydrogenation treatment on the amorphous silicon layer, converting it into a polysilicon layer through a crystallization process, and patterning the polysilicon layer. Obtaining an island-shaped polysilicon layer corresponding to the first gate;
  • Step 4 applying a photoresist on the island-shaped polysilicon layer, exposing and developing the photoresist to form a photoresist layer; using the photoresist layer as a shielding layer, facing the island polysilicon layer Performing ion implantation to form an N-type heavily doped region on both sides of the island-shaped polysilicon layer and an undoped region between the two N-type heavily doped regions, and then peeling off the photoresist layer, wherein The width of the undoped region is greater than the width of the first gate;
  • Step 5 depositing a second gate insulating layer on the island-shaped polysilicon layer, depositing a second metal layer on the second gate insulating layer, and patterning the second metal layer to obtain a corresponding a second gate above the undoped region; wherein a thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer, and a width of the second gate is equal to the undoped region a width, and both ends of the second gate are beyond a distance of the two ends of the first gate, so that the first gate and the second gate are doubled on the undoped region
  • the covered region forms a channel region having a strong electric field, and a region covered by only the second gate on both sides of the undoped region forms a low electric field region;
  • Step 6 depositing an interlayer insulating layer on the second gate insulating layer and the second gate, corresponding to the island polysilicon on the interlayer insulating layer and the second gate insulating layer by a yellow light process Via holes are formed above the N-type heavily doped regions on both sides of the layer;
  • Step 7 depositing a third metal layer on the interlayer insulating layer, patterning the third metal layer to obtain a source/drain, the source/drain via the via and the island
  • the N-type heavily doped regions on both sides of the polycrystalline silicon layer are in contact.
  • the substrate is a glass substrate;
  • the buffer layer is a composite layer of a silicon nitride layer and a silicon oxide layer;
  • the thickness of the silicon nitride layer is 40-100 nm; the thickness of the silicon oxide layer For 100 to 200 nm.
  • the amorphous silicon layer has a thickness of 40 to 60 nm; and the crystallization process is an excimer laser annealing treatment or a solid phase crystallization process.
  • the material of the first gate insulating layer and the second gate insulating layer is silicon nitride or silicon oxide; the material of the first gate and the second gate is molybdenum; and the interlayer insulating layer is nitrided a silicon layer, a silicon oxide layer, or a combination of both; the source/drain is a molybdenum/aluminum/molybdenum composite layer.
  • the thickness of the second gate insulating layer is greater than the thickness of the first gate insulating layer
  • the distance between both ends of the second gate exceeding the both ends of the first gate is 1 to 2 ⁇ m.
  • the invention also provides a method for manufacturing a low temperature polysilicon TFT substrate, comprising the following steps:
  • Step 1 providing a substrate, depositing a buffer layer on the substrate;
  • Step 2 depositing a first metal layer on the buffer layer, and patterning the first metal layer to obtain a first gate; depositing a first gate insulating layer on the first gate;
  • Step 3 depositing an amorphous silicon layer on the first gate insulating layer, performing dehydrogenation treatment on the amorphous silicon layer, converting it into a polysilicon layer through a crystallization process, and patterning the polysilicon layer. Obtaining an island-shaped polysilicon layer corresponding to the first gate;
  • Step 4 applying a photoresist on the island-shaped polysilicon layer, exposing and developing the photoresist to form a photoresist layer; using the photoresist layer as a shielding layer, facing the island polysilicon layer Performing ion implantation to form an N-type heavily doped region on both sides of the island-shaped polysilicon layer and an undoped region between the two N-type heavily doped regions, and then peeling off the photoresist layer, wherein The width of the undoped region is greater than the width of the first gate;
  • Step 5 depositing a second gate insulating layer on the island-shaped polysilicon layer, depositing a second metal layer on the second gate insulating layer, and patterning the second metal layer to obtain a corresponding a second gate above the undoped region; wherein a thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer, and a width of the second gate is equal to the undoped region a width, and both ends of the second gate are beyond a distance of the two ends of the first gate, so that the first gate and the second gate are doubled on the undoped region
  • the covered region forms a channel region having a strong electric field, and a region covered by only the second gate on both sides of the undoped region forms a low electric field region;
  • Step 6 depositing an interlayer insulating layer on the second gate insulating layer and the second gate, corresponding to the island polysilicon on the interlayer insulating layer and the second gate insulating layer by a yellow light process Via holes are formed above the N-type heavily doped regions on both sides of the layer;
  • Step 7 depositing a third metal layer on the interlayer insulating layer, patterning the third metal layer to obtain a source/drain, the source/drain via the via and the island N-type heavily doped regions on both sides of the polycrystalline silicon layer are in contact;
  • the substrate is a glass substrate;
  • the buffer layer is a composite layer of a silicon nitride layer and a silicon oxide layer;
  • the thickness of the silicon nitride layer is 40-100 nm; The thickness is 100 to 200 nm;
  • the amorphous silicon layer has a thickness of 40 to 60 nm; and the crystallization process is an excimer laser annealing treatment or a solid phase crystallization process;
  • the material of the first gate insulating layer and the second gate insulating layer is silicon nitride or silicon oxide; the material of the first gate and the second gate is molybdenum; and the interlayer insulating layer is a silicon nitride layer, a silicon oxide layer, or a combination of the two; the source/drain is a molybdenum/aluminum/molybdenum composite layer;
  • the thickness of the second gate insulating layer is greater than the thickness of the first gate insulating layer
  • the distance between both ends of the second gate exceeding the both ends of the first gate is 1 to 2 ⁇ m.
  • the method for fabricating a low-temperature polysilicon TFT substrate of the present invention after forming an N-type heavily doped region on both sides of the polysilicon layer, sequentially forming a first gate insulating layer, a first gate, and a first layer on the polysilicon layer a second gate insulating layer, a second gate, and a width of the second gate is greater than a width of the first gate to form a low electric field region in the polysilicon layer, thereby reducing leakage current; or Forming a first gate, a first gate insulating layer on the buffer layer, and forming a polysilicon layer on the first gate insulating layer and an N-type heavily doped region on both sides of the polysilicon layer, and then forming a second on the polysilicon layer a gate insulating layer, a second gate, and a thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer, and a width of the second gate is greater
  • FIG. 1 is a schematic cross-sectional structural view of a conventional low temperature polysilicon TFT substrate
  • FIG. 2 is a first step to a step of a method for fabricating a low temperature polysilicon TFT substrate according to the present invention; Schematic diagram of 2;
  • step 3 is a schematic diagram of step 3 of a method for fabricating a low temperature polysilicon TFT substrate according to the present invention
  • FIG. 4 is a schematic view showing steps 4 to 5 of a method for fabricating a low-temperature polysilicon TFT substrate according to the present invention
  • step 6 is a schematic diagram of step 6 of a method for fabricating a low temperature polysilicon TFT substrate according to the present invention
  • step 7 is a schematic diagram of step 7 of a method for fabricating a low temperature polysilicon TFT substrate according to the present invention
  • FIG. 7 is a schematic view showing steps 1 to 2 of another method for fabricating a low-temperature polysilicon TFT substrate according to the present invention.
  • step 3 is a schematic diagram of step 3 of another method for fabricating a low temperature polysilicon TFT substrate according to the present invention.
  • step 4 is a schematic diagram of step 4 of another method for fabricating a low temperature polysilicon TFT substrate according to the present invention.
  • FIG. 10 is a schematic view showing steps 5 to 7 of another method for fabricating a low temperature polysilicon TFT substrate according to the present invention.
  • the present invention first provides a method for fabricating a low temperature polysilicon TFT substrate, comprising the following steps:
  • Step 1 As shown in FIG. 2, a substrate 1 is provided, on which a buffer layer 2 is deposited.
  • the substrate 1 is a glass substrate;
  • the buffer layer 2 is a composite layer of a silicon nitride (SiNx) layer 21 and a silicon oxide (SiOx) layer 22.
  • the silicon nitride layer 21 has a thickness of 40 to 100 nm; and the silicon oxide layer 22 has a thickness of 100 to 200 nm.
  • Step 2 As shown in FIG. 2, an amorphous silicon layer is deposited on the buffer layer 2, and the amorphous silicon layer is subjected to dehydrogenation treatment, and then converted into a polysilicon layer by a crystallization process to pattern the polysilicon layer.
  • the island layer polysilicon layer 3 is obtained by a chemical treatment.
  • the amorphous silicon layer has a thickness of 40 to 60 nm.
  • the crystallization process may be an excimer laser annealing process or a solid phase crystallization (SPC) process.
  • SPC solid phase crystallization
  • Step 3 as shown in FIG. 3, a photoresist is coated on the island-shaped polysilicon layer 3, and the photoresist is exposed and developed to form a photoresist layer 30; and the photoresist layer 30 is used as a shielding layer. Ion implantation on both sides of the island-shaped polysilicon layer 3 to form an N-type heavily doped region 31 on both sides of the island-shaped polysilicon layer 3 and an undoped layer between the two N-type heavily doped regions 31 The impurity region 32 is then stripped of the photoresist layer 30.
  • the ions implanted on both sides of the island-shaped polysilicon layer 3 are phosphorus (P) ions.
  • Step 4 as shown in FIG. 4, depositing a first gate insulating layer 41 on the island-shaped polysilicon layer 3, depositing a first metal layer on the first gate insulating layer 41, and depositing the first The metal layer is patterned to obtain a first gate 51 corresponding to the undoped region 32, and the width of the first gate 51 is smaller than the width of the undoped region 32.
  • Step 5 as shown in FIG. 4, a second gate insulating layer 42 is deposited on the first gate insulating layer 41 and the first gate 51, and a second metal is deposited on the second gate insulating layer 42. a layer, and patterning the second metal layer to obtain a second gate 52 corresponding to the first gate 51, the width of the second gate 52 being equal to the undoped region 32 a width, and both ends of the second gate 52 extend beyond the two ends of the first gate 51 to be the first gate 51 and the second gate on the undoped region 32.
  • the region where the pole 52 is double-covered forms a channel region 321 having a strong electric field, and a region covered only by the second gate 52 on both sides of the undoped region 32 forms a low electric field region 322.
  • the low electric field region 322 between the channel region 321 and the N-type heavily doped region 31 on both sides can replace the lightly doped drain region (LDD) in the conventional TFT substrate to reduce leakage.
  • LDD lightly doped drain region
  • the material of the first gate insulating layer 41 and the second gate insulating layer 42 is silicon nitride or silicon oxide; the material of the first gate 51 and the second gate 52 is molybdenum (Mo) .
  • the distance between both ends of the second gate 52 beyond the both ends of the first gate 51 is 1 to 2 ⁇ m.
  • Step 6 as shown in FIG. 5, an interlayer insulating layer 6 is deposited on the second gate insulating layer 42 and the second gate electrode 52; the interlayer insulating layer 6 and the first gate are processed by a yellow light process.
  • a via 61 is formed on the insulating layer 41 and the second gate insulating layer 42 above the N-type heavily doped region 31 on both sides of the island-shaped polysilicon layer 3.
  • the interlayer insulating layer 6 is a silicon nitride layer, a silicon oxide layer, or a combination of the two.
  • Step 7 as shown in FIG. 6, depositing a third metal layer on the interlayer insulating layer 6, and patterning the third metal layer to obtain a source/drain 7, the source/drain 7 Via the via 61 is in contact with the N-type heavily doped region 31 on both sides of the island-shaped polysilicon layer 3.
  • the source/drain electrodes 7 are a molybdenum/aluminum/molybdenum composite layer, that is, a composite layer composed of an aluminum layer interposed between the two molybdenum layers.
  • the method for fabricating the low-temperature polysilicon TFT substrate after forming an N-type heavily doped region on both sides of the polysilicon layer, sequentially forming a first gate insulating layer, a first gate electrode, a second gate insulating layer, and a second layer on the polysilicon layer a gate, and a width of the second gate is larger than a width of the first gate to form a low electric field region in the polysilicon layer, thereby reducing the leakage current; simplifying the process flow and reducing the production cost.
  • the present invention further provides another method for fabricating a low temperature polysilicon TFT substrate, comprising the following steps:
  • Step 1 As shown in FIG. 7, a substrate 1 is provided on which a buffer layer 2 is deposited.
  • the substrate 1 is a glass substrate;
  • the buffer layer 2 is a composite layer of the silicon nitride layer 21 and the silicon oxide layer 22.
  • the silicon nitride layer 21 has a thickness of 40 to 100 nm; and the silicon oxide layer 22 has a thickness of 100 to 200 nm.
  • Step 2 depositing a first metal layer on the buffer layer 2, and patterning the first metal layer to obtain a first gate 51; at the first gate 51 A first gate insulating layer 41 is deposited thereon.
  • Step 3 depositing an amorphous silicon layer on the first gate insulating layer 41, dehydrogenating the amorphous silicon layer, and converting it into a polysilicon layer by a crystallization process.
  • the polysilicon layer is patterned to obtain an island-shaped polysilicon layer 3 corresponding to the first gate 51.
  • the amorphous silicon layer has a thickness of 40 to 60 nm.
  • the crystallization process may be an excimer laser annealing process or a solid phase crystallization process.
  • Step 4 as shown in FIG. 9, coating a photoresist on the island-shaped polysilicon layer 3, exposing and developing the photoresist to form a photoresist layer 30; using the photoresist layer 30 as a shielding layer, Ion implantation on both sides of the island-shaped polysilicon layer 3 to form an N-type heavily doped region 31 on both sides of the island-shaped polysilicon layer 3 and an undoped layer between the two N-type heavily doped regions 31 The impurity region 32 is then stripped, wherein the width of the undoped region 32 is greater than the width of the first gate 51.
  • ions implanted on both sides of the island-shaped polysilicon layer 3 are phosphorus (P) ions.
  • Step 5 depositing a second gate insulating layer on the island polysilicon layer 3 And depositing a second metal layer on the second gate insulating layer 42 and patterning the second metal layer to obtain a second gate 52 corresponding to the undoped region 32;
  • the thickness of the second gate insulating layer 42 is greater than the thickness of the first gate insulating layer 41, the width of the second gate 52 is equal to the width of the undoped region 32, and the second gate Both ends of the 52 are beyond the two ends of the first gate 51 to form a region on the undoped region 32 that is double covered by the first gate 51 and the second gate 52.
  • the channel region 321 of the strong electric field forms a low electric field region 322 in a region covered only by the second gate 52 on both sides of the undoped region 32.
  • the low electric field region 322 can replace the light formed by the ion implantation process in the conventional TFT substrate.
  • the doped drain region (LDD) acts to reduce leakage current and reduces the number of ion implantation processes, thereby optimizing the process flow and saving manufacturing costs.
  • the material of the first gate insulating layer 41 and the second gate insulating layer 42 is silicon nitride or silicon oxide; the material of the first gate 51 and the second gate 52 is molybdenum.
  • the thickness of the second gate insulating layer 42 is larger than the thickness of the first gate insulating layer 41.
  • the distance between both ends of the second gate 52 beyond the both ends of the first gate 51 is 1 to 2 ⁇ m.
  • Step 6 as shown in FIG. 10, an interlayer insulating layer 6 is deposited on the second gate insulating layer 42 and the second gate electrode 52, and the interlayer insulating layer 6 and the second gate are processed by a yellow light process.
  • a via 61 is formed on the pole insulating layer 42 above the N-type heavily doped region 31 on both sides of the island-shaped polysilicon layer 3.
  • the interlayer insulating layer 6 is a silicon nitride layer, a silicon oxide layer, or a combination of the two.
  • Step 7 as shown in FIG. 10, depositing a third metal layer on the interlayer insulating layer 6, and patterning the third metal layer to obtain a source/drain 7, the source/drain 7
  • the N-type heavily doped region 31 on both sides of the island-shaped polysilicon layer 3 is in contact via the via 61.
  • the source/drain electrodes 7 are a molybdenum/aluminum/molybdenum composite layer, that is, a composite layer composed of an aluminum layer interposed between the two molybdenum layers.
  • the method for fabricating the low-temperature polysilicon TFT substrate comprises first forming a first gate electrode and a first gate insulating layer on the buffer layer, and forming a polysilicon layer on the first gate insulating layer and an N-type heavily doped on both sides of the polysilicon layer.
  • a second gate insulating layer and a second gate are formed on the polysilicon layer, and a thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer, and a width of the second gate is greater than the first gate
  • the width of the pole is such that the portion of the second gate beyond the first gate and the second gate insulating layer of the polysilicon layer are thicker, the generated electric field is smaller, and induced in the polysilicon layer The electrons are less, which reduces the leakage current; simplifies the process and reduces the production cost.
  • the low-temperature polysilicon TFT substrate of the present invention is formed by forming an N-type heavily doped region on both sides of the polysilicon layer, and sequentially forming a first gate insulating layer, a first gate, and a second on the polysilicon layer.
  • a gate insulating layer, a second gate, and a width of the second gate is larger than a width of the first gate to form a low electric field region in the polysilicon layer, thereby reducing leakage current; or buffering first Forming a first gate, a first gate insulating layer on the layer, and forming a polysilicon layer on the first gate insulating layer and an N-type heavily doped region on both sides of the polysilicon layer, and then forming a second gate on the polysilicon layer a second insulating layer, a second gate, and a thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer, and a width of the second gate is greater than a width of the first gate, such that the second gate is out of the The thickness of the portion of a gate and the second gate insulating layer of the polysilicon layer are thicker, the generated electric field is smaller, and less electrons are induced in the polysilicon layer, thereby reducing the leakage current; Compared

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Abstract

提供一种低温多晶硅TFT基板的制作方法，在多晶硅层（3）两侧形成N型重掺杂区域（31）后，依次形成第一栅极绝缘层（41）、第一栅极（51）、第二栅极绝缘层（42）、第二栅极（52），且第二栅极（52）的宽度大于第一栅极（51）的宽度，以制作出多晶硅层（3）中的低电场区域，从而起到减小漏电流的作用；或者先形成第一栅极（51）、第一栅极绝缘层（41），在第一栅极绝缘层（41）上形成多晶硅层（3）及N型重掺杂区域（31），再形成第二栅极绝缘层（42）、第二栅极（52），且第二栅极绝缘层（42）的厚度大于第一栅极绝缘层（41）的厚度，第二栅极（52）的宽度大于第一栅极（51）的宽度，以使得第二栅极（52）超出第一栅极（51）的部分和多晶硅层（3）夹杂的第二栅极绝缘层（42）的厚度较厚，产生的电场较小，从而起到减小漏电流的作用；简化了工艺流程，降低了生产成本。

Description

低温多晶硅TFT基板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种低温多晶硅TFT基板的制作方法。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等。
现有市场上的液晶显示装置大部分为背光型液晶显示装置，其包括壳体、设于壳体内的液晶面板及设于壳体内的背光模组(Backlight module)。传统的液晶面板的结构是由一彩色滤光片基板(Color Filter Substrate)、一薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)以及一配置于两基板间的液晶层(Liquid Crystal Layer)所构成，其工作原理是通过在两片玻璃基板上施加驱动电压来控制液晶层的液晶分子的旋转，将背光模组的光线折射出来产生画面。
低温多晶硅(Low Temperature Poly-silicon，LTPS)技术是新一代TFT基板的制造技术，与传统非晶硅(a-Si)技术的最大差异在于，低温多晶硅显示器反应速度较快，且有高亮度、高解析度与低耗电量等优点。
请参阅图1，为一种现有低温多晶硅TFT基板的剖面结构示意图，其制作方法主要包括如下步骤：先依次在基板100上沉积缓冲层200、非晶硅(a-Si)层，非晶硅层经由准分子激光退火处理(Excimer LaserAnneal，ELA)结晶转变为多晶硅(Poly-Si)，然后通过黄光/蚀刻制程得到多晶硅层300，再在多晶硅层300上用两次光罩(Mask)通过黄光光阻分别对多晶硅层300进行离子植入，得到N型重掺杂(N+)区域和N型轻掺杂(N-)区域，得到轻掺杂漏区(LDD)；之后通过多次沉积、黄光、蚀刻制程得到栅极绝缘层400、栅极500、层间绝缘层600、源/漏极700，最终得到图1所示结构的低温多晶硅TFT基板。
上述低温多晶硅TFT基板的制作方法存在一定缺点，即在定义低温多晶硅TFT基板的N型重掺杂区域和N型轻掺杂区域后需要用到两次离子植入，制作工序流程复杂，制造成本高。因此，有必要提供一种低温多晶硅TFT基板的制作方法，以解决上述问题。
发明内容
本发明的目的在于提供一种低温多晶硅TFT基板的制作方法，可减少一次离子植入制程，简化工艺流程，降低生产成本。
为实现上述目的，本发明提供一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、提供基板，在所述基板上沉积缓冲层；
步骤2、在所述缓冲层上沉积非晶硅层，对所述非晶硅层进行去氢处理后，通过结晶制程使其转变为多晶硅层，对多晶硅层进行图案化处理，得到岛状多晶硅层；
步骤3、在所述岛状多晶硅层上涂覆光阻，对所述光阻进行曝光、显影后形成光阻层；以所述光阻层为遮蔽层，对所述岛状多晶硅层两侧进行离子植入，形成位于所述岛状多晶硅层两侧的N型重掺杂区域及位于两个N型重掺杂区域之间的未掺杂区域，之后剥离所述光阻层；
步骤4、在所述岛状多晶硅层上沉积第一栅极绝缘层，在所述第一栅极绝缘层上沉积第一金属层，并对所述第一金属层进行图案化处理，得到对应所述未掺杂区域上方的第一栅极，且所述第一栅极的宽度小于所述未掺杂区域的宽度；
步骤5、在所述第一栅极绝缘层、第一栅极上沉积第二栅极绝缘层，在所述第二栅极绝缘层上沉积第二金属层，并对所述第二金属层进行图案化处理，得到对应所述第一栅极上方的第二栅极，所述第二栅极的宽度等于所述未掺杂区域的宽度，且所述第二栅极的两端均超出所述第一栅极的两端一段距离，从而在所述未掺杂区域上被所述第一栅极与第二栅极进行双重覆盖的区域形成具有强电场的沟道区，在所述未掺杂区域的两侧仅被所述第二栅极覆盖的区域形成低电场区；
步骤6、在所述第二栅极绝缘层与第二栅极上沉积层间绝缘层；通过黄光制程在所述层间绝缘层、第一栅极绝缘层、及第二栅极绝缘层上对应所述岛状多晶硅层两侧的N型重掺杂区域的上方形成过孔；
步骤7、在所述层间绝缘层上沉积第三金属层，对所述第三金属层进行图案化处理，得到源/漏极，所述源/漏极经由所述过孔与所述岛状多晶硅层两侧的N型重掺杂区域相接触。
所述步骤1中，所述基板为玻璃基板；所述缓冲层为氮化硅层与氧化硅层的复合层；所述氮化硅层的厚度为40～100nm；所述氧化硅层的厚度为100～200nm。
所述步骤2中，所述非晶硅层的厚度为40～60nm；所述结晶制程为准分子激光退火处理或者固相结晶化制程。
所述第一栅极绝缘层、第二栅极绝缘层的材料为氮化硅或氧化硅；所述第一栅极、第二栅极的材料为钼；所述层间绝缘层为氮化硅层、氧化硅层、或二者的组合；所述源/漏极为钼/铝/钼复合层。
所述第二栅极的两端超出于所述第一栅极的两端的距离均为1～2μm。
本发明还提供另一种低温多晶硅TFT基板的制作方法，包括如下步骤
步骤1、提供基板，在所述基板上沉积缓冲层；
步骤2、在所述缓冲层上沉积第一金属层，并对所述第一金属层进行图案化处理，得到第一栅极；在所述第一栅极上沉积第一栅极绝缘层；
步骤3、在所述第一栅极绝缘层上沉积非晶硅层，对所述非晶硅层进行去氢处理后，通过结晶制程使其转变为多晶硅层，对多晶硅层进行图案化处理，得到对应所述第一栅极上方的岛状多晶硅层；
步骤4、在所述岛状多晶硅层上涂覆光阻，对所述光阻进行曝光、显影后形成光阻层；以所述光阻层为遮蔽层，对所述岛状多晶硅层两侧进行离子植入，形成位于所述岛状多晶硅层两侧的N型重掺杂区域及位于两个N型重掺杂区域之间的未掺杂区域，之后剥离所述光阻层，其中，所述未掺杂区域的宽度大于所述第一栅极的宽度；
步骤5、在所述岛状多晶硅层上沉积第二栅极绝缘层，并在所述第二栅极绝缘层上沉积第二金属层，对所述第二金属层进行图案化处理，得到对应所述未掺杂区域上方的第二栅极；其中，所述第二栅极绝缘层的厚度大于第一栅极绝缘层的厚度，所述第二栅极的宽度等于所述未掺杂区域的宽度，且所述第二栅极的两端均超出所述第一栅极的两端一段距离，从而在所述未掺杂区域上被所述第一栅极与第二栅极进行双重覆盖的区域形成具有强电场的沟道区，在所述未掺杂区域的两侧仅被所述第二栅极覆盖的区域形成低电场区；
步骤6、在所述第二栅极绝缘层、第二栅极上沉积层间绝缘层，通过黄光制程在所述层间绝缘层、及第二栅极绝缘层上对应所述岛状多晶硅层两侧的N型重掺杂区域的上方形成过孔；
步骤7、在所述层间绝缘层上沉积第三金属层，对所述第三金属层进行图案化处理，得到源/漏极，所述源/漏极经由所述过孔与所述岛状多晶硅层两侧的N型重掺杂区域相接触。
所述步骤1中，所述基板为玻璃基板；所述缓冲层为氮化硅层与氧化硅层的复合层；所述氮化硅层的厚度为40～100nm；所述氧化硅层的厚度为 100～200nm。
所述步骤2中，所述非晶硅层的厚度为40～60nm；所述结晶制程为准分子激光退火处理或者固相结晶化制程。
所述第一栅极绝缘层、第二栅极绝缘层的材料为氮化硅或氧化硅；所述第一栅极、第二栅极的材料为钼；所述层间绝缘层为氮化硅层、氧化硅层、或二者的组合；所述源/漏极为钼/铝/钼复合层。
所述第二栅极绝缘层的厚度比第一栅极绝缘层的厚度大
Figure PCTCN2015099985-appb-000001
所述第二栅极的两端超出所述第一栅极的两端的距离均为1～2μm。
本发明还提供一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、提供基板，在所述基板上沉积缓冲层；
步骤2、在所述缓冲层上沉积第一金属层，并对所述第一金属层进行图案化处理，得到第一栅极；在所述第一栅极上沉积第一栅极绝缘层；
步骤3、在所述第一栅极绝缘层上沉积非晶硅层，对所述非晶硅层进行去氢处理后，通过结晶制程使其转变为多晶硅层，对多晶硅层进行图案化处理，得到对应所述第一栅极上方的岛状多晶硅层；
步骤4、在所述岛状多晶硅层上涂覆光阻，对所述光阻进行曝光、显影后形成光阻层；以所述光阻层为遮蔽层，对所述岛状多晶硅层两侧进行离子植入，形成位于所述岛状多晶硅层两侧的N型重掺杂区域及位于两个N型重掺杂区域之间的未掺杂区域，之后剥离所述光阻层，其中，所述未掺杂区域的宽度大于所述第一栅极的宽度；
步骤5、在所述岛状多晶硅层上沉积第二栅极绝缘层，并在所述第二栅极绝缘层上沉积第二金属层，对所述第二金属层进行图案化处理，得到对应所述未掺杂区域上方的第二栅极；其中，所述第二栅极绝缘层的厚度大于第一栅极绝缘层的厚度，所述第二栅极的宽度等于所述未掺杂区域的宽度，且所述第二栅极的两端均超出所述第一栅极的两端一段距离，从而在所述未掺杂区域上被所述第一栅极与第二栅极进行双重覆盖的区域形成具有强电场的沟道区，在所述未掺杂区域的两侧仅被所述第二栅极覆盖的区域形成低电场区；
步骤6、在所述第二栅极绝缘层、第二栅极上沉积层间绝缘层，通过黄光制程在所述层间绝缘层、及第二栅极绝缘层上对应所述岛状多晶硅层两侧的N型重掺杂区域的上方形成过孔；
步骤7、在所述层间绝缘层上沉积第三金属层，对所述第三金属层进行图案化处理，得到源/漏极，所述源/漏极经由所述过孔与所述岛状多晶硅层两侧的N型重掺杂区域相接触；
其中，所述步骤1中，所述基板为玻璃基板；所述缓冲层为氮化硅层与氧化硅层的复合层；所述氮化硅层的厚度为40～100nm；所述氧化硅层的厚度为100～200nm；
其中，所述步骤2中，所述非晶硅层的厚度为40～60nm；所述结晶制程为准分子激光退火处理或者固相结晶化制程；
其中，所述第一栅极绝缘层、第二栅极绝缘层的材料为氮化硅或氧化硅；所述第一栅极、第二栅极的材料为钼；所述层间绝缘层为氮化硅层、氧化硅层、或二者的组合；所述源/漏极为钼/铝/钼复合层；
其中，所述第二栅极绝缘层的厚度比第一栅极绝缘层的厚度大
Figure PCTCN2015099985-appb-000002
所述第二栅极的两端超出所述第一栅极的两端的距离均为1～2μm。
本发明的有益效果：本发明的低温多晶硅TFT基板的制作方法，在多晶硅层两侧形成N型重掺杂区域后，依次在多晶硅层上形成第一栅极绝缘层、第一栅极、第二栅极绝缘层、第二栅极，且第二栅极的宽度大于第一栅极的宽度，以制作出多晶硅层中的低电场区域，从而起到减小漏电流的作用；或者先在缓冲层上形成第一栅极、第一栅极绝缘层，并在第一栅极绝缘层上形成多晶硅层以及多晶硅层两侧的N型重掺杂区域后，再在多晶硅层上形成第二栅极绝缘层、第二栅极，且第二栅极绝缘层的厚度大于第一栅极绝缘层的厚度，第二栅极的宽度大于第一栅极的宽度，以使得第二栅极超出第一栅极的部分和多晶硅层夹杂的第二栅极绝缘层的厚度较厚，产生的电场较小，在多晶硅层中诱导产生的电子较少，从而起到减小漏电流的作用；与现有技术相比，本发明的低温多晶硅TFT基板的制作方法，在多晶硅层两侧形成N型重掺杂区域后，不需要再通过一道光罩定义N型轻掺杂区域后植入低剂量的磷离子以形成轻掺杂漏区来减小漏电流，而是利用第一栅极、第二栅极的宽度差来产生低电场，起到减小漏电流的作用，简化了工艺流程，降低了生产成本。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为一种现有的低温多晶硅TFT基板的剖面结构示意图；
图2为本发明的一种低温多晶硅TFT基板的制作方法的步骤1至步骤 2的示意图；
图3为本发明的一种低温多晶硅TFT基板的制作方法的步骤3的示意图；
图4为本发明的一种低温多晶硅TFT基板的制作方法的步骤4至步骤5的示意图；
图5为本发明的一种低温多晶硅TFT基板的制作方法的步骤6的示意图；
图6为本发明的一种低温多晶硅TFT基板的制作方法的步骤7的示意图；
图7为本发明的另一种低温多晶硅TFT基板的制作方法的步骤1至步骤2的示意图；
图8为本发明的另一种低温多晶硅TFT基板的制作方法的步骤3的示意图；
图9为本发明的另一种低温多晶硅TFT基板的制作方法的步骤4的示意图；
图10为本发明的另一种低温多晶硅TFT基板的制作方法的步骤5至步骤7的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2至图6，本发明首先提供一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、如图2所示，提供基板1，在所述基板1上沉积缓冲层2。
具体地，所述基板1为玻璃基板；所述缓冲层2为氮化硅(SiNx)层21与氧化硅(SiOx)层22的复合层。
具体地，所述氮化硅层21的厚度为40～100nm；所述氧化硅层22的厚度为100～200nm。
步骤2、如图2所示，在所述缓冲层2上沉积非晶硅层，对所述非晶硅层进行去氢处理后，通过结晶制程使其转变为多晶硅层，对多晶硅层进行图案化处理，得到岛状多晶硅层3。
具体地，所述非晶硅层的厚度为40～60nm。
具体地，所述结晶制程可以是准分子激光退火处理或者固相结晶化(Solid Phase Crystallization，SPC)制程。
步骤3、如图3所示，在所述岛状多晶硅层3上涂覆光阻，对所述光阻进行曝光、显影后形成光阻层30；以所述光阻层30为遮蔽层，对所述岛状多晶硅层3两侧进行离子植入，形成位于所述岛状多晶硅层3两侧的N型重掺杂区域31及位于两个N型重掺杂区域31之间的未掺杂区域32，之后剥离所述光阻层30。
具体的，所述步骤3中，对所述岛状多晶硅层3两侧植入的离子为磷(P)离子。
步骤4、如图4所示，在所述岛状多晶硅层3上沉积第一栅极绝缘层41，在所述第一栅极绝缘层41上沉积第一金属层，并对所述第一金属层进行图案化处理，得到对应所述未掺杂区域32上方的第一栅极51，且所述第一栅极51的宽度小于所述未掺杂区域32的宽度。
步骤5、如图4所示，在所述第一栅极绝缘层41、第一栅极51上沉积第二栅极绝缘层42，在所述第二栅极绝缘层42上沉积第二金属层，并对所述第二金属层进行图案化处理，得到对应所述第一栅极51上方的第二栅极52，所述第二栅极52的宽度等于所述未掺杂区域32的宽度，且所述第二栅极52的两端均超出所述第一栅极51的两端一段距离，从而在所述未掺杂区域32上被所述第一栅极51与第二栅极52进行双重覆盖的区域形成具有强电场的沟道区321，在所述未掺杂区域32的两侧仅被所述第二栅极52覆盖的区域形成低电场区322。
具体的，位于所述沟道区321与两侧的N型重掺杂区域31之间的低电场区322可以代替传统的TFT基板中的轻掺杂漏区(LDD)，起到减小漏电流的作用，减少了一次离子植入过程，从而可以优化工艺流程，节省制造成本。
具体地，所述第一栅极绝缘层41、第二栅极绝缘层42的材料为氮化硅或氧化硅；所述第一栅极51、第二栅极52的材料为钼(Mo)。
具体地，所述第二栅极52的两端超出所述第一栅极51的两端的距离均为1～2μm。
步骤6、如图5所示，在所述第二栅极绝缘层42与第二栅极52上沉积层间绝缘层6；通过黄光制程在所述层间绝缘层6、第一栅极绝缘层41、及第二栅极绝缘层42上对应所述岛状多晶硅层3两侧的N型重掺杂区域31的上方形成过孔61。
具体地，所述层间绝缘层6为氮化硅层、氧化硅层、或二者的组合。
步骤7、如图6所示，在所述层间绝缘层6上沉积第三金属层，对所述第三金属层进行图案化处理，得到源/漏极7，所述源/漏极7经由所述过孔 61与所述岛状多晶硅层3两侧的N型重掺杂区域31相接触。
具体地，所述源/漏极7为钼/铝/钼复合层，即两钼层之间夹设一铝层构成的复合层。
上述低温多晶硅TFT基板的制作方法，在多晶硅层两侧形成N型重掺杂区域后，依次在多晶硅层上形成第一栅极绝缘层、第一栅极、第二栅极绝缘层、第二栅极，且第二栅极的宽度大于第一栅极的宽度，以制作出多晶硅层中的低电场区域，从而起到减小漏电流的作用；简化了工艺流程，降低了生产成本。
请参阅图7至图10，本发明还提供另一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、如图7所示，提供基板1，在所述基板1上沉积缓冲层2。
具体地，所述基板1为玻璃基板；所述缓冲层2为氮化硅层21与氧化硅层22的复合层。
具体地，所述氮化硅层21的厚度为40～100nm；所述氧化硅层22的厚度为100～200nm。
步骤2、如图7所示，在所述缓冲层2上沉积第一金属层，并对所述第一金属层进行图案化处理，得到第一栅极51；在所述第一栅极51上沉积第一栅极绝缘层41。
步骤3、如图8所示，在所述第一栅极绝缘层41上沉积非晶硅层，对所述非晶硅层进行去氢处理后，并通过结晶制程使其转变为多晶硅层，对多晶硅层进行图案化处理，得到对应所述第一栅极51上方的岛状多晶硅层3。
具体地，所述非晶硅层的厚度为40～60nm。
具体地，所述结晶制程可以是准分子激光退火处理或者固相结晶化制程。
步骤4、如图9所示，在所述岛状多晶硅层3上涂覆光阻，对所述光阻进行曝光、显影后形成光阻层30；以所述光阻层30为遮蔽层，对所述岛状多晶硅层3两侧进行离子植入，形成位于所述岛状多晶硅层3两侧的N型重掺杂区域31及位于两个N型重掺杂区域31之间的未掺杂区域32，之后剥离所述光阻层30，其中，所述未掺杂区域32的宽度大于所述第一栅极51的宽度。
具体的，所述步骤4中，对所述岛状多晶硅层3两侧植入的离子为磷(P)离子。
步骤5、如图10所示，在所述岛状多晶硅层3上沉积第二栅极绝缘层 42，并在所述第二栅极绝缘层42上沉积第二金属层，对所述第二金属层进行图案化处理，得到对应所述未掺杂区域32上方的第二栅极52；其中，所述第二栅极绝缘层42的厚度大于第一栅极绝缘层41的厚度，所述第二栅极52的宽度等于所述未掺杂区域32的宽度，且所述第二栅极52的两端均超出所述第一栅极51的两端一段距离，从而在所述未掺杂区域32上被所述第一栅极51与第二栅极52进行双重覆盖的区域形成具有强电场的沟道区321，在所述未掺杂区域32的两侧仅被所述第二栅极52覆盖的区域形成低电场区322。
具体的，由于低电场区322上方仅被所述第二栅极52覆盖，且所述低电场区322与第二栅极52之间的第二栅极绝缘层42的厚度较大，从而可以保证在该低电场区322中产生的电场较小，诱导产生的电子也较少，与传统的TFT基板相比，该低电场区322可以代替传统的TFT基板中通过离子植入制程形成的轻掺杂漏区(LDD)，起到减小漏电流的作用，并且减少了一次离子植入过程，从而可以优化工艺流程，节省制造成本。
具体地，所述第一栅极绝缘层41、第二栅极绝缘层42的材料为氮化硅或氧化硅；所述第一栅极51、第二栅极52的材料为钼。
具体地，所述第二栅极绝缘层42的厚度比第一栅极绝缘层41的厚度大
Figure PCTCN2015099985-appb-000003
所述第二栅极52的两端超出所述第一栅极51的两端的距离均为1～2μm。
步骤6、如图10所示，在所述第二栅极绝缘层42、第二栅极52上沉积层间绝缘层6，通过黄光制程在所述层间绝缘层6、及第二栅极绝缘层42上对应所述岛状多晶硅层3两侧的N型重掺杂区域31的上方形成过孔61。
具体地，所述层间绝缘层6为氮化硅层、氧化硅层、或二者的组合。
步骤7、如图10所示，在所述层间绝缘层6上沉积第三金属层，对所述第三金属层进行图案化处理，得到源/漏极7，所述源/漏极7经由所述过孔61与所述岛状多晶硅层3两侧的N型重掺杂区域31相接触。
具体地，所述源/漏极7为钼/铝/钼复合层，即两钼层之间夹设一铝层构成的复合层。
上述低温多晶硅TFT基板的制作方法，先在缓冲层上形成第一栅极、第一栅极绝缘层，并在第一栅极绝缘层上形成多晶硅层以及多晶硅层两侧的N型重掺杂区域后，再在多晶硅层上形成第二栅极绝缘层、第二栅极，且第二栅极绝缘层的厚度大于第一栅极绝缘层的厚度，第二栅极的宽度大于第一栅极的宽度，以使得第二栅极超出第一栅极的部分和多晶硅层夹杂的第二栅极绝缘层的厚度较厚，产生的电场较小，在多晶硅层中诱导产生 的电子较少，从而起到减小漏电流的作用；简化了工艺流程，降低了生产成本。
综上所述，本发明的低温多晶硅TFT基板的制作方法，在多晶硅层两侧形成N型重掺杂区域后，依次在多晶硅层上形成第一栅极绝缘层、第一栅极、第二栅极绝缘层、第二栅极，且第二栅极的宽度大于第一栅极的宽度，以制作出多晶硅层中的低电场区域，从而起到减小漏电流的作用；或者先在缓冲层上形成第一栅极、第一栅极绝缘层，并在第一栅极绝缘层上形成多晶硅层以及多晶硅层两侧的N型重掺杂区域后，再在多晶硅层上形成第二栅极绝缘层、第二栅极，且第二栅极绝缘层的厚度大于第一栅极绝缘层的厚度，第二栅极的宽度大于第一栅极的宽度，以使得第二栅极超出第一栅极的部分和多晶硅层夹杂的第二栅极绝缘层的厚度较厚，产生的电场较小，在多晶硅层中诱导产生的电子较少，从而起到减小漏电流的作用；与现有技术相比，本发明的低温多晶硅TFT基板的制作方法，在多晶硅层两侧形成N型重掺杂区域后，不需要再通过一道光罩定义N型轻掺杂区域后植入低剂量的磷离子以形成轻掺杂漏区来减小漏电流，而是利用第一栅极、第二栅极的宽度差来产生低电场，起到减小漏电流的作用，简化了工艺流程，降低了生产成本。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (11)

  1. 一种低温多晶硅TFT基板的制作方法，包括如下步骤：
    步骤1、提供基板，在所述基板上沉积缓冲层；
    步骤2、在所述缓冲层上沉积非晶硅层，对所述非晶硅层进行去氢处理后，通过结晶制程使其转变为多晶硅层，对所述多晶硅层进行图案化处理，得到岛状多晶硅层；
    步骤3、在所述岛状多晶硅层上涂覆光阻，对所述光阻进行曝光、显影后形成光阻层；以所述光阻层为遮蔽层，对所述岛状多晶硅层两侧进行离子植入，形成位于所述岛状多晶硅层两侧的N型重掺杂区域及位于两个N型重掺杂区域之间的未掺杂区域，之后剥离所述光阻层；
    步骤4、在所述岛状多晶硅层上沉积第一栅极绝缘层，在所述第一栅极绝缘层上沉积第一金属层，并对所述第一金属层进行图案化处理，得到对应所述未掺杂区域上方的第一栅极，且所述第一栅极的宽度小于所述未掺杂区域的宽度；
    步骤5、在所述第一栅极绝缘层、及第一栅极上沉积第二栅极绝缘层，在所述第二栅极绝缘层上沉积第二金属层，并对所述第二金属层进行图案化处理，得到对应所述第一栅极上方的第二栅极，所述第二栅极的宽度等于所述未掺杂区域的宽度，且所述第二栅极的两端均超出所述第一栅极的两端一段距离，从而在所述未掺杂区域上被所述第一栅极与第二栅极进行双重覆盖的区域形成具有强电场的沟道区，在所述未掺杂区域的两侧仅被所述第二栅极覆盖的区域形成低电场区；
    步骤6、在所述第二栅极绝缘层与第二栅极上沉积层间绝缘层；通过黄光制程在所述层间绝缘层、第一栅极绝缘层、及第二栅极绝缘层上对应所述岛状多晶硅层两侧的N型重掺杂区域的上方形成过孔；
    步骤7、在所述层间绝缘层上沉积第三金属层，对所述第三金属层进行图案化处理，得到源/漏极，所述源/漏极经由所述过孔与所述岛状多晶硅层两侧的N型重掺杂区域相接触。
  2. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所述步骤1中，所述基板为玻璃基板；所述缓冲层为氮化硅层与氧化硅层的复合层；所述氮化硅层的厚度为40～100nm；所述氧化硅层的厚度为100～200nm。
  3. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所 述步骤2中，所述非晶硅层的厚度为40～60nm；所述结晶制程为准分子激光退火处理或者固相结晶化制程。
  4. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所述第一栅极绝缘层、第二栅极绝缘层的材料为氮化硅或氧化硅；所述第一栅极、第二栅极的材料为钼；所述层间绝缘层为氮化硅层、氧化硅层、或二者的组合；所述源/漏极为钼/铝/钼复合层。
  5. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所述第二栅极的两端超出所述第一栅极的距离均为1～2μm。
  6. 一种低温多晶硅TFT基板的制作方法，包括如下步骤：
    步骤1、提供基板，在所述基板上沉积缓冲层；
    步骤2、在所述缓冲层上沉积第一金属层，并对所述第一金属层进行图案化处理，得到第一栅极；在所述第一栅极上沉积第一栅极绝缘层；
    步骤3、在所述第一栅极绝缘层上沉积非晶硅层，对所述非晶硅层进行去氢处理后，通过结晶制程使其转变为多晶硅层，对多晶硅层进行图案化处理，得到对应所述第一栅极上方的岛状多晶硅层；
    步骤4、在所述岛状多晶硅层上涂覆光阻，对所述光阻进行曝光、显影后形成光阻层；以所述光阻层为遮蔽层，对所述岛状多晶硅层两侧进行离子植入，形成位于所述岛状多晶硅层两侧的N型重掺杂区域及位于两个N型重掺杂区域之间的未掺杂区域，之后剥离所述光阻层，其中，所述未掺杂区域的宽度大于所述第一栅极的宽度；
    步骤5、在所述岛状多晶硅层上沉积第二栅极绝缘层，并在所述第二栅极绝缘层上沉积第二金属层，对所述第二金属层进行图案化处理，得到对应所述未掺杂区域上方的第二栅极；其中，所述第二栅极绝缘层的厚度大于第一栅极绝缘层的厚度，所述第二栅极的宽度等于所述未掺杂区域的宽度，且所述第二栅极的两端均超出所述第一栅极的两端一段距离，从而在所述未掺杂区域上被所述第一栅极与第二栅极进行双重覆盖的区域形成具有强电场的沟道区，在所述未掺杂区域的两侧仅被所述第二栅极覆盖的区域形成低电场区；
    步骤6、在所述第二栅极绝缘层、第二栅极上沉积层间绝缘层，通过黄光制程在所述层间绝缘层、及第二栅极绝缘层上对应所述岛状多晶硅层两侧的N型重掺杂区域的上方形成过孔；
    步骤7、在所述层间绝缘层上沉积第三金属层，对所述第三金属层进行图案化处理，得到源/漏极，所述源/漏极经由所述过孔与所述岛状多晶硅层两侧的N型重掺杂区域相接触。
  7. 如权利要求6所述的低温多晶硅TFT基板的制作方法，其中，所述步骤1中，所述基板为玻璃基板；所述缓冲层为氮化硅层与氧化硅层的复合层；所述氮化硅层的厚度为40～100nm；所述氧化硅层的厚度为100～200nm。
  8. 如权利要求6所述的低温多晶硅TFT基板的制作方法，其中，所述步骤2中，所述非晶硅层的厚度为40～60nm；所述结晶制程为准分子激光退火处理或者固相结晶化制程。
  9. 如权利要求6所述的低温多晶硅TFT基板的制作方法，其中，所述第一栅极绝缘层、第二栅极绝缘层的材料为氮化硅或氧化硅；所述第一栅极、第二栅极的材料为钼；所述层间绝缘层为氮化硅层、氧化硅层、或二者的组合；所述源/漏极为钼/铝/钼复合层。
  10. 如权利要求6所述的低温多晶硅TFT基板的制作方法，其中，所述第二栅极绝缘层的厚度比第一栅极绝缘层的厚度大
    Figure PCTCN2015099985-appb-100001
    所述第二栅极的两端超出所述第一栅极的两端的距离均为1～2μm。
  11. 一种低温多晶硅TFT基板的制作方法，包括如下步骤：
    步骤1、提供基板，在所述基板上沉积缓冲层；
    步骤2、在所述缓冲层上沉积第一金属层，并对所述第一金属层进行图案化处理，得到第一栅极；在所述第一栅极上沉积第一栅极绝缘层；
    步骤3、在所述第一栅极绝缘层上沉积非晶硅层，对所述非晶硅层进行去氢处理后，通过结晶制程使其转变为多晶硅层，对多晶硅层进行图案化处理，得到对应所述第一栅极上方的岛状多晶硅层；
    步骤4、在所述岛状多晶硅层上涂覆光阻，对所述光阻进行曝光、显影后形成光阻层；以所述光阻层为遮蔽层，对所述岛状多晶硅层两侧进行离子植入，形成位于所述岛状多晶硅层两侧的N型重掺杂区域及位于两个N型重掺杂区域之间的未掺杂区域，之后剥离所述光阻层，其中，所述未掺杂区域的宽度大于所述第一栅极的宽度；
    步骤5、在所述岛状多晶硅层上沉积第二栅极绝缘层，并在所述第二栅极绝缘层上沉积第二金属层，对所述第二金属层进行图案化处理，得到对应所述未掺杂区域上方的第二栅极；其中，所述第二栅极绝缘层的厚度大于第一栅极绝缘层的厚度，所述第二栅极的宽度等于所述未掺杂区域的宽度，且所述第二栅极的两端均超出所述第一栅极的两端一段距离，从而在所述未掺杂区域上被所述第一栅极与第二栅极进行双重覆盖的区域形成具有强电场的沟道区，在所述未掺杂区域的两侧仅被所述第二栅极覆盖的区域形成低电场区；
    步骤6、在所述第二栅极绝缘层、第二栅极上沉积层间绝缘层，通过黄光制程在所述层间绝缘层、及第二栅极绝缘层上对应所述岛状多晶硅层两侧的N型重掺杂区域的上方形成过孔；
    步骤7、在所述层间绝缘层上沉积第三金属层，对所述第三金属层进行图案化处理，得到源/漏极，所述源/漏极经由所述过孔与所述岛状多晶硅层两侧的N型重掺杂区域相接触；
    其中，所述步骤1中，所述基板为玻璃基板；所述缓冲层为氮化硅层与氧化硅层的复合层；所述氮化硅层的厚度为40～100nm；所述氧化硅层的厚度为100～200nm；
    其中，所述步骤2中，所述非晶硅层的厚度为40～60nm；所述结晶制程为准分子激光退火处理或者固相结晶化制程；
    其中，所述第一栅极绝缘层、第二栅极绝缘层的材料为氮化硅或氧化硅；所述第一栅极、第二栅极的材料为钼；所述层间绝缘层为氮化硅层、氧化硅层、或二者的组合；所述源/漏极为钼/铝/钼复合层；
    其中，所述第二栅极绝缘层的厚度比第一栅极绝缘层的厚度大
    Figure PCTCN2015099985-appb-100002
    所述第二栅极的两端超出所述第一栅极的两端的距离均为1～2μm。
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