WO2017070995A1 - 三维半导体器件及其制造方法 - Google Patents

三维半导体器件及其制造方法 Download PDF

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WO2017070995A1
WO2017070995A1 PCT/CN2015/095254 CN2015095254W WO2017070995A1 WO 2017070995 A1 WO2017070995 A1 WO 2017070995A1 CN 2015095254 W CN2015095254 W CN 2015095254W WO 2017070995 A1 WO2017070995 A1 WO 2017070995A1
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layer
substrate contact
forming
substrate
common source
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PCT/CN2015/095254
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English (en)
French (fr)
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霍宗亮
叶甜春
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中国科学院微电子研究所
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Priority to US15/770,020 priority Critical patent/US10644020B2/en
Publication of WO2017070995A1 publication Critical patent/WO2017070995A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Definitions

  • the present invention relates to a semiconductor device and a method of fabricating the same, and, in particular, to a three-dimensional semiconductor memory device and a method of fabricating the same.
  • a multilayer stacked structure (for example, a plurality of ONO structures in which oxide and nitride are alternated) may be first deposited on a substrate; and a multilayer stack on the substrate by an anisotropic etching process Structural etching to form a plurality of channel vias distributed along the extending direction of the memory cell word line (WL), perpendicular to the surface of the substrate (either directly to the surface of the substrate or having a certain overetch); in the via of the channel Depositing a material such as polysilicon to form a columnar channel; etching the multilayer laminate structure along the WL direction to form a trench directly to the substrate, exposing a multilayer stack surrounding the columnar channel; and wet removing a certain type of material in the stack (eg, thermal phosphoric acid removes silicon nitride, or HF removes silicon oxide), leaving a laterally distributed protrusion structure around the columnar channel; depositing a gate dielectric
  • a portion of the protrusions of the stacked structure left on the side walls of the columnar channel form an isolation layer between the gate electrodes, and the remaining gate stack is sandwiched between the plurality of isolation layers as a control electrode.
  • the fringe field of the gate causes For example, a source/drain region is induced on the columnar channel sidewall of the polysilicon material, thereby forming a gate array of a plurality of series-parallel MOSFETs to record the stored logic state.
  • an aspect of the present invention provides a three-dimensional semiconductor device including: a peripheral circuit distributed on a substrate; a plurality of memory cells on the peripheral circuit, each of which includes: a common source region, at the memory cell and the periphery Between the circuits; a channel layer, distributed in a direction perpendicular to the surface of the substrate; at least one substrate contact layer extending horizontally from the middle of the channel layer parallel to the surface of the substrate, each comprising at least one substrate contact region; An insulating layer on the sidewall of the channel layer; a plurality of control gates sandwiched between adjacent insulating layers; a gate dielectric layer between the channel layer and the control gate; and a drain region in the trench
  • the channel layer is divided into a plurality of segments by the substrate contact layer; optionally, the cross-sectional shape of the channel layer parallel to the substrate surface comprises a shape selected from the group consisting of a rectangle, a square, a diamond, a circle, a semicircle, an ellipse, a triangle, Geometry of a pentagon, a pentagon, a hexagon, an octagon, and combinations thereof, and a solid geometry selected from the evolution of the geometry, a hollow annular geometry, or a hollow annular peripheral layer and an insulating layer a combined pattern of centers; optionally, the channel layer is a single crystal, polycrystalline, microcrystalline or amorphous layer and the material is selected from the group consisting of Group IV elements, Group IV compounds, Group III-V compounds, Group II-VI compound semiconductors.
  • the ground further includes a channel fill layer of air or oxide or nitride.
  • the gate dielectric layer further comprises a tunneling layer, a storage layer, a barrier layer; preferably, the tunneling layer comprises a single layer structure or a multi-layer stacked structure of SiO 2 or high-k material; preferably, the storage layer has charge trapping A single layer structure or a multilayer stack structure of a dielectric material, such as any one of SiN, SiON, HfO, ZrO, and combinations thereof; preferably, the barrier layer is a single layer of a dielectric material such as silicon oxide, aluminum oxide, or cerium oxide. Structure or multilayer stack structure.
  • control gate material is selected from the group consisting of doped polysilicon, doped single crystal silicon, metal, metal alloy, conductive metal oxide, conductive metal nitride, conductive metal silicide or a combination thereof; optionally, phase Between adjacent insulating layers further includes a floating gate horizontally adjacent to the control gate via an insulating layer and/or a gate dielectric layer.
  • the common source region comprises any one of doped polysilicon, doped single crystal silicon, metal silicide, metal nitride or a combination thereof; preferably, the common source region has a different contact region from the channel layer and/or the substrate The type of conductivity.
  • the invention also provides a method for manufacturing a three-dimensional semiconductor device, comprising the steps of:
  • the channel layer at the top of the adjacent insulating layer stack constitutes at least one substrate contact layer
  • the present invention further provides a method of fabricating a three-dimensional semiconductor device, comprising the steps of:
  • G2 selectively etching to remove the second material layer, forming a gate dielectric layer and a control gate between the remaining first material layers;
  • step b further comprises: etching the ILD on the peripheral circuit to form a recess, filling the doped semiconductor or the conductor to form a common source region, planarizing the common source region until the ILD is exposed; or depositing and etching on the peripheral circuit to form a doping
  • the common source region of the semiconductor or conductor forms an ILD covering the common source region and planarizes the ILD until the common source region is exposed.
  • step g or g2 further comprises: selectively etching to remove the second material layer, leaving a lateral groove between the remaining first material layers, forming a floating gate in the lateral groove, and forming an insulating layer on the floating gate And/or a gate dielectric layer, the control gate is formed on the insulating layer and/or the gate dielectric layer in the lateral recess.
  • step h ion implantation is performed to form a substrate contact region; preferably, the substrate contact region is different from the common source region in conductivity type.
  • 1A is a cross-sectional view of a prior art three-dimensional semiconductor memory device
  • 1B is a top view of a prior art flash chip layout
  • Figure 1C is a top view of the chip layout to be implemented
  • FIGS. 2A through 2L are cross-sectional views showing respective steps of a method of fabricating a three-dimensional semiconductor memory device in accordance with one embodiment of the present invention
  • 3A to 3F illustrate a three-dimensional semiconductor memory device in accordance with another embodiment of the present invention.
  • FIGS. 2A through 2L are cross-sectional views showing respective steps of a method of fabricating a three-dimensional semiconductor memory device in accordance with one embodiment of the present invention.
  • a peripheral access circuit is formed on the chip substrate 1.
  • a substrate 1 is provided, which may be made of bulk Si, bulk Ge, silicon-on-insulator (SOI), germanium on insulator (GeOI) or other compound semiconductor substrate such as SiGe, SiC, GaN. , GaAs, InP, etc., and combinations of these substances.
  • substrate 1 is preferably a silicon-containing substrate such as Si, SOI, SiGe, Si:C, and the like.
  • a peripheral access circuit is formed in and/or on the substrate 1 by a CMOS compatible planar process, and has a source and drain region, a gate stack (including a gate dielectric layer and a gate conductive layer), a contact wiring, etc., as shown in FIG. 2A. (all are not separately marked).
  • an interlayer dielectric layer (ILD) or an inter-poly dielectric layer (IPD) 2 of silicon oxide or a low-k material is formed by a process such as CVD, spin coating, spray coating, screen printing, pyrolysis, oxidation, etc.
  • the low-k material includes Not limited to organic low-k materials (such as organic polymers containing aryl or polycyclic rings), inorganic low-k materials (such as amorphous carbon nitride film, polycrystalline boron nitride film, fluorosilicate glass, BSG, PSG, BPSG), porous Low-k materials (eg, disilane trioxane (SSQ)-based porous low-k materials, porous silica, porous SiOCH, C-doped silica, F-doped amorphous carbon, porous diamond, porous organic polymer).
  • organic low-k materials such as organic polymers containing aryl or polycyclic rings
  • inorganic low-k materials such as
  • CMP planarizes ILD 2 .
  • the thickness of the ILD 2 is greater than the topmost wiring height of the peripheral access circuit, for example, 100 nm to 10 ⁇ m above the topmost wiring height to leave room for the source of subsequent devices.
  • the source region 3 of the memory array device unit and the stack 4A/4B of the multilayer film are formed on top of the ILD 2 of the peripheral access circuit.
  • the common source region 3 of the memory device may be formed by forming a recess on the top of the ILD 2 by a photolithography/etching process and then filling the doped semiconductor or conductor material by a CVD, PVD film forming process; or Forming a doped semiconductor or conductor material film by a film forming process on top of ILD 2, etching to form a common source region 3 pattern, and then continuing to form silicon oxide or a low-k material (in combination with ILD 2) to surround the common source District 3.
  • the material of the common source region 3, such as doped polysilicon, doped single crystal silicon, has a first doping type, such as N+ (or P+), and may further include a metal silicide (CoSi x , NiSi x , on the (top) surface. PtSi x or the like) to reduce contact resistance, or include metal nitrides (WN, TiN, TaN, etc.) to block diffusion of metal ions such as Al, Cu, etc., to affect device performance and improve adhesion.
  • a metal silicide CoSi x , NiSi x , on the (top) surface.
  • PtSi x or the like to reduce contact resistance
  • metal nitrides (WN, TiN, TaN, etc.) to block diffusion of metal ions such as Al, Cu, etc., to affect device performance and improve adhesion.
  • the CMP planarizes the common source region 3 until the ILD 2 is exposed, or the CMP planarizes the ILD 2 (including the ILD material formed after the formation of the common source region 3) until the common source region 3 is exposed, in which the ILD 2 and the common source region 3 are topped. Qi Ping.
  • a stacked structure 4 of a plurality of insulating dielectric films is formed on top of the ILD 2 / common source region 3, including a plurality of first material layers 4A and a plurality of second material layers 4B which are alternately stacked.
  • the material of the stacked structure 4 is selected from the group consisting of the following materials and includes at least one insulating medium: silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, diamond-like amorphous carbon (DLC), cerium oxide, aluminum oxide, And so on.
  • the first material layer 4A has a first etch selectivity
  • the second material layer 4B has a second etch selectivity and is different from the first etch selectivity.
  • the combination of stacked structures 4A/4B is, for example, a combination of silicon oxide and silicon nitride, a combination of silicon oxide or silicon nitride with amorphous carbon, and the like.
  • layer 4A and layer 4B have a greater etch selectivity (e.g., greater than 5:1) under wet etching conditions or under oxygen plasma dry etching conditions.
  • a gate dielectric layer and a channel layer are formed in a stacked structure.
  • An anisotropic etching process is selected, for example, a plasma-dry etching or RIE using a fluorocarbon (C x H y F z constituting a fluorinated hydrocarbon) as an etching gas, and vertically etching the insulating layer stack 4A/4B Deep holes or trenches (not shown) are formed until the common source region 3 is exposed.
  • the cross-sectional shape of the groove cut parallel to the surface of the substrate 1 may be rectangular, square, diamond, circular, semi-circular, elliptical, triangular, pentagonal, pentagon, hexagonal, octagonal, etc. Geometric shapes.
  • the gate dielectric layer 5A and the channel layer 5B are sequentially deposited in a deep hole by a process such as PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, or the like.
  • the gate dielectric layer 5A may include a single layer or a plurality of sub-layer structures, for example, at least a tunneling layer, a storage layer, a barrier layer, and the barrier layer directly contacts the insulating layer stack 4A/4B of the deep hole sidewall, and the tunneling layer is closest to the deep layer The center axis of the hole is in contact with the subsequently deposited channel layer.
  • the tunneling layer comprises SiO 2 or high-k materials, wherein the high-k materials include, but are not limited to, nitrides (eg, SiN, AlN, TiN), metal oxides (mainly sub-groups and lanthanide metal element oxides, such as MgO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZnO, ZrO 2 , HfO 2 , CeO 2 , Y 2 O 3 , La 2 O 3 ), nitrogen oxides (such as SiON, HfSiON), perovskite phase oxidation
  • the tunneling layer may be a single layer structure or a multilayer stack structure of the above materials (for example, PbZr x Ti 1-x O 3 (PZT), Ba x Sr 1-x TiO 3 (BST)) or the like.
  • the memory layer is a dielectric material having charge trapping ability, such as SiN, SiON, HfO, ZrO, etc., and combinations thereof, and may also be a single layer structure or a multilayer stack structure of the above materials.
  • the barrier layer may be a single layer structure or a multilayer stack structure of a dielectric material such as silicon oxide, aluminum oxide, or cerium oxide.
  • the gate dielectric layer 5A is, for example, an ONO structure composed of silicon oxide, silicon nitride, or silicon oxide.
  • a channel layer 5B is formed on the bottom and sidewalls of the deep hole, and may be a single crystal, a polycrystalline, or an amorphous material.
  • a process such as MOCVD, MBE, ALD, CVD (LPCVD, PECVD, HDPCVD, UHVCVD) or the like may be employed, and the channel layer 5B material may be selected from a group IV element or compound, a group III-V or a group II-VI compound semiconductor such as Si. , Ge, SiGe, SiC, GeSn, InSn, InN, InP, GaN, GaP, GaSn, GaAs, etc., and combinations thereof.
  • the channel layer 5B is deposited in such a manner as to partially fill the sidewalls of the holes and form a hollow cylindrical shape having an air gap 5C.
  • the deposition of the channel layer 5B is selected to completely or partially fill the apertures to form a solid pillar, a hollow ring, or a hollow ring filled with an insulating layer (not shown). Core - shell structure.
  • the horizontal section of the channel layer 5B has a shape similar to that of the aperture and is preferably conformal, and may be a solid rectangle, a square, a diamond, a circle, a semicircle, an ellipse, a triangle, a pentagon, a pentagon, or a hexagon.
  • Various geometric shapes, octagons, etc., or hollow annular, barrel-like structures that evolved from the above-described geometric shapes (and the interior of which may be filled with an insulating layer).
  • the insulating layer 5C may be further filled inside the channel layer 5B, for example, a layer 5C of a silicon oxide material is formed by a process such as LPCVD, PECVD, HDPCVD, etc., for supporting and insulating.
  • the channel layer 5B is isolated.
  • the deposition thickness of the channel layer 5B is controlled such that the channel layer 5B of the semiconductor material is not only distributed in the trench but also grown on top of the dielectric stack 4A/4B for use as a lining for future memory strings.
  • the bottom draws out the structure.
  • the channel layer 5B has a second doping type, such as P+ or intrinsic non-doping, by ion implantation or in-situ doping.
  • a second dielectric stack 4A'/4B' is formed on the bottom storage string.
  • a second gate dielectric layer 5A' and a second channel layer 5B' are formed in the second dielectric stack 4A'/4B' in the same or similar process steps and materials as those shown in Fig. 2B.
  • the channel layer semiconductor material between adjacent strings will be fused to form a substrate contact layer to facilitate substrate contact extraction in the middle of the string, such that in an ultra-high stack, the substrate The distance between the holes reaching the upper and lower regions is reduced, and the rapid transfer of holes can be realized, and the performance and reliability of the memory erasing can be improved.
  • the separation can make
  • the lower selection tube is changed from the L-type to the vertical tube, which can further reduce the width of the selection tube gate electrode and increase the storage density of the storage array; and the design of the substrate in the middle section can truly realize that the storage array is located directly above the peripheral access circuit. Reduce the area of the entire memory chip and reduce costs.
  • the steps of FIG. 2B to FIG. 2E may be cycled to form an alternating stack of a plurality of dielectric stacks and a plurality of substrate contact layers (horizontal portions of the layer 5B) to further distribute the substrate contacts evenly, thereby further improving the reliability of the device. Sex.
  • a drain region (or bit line contact region) and an insulating layer are formed on top of the channel layer.
  • the material is the same as or similar to the channel layer 5B/5B' (for example, a material similar to Si, such as amorphous Si, polycrystalline Si, SiGe, SiC, etc., in order to fine-tune the lattice constant and improve carrier mobility, thereby
  • a material for controlling the driving performance of the cell device is deposited on top of the channel layer to form a drain region 5D of the memory device cell transistor.
  • the channel layer 5B is a completely filled solid structure, the portion of the channel layer 5B at the top of the device constitutes the corresponding drain region 5D without an additional drain region deposition step.
  • the drain region 5D may also be a metal, a metal nitride, or a metal silicide, forming a gold half-contact to form a Schottky-type device on top.
  • an insulating layer 6 (for example, an interlayer dielectric layer ILD, or a hard mask HM) is formed over the entire device.
  • the CMP planarizes the insulating layer 6.
  • the insulating layer 6 and the dielectric stack 4/4' are etched until the top of the ILD 2 of the peripheral access circuitry of the bottom is exposed, thereby exposing the sides of the dielectric stack.
  • An anisotropic etching process is performed using a photoresist mask pattern (not shown), which sequentially etches the insulating layer 6, the second dielectric stack 4A'/4B', the channel layer 5B, and the first dielectric stack 4A/4B Until the top of the ILD 2 of the peripheral access circuit is exposed, a plurality of vertical openings 6T are formed.
  • a plurality of vertical openings 6T will surround each of the vertical channels 5B/5C, for example, each vertical channel has an average of 2 to 6 vertical openings 6T around the periphery.
  • Sectional shape of the opening 6T The shape can be the same as the cross section of the deep hole or the channel layer.
  • the side of the opening 6T exposes the side walls of the first material layer 4A/4A' of the dielectric stack and the second material layer 4B/4B' to facilitate later etching to remove the second material layer.
  • the second material layers 4B, 4B' are selectively removed.
  • the isotropic etch process is selected to remove all of the second material layers 4B/4B' in the dielectric layer stack 4/4', leaving only a plurality of first material layers 4A/4A'.
  • the wet etching solution may be selected to etch the layer 4B isotropically. Specifically, an HF-based etching solution is used for the silicon oxide material, a hot phosphoric acid etching solution is used for the silicon nitride material, and a strong alkali etching solution such as KOH or TMAH is used for the polycrystalline silicon or the amorphous silicon material.
  • oxygen plasma dry etching may be used for carbon-based materials such as amorphous carbon and DLC, so that O and C react to form a gas and are extracted.
  • a control gate stack 7 is formed in a plurality of recesses, including an optional (possible or absent) gate dielectric layer 7A and a gate conductive layer 7B.
  • the layer 7A of high-k material or nitride is formed by a conventional method such as PVD, CVD, ALD, or the like, and may be a single layer structure or a multilayer stacked structure, and the nitride material is, for example, M x N y , M x Si y N z M x Al y N z , M a Al x Si y N z , wherein M is Ta, Ti, Hf, Zr, Mo, W or other elements.
  • the gate conductive layer 7B is formed by a process such as MOCVD, MBE, ALD, etc., and may be polysilicon, polysilicon, or metal, wherein the metal may include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta. a metal element such as Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, or an alloy of these metals and a nitride of these metals, and the gate electrode 7B may be doped with C, F, N, O , B, P, As and other elements to adjust the work function.
  • a floating gate (not shown) of polysilicon, amorphous silicon or the like may be formed in the recess before the control gate 7B is formed, and the control gate is formed after the insulating layer is deposited, so that the floating gate and the control gate Horizontally adjacent to improve gate control.
  • a substrate contact region is formed.
  • an additional insulating layer 6' is further formed to fill the opening 6T.
  • the insulating layer 6, the first material layer 4A' of the upper stage, and the gate stack 7A/7B are anisotropically etched by a photolithography/etching process to form a plurality of openings 6T' up to the exposed substrate contact layer 5B.
  • a substrate contact region 5E is formed in the substrate contact layer 5B by ion implantation, having a second doping type such as a p+ doped region formed by implanting B, BF 2 , Ga, Al, In.
  • the opening 6T' may be a deep hole formed by etching or a strip groove to be connected by a lead wire. In a top plan view (not shown), the openings 6T' are distributed around the vertical channel 5B, and the number may be plural, for example, 2, 4, 6, or the like.
  • a metal is formed in the opening 6T' to form a substrate contact line.
  • an insulating dielectric is first deposited and etched to remove the horizontal bottom, leaving a sidewall 8A, such as silicon oxide, silicon nitride, silicon oxynitride, on the sidewall of the opening 6T' for isolating the insulated gate conductive layer 7B.
  • the substrate contact line 8B is formed by MOCVD, ALD, evaporation, sputtering, etc. in the remaining space of the opening 6T', and the material is metal, metal alloy, conductive metal oxide/nitride/silicide, and the metal is selected from Co, Ni. Any one or a combination of Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, or the like.
  • the wiring of the memory array and the peripheral circuits is completed.
  • the insulating layer 6 is etched to form a hole exposing the drain portion 5D of the memory array device unit, and the insulating layer 6' is etched to form a deep hole exposing the top wiring of the peripheral access circuit, and the filling metal is deposited to form a connecting line 9 connecting the drain region or the peripheral wiring.
  • a wiring 10 (bit line wiring 10: BL, or substrate contact wiring 10: SB) is then formed on the entire device to electrically connect the peripheral access circuit to the memory array device unit.
  • FIG. 2L A cross-sectional view of the finally implemented device is shown in FIG. 2L, a three-dimensional semiconductor device including a plurality of memory cells on top of a peripheral circuit, each of the plurality of memory cells including: a common source region 3 between the memory cells and peripheral circuits a channel layer 5B distributed in a direction perpendicular to the surface of the substrate 1; a substrate contact layer 5B (a horizontal portion of the middle portion) extending horizontally from the middle of the channel layer 5B parallel to the surface of the substrate, including at least one substrate contact region 5E a plurality of insulating layers 4A on the sidewalls of the channel layer 5B; a plurality of control gates 7B sandwiched between adjacent insulating layers; a gate dielectric layer 5A/5A' located in the channel layer 5B and Between the control gates 7B; the drain region 5D, at the top of the channel layer 5B; the substrate contact lead-out line 8B, electrically connecting the substrate contact region 5E; the bit line wiring (9, 10), electrically connecting
  • the gate dielectric layer is divided into two parts, 5A and 5A', and the channel layer is also divided into upper and lower parts 5B and 5B', and the further channel filling layer is also divided into 5C and 5C'. Portions are separated by a substrate contact layer 5B.
  • 3A through 3F are cross-sectional views showing respective steps of a method of fabricating a three-dimensional semiconductor memory device in accordance with another embodiment of the present invention.
  • a peripheral circuit is formed on the substrate 1, and the ILD 2 is formed.
  • a common source region 3 is formed in the ILD 2, and A plurality of dielectric stacks 4A/4B are formed on the common source region 3, a substrate contact layer 5B1 is formed on the dielectric stack, and a plurality of dielectric stacks 4A'/4B' are further formed on the substrate contact layer 5B1.
  • a plurality of dielectric stacks and layers 5B1 are etched to form openings until the common source region 3 is exposed, and a vertical channel layer 5B2 is formed in the openings (preferably, a vertical channel layer)
  • the 5B2 material and the substrate contact layer 5B1 have the same material and doping type to facilitate subsequent substrate extraction of the transistor cell, the channel filling layer 5C, and the drain region 5D.
  • An insulating layer 6 of ILD is formed covering the entire device, and photolithography/etching forms a vertical opening until the top of the ILD 2 of the bottom peripheral circuitry is exposed.
  • the second material layer 4B/4B' is selectively etched away from the side of the vertical opening, leaving a recess between the first material layers 4A/4A'.
  • the gate dielectric layer 7A' and the gate conductive layer 7B are filled in the lateral grooves.
  • the gate dielectric layer 7A' is similar to the gate dielectric layer 5A in FIG. 2C, and also includes a plurality of sub-layer stack structures of a tunneling layer, a storage layer, and a barrier layer, and the layers are similar or identical in material.
  • the gate dielectric layer 7A' may also form a floating gate (not shown, which is equivalent to that described in FIG. 2I) near the inner side of the channel 5B2, and pass through the gate dielectric layer 7A with the gate conductive layer 7B. 'Insulation isolation.
  • the insulating layer 6, the first material layer 4A/4A', and the gate conductive layer 7B are etched until the substrate contact layer 5B1 (horizontal portion) is exposed, and ion implantation is performed.
  • a substrate contact region 5E is formed, and a substrate contact line 8B is formed.
  • bit line wirings (9, 10) are formed to electrically connect the drain region 5D of the memory cell and the top layer wiring of the peripheral circuit.
  • the device structure formed is similar to that of FIG. 2L, except that since the horizontal portion and the upper and lower layers of the substrate contact layer 5B1 are deposited first and then the channel is etched, the channel stack structure, 5B2, 5C will be connected until the common source region 3 is contacted. That is, the respective structural portions of the channel stack are connected in one body, and the substrate contact layer 5B1 horizontally surrounds the middle portion of the channel stack 5B2.
  • FIG. 3A to FIG. 3F may be equivalent to those shown in FIG. 2A to FIG. 2L, and details are not described herein again.
  • the substrate is formed in the middle of the memory string, so that in the ultra-high stack, the distance between the substrate holes reaching the upper and lower regions is reduced, and the rapid transmission of holes can be realized, and the performance and reliability of the memory erasing can be improved;
  • this separation can make the lower selection tube from L-shaped to vertical tube, which can further reduce the width of the selection tube gate electrode and increase the storage density of the storage array.
  • the design of the substrate in the middle section can truly realize the positiveness of the memory array located in the peripheral access circuit. Above, reduce the area of the entire memory chip and reduce costs.
  • substrate contact is formed in the middle of the memory string, the performance and reliability of the memory erasing are improved, the memory density of the memory array is increased, the area of the entire memory chip is reduced, and the cost is reduced.

Abstract

一种三维半导体器件，包括：外围电路，分布在衬底（1）上；多个存储单元，在外围电路之上，每一个包括：共源区（3），在存储单元与外围电路之间；沟道层（5B），沿垂直于衬底（1）表面的方向分布；至少一个衬底接触层，从沟道层（5B）中部平行于衬底（1）表面水平延伸，每个包括至少一个衬底接触区；多个绝缘层，位于沟道层（5B）的侧壁上；多个控制栅极，夹设在相邻的绝缘层之间；栅极介质层（5A），位于沟道层（5B）与控制栅极之间；漏区（5D），在沟道层（5B）顶部；衬底接触引出线，电连接衬底接触区；以及位线布线，电连接每个存储单元的漏区（5D）与外围电路。在存储串的中段形成衬底接触，提高存储器擦写的性能和可靠性，提高存储阵列的存储密度，减少整个存储芯片的面积，降低成本。

Description

三维半导体器件及其制造方法 技术领域
本发明涉及一种半导体器件及其制造方法，特别是涉及一种三维半导体存储器件及其制造方法。
背景技术
为了改善存储器件的密度，业界已经广泛致力于研发减小二维布置的存储器单元的尺寸的方法。随着二维(2D)存储器件的存储器单元尺寸持续缩减，信号冲突和干扰会显著增大，以至于难以执行多电平单元(MLC)操作。为了克服2D存储器件的限制，业界已经研发了具有三维(3D)结构的存储器件，通过将存储器单元三维地布置在衬底之上来提高集成密度。
具体地，如图1A所示，可以首先在衬底上沉积多层叠层结构(例如氧化物和氮化物交替的多个ONO结构)；通过各向异性的刻蚀工艺对衬底上多层叠层结构刻蚀而形成沿着存储器单元字线(WL)延伸方向分布、垂直于衬底表面的多个沟道通孔(可直达衬底表面或者具有一定过刻蚀)；在沟道通孔中沉积多晶硅等材料形成柱状沟道；沿着WL方向刻蚀多层叠层结构形成直达衬底的沟槽，露出包围在柱状沟道周围的多层叠层；湿法去除叠层中的某一类型材料(例如热磷酸去除氮化硅，或HF去除氧化硅)，在柱状沟道周围留下横向分布的突起结构；在沟槽中突起结构的侧壁沉积栅极介质层(例如高k介质材料)以及栅极导电层(例如Ti、W、Cu、Mo等)形成栅极堆叠，，例如包括底部选择栅极线BSG、虚设栅极线DG、字线WL0～WL31、顶部选择栅极线TSG；垂直各向异性刻蚀去除突起侧平面之外的栅极堆叠，直至露出突起侧面的栅极介质层；刻蚀叠层结构形成源漏接触并完成后端制造工艺。此时，叠层结构在柱状沟道侧壁留下的一部分突起形成了栅电极之间的隔离层，而留下的栅极堆叠夹设在多个隔离层之间作为控制电极。当向栅极施加电压时，栅极的边缘电场会使得 例如多晶硅材料的柱状沟道侧壁上感应形成源漏区，由此构成多个串并联的MOSFET构成的门阵列而记录所存储的逻辑状态。
然而，这种高密度三维半导体存储器存在布线的难题。如图1B的顶视图所示，传统的闪存芯片中，外围访问电路与存储阵列区域在同一个平面，占据整个Die面积的20-40％。对于高密度存储器来说，压缩外围访问电路的面积成为闪存设计的关键议题。在图1A所示的3D NAND存储器中，尽管可以通过增加闪存的层数来提高密度，但是外围访问电路面积的减少一直比较困难。特别是对于基于空穴擦除的TCAT结构来说，因为衬底的存在，很难如图1C顶视图所示把存储阵列区域集成在外围访问电路的上方来减少外围电路占用的面积。
发明内容
由上所述，本发明的目的在于克服上述技术困难，提出一种创新性三维半导体存储器件及其制造方法。
为此，本发明一方面提供了一种三维半导体器件，包括：外围电路，分布在衬底上；多个存储单元，在外围电路之上，每一个包括：共源区，在存储单元与外围电路之间；沟道层，沿垂直于衬底表面的方向分布；至少一个衬底接触层，从沟道层中部平行于衬底表面水平延伸，每个包括至少一个衬底接触区；多个绝缘层，位于沟道层的侧壁上；多个控制栅极，夹设在相邻的绝缘层之间；栅极介质层，位于沟道层与控制栅极之间；漏区，在沟道层顶部；衬底接触引出线，电连接衬底接触区；以及位线布线，电连接每个存储单元的漏区与外围电路。
其中，沟道层由衬底接触层分隔为多段；任选地，沟道层平行于衬底表面的截面形状包括选自矩形、方形、菱形、圆形、半圆形、椭圆形、三角形、五边形、五角形、六边形、八边形及其组合的几何形状，以及包括选自所述几何形状演化得到的实心几何图形、空心环状几何图形、或者空心环状外围层与绝缘层中心的组合图形；任选地，沟道层为单晶、多晶、微晶或非晶层且材料选自IV族单质、IV族化合物、III-V族化合物、II-VI族化合物半导体的，例如为单晶Si、非晶Si、多晶Si、微晶Si、单晶Ge、SiGe、Si:C、SiGe:C、SiGe:H、GeSn、InSn、InN、InP、GaN、GaP、GaSn、GaAs的任一种或其组合，优 选地进一步包括材料为空气或氧化物、氮化物的沟道填充层。
其中，栅极介质层进一步包括隧穿层、存储层、阻挡层；优选地，隧穿层包括SiO2或高k材料的单层结构或多层堆叠结构；优选地，存储层是具有电荷俘获能力的介质材料的单层结构或多层堆叠结构，例如SiN、SiON、HfO、ZrO的任一种及其组合；优选地，阻挡层是氧化硅、氧化铝、氧化铪等介质材料的单层结构或多层堆叠结构。
其中，控制栅极材料选自掺杂多晶硅、掺杂单晶硅、金属、金属合金、导电金属氧化物、导电金属氮化物、导电金属硅化物的任一种或其组合；任选地，相邻的绝缘层之间进一步包括经由绝缘层和/或栅极介质层与控制栅极水平相邻的浮栅。
其中，共源区包括掺杂多晶硅、掺杂单晶硅、金属硅化物、金属氮化物的任一种或其组合；优选地，共源区具有与沟道层和/或衬底接触区不同的导电类型。
本发明还提供了一种三维半导体器件制造方法，包括步骤：
a、在衬底上形成外围电路；
b、在外围电路上形成共源区；
c、形成第一材料层与第二材料层交替构成的绝缘层堆叠；
d、刻蚀绝缘层堆叠形成多个垂直的开口，在开口侧壁形成栅极介质层，在开口侧壁以及绝缘层堆叠顶部形成沟道层；
e、循环步骤c和d，相邻的绝缘层堆叠顶部的沟道层构成至少一个衬底接触层；
f、在沟道层顶部形成漏区；
g、选择性刻蚀去除第二材料层，在留下的第一材料层之间形成控制栅极；
h、刻蚀第一材料层和控制栅极形成暴露衬底接触层的开口，在开口底部形成衬底接触区，在开口中形成衬底接触引出线；
i、形成位线布线，电连接漏区与外围电路。
本发明进一步提供了一种三维半导体器件制造方法，包括步骤：
a、在衬底上形成外围电路；
b、在外围电路上形成共源区；
c2、在共源区上形成第一材料层与第二材料层交替构成的多个绝缘层堆叠，并且相邻绝缘层堆叠之间形成至少一个衬底接触层；
d2、刻蚀多个绝缘层堆叠和至少一个衬底接触层形成多个垂直的开口；
e2、在开口侧壁以及绝缘层堆叠顶部形成沟道层；
f、在沟道层顶部形成漏区；
g2、选择性刻蚀去除第二材料层，在留下的第一材料层之间形成栅级介质层和控制栅极；
h、刻蚀第一材料层和控制栅极形成暴露衬底接触层的开口，在开口底部形成衬底接触区，在开口中形成衬底接触引出线；
i、形成位线布线，电连接漏区与外围电路。
其中，步骤b进一步包括：刻蚀外围电路上的ILD形成凹槽，填充掺杂半导体或导体形成共源区，平坦化共源区直至暴露ILD；或者在外围电路上沉积并刻蚀形成掺杂半导体或导体的共源区，形成ILD覆盖共源区，平坦化ILD直至暴露共源区。
其中，步骤g或g2进一步包括：选择性刻蚀去除第二材料层，在留下的第一材料层之间留下横向凹槽，在横向凹槽中形成浮栅，在浮栅上形成绝缘层和/或栅极介质层，在横向凹槽中绝缘层和/或栅极介质层上形成控制栅极。
其中，在步骤h中，执行离子注入形成衬底接触区；优选地，衬底接触区与共源区导电类型不同。
依照本发明的三维半导体存储器件及其制造方法，依照本发明的三维半导体存储器件及其制造方法，在存储串的中段形成衬底接触，提高存储器擦写的性能和可靠性，提高存储阵列的存储密度，减少整个存储芯片的面积，降低成本。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1A为现有技术的三维半导体存储器件的剖视图；
图1B为现有技术的闪存芯片布局顶视图；
图1C为有待实现的芯片布局顶视图；
图2A至图2L为依照本发明一个实施例的三维半导体存储器件制造方法的各个步骤的剖视图；以及
图3A至图3F为依照本发明另一实施例的三维半导体存储器件制 造方法的各个步骤的剖视图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果，公开了有效提高存储密度的三维半导体存储器件及其制造方法。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”等等可用于修饰各种器件结构或制造工序。这些修饰除非特别说明并非暗示所修饰器件结构或制造工序的空间、次序或层级关系。
图2A至图2L示出了依照本发明一个实施例的三维半导体存储器件制造方法的各个步骤的剖视图。
如图2A所示，在芯片衬底1上形成外围访问电路。提供衬底1，其材质可以包括体硅(bulk Si)、体锗(bulk Ge)、绝缘体上硅(SOI)、绝缘体上锗(GeOI)或者是其他化合物半导体衬底，例如SiGe、SiC、GaN、GaAs、InP等等，以及这些物质的组合。为了与现有的IC制造工艺兼容，衬底1优选地为含硅材质的衬底，例如Si、SOI、SiGe、Si:C等。通过CMOS兼容的平面工艺，在衬底1中和/或上形成外围访问电路，图2A中示出具有源漏区、栅极堆叠(包括栅极介质层和栅极导电层)、接触布线等(均未单独标出)。随后通过CVD、旋涂、喷涂、丝网印刷、热解、氧化等工艺，形成氧化硅或低k材料的层间介质层(ILD)或多晶硅间介质层(IPD)2，低k材料包括但不限于有机低k材料(例如含芳基或者多元环的有机聚合物)、无机低k材料(例如无定形碳氮薄膜、多晶硼氮薄膜、氟硅玻璃、BSG、PSG、BPSG)、多孔低k材料(例如二硅三氧烷(SSQ)基多孔低k材料、多孔二氧化硅、多孔SiOCH、掺C二氧化硅、掺F多孔无定形碳、多孔金刚石、多孔有机聚合物)。优选地，CMP平坦化ILD 2。ILD 2厚度大于外围访问电路的最顶层布线高度，例如超过最顶层布线高度100nm～10μm，以便为后续器件的源极留下空间。
如图2B所示，在外围访问电路的ILD 2顶部形成存储阵列器件单元的源区3，以及多层薄膜的堆叠4A/4B。
在本发明一个优选实施例中，可以通过光刻/刻蚀工艺在ILD 2顶部形成凹槽并随后通过CVD、PVD成膜工艺填充掺杂半导体或导体 材料形成存储器件的共源区3；或者通过在ILD 2顶部通过成膜工艺形成掺杂半导体或导体材料薄膜、刻蚀形成共源区3图形、并随后继续形成氧化硅或低k材料(与ILD 2合而为一)以包围共源区3。共源区3的材料例如掺杂多晶硅、掺杂单晶硅，具有第一掺杂类型，例如N+(或者P+)，还可以进一步在(顶)表面包括金属硅化物(CoSix、NiSix、PtSix等)以减小接触电阻，或者包括金属氮化物(WN、TiN、TaN等)以阻挡Al、Cu等金属离子扩散影响器件性能并且改善粘附性。优选地，CMP平坦化共源区3直至暴露ILD 2，或者CMP平坦化ILD 2(包括共源区3形成之后形成的ILD材料)直至暴露共源区3，总之使得ILD 2与共源区3顶部齐平。
随后，在ILD 2/共源区3顶部上形成多层绝缘介质薄膜的堆叠结构4，包括交替层叠的多个第一材料层4A和多个第二材料层4B。堆叠结构4的材料选自以下材料的组合并且至少包括一种绝缘介质：如氧化硅、氮化硅、氮氧化硅、非晶碳、类金刚石无定形碳(DLC)、氧化锗、氧化铝、等及其组合。第一材料层4A具有第一刻蚀选择性，第二材料层4B具有第二刻蚀选择性并且不同于第一刻蚀选择性。在本发明一个优选实施例中，叠层结构4A/4B的组合例如氧化硅与氮化硅的组合、氧化硅或氮化硅与非晶碳的组合等等。在本发明一个优选实施例中，层4A与层4B在湿法腐蚀条件或者在氧等离子干法刻蚀条件下具有较大的刻蚀选择比(例如大于5:1)。
如图2C所示，在堆叠结构中形成栅极介质层和沟道层。
选择各向异性刻蚀工艺，例如选用碳氟基(CxHyFz构成氟代烃)作为刻蚀气体的等离子体干法刻蚀或RIE，垂直向下刻蚀绝缘层堆叠4A/4B形成深孔或沟槽(未示出)，直至暴露共源区3。平行于衬底1表面切得的沟槽的截面形状可以为矩形、方形、菱形、圆形、半圆形、椭圆形、三角形、五边形、五角形、六边形、八边形等等各种几何形状。
采用PECVD、HDPCVD、UHVCVD、MOCVD、MBE、ALD等工艺，在深孔中依次沉积形成栅极介质层5A和沟道层5B。栅极介质层5A可以包括单层或多子层结构，例如至少包括隧穿层、存储层、阻挡层，阻挡层直接接触深孔侧壁的绝缘层堆叠4A/4B，隧穿层最靠近深孔中心轴线并接触后续沉积的沟道层。其中隧穿层包括SiO2或 高k材料，其中高k材料包括但不限于氮化物(例如SiN、AlN、TiN)、金属氧化物(主要为副族和镧系金属元素氧化物，例如MgO、Al2O3、Ta2O5、TiO2、ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3)、氮氧化物(如SiON、HfSiON)、钙钛矿相氧化物(例如PbZrxTi1-xO3(PZT)、BaxSr1-xTiO3(BST))等，隧穿层可以是上述材料的单层结构或多层堆叠结构。存储层是具有电荷俘获能力的介质材料，例如SiN、SiON、HfO、ZrO等及其组合，同样可以是上述材料的单层结构或多层堆叠结构。阻挡层可以是氧化硅、氧化铝、氧化铪等介质材料的单层结构或多层堆叠结构。在本发明一个实施例中，栅极介质层5A例如是氧化硅、氮化硅、氧化硅组成的ONO结构。
在深孔底部和侧壁上形成沟道层5B，可以为单晶、多晶、或非晶材料。可以采用工艺例如MOCVD、MBE、ALD、CVD(LPCVD、PECVD、HDPCVD、UHVCVD)等，沟道层5B材料可以选自IV族单质或化合物、III-V族或II-VI族化合物半导体，诸如Si、Ge、SiGe、SiC、GeSn、InSn、InN、InP、GaN、GaP、GaSn、GaAs等及其组合。在本发明一个实施例中，沟道层5B的沉积方式为局部填充孔槽的侧壁而形成为具有空气隙5C的中空柱形。在本发明图中未示出的其他实施例中，选择沟道层5B的沉积方式以完全或者局部填充孔槽，形成实心柱、空心环、或者空心环内填充绝缘层(未示出)的核心-外壳结构。沟道层5B的水平截面的形状与孔槽类似并且优选地共形，可以为实心的矩形、方形、菱形、圆形、半圆形、椭圆形、三角形、五边形、五角形、六边形、八边形等等各种几何形状，或者为上述几何形状演化得到的空心的环状、桶状结构(并且其内部可以填充绝缘层)。优选地，对于空心的柱状沟道层5B结构，可以进一步在沟道层5B内侧填充绝缘隔离层5C，例如通过LPCVD、PECVD、HDPCVD等工艺形成例如氧化硅材质的层5C，用于支撑、绝缘并隔离沟道层5B。如图2C所示，控制沟道层5B的沉积厚度，使得半导体材料的沟道层5B不仅分布在沟槽中，而且进一步生长在介质堆叠4A/4B的顶部，以便用作未来存储串的衬底引出结构。优选地，沟道层5B通过离子注入或者原位掺杂具有第二掺杂类型，例如P+或者本征非掺杂。
如图2D所示，以与图2B所示相同或类似的工艺步骤和材料，在 底部存储串上形成第二介质堆叠4A’/4B’。
如图2E所示，以与图2B所示相同或类似的工艺步骤和材料，在第二介质堆叠4A’/4B’中形成第二栅极介质层5A’和第二沟道层5B’。如图2E所示，相邻存储串之间的沟道层半导体材料将融合相接，形成衬底接触层以便于在存储串的中段形成衬底接触引出，这样在超高堆栈中，衬底空穴到达上下区域的距离减少，可以实现空穴的快速传输，提高存储器擦写的性能和可靠性；同时，代替传统3D NAND中衬底和源区都在下段的思路，这种分离可以使得下选择管从L型转为垂直管，这样可以进一步减少选择管栅电极的宽度，提高存储阵列的存储密度；而且衬底在中段的设计，可以真正实现存储阵列位于外围访问电路的正上方，减少整个存储芯片的面积，降低成本。进一步的，可以循环图2B～图2E的步骤，形成多个介质堆叠与多个衬底接触层(层5B水平部分)的交替堆叠，以使得衬底接触进一步分布均匀，从而进一步提高器件的可靠性。
如图2F所示，在沟道层顶部形成漏区(或称位线接触区)和绝缘层。优选地，采用与沟道层5B/5B’材质相同或者相近(例如与Si相近的材质非晶Si、多晶Si、SiGe、SiC等，以便微调晶格常数而提高载流子迁移率，从而控制单元器件的驱动性能)的材质沉积在沟道层的顶部而形成存储器件单元晶体管的漏区5D。自然，如果沟道层5B为完全填充的实心结构，则沟道层5B在整个器件顶部的部分则构成相应的漏区5D而无需额外的漏区沉积步骤。在本发明其他实施例中，漏区5D也可以为金属、金属氮化物、金属硅化物，构成金半接触而在顶部形成肖特基型器件。接着，在整个器件之上形成绝缘层6(例如层间介质层ILD，或者硬掩模HM)。优选地，CMP平坦化绝缘层6。
如图2G所示，刻蚀绝缘层6和介质堆叠4/4’，直至暴露底部的外围访问电路的ILD 2顶部，从而暴露介质堆叠的侧面。利用光刻胶掩模图形(未示出)执行各向异性刻蚀工艺，依次垂直刻蚀绝缘层6、第二介质堆叠4A’/4B’、沟道层5B、第一介质堆叠4A/4B，直至暴露外围访问电路的ILD 2顶部，形成多个垂直开口6T。在平面图(未示出)中，多个垂直开口6T将围绕每一个垂直沟道5B/5C，例如每个垂直沟道平均具有2～6个垂直开口6T围绕周边。开口6T的截面形 状可以与深孔或沟道层截面相同。开口6T侧面暴露了介质堆叠的第一材料层4A/4A’、和第二材料层4B/4B’的侧壁，以利于稍后刻蚀去除第二材料层。
如图2H所示，选择性去除第二材料层4B、4B’。选用各向同性刻蚀工艺，去除介质层堆叠4/4’中的所有第二材料层4B/4B’，仅保留多个第一材料层4A/4A’。根据层4A/层4B的材质不同，可以选择湿法腐蚀液以各向同性地刻蚀去除层4B。具体地，针对氧化硅材质采取HF基腐蚀液，针对氮化硅材质采用热磷酸腐蚀液，针对多晶硅或非晶硅材质采用KOH或TMAH等强碱腐蚀液。另外还可以针对非晶碳、DLC等碳基材质而选用氧等离子干法刻蚀，使得O与C反应形成气体而抽出。去除第二材料层4B、4B’之后，在多个第一材料层4A、4A’之间留下了横向(平行于衬底表面的水平方向)的多个凹槽，以用于稍后形成控制栅极(或称字线WL)。
如图2I所示，在多个凹槽中形成控制栅极堆叠7，包括任选的(可以存在或不存在)栅极介质层7A以及栅极导电层7B。优选通过PVD、CVD、ALD等常规方法形成高k材料或氮化物的层7A，可以是单层结构也可以是多层堆叠结构，氮化物材质例如为MxNy、MxSiyNz、MxAlyNz、MaAlxSiyNz，其中M为Ta、Ti、Hf、Zr、Mo、W或其它元素。通过MOCVD、MBE、ALD等工艺形成栅极导电层7B，可以是多晶硅、多晶锗硅、或金属，其中金属可包括Co、Ni、Cu、Al、Pd、Pt、Ru、Re、Mo、Ta、Ti、Hf、Zr、W、Ir、Eu、Nd、Er、La等金属单质、或这些金属的合金以及这些金属的氮化物，栅电极7B中还可掺杂有C、F、N、O、B、P、As等元素以调节功函数。
任选地，形成控制栅极7B之前可以在凹槽中先形成多晶硅、非晶硅等材料的浮栅(未示出)，沉积绝缘层之后再形成控制栅极，使得浮栅与控制栅极水平相邻，提高栅极控制能力。
如图2J所示，形成衬底接触区。优选地，进一步形成额外的绝缘层6’填充开口6T。通过光刻/刻蚀工艺，各向异性刻蚀绝缘层6、上段的第一材料层4A’、栅极堆叠7A/7B，形成多个开口6T’直至暴露中段的衬底接触层5B。通过离子注入，在衬底接触层5B中形成衬底接触区5E，具有第二掺杂类型，例如注入B、BF2、Ga、Al、In形成的p+掺杂区。开口6T’可以是刻蚀形成的深孔，也可以是条状沟槽以 通过引出线连接。在顶视平面图中(未示出)，开口6T’分布在垂直沟道5B周围，数目可以为多个，例如2个、4个、6个等。
如图2K所示，在开口6T’中填充金属形成衬底接触线。例如先沉积绝缘介质并刻蚀去除水平底部，在开口6T’侧壁留下侧墙8A，例如氧化硅、氮化硅、氮氧化硅，用于隔离绝缘栅极导电层7B。随后在开口6T’剩余空间内通过MOCVD、ALD、蒸发、溅射等工艺形成衬底接触线8B，材料为金属、金属合金、导电金属氧化物/氮化物/硅化物，金属选自Co、Ni、Cu、Al、Pd、Pt、Ru、Re、Mo、Ta、Ti、Hf、Zr、W、Ir、Eu、Nd、Er、La等任一种或其组合。
最后，如图2L所示，完成存储阵列与外围电路的布线。刻蚀绝缘层6形成暴露存储阵列器件单元漏区5D的孔，并刻蚀绝缘层6’形成暴露外围访问电路顶部布线的深孔，沉积填充金属形成连接漏区或外围布线的连接线9。随后在整个器件顶部形成布线10(位线布线10:BL，或衬底接触布线10:SB)，将外围访问电路与存储阵列器件单元电连接。
最终实现的器件剖视图如图2L所示，一种三维半导体器件，包括在外围电路顶部的多个存储单元，多个存储单元的每一个包括：共源区3，在存储单元与外围电路之间；沟道层5B，沿垂直于衬底1表面的方向分布；衬底接触层5B(中段水平部分)，从沟道层5B中部平行于衬底表面水平延伸，包括至少一个衬底接触区5E；多个绝缘层4A，位于沟道层5B的侧壁上；多个控制栅极7B，夹设在相邻的绝缘层之间；栅极介质层5A/5A’，位于沟道层5B与控制栅极7B之间；漏区5D，在沟道层5B顶部；衬底接触引出线8B，电连接衬底接触区5E；位线布线(9、10)，电连接存储单元的漏区5D与外围电路的顶层布线。其中，由于上下两段分开沉积，因此栅极介质层分为5A、5A’两部分，沟道层也分为上下5B、5B’两部分，进一步沟道填充层也分为5C、5C’两部分，均由衬底接触层5B分隔开。
图3A至图3F为依照本发明另一实施例的三维半导体存储器件制造方法的各个步骤的剖视图。
如图3A所示，类似于或等同于图2A，在衬底1上形成外围电路，并形成ILD 2。
如图3B所示，类似于图2B工艺，在ILD 2中形成共源区3，并 在共源区3上形成多个介质堆叠4A/4B，在介质堆叠上形成衬底接触层5B1，并在衬底接触层5B1上进一步形成多个介质堆叠4A’/4B’。
如图3C所示，类似于图2E～2H的工艺，刻蚀多个介质堆叠和层5B1形成开口直至暴露共源区3，在开口中形成垂直沟道层5B2(优选地，垂直沟道层5B2材质与衬底接触层5B1材质和掺杂类型相同，以便于后续能实现晶体管单元的衬底引出)、沟道填充层5C，并沉积漏区5D。形成ILD的绝缘层6，覆盖整个器件，光刻/刻蚀形成垂直开口直至暴露底部外围电路的ILD 2顶部。从垂直开口的侧面选择性刻蚀去除第二材料层4B/4B’，留下第一材料层4A/4A’之间的凹槽。
如图3D所示，在横向凹槽中填充栅极介质层7A’和栅极导电层7B。其中，栅极介质层7A’类似于图2C中的栅极介质层5A，也包括隧穿层、存储层、阻挡层的多个子层堆叠结构，各层材质类似或相同。此外，栅极介质层7A’靠近沟道5B2的内侧也可以先形成浮栅(未示出，材质等同于描述图2I时所述)，与栅极导电层7B之间通过栅极介质层7A’绝缘隔离。
如图3E所示，类似于图2J、图2K工艺，刻蚀绝缘层6、第一材料层4A/4A’、栅极导电层7B，直至暴露衬底接触层5B1(水平部分)，离子注入形成衬底接触区5E，并形成衬底接触线8B。
最后如图3F所示，类似于图2L工艺，形成位线布线(9、10)，电连接存储单元的漏区5D与外围电路的顶层布线。形成的器件结构类似于图2L，区别在于由于先沉积衬底接触层5B1水平部分与上下两层然后在刻蚀填充沟道，因此沟道堆叠结构、5B2、5C将连通直至接触共源区3，也即沟道堆叠各个结构部分联通一体，衬底接触层5B1水平包围了沟道堆叠5B2的中部。
图3A～图3F其余各个工艺步骤和材料可以等同于图2A～图2L所示，在此不再赘述。
本发明中，衬底在存储串的中段形成，这样在超高堆栈中，衬底空穴到达上下区域的距离减少，可以实现空穴的快速传输，提高存储器擦写的性能和可靠性；同时，代替传统3D NAND中衬底和源区都在下段的思路，这种分离可以使得下选择管从L型转为垂直管，这样可以进一步减少选择管栅电极的宽度，提高存储阵列的存储密度；而且衬底在中段的设计，可以真正实现存储阵列位于外围访问电路的正 上方，减少整个存储芯片的面积，降低成本。
值得注意的是，虽然本发明实施例附图仅示出了一个衬底接触层将沟道层分为上下两部分，但是也可以采用多个衬底接触层将沟道层分为三段、四段、五段或更多段。此外，虽然附图示出了存储器阵列单元在外围电路正上方并至少部分地或完全重叠，但是也可以在外围电路的周边，只要使得衬底接触层5B水平部分与共源区3、漏区5D位于不同平面上。
依照本发明的三维半导体存储器件及其制造方法，在存储串的中段形成衬底接触，提高存储器擦写的性能和可靠性，提高存储阵列的存储密度，减少整个存储芯片的面积，降低成本。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对器件结构或方法流程做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (10)

  1. 一种三维半导体器件，包括：
    外围电路，分布在衬底上；
    多个存储单元，在外围电路之上，每一个包括：
    共源区，在存储单元与外围电路之间；
    沟道层，沿垂直于衬底表面的方向分布；
    至少一个衬底接触层，从沟道层中部平行于衬底表面水平延伸，每个包括至少一个衬底接触区；
    多个绝缘层，位于沟道层的侧壁上；
    多个控制栅极，夹设在相邻的绝缘层之间；
    栅极介质层，位于沟道层与控制栅极之间；
    漏区，在沟道层顶部；
    衬底接触引出线，电连接衬底接触区；以及
    位线布线，电连接每个存储单元的漏区与外围电路。
  2. 如权利要求1的三维半导体器件，其中，沟道层由衬底接触层分隔为多段；任选地，沟道层平行于衬底表面的截面形状包括选自矩形、方形、菱形、圆形、半圆形、椭圆形、三角形、五边形、五角形、六边形、八边形及其组合的几何形状，以及包括选自所述几何形状演化得到的实心几何图形、空心环状几何图形、或者空心环状外围层与绝缘层中心的组合图形；任选地，沟道层为单晶、多晶、微晶或非晶层且材料选自IV族单质、IV族化合物、III--V族化合物、II--VI族化合物半导体的，例如为单晶Si、非晶Si、多晶Si、微晶Si、单晶Ge、SiGe、Si:C、SiGe:C、SiGe:H、GeSn、InSn、InN、InP、GaN、GaP、GaSn、GaAs的任一种或其组合，优选地进一步包括材料为空气或氧化物、氮化物的沟道填充层。
  3. 如权利要求1的三维半导体器件，其中，栅极介质层进一步包括隧穿层、存储层、阻挡层；优选地，隧穿层包括SiO2或高k材料的单层结构或多层堆叠结构；优选地，存储层是具有电荷俘获能力的介质材料的单层结构或多层堆叠结构，例如SiN、SiON、HfO、ZrO的任一种及其组合；优选地，阻挡层是氧化硅、氧化铝、氧化铪等介质材料的单层结构或多层堆叠结构。
  4. 如权利要求1的三维半导体器件，其中，控制栅极材料选自掺杂多晶硅、掺杂单晶硅、金属、金属合金、导电金属氧化物、导电金属氮化物、导电金属硅化物的任一种或其组合；任选地，相邻的绝缘层之间进一步包括经由绝缘层和/或栅极介质层与控制栅极水平相邻的浮栅。
  5. 如权利要求1的三维半导体器件，其中，共源区包括掺杂多晶硅、掺杂单晶硅、金属硅化物、金属氮化物的任一种或其组合；优选地，共源区具有与沟道层和/或衬底接触区不同的导电类型。
  6. 一种三维半导体器件制造方法，包括步骤：
    a、在衬底上形成外围电路；
    b、在外围电路上形成共源区；
    c、形成第一材料层与第二材料层交替构成的绝缘层堆叠；
    d、刻蚀绝缘层堆叠形成多个垂直的开口，在开口侧壁形成栅极介质层，在开口侧壁以及绝缘层堆叠顶部形成沟道层；
    e、循环步骤c和d，相邻的绝缘层堆叠顶部的沟道层构成至少一个衬底接触层；
    f、在沟道层顶部形成漏区；
    g、选择性刻蚀去除第二材料层，在留下的第一材料层之间形成控制栅极；
    h、刻蚀第一材料层和控制栅极形成暴露衬底接触层的开口，在开口底部形成衬底接触区，在开口中形成衬底接触引出线；
    i、形成位线布线，电连接漏区与外围电路。
  7. 一种三维半导体器件制造方法，包括步骤：
    a、在衬底上形成外围电路；
    b、在外围电路上形成共源区；
    c2、在共源区上形成第一材料层与第二材料层交替构成的多个绝缘层堆叠，并且相邻绝缘层堆叠之间形成至少一个衬底接触层；
    d2、刻蚀多个绝缘层堆叠和至少一个衬底接触层形成多个垂直的开口；
    e2、在开口侧壁以及绝缘层堆叠顶部形成沟道层；
    f、在沟道层顶部形成漏区；
    g2、选择性刻蚀去除第二材料层，在留下的第一材料层之间形成栅级 介质层和控制栅极；
    h、刻蚀第一材料层和控制栅极形成暴露衬底接触层的开口，在开口底部形成衬底接触区，在开口中形成衬底接触引出线；
    i、形成位线布线，电连接漏区与外围电路。
  8. 如权利要求6或7的三维半导体器件制造方法，其中，步骤b进一步包括：刻蚀外围电路上的ILD形成凹槽，填充掺杂半导体或导体形成共源区，平坦化共源区直至暴露ILD；或者在外围电路上沉积并刻蚀形成掺杂半导体或导体的共源区，形成ILD覆盖共源区，平坦化ILD直至暴露共源区。
  9. 如权利要求6或7的三维半导体器件制造方法，其中，步骤g或g2进一步包括：选择性刻蚀去除第二材料层，在留下的第一材料层之间留下横向凹槽，在横向凹槽中形成浮栅，在浮栅上形成绝缘层和/或栅极介质层，在横向凹槽中绝缘层和/或栅极介质层上形成控制栅极。
  10. 如权利要求6或7的三维半导体器件制造方法，其中，在步骤h中，执行离子注入形成衬底接触区；优选地，衬底接触区与共源区导电类型不同。
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