WO2017065221A1 - 正弦波乗算装置とこれを有する入力装置 - Google Patents
正弦波乗算装置とこれを有する入力装置 Download PDFInfo
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- WO2017065221A1 WO2017065221A1 PCT/JP2016/080397 JP2016080397W WO2017065221A1 WO 2017065221 A1 WO2017065221 A1 WO 2017065221A1 JP 2016080397 W JP2016080397 W JP 2016080397W WO 2017065221 A1 WO2017065221 A1 WO 2017065221A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/06—Arrangements for sorting, selecting, merging, or comparing data on individual record carriers
- G06F7/14—Merging, i.e. combining at least two sets of record carriers each arranged in the same ordered sequence to produce a single set having the same ordered sequence
- G06F7/16—Combined merging and sorting
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
- G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/00006—Changing the frequency
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0416—Control or interface arrangements specially adapted for digitisers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
Definitions
- the present invention relates to a sine wave multiplication device that multiplies an input signal by a sine wave and an input device having the same.
- the Gilbert cell type analog multiplier has been put into practical use, for example, with the configuration shown in FIG.
- the thermal voltage VT is included as a coefficient in the multiplication result, as shown in the equations (14) and (20) of Patent Document 1.
- the thermal voltage VT is expressed by “k ⁇ T / q”, where k is a Boltzmann constant, T is an absolute temperature, and q is an elementary charge of an electron. Therefore, the multiplication result of the Gilbert cell, that is, the output voltage changes depending on the temperature.
- analog multiplier it is necessary to limit the range of the input voltage in order to ensure the multiplication accuracy due to the nonlinearity of the input / output characteristics of the transistor. For this reason, for example, when an analog multiplier is used in a capacitance type input device, securing a dynamic range of a signal and fluctuation due to temperature are problems.
- sine wave multiplication is performed using an analog multiplier, it is necessary to generate a sine wave separately. Therefore, for example, in order to perform high-precision signal extraction by multiplying the input signal by a sine wave, it is necessary to generate a high-precision sine wave, which increases the circuit scale for generating a sine wave and reduces power consumption. There is a problem that increases.
- the present invention has been made in view of such circumstances, and an object of the present invention is to provide a sine wave multiplication device having a simple configuration, a wide range of input signal levels, and a small variation in characteristics due to temperature.
- a first aspect of the present invention is a sine wave multiplier that multiplies a differential signal by a sine wave having a predetermined frequency, which is different from a first input terminal and a second input terminal to which the input signal is input.
- a plurality of square wave multipliers for multiplying the input signal by a square wave of frequency; and a signal synthesizer for combining signals of multiplication results in the plurality of square wave multipliers.
- the square wave can be approximated as the sum of a fundamental wave that is a sine wave having the lowest frequency and a plurality of harmonics that are sine waves each having an integer multiple of the fundamental wave.
- the plurality of square wave multipliers are included in the first square wave, and one first square wave multiplier that multiplies the input signal by a first square wave having the sine wave of the predetermined frequency as the fundamental wave.
- One or more second square waves that multiply the input signal by a second square wave having the fundamental wave as a sine wave equal to one of the above-mentioned harmonics or a sine wave obtained by inverting the phase of the one harmonic.
- the signal synthesizer is configured to output a signal component corresponding to a product of at least one harmonic of the first square wave and the input signal included in the signal of the multiplication result of the first square wave multiplier.
- Each of the square wave multiplication units includes two capacitors having the same capacitance, and each of one half cycle and the other half cycle in one cycle of the square wave multiplied by the input signal.
- the relationship between the polarity of the input signal during the charging operation and the polarity of the difference between the charges output from the two capacitors to the signal combining unit during the charge output operation is alternately repeated at a predetermined interval. And the other half cycle.
- the signal synthesizer synthesizes the charges output by the charge output operation from the two capacitors in the plurality of square wave multipliers.
- a signal component corresponding to a product of at least one harmonic of the first square wave and the input signal included in the output signal of the first square wave multiplier is the second square wave.
- the signal is canceled by a signal component corresponding to the product of the fundamental wave of the second square wave and the input signal included in the output signal of the wave multiplier. Therefore, in the signal resulting from the synthesis by the signal synthesis unit, the signal component corresponding to the product of the harmonic of the first square wave and the input signal is reduced, and the fundamental wave of the first square wave (the A signal component corresponding to a product of a sine wave having a predetermined frequency and the input signal becomes a dominant component.
- the square wave multiplication unit is used to multiply the sine wave (the fundamental wave of the first square wave) and the input signal. Less susceptible to fluctuations, and changes in characteristics due to temperature are small. Further, the use of the square wave multiplication unit makes it difficult to be affected by the input / output nonlinear characteristics of the transistor as in the case of an analog multiplier, so that the range of the level of the input signal is widened. Further, in the sine wave multiplication device, the sine wave generator can be omitted by using the square wave multiplication unit, so that the circuit configuration is simplified.
- the plurality of square wave multipliers multiply the input signal and the square wave based on the difference in charge according to the input signal, and the multiplication result signal is obtained.
- the obtained charge difference is synthesized in the signal synthesis unit. Therefore, common-mode noise is easily removed, and noise resistance is improved.
- the ratio of the capacitance of the capacitor in the first square wave multiplier and the capacitance of the capacitor in one second square wave multiplier is the amplitude of the fundamental wave of the first square wave And a value corresponding to the ratio of the harmonics of the first square wave having the same frequency as the fundamental wave of the second square wave in the one second square wave multiplier.
- the harmonics of the first square wave and the input signal It is possible to cancel the signal component corresponding to the product and the signal component corresponding to the product of the fundamental wave of the second square wave and the input signal. Since the capacitance ratio of the capacitor is hardly affected by variations due to temperature and manufacturing process, the signal components can be accurately canceled.
- the first common node, the second common node, the third common node, and the fourth common node to which the plurality of square wave multiplication units are connected in common may be provided.
- the square wave multiplication unit may include a first capacitor and a second capacitor having the same capacitance.
- the square wave multiplier applies a voltage generated between one of the first input terminal and the second input terminal and the first common node to the first capacitor, and A voltage generated between the other of the first input terminal and the second input terminal and the second common node is applied to the second capacitor, and in the charge output operation, the first capacitor is connected to the first common node.
- the second capacitor may be connected between the second common node and the fourth common node while being connected to the third common node.
- the square wave multiplication unit has a charge difference obtained by subtracting the charge accumulated in the second capacitor from the polarity of the input signal during the charge operation and the charge accumulated in the first capacitor during the charge operation. The relationship with the polarity may be reversed between the one half cycle and the other half cycle.
- the signal synthesis unit may adjust the voltage of the third common node and the voltage of the fourth common node so that the voltage of the first common node is equal to the voltage of the second common node.
- the signal synthesis unit uses the voltage difference between the third common node and the fourth common node as a signal corresponding to a result of synthesis of charges output from the plurality of square wave multiplication units by the charge output operation. You may output.
- the square wave multiplication unit includes a first capacitor having one end connected to the first common node, and a second capacitor having one end connected to the second common node and having the same capacitance as the first capacitor.
- the other end of the first capacitor is connected to the first input terminal and the second capacitor
- the other end is connected to the second input terminal
- the other end of the first capacitor is connected to the second input terminal in the charging operation of the other half cycle in the one period of the square wave.
- the other end of the second capacitor is connected to the first input terminal.
- the other end of the first capacitor and the other end of the second capacitor are connected to the first input.
- a second switch circuit that is turned on; a third switch circuit that is provided in a path between the other end of the second capacitor and the fourth common node; and is turned off in the charge operation and turned on in the charge output operation; May be included.
- the signal synthesis unit amplifies the voltage difference between the inverting input terminal connected to the first common node and the non-inverting input terminal connected to the second common node, and the amplification result is An operational amplifier that outputs a voltage difference between a non-inverting output terminal connected to three common nodes and an inverting output terminal connected to the fourth common node; the inverting input terminal and the non-inverting output terminal of the operational amplifier; Provided in a path between the non-inverting input terminal and the inverting output terminal of the operational amplifier, and a fourth switch circuit that is turned on in the charging operation and turned off in the charge output operation. A fifth switch circuit that is turned on in the charging operation and turned off in the charge output operation.
- the sine wave multiplier according to the first aspect of the present invention is a noise component included in the input signal input to the plurality of square wave multipliers, and the frequency at which the charging operation is repeated.
- a first low-pass filter for attenuating the noise component that may cause aliasing from a frequency that is an integral multiple to the signal band of the signal.
- the aliasing noise in the signal generated in the signal synthesis unit is reduced.
- the sine wave multiplication device corresponds to the first to Nth harmonics in order of decreasing frequency among the harmonics included in the first square wave.
- N square wave multipliers for multiplying the input signal by the second square wave of the N pattern may be provided.
- the first low-pass filter may include the harmonic included in the first square wave.
- the noise component of the input signal having a frequency corresponding to the (N + 1) th and higher harmonics in order of increasing frequency may be attenuated. This makes it difficult for a direct current component corresponding to the product of the noise component of the input signal and the harmonic included in the first square wave to be mixed into the signal resulting from the synthesis of the signal synthesis unit.
- the sine wave multiplication device may include a second low-pass filter that extracts a DC component included in a signal resulting from the synthesis by the signal synthesis unit. Thereby, a DC component corresponding to the amplitude of the frequency component of the sine wave included in the input signal is extracted.
- the sine wave multiplication device corresponds to the first to Nth harmonics in order of decreasing frequency among the harmonics included in the first square wave.
- N harmonics included in the first square wave are obtained from N square wave multipliers that multiply the input signal by the second square wave of the N patterns, and a signal resulting from the synthesis of the signal synthesizer.
- a third low-pass filter for attenuating a component having a frequency corresponding to the (N + 1) th and higher harmonics in order of increasing frequency, and the input signal may be a DC signal.
- a sine wave is obtained as a signal resulting from the synthesis of the signal synthesis unit, and harmonics of the first square wave included in the signal resulting from the synthesis are reduced.
- An input device is an input device that inputs information according to the proximity of an object, and includes a sensor unit including a sensor element whose capacitance changes according to the proximity of the object; A first sine wave multiplier that multiplies the DC signal by a sine wave of a predetermined frequency and outputs the first sine wave of the predetermined frequency as a result of the multiplication, and a sine wave corresponding to the first sine wave
- a detection signal generating unit configured to apply a driving voltage to the sensor element and generate a detection signal corresponding to a current flowing through the sensor element by applying the driving voltage; and a second sine wave having the predetermined frequency as the detection signal.
- a second sine wave multiplier for multiplying; and a low-pass filter for extracting a direct current component from the multiplication result signal of the second sine wave multiplier.
- the first sine wave multiplier and the second sine wave multiplier are sine wave multipliers according to the first aspect.
- the range of the level of the input signal can be widened with a simple configuration, and fluctuations in characteristics due to temperature can be reduced.
- FIG. 1A shows a block diagram
- FIG. 1B shows an example of a circuit configuration.
- FIG. 2A shows the frequency component of a square wave
- FIG. 2B shows the frequency component of a square wave.
- FIG. 3A shows a frequency component of a square wave having a predetermined frequency
- FIGS. 3B and 3C show a frequency component of a square wave including a fundamental wave equal to the harmonic of the square wave of FIG. 3A.
- FIG. 1 is a diagram showing a configuration example of a circuit that multiplies an input signal Si by a square wave.
- Square wave multiplication is different from sine wave multiplication, and can be realized by a simple circuit using fixed gain amplifier circuits 2 and 4 and a switch circuit 3, for example, as shown in FIG. 1B.
- an input signal Si or a signal obtained by inverting the input signal Si by the amplifier circuit 2 having a gain “ ⁇ 1” is input to the amplifier circuit 4 having a gain A through the switch circuit 3.
- the input signal Si is amplified (multiplied by A) by the amplifier circuit 4 having a gain A, and in the other half cycle of the square wave, the input signal Si has a gain A and a gain.
- FIG. 2 is a diagram showing frequency components of a sine wave and a square wave.
- a sine wave consists of only a single frequency component as shown in FIG. 2A, while a square wave consists of a fundamental wave and a harmonic as shown in FIG. 2B.
- the square wave multiplication result signal shown in FIG. 1 includes a signal component obtained by multiplying the input signal Si by the fundamental wave (input signal Si ⁇ fundamental wave) and a signal component obtained by multiplying the input signal Si by the harmonic wave (input signal). (Si ⁇ harmonic).
- the multiplication of the square wave has an advantage that the circuit configuration is simple and it is difficult to be influenced by the temperature characteristics and input / output nonlinear characteristics of the transistor as in the case of using an analog multiplier.
- the signal of the square wave multiplication result includes the harmonic signal component (input signal Si ⁇ harmonic) as described above, it cannot be used as it is as the multiplication result of the input signal Si and the sine wave. Therefore, in the sine wave multiplication device according to the present embodiment, a plurality of circuits that multiply the input signal and the square wave are provided, and their outputs are combined to be included in the multiplication result of the input signal and the square wave. Unnecessary signal components (input signal x harmonic) are canceled.
- FIG. 3 is a diagram showing frequency components of a square wave.
- FIG. 3A shows the frequency component of a square wave of frequency fs.
- FIG. 3B shows frequency components of a square wave having a frequency (3fs) that is three times that of the square wave of FIG. 3A and an amplitude (A / 3) that is one third.
- FIG. 3C shows a frequency component of a square wave having a frequency (5 fs) five times that of the square wave of FIG. 3A and an amplitude (A / 5) of one fifth.
- the square wave having the frequency fs includes a fundamental wave having the frequency fs and harmonics having frequencies (3fs, 5fs, 7fs,...) That are odd multiples thereof.
- the amplitude of the fundamental wave is “B”
- the amplitude of the harmonic having the frequency “K ⁇ fs” (hereinafter referred to as “Kth harmonic”) is “B / K”.
- the fundamental wave in the square wave of frequency 3fs and amplitude B / 3 shown in FIG. 3B is equal to the third harmonic in the square wave of frequency fs and amplitude B shown in FIG. 3A.
- the fundamental wave in the square wave of frequency 5fs and amplitude B / 5 shown in FIG. 3C is equal to the fifth harmonic in the square wave of frequency fs and amplitude B shown in FIG. 3A.
- FIG. 4 is a diagram illustrating an example of the configuration of the sine wave multiplier according to the first embodiment of the present invention.
- the sine wave multiplier shown in FIG. 1 includes three square wave multipliers U1, U2, and U3 that multiply square signals W1, W2, and W3 having different frequencies by an input signal Vi, and the square wave multipliers U1, U2, and U3.
- a signal synthesizer 10 that synthesizes the output signals Qu1, Qu2, and Qu3 of U3 is provided.
- square wave multiplier U an arbitrary one of the square wave multipliers U1 to U3 is referred to as a “square wave multiplier U”
- an arbitrary one of the output signals Qu1 to Qu3 is referred to as an “output signal Qu”
- the square waves W1 to W3 Arbitrary one is described as “square wave W”.
- the square wave W multiplied by the input signal Vi in the square wave multiplication unit U has a waveform in which the amplitude is the same and the polarity is reversed in one half cycle and the other half cycle.
- This square wave W can be approximated as the sum of a fundamental wave and a harmonic wave as shown in FIGS. 2 and 3, and the Kth harmonic wave has a frequency K times that of the fundamental wave and an amplitude of 1 / K. have.
- the square wave multiplication unit U generates, for example, an output signal Qu that is proportional to the input signal Vi in each of one half cycle and the other half cycle in one cycle of the square wave W to be multiplied by the input signal Vi.
- the output signal Qu is generated so that the absolute value of the ratio between the input signal Vi and the output signal Qu is equal in the half cycle and the other half cycle, and the sign of the ratio is inverted. That is, the square wave multiplication unit U sets the ratio of the output signal Qu to the input signal Vi to “A” in one half cycle in one cycle of the square wave W, and the other half cycle in one cycle of the square wave W.
- the ratio of the output signal Qu to the input signal Vi is “ ⁇ A”.
- the square wave multiplier U1 (hereinafter referred to as “first square wave multiplier U1”) has a square wave W1 having a sine wave of frequency fs as a fundamental wave (hereinafter referred to as “first square wave W1”). Is multiplied by the input signal Vi.
- the frequency of the first square wave W1 is “fs”, and the amplitude is “A”.
- Square wave multipliers U2 and U3 are used to generate one harmonic wave included in first square wave W1 having frequency fs.
- Square waves W2 and W3 (hereinafter referred to as “second square wave W2” and “second square wave W3”) having a sine wave with the phase inverted as a fundamental wave are respectively multiplied by the input signal Vi. That is, the second square wave multiplication unit U2 multiplies the input signal Vi by the second square wave W2 having a sine wave obtained by inverting the phase of the third harmonic in the first square wave W1 as a fundamental wave. As shown in FIG.
- the frequency of the second square wave W2 is “3fs” and the amplitude is “A / 3”.
- the second square wave multiplication unit U3 multiplies the input signal Vi by a second square wave W3 having a sine wave obtained by inverting the phase of the fifth harmonic in the first square wave W1 as a fundamental wave. As shown in FIG. 4, the frequency of the second square wave W3 is “5fs” and the amplitude is “A / 5”.
- the signal synthesis unit 10 adds the output signal Qu1 of the first square wave multiplication unit U1 and the output signals Qu2 and Qu3 of the second square wave multiplication units U2 and U3.
- the signal synthesizer 10 outputs the signal component corresponding to the product of the third harmonic of the first square wave W1 included in the output signal Qu1 and the input signal Vi by adding the output signals Qu1 to Qu3. It cancels out by the signal component corresponding to the product of the fundamental wave of the second square wave W2 included in the signal Qu2 and the input signal Vi. Further, the signal synthesizer 10 generates a signal component corresponding to the product of the fifth harmonic of the first square wave W1 included in the output signal Qu1 and the input signal Vi, and the second square wave W3 included in the output signal Qu3. Are canceled out by a signal component corresponding to the product of the fundamental wave of the signal and the input signal Vi.
- the signal component corresponding to the product of the third harmonic wave of the first square wave W1 included in the output signal Qu1 and the input signal Vi, and the first square A signal component corresponding to the product of the fifth harmonic of the wave W1 and the input signal Vi is a signal component corresponding to the product of the fundamental wave of the second square wave W2 included in the output signal Qu2 and the input signal Vi; and
- the signal component corresponding to the product of the fundamental wave of the second square wave W3 included in the output signal Qu3 and the input signal Vi is canceled.
- the output signal Vo obtained as a result of combining the output signals Qu1 to Qu3 signal components corresponding to the third harmonic and the fifth harmonic of the first square wave W1 are reduced, and the basic of the first square wave W1 is reduced.
- the signal component corresponding to the product of the wave (sine wave of frequency fs) and the input signal Vi becomes the dominant component. Therefore, the output signal Vo corresponding to the product of the sine wave of the frequency fs and the input signal Vi can be generated.
- the input signal Vi in one half cycle and the other half cycle in one cycle of the square wave W multiplied by the input signal Vi.
- the output signal Qu is generated so that the absolute value of the ratio between the output signal Qu and the output signal Qu is equal, and the sign of the ratio is inverted. That is, the input signal Vi and the square wave W are multiplied by inverting the positive / negative sign for each half cycle of the square wave W while maintaining the absolute value of the ratio (signal gain) of the output signal Qu to the input signal Vi. Done.
- Such multiplication of the square wave W is discrete signal processing in which a fixed signal gain is switched every half cycle, and the influence of the analog characteristics of the transistor current and voltage on the multiplication result is reduced. Therefore, it is possible to make it difficult to be influenced by the temperature characteristics and input / output nonlinear characteristics of the transistor as in the case of using an analog multiplier.
- FIG. 5 is a diagram illustrating an example of the configuration of the sine wave multiplication device according to the second embodiment.
- the sine wave multiplier shown in FIG. 5 includes a first square wave multiplier U1 that multiplies an input signal Vi by a first square wave W1, and a second square wave multiplier that multiplies the input signal Vi by second square waves W2 and W3. And U2 and U3, and a signal synthesizer 10 that synthesizes signals resulting from the multiplication of the first square wave multiplier U1 and the second square wave multipliers U2 and U3.
- the first input terminal Ti1 and the second input terminal Ti2 to which a differential signal is input as the input signal Vi, and the three square wave multipliers (U1 to U3) are common. And a first common node N1 and a second common node N2, and a third common node N3 and a fourth common node N4.
- the square wave multiplication unit U has two capacitors (first capacitor C1 and second capacitor C2) having the same capacitance.
- the square wave multiplier U responds to the input signal Vi in one half cycle and the other half cycle in one cycle of a square wave (first square wave or second square wave) to be multiplied with the input signal Vi.
- the charging operation for accumulating charges in the capacitors (C1, C2) and the charge output operation for outputting the charges accumulated in the capacitors (C1, C2) by the charging operation to the signal synthesizer 10 are alternately repeated at predetermined intervals.
- the square wave multiplication unit U has a relationship between the polarity of the input signal Vi during the charging operation and the polarity of the difference between the charges output from the two capacitors (C1, C2) to the signal combining unit 10 during the charge output operation. Inversion occurs in one half cycle and the other half cycle in one cycle of the square wave. For example, when the polarity of the input signal Vi is “positive”, the polarity of the difference between the charges output from the two capacitors (C1, C2) to the signal combining unit 10 is set to “positive” in one half cycle of the square wave. In the other half cycle of the square wave, the polarity of the charge difference is “negative”.
- the square wave multiplication unit U performs multiplication of the input signal Vi and a square wave (first square wave or second square wave) by such polarity inversion every half cycle.
- the square wave multiplication unit U applies a voltage generated between one of the first input terminal Ti1 and the second input terminal Ti2 and the first common node N1 to the first capacitor C1, and A voltage generated between the other of the first input terminal Ti1 and the second input terminal Ti2 and the second common node N2 is applied to the second capacitor C2.
- the square wave multiplication unit U connects the first capacitor C1 between the first common node N1 and the third common node N3, and connects the second capacitor C2 to the second common node N2 and the fourth common node N2. Connected to the common node N4.
- the square wave multiplier U has a charge difference obtained by subtracting the charge accumulated in the second capacitor C2 from the polarity of the input signal Vi during the charge operation and the charge accumulated in the first capacitor C1 during the charge operation.
- the relationship with the polarity is reversed between one half cycle and the other half cycle in one cycle of the square wave.
- the square wave multiplication unit U includes a first capacitor C1 and a second capacitor C2 having the same capacitance, a first switch circuit 31, a second switch circuit 32, and a third switch circuit 33. .
- the first capacitor C1 has one terminal connected to the first common node N1 and the other terminal connected to the first input terminal Ti1 or the second input terminal Ti2 via the first switch circuit 31.
- the second capacitor C2 has one terminal connected to the second common node N2, and the other terminal connected to the first input terminal Ti1 or the second input terminal Ti2 via the first switch circuit 31.
- the first switch circuit 31 connects the other terminal of the first capacitor C1 to the first input terminal Ti1 in the charging operation of one half cycle in one cycle of the first square wave W1 multiplied by the input signal Vi.
- the other terminal of the second capacitor C2 is connected to the second input terminal Ti2.
- the first switch circuit 31 connects the other terminal of the first capacitor C1 to the second input terminal Ti2 and the second capacitor in the charging operation of the other half cycle in one cycle of the first square wave W1.
- the other terminal of C2 is connected to the first input terminal Ti1. In the charge output operation, the first switch circuit 31 disconnects the other terminal of the first capacitor C1 and the other terminal of the second capacitor C2 from the first input terminal Ti1 and the second input terminal Ti2.
- the first switch circuit 31 includes, for example, four switch elements (S1 to S4) as shown in FIG.
- the switch element S1 is provided in a path between the other terminal of the first capacitor C1 and the first input terminal Ti1.
- the switch element S2 is provided in a path between the other terminal of the first capacitor C1 and the second input terminal Ti2.
- the switch element S3 is provided in a path between the other terminal of the second capacitor C2 and the first input terminal Ti1.
- the switch element S4 is provided in a path between the other terminal of the second capacitor C2 and the second input terminal Ti2.
- In one half cycle charging operation in one cycle of the first square wave W1 the switch elements S1 and S4 are turned on and the switch elements S2 and S3 are turned off.
- the switch elements S1 and S4 are turned off and the switch elements S2 and S3 are turned on.
- all the switch elements S1 to S4 are turned off.
- the second switch circuit 32 is provided in a path between the other terminal of the first capacitor C1 and the third common node N3, and is turned off in the charging operation of the square wave multiplier U and turned on in the charge output operation.
- the second switch circuit 32 includes a switch element S6 connected between the other terminal of the first capacitor C1 and the third common node N3.
- the third switch circuit 33 is provided in a path between the other terminal of the second capacitor C2 and the fourth common node N4, and is turned off in the charging operation of the square wave multiplier U and turned on in the charge output operation.
- the third switch circuit 33 has a switch element S7 connected between the other terminal of the second capacitor C2 and the fourth common node N4.
- the second square wave multipliers U2 and U3 have the same configuration as the first square wave multiplier U1.
- the capacitances of the first capacitor C1 and the second capacitor C2 in the first square wave multiplier U1 and the second square wave multipliers U2 and U3 are the harmonics of the first square wave W1 and the second square wave W2, respectively. It is set so that the fundamental wave of W3 has the same amplitude.
- the capacitance of the capacitors (C1, C2) in the second square wave multiplication unit U2 is set to 1/3 of the capacitance of the capacitors (C1, C2) in the first square wave multiplication unit U1.
- the ratio of the capacitances is that the amplitude of the fundamental wave of the first square wave W1 and the amplitude of the third harmonic of the first square wave W1 having the same frequency (3 fs) as the fundamental wave of the second square wave W2.
- the ratio is the same. Since the amount of charge with respect to the same voltage becomes 1/3 because the capacitance becomes 1/3, the amplitude of the second square wave W2 multiplied by the input signal Vi in the second square wave multiplier U2 is One-third of the amplitude of the square wave W1.
- the capacitance of the capacitors (C1, C2) in the second square wave multiplication unit U3 is set to 1/5 of the capacitance of the capacitors (C1, C2) in the first square wave multiplication unit U1.
- the ratio of the capacitances is that the amplitude of the fundamental wave of the first square wave W1 and the amplitude of the fifth harmonic of the first square wave W1 having the same frequency (5 fs) as the fundamental wave of the second square wave W3.
- the ratio is the same. Since the amount of charge with respect to the same voltage becomes 1/5 because the electrostatic capacity becomes 1/5, the amplitude of the second square wave W3 multiplied by the input signal Vi in the second square wave multiplier U3 is It becomes 1/5 of the amplitude of one square wave W1.
- the capacitances of the first capacitor C1 and the second capacitor C2 in the first square wave multiplication unit U1 are “Cu1”, and the capacitances of the first capacitor C1 and the second capacitor C2 in the second square wave multiplication unit U2 are “Cu2”. If the capacitances of the first capacitor C1 and the second capacitor C2 in the second square wave multiplication unit U3 are “Cu3”, these capacitances are set as follows.
- a charge difference that is a value obtained by subtracting the charge accumulated in the second capacitor C2 from the charge accumulated in the first capacitor C1 of the first square wave multiplier U1 during the charging operation is defined as “ ⁇ Q1”.
- ⁇ Q1 a component corresponding to the product of the third harmonic (frequency 3fs) of the first square wave W1 and the input signal Vi.
- ⁇ Q1 (5fs) a component corresponding to the product of the fifth harmonic (frequency 5fs) of the first square wave W1 and the input signal Vi.
- a charge difference that is a value obtained by subtracting the charge accumulated in the second capacitor C2 from the charge accumulated in the first capacitor C1 of the second square wave multiplier U2 during the charging operation is defined as “ ⁇ Q2”, and this charge difference ⁇ Q2
- the component corresponding to the product of the fundamental wave (frequency 3fs) of the second square wave W2 and the input signal Vi is denoted as “ ⁇ Q2 (3fs)”.
- a charge difference that is a value obtained by subtracting the charge accumulated in the second capacitor C2 from the charge accumulated in the first capacitor C1 of the second square wave multiplier U3 during the charging operation is defined as “ ⁇ Q3”, and this charge difference ⁇ Q3
- the component corresponding to the product of the fundamental wave (frequency 5 fs) of the second square wave W3 and the input signal Vi is denoted as “ ⁇ Q2 (3fs)”.
- phase relationship between the first square wave W1 and the second square wave W2 is set so that the third harmonic of the first square wave W1 and the fundamental wave of the second square wave W2 are in opposite phases.
- the phase relationship between the first square wave W1 and the second square wave W3 is set so that the fifth harmonic of the first square wave W1 and the fundamental wave of the second square wave W3 are in reverse phase.
- the charge difference ⁇ Q1, ⁇ Q2, and ⁇ Q3 during the charging operation are combined (added) by the signal combining unit 10D during the charge output operation, whereby the first square wave
- the component ⁇ Q1 (3fs) corresponding to the product of the third harmonic of W1 and the input signal Vi is canceled by the component ⁇ Q2 (3fs) corresponding to the product of the fundamental wave of the second square wave W2 and the input signal Vi.
- the component ⁇ Q1 (5fs) corresponding to the product of the fifth harmonic of the first square wave W1 and the input signal Vi is a component ⁇ Q3 corresponding to the product of the fundamental wave of the second square wave W3 and the input signal Vi. It is canceled out by (5fs). That is, the signal components resulting from the third harmonic and the fifth harmonic of the first square wave W1 are removed by addition with the signal components output from the second square wave multipliers U2 and U3.
- the signal synthesis unit 10 adjusts the voltage of the third common node N3 and the voltage of the fourth common node N4 so that the voltage of the first common node N1 and the voltage of the second common node N2 are equal.
- the signal synthesis unit 10 determines the voltage difference between the third common node N3 and the fourth common node N4 according to the synthesis result of the charges output by the charge output operation from the three square wave multiplication units (U1 to U3). Output as signal Vo.
- the signal synthesis unit 10 includes an operational amplifier 11, a fourth switch circuit 12, and a fifth switch circuit 13.
- the operational amplifier 11 amplifies the voltage difference between the inverting input terminal connected to the first common node N1 and the non-inverting input terminal connected to the second common node N2, and the amplification result is supplied to the third common node N3.
- a voltage difference between the connected non-inverting output terminal and the inverting output terminal connected to the fourth common node N4, that is, a signal Vo is output.
- the fourth switch circuit 12 is provided in a path between the inverting input terminal and the non-inverting output terminal of the operational amplifier 11, and is turned on in the charging operation of the square wave multiplication unit U and turned off in the charge output operation.
- the fourth switch circuit 12 includes a switch element S8 connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier 11.
- the fifth switch circuit 13 is provided in a path between the non-inverting input terminal and the inverting output terminal of the operational amplifier 11, and is turned on in the charging operation of the square wave multiplication unit U and turned off in the charge output operation.
- the fifth switch circuit 13 includes a switch element S ⁇ b> 9 connected between the non-inverting input terminal and the inverting output terminal of the operational amplifier 11.
- FIG. 6 is a diagram for explaining the state of each switch element during the charging operation and the charge output operation of the sine wave multiplier shown in FIG. 6A shows the state of the switch element during the charging operation, and FIG. 6B shows the state of the switch element during the charge output operation.
- the second square wave multiplication units U2 and U3 are also in the same switch state in the charging operation and the charge output operation.
- the first capacitor C1 is connected between the first input terminal Ti1 and the first common node N1
- the second capacitor C2 is connected between the second input terminal Ti2 and the first common node N1. Connected between.
- the fourth switch circuit 12 and the fifth switch circuit 13 are turned on, the voltages of the first common node N1 and the second common node N2 become substantially equal due to the negative feedback operation of the operational amplifier 11.
- the difference voltage obtained by subtracting the voltage of the second input terminal Ti2 from the voltage of the first input terminal Ti1 is “Vi”, and the capacitances of the first capacitor C1 and the second capacitor C2 are “C”.
- the charge difference ⁇ Q3 between the first capacitor C1 and the second capacitor C2 of the second square wave multiplication unit U3 is represented by the following equations, respectively.
- ⁇ Q1 ⁇ Vi ⁇ C (4)
- ⁇ Q2 ⁇ Vi ⁇ (C / 3)
- ⁇ Q3 ⁇ Vi ⁇ (C / 5) (6)
- the positive and negative polarities shown on the right side of Equation (4) are switched between one half cycle and the other half cycle of the first square wave W1 (frequency fs).
- the positive and negative polarities shown on the right side of Equation (5) are switched between one half cycle and the other half cycle of the second square wave W2 (frequency 3fs).
- the positive and negative polarities shown on the right side of the equation (6) are switched between one half cycle and the other half cycle of the third square wave W3 (frequency 5 fs).
- the other terminal of the first capacitor C1 is connected to the third common node N3.
- the first capacitor C1 of the first square wave multiplication unit U1 is connected to the first common node N1 together with the first capacitor C1 of the second square wave multiplication unit U2 and the first capacitor C1 of the second square wave multiplication unit U3.
- the third common node N3 is connected in parallel. The charges accumulated in the first capacitors C1 of the three square wave multipliers (U1 to U3) during the charging operation are directly combined by connecting the first capacitors C1 in parallel during the charge output operation.
- the other terminal of the second capacitor C2 is connected to the fourth common node N4.
- the second capacitor C2 of the first square wave multiplication unit U1 is connected to the second common node N2 together with the second capacitor C2 of the second square wave multiplication unit U2 and the second capacitor C2 of the second square wave multiplication unit U3.
- the fourth common node N4 is connected in parallel.
- a charge difference is a value obtained by subtracting the total charge synthesized by connecting the three second capacitors C2 in parallel from the total charge synthesized by connecting the three first capacitors C1 in parallel. Is represented by “ ⁇ QS”, the charge difference ⁇ QS is expressed by the following equation.
- the output signal Vo of the operational amplifier 11 has a charge difference ⁇ QS. Proportional. Further, as shown in Expression (7), since the charge difference ⁇ QS is the sum of the charge differences ⁇ Q1, ⁇ Q2, and ⁇ Q3, the charge difference ⁇ QS is proportional to the input signal Vi from the relations of Expressions (4) to (6). . Therefore, the output signal Vo of the operational amplifier 11 increases or decreases in proportion to the input signal Vi.
- the harmonics of the charge difference ⁇ Q1 (third harmonic and fifth harmonic) are removed. Therefore, in the output signal Vo of the operational amplifier 11, the signal component corresponding to the product of the input signal Vi and the sine wave (frequency fs) becomes dominant, and the product of the input signal Vi and the harmonics (frequency 3fs, 5fs). The signal component corresponding to is reduced.
- FIG. 7 is a timing chart showing the state of each switch element in the sine wave multiplier according to the second embodiment.
- a high level indicates an on state of the switch element
- a low level indicates an off state of the switch element.
- switch elements S1 to S4, S8, and S9 and switch elements S6 and S7 are over-on each other in order to avoid crosstalk due to a delay in the on / off operation. It is controlled not to wrap.
- the charging operation and the charge output operation are performed once every period T.
- One period (1 / fs) of the first square wave W1 is set to 60 cycles (60T) of the period T, and one period (1/3 fs) of the second square wave W2 is set to 20 cycles (20T of the period T).
- one period (1/5 fs) of the second square wave W3 is set to 12 cycles (12T) of the period T.
- the number of cycles of period T (30 cycles in the example of FIG. 7) defining the half period of the first square wave W1 is canceled by the output of the second square wave multiplier (U2, U3).
- the harmonic frequencies (3fs, 5fs) are set to be a common multiple of the magnification (3 times, 5 times) of the fundamental frequency fs.
- the sine wave multiplier shown in FIG. 5 since the third harmonic and the fifth harmonic of the first square wave W1 are harmonics to be canceled, they are common multiples of “3” and “5”. 30 "is set as the number of cycles of the period T in the half cycle of the first square wave W1.
- the number of cycles of the period T in the half cycle of the first square wave W1 can be made an integer value.
- the ratio between the period of the first square wave W1 and the period of the second square waves W2, W3 can be strictly set by the number of cycles of the period T.
- an operation mode in which the polarity shown on the right side of the equations (4), (5), and (6) is “positive” is called “forward rotation mode”, and the polarity shown on the right side of these equations is “negative”.
- This operation mode is called “inversion mode”.
- the square wave multipliers (U1 to U3) are in the “forward rotation mode” in one half cycle in one cycle of the square wave and in the “inversion mode” in the other half cycle.
- the switch elements S1 and S4 of the first switch circuit 31 are turned on and the switch elements S2 and S3 are turned off during the charging operation.
- the switch elements S1 and S4 of the first switch circuit 31 are turned off and the switch elements S2 and S3 are turned on during the charging operation.
- the operation in the normal rotation mode is repeated 30 cycles in the first half period (30T) of the first square wave W1, and the inversion mode is performed in the second half period (30T) of the first square wave W1. This operation is repeated 30 cycles.
- the operation in the inversion mode is repeated 10 cycles in the first half cycle (10T) of the second square wave W2, and the forward rotation mode in the second half cycle (10T) of the second square wave W2. Is repeated 10 cycles.
- the first square wave multiplication unit U1 starts the forward rotation mode operation
- the second square wave multiplication unit U2 starts the inversion mode operation. Therefore, the fundamental wave of the second square wave W2 is the first square wave W1. It has an opposite phase to the third harmonic.
- the operation in the inversion mode is repeated 6 cycles in the first half cycle (6T) of the second square wave W3, and the forward rotation mode in the second half cycle (6T) of the second square wave W3.
- the above operation is repeated 6 cycles.
- the operation in the normal mode is started in the first square wave multiplier U1
- the operation in the inversion mode is started in the second square wave multiplier U3. Therefore, the fundamental wave of the second square wave W3 is the first square wave W1. Have the opposite phase to the fifth harmonic.
- the switch elements (S8, S9) of the fourth switch circuit 12 and the fifth switch circuit 13 are turned on during the charge operation and turned off during the charge output operation.
- the switch elements (S6, S7) of the second switch circuit 32 and the third switch circuit 33 are turned off during the charging operation and turned on during the charge output operation.
- the three square wave multipliers (U1 to U3) sample the charge difference ( ⁇ Q1, ⁇ Q2, ⁇ Q3) proportional to the input signal Vi every time the charging operation is performed, and the signal synthesis unit 10
- the charge differences ( ⁇ Q1, ⁇ Q2, ⁇ Q3) of the wave multipliers (U1 to U3) are combined and held every time the charge output operation is performed.
- a subsequent circuit (not shown) that processes the output signal Vo of the signal synthesis unit 10 performs processing such as low-pass filter processing and analog-digital conversion on the output signal Vo held during the charge output operation period.
- the charging operation and the charge output operation of the capacitors (C1, C2) are repeated at regular intervals in the square wave multiplication unit U.
- the input signal Vi and the square wave W are multiplied. Therefore, the period and phase of the square wave in the square wave multiplication unit U can be strictly set by the number of cycles of the period T.
- the capacitance ratio of the capacitors in the square wave multiplication unit U is not easily affected by variations due to temperature or manufacturing process, and therefore is input at each square wave multiplication unit U.
- the amplitude ratio of the square wave W multiplied by the signal Vi can be set with high accuracy. Accordingly, the signal component (charge) corresponding to the product of the harmonic of the first square wave W1 included in the output of the first square wave multiplier U1 and the input signal Vi is output to the outputs of the second square wave multipliers U2 and U3. Can be accurately canceled by the signal component (charge) corresponding to the product of the fundamental wave of the second square waves W2 and W3 and the input signal Vi.
- each of the three square wave multiplication units (U1 to U3) performs square wave multiplication based on the difference in charge according to the differential signal (Vi).
- the signal difference corresponding to the product of the differential signal (Vi) and the sine wave is obtained by combining the charge difference ( ⁇ Q1 to ⁇ Q3) obtained as a signal of the multiplication result in the signal combining unit. . Therefore, common-mode noise superimposed on each differential signal can be easily removed, and noise resistance can be improved.
- the capacitors (C1, C2) of the respective square wave multiplication units U are connected in parallel in the signal synthesis unit 10, so that the charges accumulated in these capacitors can be directly Since they are combined, the charge / discharge current of the capacitors (C1, C2) by the operational amplifier 11 hardly flows. That is, the current driving speed in the operational amplifier 11 does not significantly affect the charge synthesis in the signal synthesis unit 10D. As a result, charge synthesis can be performed at high speed in the signal synthesis unit 10 without being limited by the speed of the operational amplifier 11, so that multiplication of sine waves can be performed at high speed.
- FIG. 8 is a diagram illustrating an example of the configuration of the sine wave multiplication device according to the third embodiment.
- the sine wave multiplier shown in FIG. 8 is obtained by providing a first low-pass filter 40 in the sine wave multiplier (FIGS. 4 and 5) according to the first and second embodiments. This is the same as the sine wave multiplier according to the third embodiment.
- the first low-pass filter 40 is for reducing the aliasing noise, and attenuates the high-frequency component of the input signal Vi input to the square wave multiplication unit. That is, the first low-pass filter 40 is a noise component included in the input signal Vi, and returns to the signal band of the input signal Vi from a frequency that is an integral multiple of the frequency (1 / T) at which the charging operation is repeated. Attenuating noise components that may cause noise. As a result, even when the input signal Vi includes noise having a relatively high frequency, aliasing noise in the signal band of the input signal Vi can be prevented and highly accurate multiplication processing can be performed.
- the outputs of the square wave multipliers (U1 to U3) are combined to cause the third harmonic and the fifth harmonic of the first square wave W1.
- the component to be canceled (harmonic ⁇ input signal Vi) is canceled.
- components due to those harmonics remain in the output signal Vo.
- the seventh harmonic having the next largest amplitude after the fifth harmonic may affect the accuracy of the multiplication result.
- the second square waves W2 and W3 are not only the fundamental wave, but also their harmonics are some harmonics of the first square wave W1 (FIG. 3A). Is equal to In the example of FIG. 3, the third and fifth harmonics of the second square wave W2 are equal to the ninth and fifteenth harmonics of the first square wave W1. Further, the third harmonic of the second square wave W3 is equal to the fifteenth harmonic of the first square wave W1. Therefore, since the 15th harmonic of the first square wave W1 is subtracted by both the second square wave W2 and the second square wave W3, an error occurs.
- the first low-pass filter 40 attenuates the high-frequency component of the input signal Vi before inputting it to the square wave multipliers (U1 to U3), thereby reducing the influence of the error caused by the product of the above-described harmonic wave and the input signal Vi. Can be made. Since the lowest harmonic that may affect the accuracy is the seventh harmonic (frequency 7 fs) of the first square wave W1, the frequency characteristic of the first low-pass filter 30 is, for example, a frequency higher than the frequency 7 fs. It is set so that the component attenuates to the extent that it does not affect the multiplication accuracy.
- FIG. 9 is a diagram illustrating another configuration example of the sine wave multiplication device according to the third embodiment.
- the sine wave multiplier shown in FIG. 9 is obtained by adding a second low-pass filter 50 to the sine wave multiplier shown in FIG. 8, and the other configuration is the same as that of the sine wave multiplier shown in FIG.
- the sine wave multiplier shown in FIG. 9 can be operated as a circuit (narrowband bandpass filter circuit) that extracts only the signal component of the frequency fs contained in the input signal Vi.
- the level of the DC component becomes a level corresponding to the amplitude of the signal component of the frequency fs included in the input signal Vi.
- the second low-pass filter 50 is configured by, for example, a digital filter that discretely processes an AD conversion result of the output signal Vo.
- FIG. 10 is a diagram illustrating an example of the configuration of the sine wave multiplication device according to the fourth embodiment.
- the sine wave multiplier shown in FIG. 10 is provided with a third low-pass filter 60 in the sine wave multipliers (FIGS. 4 and 5) according to the second and third embodiments, and the input signal Vi is a DC voltage VDD.
- Other configurations are the same as those of the sine wave multiplier according to the second and third embodiments.
- the output signal Vo is a signal obtained by multiplying the DC voltage VDD and the sine wave, that is, a sine wave.
- the sine wave multiplier shown in FIG. 8 converts the signal component of the frequency fs into a DC component.
- the sine wave multiplier shown in FIG. 10 generates a signal of the frequency fs from the DC component, the input / output relationship. Is reversed.
- the third low-pass filter 60 has a higher frequency than the lowest harmonic of the first square wave W1 (seventh harmonic) that may affect the accuracy, as in the sine wave multiplier shown in FIG. Is attenuated.
- the sine wave multiplication device can be operated as a highly accurate sine wave generation circuit.
- the input device is an input device such as a touch sensor that inputs information according to the proximity of an object, and includes a sensor unit 110, a selection unit 120, a detection signal generation unit 130, 1 sine wave multiplication unit 140, second sine wave multiplication unit 150, and low-pass filter 160 are provided.
- the sensor unit 110 includes a sensor element whose capacitance changes according to the proximity of an object.
- the sensor unit 110 includes electrodes ES1 to ESn that form capacitors with the object.
- an object such as a fingertip
- the capacitance of the capacitor formed between the electrodes ES1 to ESn and the object changes.
- the selection unit 120 selects one of the electrodes ES1 to ESn in the sensor unit 110 and connects it to the input of the detection signal generation unit 130.
- the detection signal generation unit 130 applies a sine wave drive voltage corresponding to the first sine wave supplied by the first sine wave multiplication unit 140 to the electrodes (ES1 to ESn) of the sensor unit 110 selected by the selection unit 120. And a detection signal Sn corresponding to the current flowing in the electrode is generated by applying the drive voltage.
- the detection signal generation unit 130 includes an operational amplifier OP3, a capacitor Cf, and a subtracter 131, for example, as shown in FIG.
- the capacitor Cf is connected between the inverting input terminal and the output terminal of the operational amplifier OP3.
- the first sine wave of the first sine wave multiplier 140 is input to the non-inverting input terminal of the operational amplifier OP3.
- the subtracter 131 subtracts the first sine wave from the output signal of the operational amplifier OP3, and outputs the subtraction result as the detection signal Sn.
- the detection signal Sn is a signal that vibrates at the same frequency fs as the first sine wave, and the amplitude thereof is proportional to the capacitance formed between the electrode of the sensor unit 110 and the object (fingertip).
- the first sine wave multiplication unit 140 is a circuit that multiplies a DC signal by a sine wave having a frequency fs and outputs a first sine wave having a predetermined frequency as a result of the multiplication.
- the first sine wave multiplication device shown in FIG. It has the same configuration as.
- the second sine wave multiplication unit 150 is a circuit that multiplies the detection signal Sn generated by the detection signal generation unit 130 by the second sine wave having the frequency fs.
- the second sine wave multiplication unit 150 has the same configuration as the sine wave multiplication device shown in FIG. Have
- the low-pass filter 160 extracts a DC component signal Da from the signal Ds obtained as a multiplication result of the second sine wave multiplication unit 150.
- the second sine wave multiplier 150 and the low-pass filter 160 operate as a narrow-band band-pass filter that extracts a signal component of the frequency fs included in the detection signal Sn.
- the DC component signal Da has a level corresponding to the amplitude of the signal component of the frequency fs included in the detection signal Sn, and is an electrostatic capacitance formed between the electrode of the sensor unit 110 and the object (fingertip). Is proportional to
- the first sine wave multiplication unit 140 and the second sine wave multiplication unit 150 having a simple configuration are used to detect capacitance with high accuracy from which the influence of external noise has been removed. A value can be obtained.
- the phase of the fundamental wave of the second square wave W2, W3 multiplied by the input signal Vi in the second square wave multiplier U2, U3 is changed to the phase of the harmonic wave in the first square wave W1.
- the present invention is not limited to this example.
- the phase of the fundamental wave of the second square waves W2, W3 multiplied by the input signal Vi in the second square wave multipliers U2, U3 is changed to the first square wave. You may make it become the same phase as the phase of the harmonic in W1.
- the signal combining unit 10 combines the signals so as to subtract the output signals Qu2 and Qu3 of the second square wave multipliers U2 and U3 from the output signal Qu1 of the first square wave multiplier U1.
- the harmonic component can be canceled as in the sine wave multiplier shown in FIG.
- the signal components corresponding to the third harmonic and the fifth harmonic in the first square wave W1 are canceled by the signal components corresponding to the fundamental waves of the second square waves W2 and W3.
- the present invention is not limited to this example.
- the number of square wave multipliers may be three or more so that signal components corresponding to higher harmonics can be canceled.
- square wave multiplication processing and multiplication result synthesis processing are performed by analog circuits.
- these signal processing may be performed by digital signal processing.
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Abstract
Description
上記正弦波乗算装置では、前記方形波乗算部を用いて正弦波(前記第1方形波の前記基本波)と前記入力信号との乗算を行うため、アナログ乗算器のようにトランジスタの温度特性の影響を受け難くなり、温度による特性の変動が少ない。また、前記方形波乗算部を用いることによって、アナログ乗算器のようにトランジスタの入出力非線形特性の影響を受け難くなるため、入力信号のレベルの範囲が広くなる。
更に、上記正弦波乗算装置では、前記方形波乗算部を用いることによって正弦波発生器を省略できることから、回路構成が簡易となる。
上記の構成によれば、前記第1方形波乗算部のキャパシタと前記第2方形波乗算部のキャパシタとの静電容量比に基づいて、前記第1方形波の高調波と前記入力信号との積に応じた信号成分と、前記第2方形波の基本波と前記入力信号との積に応じた信号成分とを相殺することが可能となる。キャパシタの静電容量比は、温度や製造プロセスによるばらつきの影響を受け難いため、上記信号成分の相殺を精度よく行うことが可能となる。
前記方形波乗算部は、同じ静電容量を持つ第1キャパシタ及び第2キャパシタを有してよい。前記方形波乗算部は、前記充電動作においては、前記第1入力端子及び前記第2入力端子の一方と前記第1共通ノードとの間に生じる電圧を前記第1キャパシタに印加するとともに、前記第1入力端子及び前記第2入力端子の他方と前記第2共通ノードとの間に生じる電圧を前記第2キャパシタに印加し、前記電荷出力動作においては、前記第1キャパシタを前記第1共通ノードと前記第3共通ノードとの間に接続するとともに、前記第2キャパシタを前記第2共通ノードと前記第4共通ノードとの間に接続してよい。また、前記方形波乗算部は、前記充電動作時における前記入力信号の極性と、前記充電動作時に前記第1キャパシタに蓄積される電荷より前記第2キャパシタに蓄積される電荷を引いた電荷差の極性との関係を、当該一方の半周期と当該他方の半周期とで反転してよい。
前記信号合成部は、前記第1共通ノードの電圧と前記第2共通ノードの電圧とが等しくなるように前記第3共通ノードの電圧及び前記第4共通ノードの電圧を調節してよい。また、前記信号合成部は、前記第3共通ノードと前記第4共通ノードとの電圧差を、前記複数の方形波乗算部から前記電荷出力動作によって出力される電荷の合成結果に応じた信号として出力してよい。
この場合、前記信号合成部は、前記第1共通ノードに接続された反転入力端子と前記第2共通ノードに接続された非反転入力端子との電圧差を増幅し、当該増幅結果を、前記第3共通ノードに接続された非反転出力端子と前記第4共通ノードに接続された反転出力端子との電圧差として出力する演算増幅器と、前記演算増幅器の前記反転入力端子と前記非反転出力端子との間の経路に設けられ、前記充電動作においてオンし、前記電荷出力動作においてオフする第4スイッチ回路と、前記演算増幅器の前記非反転入力端子と前記反転出力端子との間の経路に設けられ、前記充電動作においてオンし、前記電荷出力動作においてオフする第5スイッチ回路とを有してよい。
これにより、前記信号合成部において生成される信号中の前記折り返し雑音が低減する。
これにより、前記入力信号のノイズ成分と前記第1方形波に含まれる前記高調波との積に応じた直流成分が前記信号合成部の合成結果の信号に混入され難くなる。
これにより、前記入力信号に含まれる前記正弦波の周波数成分の振幅に応じた直流成分が抽出される。
これにより、前記信号合成部の合成結果の信号として正弦波が得られるとともに、当該合成結果の信号に含まれる前記第1方形波の高調波が低減する。
図4は、本発明の第1の実施形態に係る正弦波乗算装置の構成の一例を示す図である。図1に示す正弦波乗算装置は、それぞれ異なる周波数の方形波W1,W2,W3を入力信号Viに乗算する3つの方形波乗算部U1,U2,U3と、当該方形波乗算部U1,U2,U3の出力信号Qu1,Qu2,Qu3を合成する信号合成部10を有する。以下、方形波乗算部U1~U3の任意の1つを「方形波乗算部U」と記し、出力信号Qu1~Qu3の任意の1つを「出力信号Qu」と記し、方形波W1~W3の任意の1つを「方形波W」と記す。
すなわち、第2方形波乗算部U2は、第1方形波W1における第3次高調波の位相を反転させた正弦波を基本波とする第2方形波W2を入力信号Viに乗算する。図4において示すように、この第2方形波W2の周波数は「3fs」、振幅は「A/3」である。
また、第2方形波乗算部U3は、第1方形波W1における第5次高調波の位相を反転させた正弦波を基本波とする第2方形波W3を入力信号Viに乗算する。図4において示すように、この第2方形波W3の周波数は「5fs」、振幅は「A/5」である。
次に、第2の実施形態として、図4に示す正弦波乗算装置のより詳細な構成の一例を説明する。
また、例えば、方形波乗算部Uは、充電動作時における入力信号Viの極性と、充電動作時に第1キャパシタC1に蓄積される電荷より第2キャパシタC2に蓄積される電荷を引いた電荷差の極性との関係を、方形波の1周期中における一方の半周期と他方の半周期とで反転する。
第2キャパシタC2は、一方の端子が第2共通ノードN2に接続され、他方の端子が第1スイッチ回路31を介して第1入力端子Ti1又は第2入力端子Ti2に接続される。
また、第2方形波乗算部U3におけるキャパシタ(C1,C2)の静電容量は、第1方形波乗算部U1におけるキャパシタ(C1,C2)の静電容量に対して1/5に設定される。この静電容量の比は、第1方形波W1の基本波の振幅と、第2方形波W3の基本波と等しい周波数(5fs)を有する第1方形波W1の第5次高調波の振幅との比と同じである。静電容量が1/5になることで、同一電圧に対する電荷量が1/5になるため、第2方形波乗算部U3において入力信号Viに乗算される第2方形波W3の振幅は、第1方形波W1の振幅の1/5になる。
他方、充電動作時に第2方形波乗算部U2の第1キャパシタC1に蓄積される電荷より第2キャパシタC2に蓄積される電荷を減算した値である電荷差を「ΔQ2」とし、この電荷差ΔQ2の中で、第2方形波W2の基本波(周波数3fs)と入力信号Viとの積に応じた成分を「ΔQ2(3fs)」と記す。
また、充電動作時に第2方形波乗算部U3の第1キャパシタC1に蓄積される電荷より第2キャパシタC2に蓄積される電荷を減算した値である電荷差を「ΔQ3」とし、この電荷差ΔQ3の中で、第2方形波W3の基本波(周波数5fs)と入力信号Viとの積に応じた成分を「ΔQ2(3fs)」と記す。
各方形波乗算部のキャパシタ(C1,C2)の静電容量が式(1)のように設定されることにより、上述した電荷差の成分には次の関係が成立する。
ΔQ1(5fs) = -ΔQ3(5fs) …(3)
演算増幅器11は、第1共通ノードN1に接続された反転入力端子と第2共通ノードN2に接続された非反転入力端子との電圧差を増幅し、当該増幅結果を、第3共通ノードN3に接続された非反転出力端子と第4共通ノードN4に接続された反転出力端子との電圧差、すなわち信号Voとして出力する。
ΔQ2 = ±Vi×(C/3) …(5)
ΔQ3 = ±Vi×(C/5) …(6)
次に、本発明の第3の実施形態について説明する。
図8は、第3の実施形態に係る正弦波乗算装置の構成の一例を示す図である。図8に示す正弦波乗算装置は、第1,第2の実施形態に係る正弦波乗算装置(図4,5)に第1ローパスフィルタ40を設けたものであり、他の構成は第2,第3の実施形態に係る正弦波乗算装置と同じである。
次に、本発明の第4の実施形態について説明する。
図10は、第4の実施形態に係る正弦波乗算装置の構成の一例を示す図である。図10に示す正弦波乗算装置は、第2,第3の実施形態に係る正弦波乗算装置(図4,図5)に第3ローパスフィルタ60を設け、入力信号Viを直流電圧VDDとしたものであり、他の構成は第2,第3の実施形態に係る正弦波乗算装置と同じである。
このように、本実施形態に係る正弦波乗算装置は、精度の高い正弦波発生回路として動作させることも可能である。
次に、本発明の第5の実施形態に係る入力装置について、図11を参照して説明する。
Claims (9)
- 所定の周波数の正弦波を入力信号に乗算する正弦波乗算装置であって、
前記入力信号として差動信号が入力される第1入力端子及び第2入力端子と、
それぞれ異なる周波数の方形波を前記入力信号に乗算する複数の方形波乗算部と、
前記複数の方形波乗算部における乗算結果の信号を合成する信号合成部とを備え、
前記方形波は、最も周波数が低い正弦波である基本波と、前記基本波に対してそれぞれ整数倍の周波数を持つ正弦波である複数の高調波との和として近似可能であり、
前記複数の方形波乗算部は、
前記所定の周波数の正弦波を前記基本波とする第1方形波を前記入力信号に乗算する1つの第1方形波乗算部と、
前記第1方形波に含まれる1つの前記高調波と等しい正弦波若しくは当該1つの高調波の位相を反転させた正弦波を前記基本波とする第2方形波を前記入力信号に乗算する1つ又は複数の第2方形波乗算部とを有し、
前記信号合成部は、前記第1方形波乗算部の乗算結果の信号に含まれる前記第1方形波の少なくとも1つの前記高調波と前記入力信号との積に応じた信号成分を、前記第2方形波乗算部の乗算結果の信号に含まれる前記第2方形波の前記基本波と前記入力信号との積に応じた信号成分によって相殺し、
個々の前記方形波乗算部は、同じ静電容量を持つ2つのキャパシタを有しており、前記入力信号に乗算する前記方形波の1周期中における一方の半周期と他方の半周期のそれぞれにおいて、前記入力信号に応じた差を持つ電荷を前記2つのキャパシタにそれぞれ蓄積する充電動作と、前記充電動作により前記2つのキャパシタに蓄積した電荷をそれぞれ前記信号合成部へ出力する電荷出力動作とを所定の間隔で交互に反復し、前記充電動作時における前記入力信号の極性と、前記電荷出力動作時に前記2つのキャパシタから前記信号合成部へ出力する電荷の差の極性との関係を、当該一方の半周期と当該他方の半周期とで反転し、
前記信号合成部は、前記複数の方形波乗算部における前記2つのキャパシタから前記電荷出力動作により出力される電荷をそれぞれ合成する
ことを特徴とする正弦波乗算装置。 - 前記第1方形波乗算部における前記キャパシタの静電容量と、1つの前記第2方形波乗算部における前記キャパシタの静電容量との比が、前記第1方形波の基本波の振幅と、当該1つの第2方形波乗算部における前記第2方形波の基本波と等しい周波数を有する前記第1方形波の高調波の振幅との比に応じた値を有する
ことを特徴とする請求項1に記載の正弦波乗算装置。 - 前記複数の方形波乗算部が共通に接続される第1共通ノード、第2共通ノード、第3共通ノード及び第4共通ノードを備え、
前記方形波乗算部は、同じ静電容量を持つ第1キャパシタ及び第2キャパシタを有しており、前記充電動作においては、前記第1入力端子及び前記第2入力端子の一方と前記第1共通ノードとの間に生じる電圧を前記第1キャパシタに印加するとともに、前記第1入力端子及び前記第2入力端子の他方と前記第2共通ノードとの間に生じる電圧を前記第2キャパシタに印加し、前記電荷出力動作においては、前記第1キャパシタを前記第1共通ノードと前記第3共通ノードとの間に接続するとともに、前記第2キャパシタを前記第2共通ノードと前記第4共通ノードとの間に接続し、前記充電動作時における前記入力信号の極性と、前記充電動作時に前記第1キャパシタに蓄積される電荷より前記第2キャパシタに蓄積される電荷を引いた電荷差の極性との関係を、当該一方の半周期と当該他方の半周期とで反転し、
前記信号合成部は、前記第1共通ノードの電圧と前記第2共通ノードの電圧とが等しくなるように前記第3共通ノードの電圧及び前記第4共通ノードの電圧を調節し、前記第3共通ノードと前記第4共通ノードとの電圧差を、前記複数の方形波乗算部から前記電荷出力動作によって出力される電荷の合成結果に応じた信号として出力する
ことを特徴とする請求項1又は2に記載の正弦波乗算装置。 - 前記複数の方形波乗算部が共通に接続される第1共通ノード、第2共通ノード、第3共通ノード及び第4共通ノードを備え、
前記方形波乗算部は、
一端が前記第1共通ノードに接続された第1キャパシタと、
一端が前記第2共通ノードに接続され、前記第1キャパシタと同じ静電容量を持つ第2キャパシタと、
前記入力信号に乗算する前記方形波の1周期中における一方の半周期の前記充電動作においては、前記第1キャパシタの他端を前記第1入力端子に接続するとともに前記第2キャパシタの他端を前記第2入力端子に接続し、前記方形波の前記1周期中における他方の半周期の前記充電動作においては、前記第1キャパシタの前記他端を前記第2入力端子に接続するとともに前記第2キャパシタの前記他端を前記第1入力端子に接続し、前記電荷出力動作においては、前記第1キャパシタの前記他端及び前記第2キャパシタの前記他端を前記第1入力端子及び前記第2入力端子から切り離す第1スイッチ回路と、
前記第1キャパシタの前記他端と前記第3共通ノードとの間の経路に設けられ、前記充電動作においてオフし、前記電荷出力動作においてオンする第2スイッチ回路と、
前記第2キャパシタの前記他端と前記第4共通ノードとの間の経路に設けられ、前記充電動作においてオフし、前記電荷出力動作においてオンする第3スイッチ回路とを有し、
前記信号合成部は、
前記第1共通ノードに接続された反転入力端子と前記第2共通ノードに接続された非反転入力端子との電圧差を増幅し、当該増幅結果を、前記第3共通ノードに接続された非反転出力端子と前記第4共通ノードに接続された反転出力端子との電圧差として出力する演算増幅器と、
前記演算増幅器の前記反転入力端子と前記非反転出力端子との間の経路に設けられ、前記充電動作においてオンし、前記電荷出力動作においてオフする第4スイッチ回路と、
前記演算増幅器の前記非反転入力端子と前記反転出力端子との間の経路に設けられ、前記充電動作においてオンし、前記電荷出力動作においてオフする第5スイッチ回路とを有する
ことを特徴とする請求項1又は2に記載の正弦波乗算装置。 - 前記複数の方形波乗算部に入力される前記入力信号に含まれたノイズ成分であって、前記充電動作が反復される周波数に対して整数倍の周波数から前記信号の信号帯域へ折り返し雑音を生じ得る前記ノイズ成分を減衰させる第1ローパスフィルタを有する
ことを特徴とする請求項1乃至4の何れか一項に記載の正弦波乗算装置。 - 前記第1方形波に含まれる前記高調波の中で、周波数が低い順における1番目からN番目までの前記高調波に対応したNパターンの前記第2方形波を前記入力信号に乗算するN個の前記方形波乗算部を有し、
前記第1ローパスフィルタは、前記第1方形波に含まれる前記高調波であって、前記周波数が低い順における(N+1)番目以降の前記高調波に相当する周波数を持つ前記入力信号のノイズ成分を減衰させる
ことを特徴とする請求項5に記載の正弦波乗算装置。 - 前記信号合成部の合成結果の信号に含まれる直流成分を抽出する第2ローパスフィルタを有する
ことを特徴とする請求項1乃至6の何れか一項に記載の正弦波乗算装置。 - 前記第1方形波に含まれる前記高調波の中で、周波数が低い順における1番目からN番目までの前記高調波に対応したNパターンの前記第2方形波を前記入力信号に乗算するN個の前記方形波乗算部と、
前記信号合成部の合成結果の信号から、前記第1方形波に含まれる前記高調波であって、前記周波数が低い順における(N+1)番目以降の前記高調波に相当する周波数を持つ成分を減衰させる第3ローパスフィルタとを有し、
前記入力信号が直流信号である
ことを特徴とする請求項1乃至4の何れか一項に記載の正弦波乗算装置。 - 物体の近接に応じた情報を入力する入力装置であって、
前記物体の近接に応じて静電容量が変化するセンサ素子を含んだセンサ部と、
所定の周波数の正弦波を直流信号に乗算し、当該乗算の結果として前記所定の周波数の第1正弦波を出力する第1正弦波乗算部と、
前記第1正弦波に応じた正弦波の駆動電圧を前記センサ素子に印加し、前記駆動電圧の印加によって前記センサ素子に流れる電流に応じた検出信号を生成する検出信号生成部と、
前記所定の周波数の第2正弦波を前記検出信号に乗算する第2正弦波乗算部と、
前記第2正弦波乗算部の乗算結果の信号から直流成分を抽出するローパスフィルタとを備え、
前記第1正弦波乗算部及び前記第2正弦波乗算部は、請求項1乃至6の何れか一項に記載された正弦波乗算装置である
ことを特徴とする入力装置。
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JP2005143804A (ja) * | 2003-11-14 | 2005-06-09 | Glory Ltd | 生体検知装置、生体検知方法および指紋認証装置 |
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CN107544770A (zh) * | 2017-09-15 | 2018-01-05 | 中国科学技术大学 | 一种数模混合输入的、电荷域的模拟乘加器电路 |
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KR20180042388A (ko) | 2018-04-25 |
KR102099519B1 (ko) | 2020-04-09 |
EP3349092A4 (en) | 2018-10-24 |
US20180234085A1 (en) | 2018-08-16 |
EP3349092A1 (en) | 2018-07-18 |
JPWO2017065221A1 (ja) | 2018-08-09 |
US10511290B2 (en) | 2019-12-17 |
CN108139768A (zh) | 2018-06-08 |
JP6387469B2 (ja) | 2018-09-05 |
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