WO2017063269A1 - 栅极驱动基板和使用栅极驱动基板的液晶显示器 - Google Patents

栅极驱动基板和使用栅极驱动基板的液晶显示器 Download PDF

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Publication number
WO2017063269A1
WO2017063269A1 PCT/CN2015/098399 CN2015098399W WO2017063269A1 WO 2017063269 A1 WO2017063269 A1 WO 2017063269A1 CN 2015098399 W CN2015098399 W CN 2015098399W WO 2017063269 A1 WO2017063269 A1 WO 2017063269A1
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Prior art keywords
shift buffer
buffer unit
coupled
node
output
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PCT/CN2015/098399
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English (en)
French (fr)
Inventor
李亚锋
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/905,024 priority Critical patent/US10078993B2/en
Publication of WO2017063269A1 publication Critical patent/WO2017063269A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the invention relates to a liquid crystal display, in particular to a gate driver (Gate driver on Array, GOA) liquid crystal display of the substrate.
  • GOA Gate driver on Array
  • the GOA circuit uses a thin film transistor liquid crystal display Array process to fabricate a gate driver with a thin film transistor (Thin film).
  • the gate of the transistor (TFT) array is driven on the substrate to implement a progressive scan driving method.
  • the GOA circuit includes a plurality of shift buffer units, and each shift buffer unit is pulled up by a pull-up circuit (Pull-up Circuit), pull-up control circuit, pull-down circuit (Pull-down) Circuit), a pull-down holding circuit, and a boost circuit responsible for potential rise.
  • a pull-up circuit Pull-up Circuit
  • pull-up control circuit pull-up control circuit
  • pull-down circuit Pull-down Circuit
  • the pull-up circuit is mainly responsible for outputting the input clock signal (Clock) to the gate of the thin film transistor as a driving signal of the liquid crystal display.
  • the pull-up control circuit is responsible for controlling the opening of the pull-up circuit, which is generally a signal transmitted by the upper-level GOA circuit.
  • the pull-down circuit is responsible for quickly pulling the scan signal (that is, the potential of the gate of the thin film transistor) to a low level after outputting the scan signal.
  • the pull-down holding circuit is responsible for keeping the scan signal and the signal of the pull-up circuit (that is, the signal applied to the Q point) in the off state (ie, the set negative potential), and usually two pull-down holding circuits alternate.
  • the rising circuit is responsible for the secondary rise of the Q point potential, thus ensuring the normal output of the G(n) of the pull-up circuit.
  • the GOA circuit requires at least two start signals STV1 and STV2, wherein the start signal STV1 is used as the Q-point pull-up signal of the first-stage shift buffer unit, and the start signal STV2 is used as the pull-down of the Q-point of the last-stage shift buffer unit. signal.
  • the start signal STV1 is used as the Q-point pull-up signal of the first-stage shift buffer unit
  • the start signal STV2 is used as the pull-down of the Q-point of the last-stage shift buffer unit. signal.
  • using two start signals STV1 and STV2 requires more wires to transmit signals, increasing the complexity of the design.
  • the technical solution of the present invention provides a gate driving substrate, comprising: a plurality of pixel units arranged in a matrix; a plurality of transistors each electrically connected to one of the pixel units; and N shift buffer units, N
  • the shift buffer units are coupled in series, and each of the M shift buffer units is controlled by M clock signals, and the first stage shift buffer unit is configured to use the first clock signal and the start signal.
  • the output terminal outputs a scan signal pulse
  • the last stage shift buffer unit is configured to output a scan signal pulse at the output end according to the Mth clock signal and the start signal, wherein N and M are positive integers, and N is greater than M
  • the frequency of the start signal is equal to the update frequency of displaying one frame of the picture
  • the M clock signals are sequentially outputting the signal pulse
  • the signal pulse output times of the M clock signals do not overlap each other.
  • the pulse width of the start signal starts from a falling edge of the Mth clock signal applied to the last stage shift buffer unit when the first frame picture is scanned, and ends at the second scan
  • the second frame of the next frame picture is a frame picture of the first picture.
  • each of the shift buffer units includes a pull-up circuit including a first transistor having a gate coupled to the first node, a source coupled to the clock signal, and a drain coupled to the output a terminal for providing the scan signal pulse by the output terminal according to the clock signal;
  • a pull-up control circuit includes a second transistor having a gate coupled to an output of a previous shift buffer unit of each of the shift buffer units, a source coupled to the first power supply voltage, and a drain coupled
  • the first node is configured to turn on the pull-up circuit according to the scan signal pulse of a previous shift buffer unit of each shift buffer unit; and the rising circuit is coupled to the first a potential between the node and the output terminal for raising the first node;
  • a pull-down holding circuit coupled to the first node, the clock signal, and a second power voltage for maintaining the first a low level of a node; and a pull-down circuit coupled to the second power voltage, the output, and an output of a next shift buffer unit of each of the shift buffer units
  • the pull-down circuit includes: a third transistor having a drain electrically connected to the output terminal, a source electrically connected to the second power supply voltage; and a fourth transistor having a drain electrical property Connected to the first node, the source is electrically connected to the second power voltage, and the gate thereof is electrically connected to the gate of the third transistor.
  • the technical solution of the present invention further provides a gate driving substrate comprising a plurality of pixel units arranged in a matrix; a plurality of transistors each electrically connected to one of the pixel units; and N shift buffer units, N
  • the shift buffer units are coupled in series, and each of the M shift buffer units is controlled by M clock signals, and the first stage shift buffer unit is configured to use the first clock signal and the start signal.
  • the output terminal outputs a scan signal pulse
  • the last stage shift buffer unit is configured to output a scan signal pulse at the output end according to the Mth clock signal and the start signal, wherein N and M are positive integers, and N is greater than M
  • the pulse width of the start signal starts from a falling edge of the Mth clock signal applied to the last stage shift buffer unit when scanning the first frame picture, and ends at scanning the second frame picture And applying a rising edge of the first clock signal of the first stage shift buffer unit, wherein the second frame picture is a next frame picture of the first frame picture.
  • the frequency of the start signal is equal to the update frequency of displaying a frame of picture.
  • the M clock signals sequentially output signal pulses in turn, and the signal pulse output times of the M clock signals do not overlap each other.
  • each of the shift buffer units includes a pull-up circuit including a first transistor having a gate coupled to the first node, a source coupled to the clock signal, and a drain coupled to the output a terminal for providing the scan signal pulse by the output terminal according to the clock signal;
  • a pull-up control circuit includes a second transistor having a gate coupled to an output of a previous shift buffer unit of each of the shift buffer units, a source coupled to the first power supply voltage, and a drain coupled
  • the first node is configured to turn on the pull-up circuit according to the scan signal pulse of a previous shift buffer unit of each shift buffer unit; and a pull-down hold circuit coupled to the first a node, the clock signal, and a second power voltage for maintaining a low level of the first node; and a pull-down circuit coupled to the second power voltage, the output, and each of The output of the next shift buffer unit of the shift buffer unit is configured to pull down the potential of the first node to the second power voltage.
  • the shift buffer unit further includes a rising circuit coupled between the first node and the output terminal for raising the potential of the first node.
  • the pull-down circuit includes: a third transistor having a drain electrically connected to the output terminal, a source electrically connected to the second power supply voltage; and a fourth transistor having a drain electrical property Connected to the first node, the source is electrically connected to the second power voltage, and the gate thereof is electrically connected to the gate of the third transistor.
  • the technical solution of the present invention further provides a liquid crystal display including a source driver for outputting a data signal to a plurality of pixel units to display gray scales, and a gate driving circuit for outputting a scan signal to turn on a plurality of transistors .
  • the gate driving circuit includes: N shift buffer units, N of the shift buffer units are coupled in series, and each M of the shift buffer units is controlled by M clock signals, and the first stage shift The bit buffer unit is configured to output a scan signal pulse at the output end according to the first clock signal and the start signal, and the last stage shift buffer unit is configured to output the scan at the output end according to the Mth clock signal and the start signal.
  • N and M are both positive integers, and N is greater than M
  • a pulse width of the start signal begins at the first stage of the last stage shift buffer unit when scanning a first frame picture a falling edge of the M clock signals, and ending at a rising edge of the first clock signal applied to the first stage shift buffer unit when scanning the second frame picture, the second frame picture being the The next frame of a frame.
  • the frequency of the start signal is equal to the update frequency of displaying a frame of picture.
  • the M clock signals sequentially output signal pulses in turn, and the signal pulse output times of the M clock signals do not overlap each other.
  • each of the shift buffer units includes a pull-up circuit including a first transistor having a gate coupled to the first node, a source coupled to the clock signal, and a drain coupled to the output a terminal for providing the scan signal pulse by the output terminal according to the clock signal;
  • a pull-up control circuit includes a second transistor having a gate coupled to an output of a previous shift buffer unit of each of the shift buffer units, a source coupled to the first power supply voltage, and a drain coupled
  • the first node is configured to turn on the pull-up circuit according to the scan signal pulse of a previous shift buffer unit of each shift buffer unit; and a pull-down hold circuit coupled to the first a node, the clock signal, and a second power voltage for maintaining a low level of the first node; and a pull-down circuit coupled to the second power voltage, the output, and each of The output of the next shift buffer unit of the shift buffer unit is configured to pull down the potential of the first node to the second power voltage.
  • the shift buffer unit further includes a rising circuit coupled between the first node and the output terminal for raising the potential of the first node.
  • the pull-down circuit includes: a third transistor having a drain electrically connected to the output terminal, a source electrically connected to the second power supply voltage; and a fourth transistor having a drain electrical property Connected to the first node, the source is electrically connected to the second power voltage, and the gate thereof is electrically connected to the gate of the third transistor.
  • the first stage shift buffer unit and the last stage shift buffer unit of the gate drive substrate of the present invention are both driven according to the start signal to output scan signal pulses. Therefore, the number of wires for transmitting the start signal can be reduced, and the complexity of the layout design can be simplified.
  • Figure 1 is a functional block diagram of a liquid crystal display of the present invention.
  • FIG. 2 is a block diagram of a shift buffer unit SR(n) of a gate drive substrate of the present invention.
  • FIG. 3 is a circuit diagram of a preferred embodiment of the shift buffer unit of FIG. 2.
  • FIG. 4 is a timing diagram of various input signals, output signals, and node voltages shown in FIG.
  • FIG. 1 is a functional block diagram of a liquid crystal display device 10 of the present invention.
  • the liquid crystal display 10 includes a gate driving substrate 12, a gate driving circuit 14, and a source driver (source) Driver)16.
  • the gate driving substrate 12 includes a plurality of pixels arranged in a matrix, and each pixel includes three pixel units 20 respectively representing three primary colors of red, green and blue (RGB). Take a 1024 ⁇ 768 resolution LCD monitor 10, a total of 1024 ⁇ 768 ⁇ Three pixel units 20 are combined.
  • the gate driving circuit 14 outputs a scan signal such that the transistors 22 of each row are sequentially turned on, and the source driver 16 outputs corresponding data signals to an entire column of pixel units 20 to charge them to respective required voltages to display different Grayscale. After the same row is charged, the gate driving circuit 14 turns off the scan signal of the row, and then the gate driving circuit 14 outputs the scan signal to turn on the transistor 22 of the next row, and then the pixel of the next row is driven by the source driver 16.
  • the unit 20 performs charging and discharging. This is continued until all the pixel units 20 of the gate drive substrate 12 are fully charged, and charging is started from the first row.
  • the source driver 16 charges and discharges the pixel unit 20 to a desired voltage during the 21.7 ⁇ s period to display the corresponding gray scale.
  • FIG. 2 is a block diagram of the shift buffer unit SR(n) of the gate driving circuit 14 of the present invention.
  • the gate driving circuit 14 includes N cascade-connected shift buffer units SR(n), and each M shift buffer unit SR(n) is controlled by M clock signals, wherein n, N, and M are Is a positive integer, and N is greater than M, and n is less than or equal to N.
  • n, N, and M are Is a positive integer, and N is greater than M, and n is less than or equal to N.
  • Each of the four shift buffer units SR(4m-3), SR(4m-2), SR(4m-1), and SR(4m) of the present embodiment is controlled by four clock signals CK1-CK4, respectively, where m Is 0 or a positive integer, and m is less than or equal to M/4.
  • the pulses of the four clock signals CK1-CK4 are sequentially generated in turn, and the pulses of the four clock signals CK1-CK4 do not overlap each other.
  • the shift buffer unit SR(n) is used to output a scan signal according to the clock signal and the output terminal G(n-1) of the first stage shift buffer unit SR(n-1) before each shift buffer unit SR(n) The scan signal is output from the output terminal G(n).
  • the first stage shift buffer unit SR(1) receives the start pulse (start After the pulse) STV, the shift buffer unit SR(1) outputs a scan signal pulse at the output terminal G(1) according to the clock signal CK1.
  • the second stage shift buffer unit SR(2) receives the scan signal pulse outputted by the previous stage shift buffer unit SR(1) at the output terminal G(1), and is output to the output terminal G according to the clock signal CK2. (2) Outputting a scan signal pulse of the shift buffer unit SR(2).
  • each shift buffer unit SR(n) receives each shift buffer unit SR(n) After the scan signal pulse outputted by the output terminal G(n-1), the previous stage shift buffer unit SR(n-1) outputs the shift at the output terminal G(n) according to the corresponding clock signal CK1-CK4.
  • the scan signal pulse of the bit buffer unit SR(n). The scan signal pulse is used to turn on the transistors of the corresponding pixel unit 20.
  • FIG. 3 is a circuit diagram of a preferred embodiment of the shift buffer unit of FIG.
  • Each shift buffer unit SR(n) includes a pull-up control circuit (pull-up control) Circuit) 100, pull-up circuit 200, pull-down circuit (pull-down Circuit) 400, pull-down holding circuit 500, and rising circuit 600.
  • the clock signal CK of the following embodiment represents one of the clock signals CK1-CK4 for simplicity of explanation.
  • the pull-up circuit 200 can be a first transistor T1 having a gate coupled to the first node Q(n), a source coupled to the clock signal CK, and a drain coupled to the output terminal G(n).
  • the pull-up circuit 200 is used to provide a scan signal pulse from the output terminal G(n) in accordance with the clock signal CK.
  • the pull-up control circuit 100 can be a second transistor T2 having a gate coupled to the first power supply voltage VDD and a source coupled to the output terminal G(n-1) of the previous shift buffer unit SR(n-1). The drain is coupled to the first node Q(n).
  • the pull-up control circuit 100 is configured to turn on the pull-up circuit 200 in accordance with the scan signal pulse of the previous shift buffer unit SR(n-1).
  • the rising circuit 600 can be a capacitor Cb coupled between the first node Q(n) and the output terminal G(n) for raising the potential Q(n) of the first node.
  • the pull-down holding circuit 500 is coupled to the first node G(n), the clock signal CK, and the second power voltage VSS for maintaining a low level of the first node Q(n).
  • the pull-down circuit 400 is coupled to the second power voltage VSS, the output signal terminal G(n), and the output terminal G(n+1) of the next shift buffer unit SR(n+1) of each shift buffer unit. The potential of the first node Q(n) is pulled down to the second power supply voltage VSS.
  • the pull-down circuit 400 includes a third transistor T3 and a fourth transistor T4.
  • the gate of the third transistor T3 is coupled to the output terminal G(n+1) of the next shift buffer unit SR(n+1) of each shift buffer unit, and the source is coupled to the output terminal G(n).
  • the drain is coupled to the second power voltage VSS.
  • the gate of the fourth transistor T4 is coupled to the output terminal G(n+1) of the next shift buffer unit SR(n+1) of each shift buffer unit, and the source is coupled to the first node Q(n).
  • the drain is coupled to the second power voltage VSS.
  • the gate of the third transistor T3 of the pull-down circuit 400 of the last stage shift buffer unit SR(n) and the gate of the fourth transistor T4 are electrically connected to the start pulse STV.
  • FIG. 4 is a timing diagram of various input signals, output signals and node voltages shown in FIG.
  • the pulse width of the start signal STV starts from a falling edge of the clock signal CK4 applied to the last stage shift buffer unit SR(N) when the first frame picture is scanned, and ends when the second frame picture is scanned.
  • the rising edge of the first clock signal CK1 applied to the first stage shift buffer unit SR(1) which is the next frame picture of the first frame picture. Because the clock signal CK4 corresponding to the last stage shift buffer unit SR(N) is in an un-blank state, that is, at a low level, the high level of the start signal STV is not shifted to the last stage.
  • the cache unit SR(N) has any effect. When all of the clock signals CK1-CK4 enter the untriggered state again, the start signal STV is turned on again, and the Q-point voltage of the last-stage shift buffer unit SR(N) is pulled down.
  • the high level time of the start signal STV continues until the second frame picture to serve as a signal for pulling up the Q point voltage of the first stage shift buffer unit SR(1) when scanning the second frame picture.
  • the start signal STV can be used as the signal of the Q point voltage of the pull-up shift buffer unit SR(1), and can also be used as the Q-point voltage of the last-stage shift buffer unit SR(N).
  • the signal therefore, can reduce the number of starting signals.
  • the first stage shift buffer unit and the last stage shift buffer unit of the gate drive substrate of the present invention are both used to drive according to the start signal to output a scan signal pulse. Therefore, the number of wires for transmitting the start signal can be reduced, and the complexity of the layout design can be simplified.

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  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

一种栅极驱动基板(12)，包含N个移位缓存单元SR(n)。每M个所述移位缓存单元SR(n)由M个时钟信号控制，第一级移位缓存单元SR(1)用来依据第一时钟信号CK1以及起始信号STV，在输出端G(1)输出扫描信号脉冲，最后一级移位缓存单元SR(n)用来依据第M个时钟信号以及所述起始信号STV，在输出端G(N)输出扫描信号脉冲。起始信号STV的频率等于显示一帧画面的更新频率。起始信号STV的脉宽起始于扫描第一帧画面时施加在所述最后一级移位缓存单元SR(n)的所述第M个时钟信号的下降沿，并结束于扫描第二帧画面时施加在所述第一级移位缓存单元SR(1)的所述第一个时钟信号CK1的上升沿。因为第一级移位缓存单元SR(1)和最后一级移位缓存单元SR(n)都是依据起始信号STV来驱动以输出扫描信号脉冲，因此可以减少传输起始信号的导线数量，简化布局设计的复杂度。

Description

栅极驱动基板和使用栅极驱动基板的液晶显示器 技术领域
本发明是有关于一种液晶显示器，尤指一种使用栅极驱动(Gate driver on array，GOA)基板的液晶显示器。
 背景技术
GOA电路是利用薄膜晶体管液晶显示器Array制程将栅极驱动器制作在具有薄膜晶体管(Thin film transistor，TFT)阵列的栅极驱动基板上，以实现逐行扫描的驱动方式。
GOA电路包含数个移位缓存单元，每一移位缓存单元由上拉电路（Pull-up circuit）、上拉控制电路（Pull-up control circuit）、下拉电路（Pull-down circuit）、下拉保持电路（Pull-down Holding circuit）、以及负责电位抬升的上升电路(Boost circuit)组成。
上拉电路主要负责将输入的时钟信号（Clock）输出至薄膜晶体管的栅极，作为液晶显示器的驱动信号。上拉控制电路负责控制上拉电路的打开，一般是由上级GOA电路传递来的信号作用。下拉电路负责在输出扫描信号后，快速地将扫描信号(亦即薄膜晶体管的栅极的电位)拉低为低电平。下拉保持电路则负责将扫描信号和上拉电路的信号（亦即施加于Q点的信号）保持在关闭状态（即设定的负电位），通常有两个下拉保持电路交替作用。上升电路则负责Q点电位的二次抬升，这样确保上拉电路的G(n)正常输出。
一般来说，本级移位缓存单元的Q点电压是由前一级移位缓存单元的输出电压将其上拉，Q点电压是由后一级移位缓存单元的输出电压将其下拉。因此GOA电路至少需要两个起始信号STV1和STV2，其中起始信号STV1作为第一级移位缓存单元的Q点上拉信号，起始信号STV2作为最后一级移位缓存单元Q点的下拉信号。但是使用两个起始信号STV1和STV2就需要更多的导线来传输信号，增加设计的复杂度。
 技术问题
有鉴于此，本发明的目的是提供一种栅极驱动基板和使用栅极驱动基板的液晶显示器，以解决现有技术的问题。
 技术解决方案
本发明的技术方案提供一种栅极驱动基板，其包含：数个呈矩阵排列的像素单元；数个晶体管，每一晶体管电性连接于其中一个像素单元；以及Ｎ个移位缓存单元，Ｎ个所述移位缓存单元以串联的方式耦接，每M个所述移位缓存单元由M个时钟信号控制，第一级移位缓存单元用来依据第一时钟信号以及起始信号，在输出端输出扫描信号脉冲，最后一级移位缓存单元用来依据第Ｍ个时钟信号以及所述起始信号，在输出端输出扫描信号脉冲，其中N、M皆为正整数，且N大于M，其中所述起始信号的频率等于显示一帧画面的更新频率，M个所述时钟信号是依序轮流输出信号脉冲，且M个所述时钟信号的信号脉冲输出时间彼此不重叠，所述起始信号的脉宽起始于扫描第一帧画面时施加在所述最后一级移位缓存单元的所述第Ｍ个时钟信号的下降沿，并结束于扫描第二帧画面时施加在所述第一级移位缓存单元的所述第一个时钟信号的上升沿，所述第二帧画面是所述第一帧画面的下一帧画面。
依据本发明，每一移位缓存单元包含：上拉电路，其包含第一晶体管，其栅极耦接于第一节点，源极耦接于所述时钟信号，漏极耦接于所述输出端，用来依据所述时钟信号，由所述输出端提供所述扫描信号脉冲； 上拉控制电路，其包含第二晶体管，其栅极耦接于所述每一移位缓存单元的前一个移位缓存单元的输出端，源极耦接于第一电源电压，漏极耦接于所述第一节点，用来依据所述每一移位缓存单元的前一个移位缓存单元的所述扫描信号脉冲，导通所述上拉电路；上升电路，耦接于所述第一节点和所述输出端之间，用来抬升所述第一节点的电位；下拉保持电路，耦接于所述第一节点、所述时钟信号以及第二电源电压，用来依据维持所述第一节点的低电平；以及下拉电路，耦接于所述第二电源电压、所述输出端以及所述每一移位缓存单元的下一个移位缓存单元的输出端，用来下拉所述第一节点的电位至所述第二电源电压。
依据本发明，所述下拉电路包含：第三晶体管，其漏极电性连接于所述输出端，其源极电性连接于所述第二电源电压；以及第四晶体管，其漏极电性连接于所述第一节点，其源极电性连接于所述第二电源电压，其栅极电性连接于所述第三晶体管的栅极。
本发明的技术方案另提供一种栅极驱动基板，其包含数个呈矩阵排列的像素单元；数个晶体管，每一晶体管电性连接于其中一个像素单元；以及Ｎ个移位缓存单元，Ｎ个所述移位缓存单元以串联的方式耦接，每M个所述移位缓存单元由M个时钟信号控制，第一级移位缓存单元用来依据第一时钟信号以及起始信号，在输出端输出扫描信号脉冲，最后一级移位缓存单元用来依据第Ｍ个时钟信号以及所述起始信号，在输出端输出扫描信号脉冲，其中N、M皆为正整数，且N大于M，其中所述起始信号的脉宽起始于扫描第一帧画面时施加在所述最后一级移位缓存单元的所述第Ｍ个时钟信号的下降沿，并结束于扫描第二帧画面时施加在所述第一级移位缓存单元的所述第一个时钟信号的上升沿，所述第二帧画面是所述第一帧画面的下一帧画面。
依据本发明，所述起始信号的频率等于显示一帧画面的更新频率。
依据本发明， M个所述时钟信号是依序轮流输出信号脉冲，且M个所述时钟信号的信号脉冲输出时间彼此不重叠。
依据本发明，每一移位缓存单元包含：上拉电路，其包含第一晶体管，其栅极耦接于第一节点，源极耦接于所述时钟信号，漏极耦接于所述输出端，用来依据所述时钟信号，由所述输出端提供所述扫描信号脉冲； 上拉控制电路，其包含第二晶体管，其栅极耦接于所述每一移位缓存单元的前一个移位缓存单元的输出端，源极耦接于第一电源电压，漏极耦接于所述第一节点，用来依据所述每一移位缓存单元的前一个移位缓存单元的所述扫描信号脉冲，导通所述上拉电路；下拉保持电路，耦接于所述第一节点、所述时钟信号以及第二电源电压，用来依据维持所述第一节点的低电平；以及下拉电路，耦接于所述第二电源电压、所述输出端以及所述每一移位缓存单元的下一个移位缓存单元的输出端，用来下拉所述第一节点的电位至所述第二电源电压。
依据本发明，所述移位缓存单元另包含上升电路，耦接于所述第一节点和所述输出端之间，用来抬升所述第一节点的电位。
依据本发明，所述下拉电路包含：第三晶体管，其漏极电性连接于所述输出端，其源极电性连接于所述第二电源电压；以及第四晶体管，其漏极电性连接于所述第一节点，其源极电性连接于所述第二电源电压，其栅极电性连接于所述第三晶体管的栅极。
本发明的技术方案又提供一种液晶显示器，其包含源极驱动器，用来输出数据信号至数个像素单元使其显示灰阶；以及栅极驱动电路，用来输出扫描信号使得数个晶体管开启。所述栅极驱动电路包含：Ｎ个移位缓存单元，Ｎ个所述移位缓存单元以串联的方式耦接，每M个所述移位缓存单元由M个时钟信号控制，第一级移位缓存单元用来依据第一时钟信号以及起始信号，在输出端输出扫描信号脉冲，最后一级移位缓存单元用来依据第Ｍ个时钟信号以及所述起始信号，在输出端输出扫描信号脉冲，其中N、M皆为正整数，且N大于M，其中所述起始信号的脉宽起始于扫描第一帧画面时施加在所述最后一级移位缓存单元的所述第Ｍ个时钟信号的下降沿，并结束于扫描第二帧画面时施加在所述第一级移位缓存单元的所述第一个时钟信号的上升沿，所述第二帧画面是所述第一帧画面的下一帧画面。
依据本发明，所述起始信号的频率等于显示一帧画面的更新频率。
依据本发明， M个所述时钟信号是依序轮流输出信号脉冲，且M个所述时钟信号的信号脉冲输出时间彼此不重叠。
依据本发明，每一移位缓存单元包含：上拉电路，其包含第一晶体管，其栅极耦接于第一节点，源极耦接于所述时钟信号，漏极耦接于所述输出端，用来依据所述时钟信号，由所述输出端提供所述扫描信号脉冲； 上拉控制电路，其包含第二晶体管，其栅极耦接于所述每一移位缓存单元的前一个移位缓存单元的输出端，源极耦接于第一电源电压，漏极耦接于所述第一节点，用来依据所述每一移位缓存单元的前一个移位缓存单元的所述扫描信号脉冲，导通所述上拉电路；下拉保持电路，耦接于所述第一节点、所述时钟信号以及第二电源电压，用来依据维持所述第一节点的低电平；以及下拉电路，耦接于所述第二电源电压、所述输出端以及所述每一移位缓存单元的下一个移位缓存单元的输出端，用来下拉所述第一节点的电位至所述第二电源电压。
依据本发明，所述移位缓存单元另包含上升电路，耦接于所述第一节点和所述输出端之间，用来抬升所述第一节点的电位。
依据本发明，所述下拉电路包含：第三晶体管，其漏极电性连接于所述输出端，其源极电性连接于所述第二电源电压；以及第四晶体管，其漏极电性连接于所述第一节点，其源极电性连接于所述第二电源电压，其栅极电性连接于所述第三晶体管的栅极。
 有益效果
相较于现有技术，本发明的栅极驱动基板的第一级移位缓存单元和最后一级移位缓存单元都是用来依据起始信号来驱动以输出扫描信号脉冲。因此可以减少传输起始信号的导线数量，简化布局设计(Layout)的复杂度。
 附图说明
图1是本发明的液晶显示器的功能方块图。
图2是本发明的栅极驱动基板的移位缓存单元SR(n)的方块图。
图3是图2移位缓存单元的较佳实施例的电路图。
图４是图３所示各种输入信号、输出信号和节点电压的时序图。
 本发明的最佳实施方式
请参阅图1，图1是本发明的液晶显示器10的功能方块图。液晶显示器10包含栅极驱动基板12、栅极驱动电路14以及源极驱动器(source driver)16。栅极驱动基板12包含数个呈矩阵排列的像素(pixel)，而每一个像素包含三个分别代表红绿蓝(RGB)三原色的像素单元20构成。以一个1024 × 768分辨率的液晶显示器10来说，共需要1024 × 768 × 3个像素单元20组合而成。栅极驱动电路14输出扫描信号使得每一行的晶体管22依序开启，同时源极驱动器16则输出对应的数据信号至一整列的像素单元20使其充电到各自所需的电压，以显示不同的灰阶。当同一行充电完毕后，栅极驱动电路14便将该行的扫描信号关闭，然后栅极驱动电路14再输出扫描信号将下一行的晶体管22打开，再由源极驱动器16对下一行的像素单元20进行充放电。如此依序下去，直到栅极驱动基板12的所有像素单元20都充电完成，再从第一行开始充电。
在目前的液晶显示面板设计中，栅极驱动电路14即每隔一固定间隔输出扫描信号。以一个1024 × 768分辨率的液晶显示器10以及60Hz的更新频率为例，每一个画面的显示时间约为1/60=16.67ms。所以每一个扫描信号的脉冲为16.67ms/768=21.7μs。而源极驱动器16则在这21.7μs的时间内，将像素单元20充放电到所需的电压，以显示出相对应的灰阶。
请参阅图2，图2是本发明的栅极驱动电路14的移位缓存单元SR(n)的方块图。栅极驱动电路14包含Ｎ个串接(cascade-connected)的移位缓存单元SR(n)，每M个移位缓存单元SR(n)由M个时钟信号控制，其中n、N、M皆为正整数，且N大于M，n小于等于N。以一个1024 × 768分辨率的液晶显示器10为例，N为768，M可以为4。本实施例的每四个移位缓存单元SR(4m-3)、SR(4m-2)、SR(4m-1)、SR(4m)分别由四个时钟信号CK1-CK4所控制，其中m为0或正整数，且m小于或等于Ｍ/４。四个时钟信号CK1-CK4的脉冲依序轮流产生，且四个时钟信号CK1-CK4的脉冲互不重叠。移位缓存单元SR(n)用来依据时钟信号以及每一移位缓存单元SR(n)之前一级移位缓存单元SR(n-1)的输出端G(n-1)输出的扫描信号，自输出端G(n)输出扫描信号。第一级移位缓存单元SR(1)接收到起始脉冲(start pulse)STV后，移位缓存单元SR(1)就会依据时钟信号CK1于输出端G(1)输出扫描信号脉冲。接下来，第二级移位缓存单元SR(2)在接收到前一级移位缓存单元SR(1)于输出端G(1)输出的扫描信号脉冲后，依据时钟信号CK2于输出端G(2)输出该移位缓存单元SR(2)的扫描信号脉冲。依此类推，每一移位缓存单元SR(n)在接收到每一移位缓存单元SR(n) 的前一级移位缓存单元SR(n-1)于输出端G(n-1)输出的扫描信号脉冲后，依据对应的时钟信号CK1-CK4于输出端G(n)输出该每一移位缓存单元SR(n)的扫描信号脉冲。该扫描信号脉冲用来开启对应的像素单元20的晶体管。
请参阅图3，图3是图2移位缓存单元的较佳实施例的电路图。每一移位缓存单元SR(n)包含上拉控制电路(pull-up control circuit)100、上拉电路(pull-up circuit)200、下拉电路(pull-down circuit)400、下拉保持电路500以及上升电路600。由于每一移位缓存单元的结构相同，为简化说明，以下实施例的时钟信号CK表示其中一个时钟信号CK1-CK4。上拉电路200可以是第一晶体管T1，其栅极耦接于第一节点Q(n)，源极耦接于时钟信号CK，漏极耦接于该输出端G(n)。上拉电路200用来依据时钟信号CK，由输出端G(n)提供扫描信号脉冲。上拉控制电路100可以是第二晶体管T2，其栅极耦接于第一电源电压VDD，源极耦接于前一个移位缓存单元SR(n-1)的输出端G(n-1)，漏极耦接于第一节点Q(n)。上拉控制电路100用来依据前一个移位缓存单元SR(n-1)的扫描信号脉冲，导通上拉电路200。上升电路600可以是一电容Cb，其耦接于第一节点Q(n)和输出端G(n)之间，用来抬升第一节点的电位Q(n)。下拉保持电路500耦接于第一节点G(n)、时钟信号CK以及第二电源电压VSS，用来依据维持第一节点Q(n)的低电平。下拉电路400耦接于第二电源电压VSS、输出信号端G(n)以及每一移位缓存单元的下一个移位缓存单元SR(n+1)的输出端G(n+1)，用来下拉第一节点Q(n)的电位至第二电源电压VSS。
下拉电路400包含第三晶体管T3和第四晶体管T4。第三晶体管T3的栅极耦接于该每一移位缓存单元的下一个移位缓存单元SR(n+1)的输出端G(n+1)，源极耦接于输出端G(n)，漏极耦接于第二电源电压VSS。第四晶体管T4的栅极耦接于每一移位缓存单元的下一个移位缓存单元SR(n+1)的输出端G(n+1)，源极耦接于第一节点Q(n)，漏极耦接于第二电源电压VSS。在本实施例中，最后一级移位缓存单元SR(n)的下拉电路400的第三晶体管T3的栅极和第四晶体管T4的栅极皆电性连接于起始脉冲STV。
请一并参阅图2-图4，图４是图３所示各种输入信号、输出信号和节点电压的时序图。起始脉冲STV的频率等于更新频率， 举例来说，以一个1024 × 768分辨率的栅极驱动基板12以及60Hz的更新频率为例，起始脉冲STV的频率约为1/60=16.67ms。较佳地，起始信号STV的脉宽起始于扫描第一帧画面时施加在最后一级移位缓存单元SR(N)的时钟信号CK4的下降沿，并结束于扫描第二帧画面时施加在第一级移位缓存单元SR(1)的第一个时钟信号CK1的上升沿，所述第二帧画面是所述第一帧画面的下一帧画面。因为最后一级移位缓存单元SR(N)对应的时钟信号CK4处于未触发(Blank)状态，亦即处于低电平，这时起始信号STV的高电平不会对最后一级移位缓存单元SR(N)产生任何的影响。在所有的时钟信号CK1－CK4都再次进入未触发状态时，这时起始信号STV再次开启，将最后一级移位缓存单元SR(N)的Q点电压拉下来。起始信号STV的高电平时间会一直持续到第二帧画面，以在扫描第二帧画面时作为上拉第一级移位缓存单元SR(1)的Q点电压的信号。通过这样的方式，该起始信号STV既可以作为上拉移位缓存单元SR(1)的Q点电压的信号，同时也可以作为下拉最后一级移位缓存单元SR(N)的Q点电压的信号，因此可以减少起始信号的数量。
本发明的栅极驱动基板的第一级移位缓存单元和最后一级移位缓存单元都是用来依据起始信号来驱动以输出扫描信号脉冲。因此可以减少传输起始信号的导线数量，简化布局设计(Layout)的复杂度。
综上所述，虽然本发明已以较佳实施例揭露如上，但该较佳实施例并非用以限制本发明，该领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (15)

  1. 一种栅极驱动基板，其包含：
    数个呈矩阵排列的像素单元；
    数个晶体管，每一晶体管电性连接于其中一个像素单元；以及
    Ｎ个移位缓存单元，Ｎ个所述移位缓存单元以串联的方式耦接，每M个所述移位缓存单元由M个时钟信号控制，第一级移位缓存单元用来依据第一时钟信号以及起始信号，在输出端输出扫描信号脉冲，最后一级移位缓存单元用来依据第Ｍ个时钟信号以及所述起始信号，在输出端输出扫描信号脉冲，其中N、M皆为正整数，且N大于M，其中所述起始信号的频率等于显示一帧画面的更新频率，M个所述时钟信号是依序轮流输出信号脉冲，且M个所述时钟信号的信号脉冲输出时间彼此不重叠，所述起始信号的脉宽起始于扫描第一帧画面时施加在所述最后一级移位缓存单元的所述第Ｍ个时钟信号的下降沿，并结束于扫描第二帧画面时施加在所述第一级移位缓存单元的所述第一个时钟信号的上升沿，所述第二帧画面是所述第一帧画面的下一帧画面。
  2. 如权利要求1所述的栅极驱动基板，其中每一移位缓存单元包含：
    上拉电路，其包含第一晶体管，其栅极耦接于第一节点，源极耦接于所述时钟信号，漏极耦接于所述输出端，用来依据所述时钟信号，由所述输出端提供所述扫描信号脉冲；
    上拉控制电路，其包含第二晶体管，其栅极耦接于所述每一移位缓存单元的前一个移位缓存单元的输出端，源极耦接于第一电源电压，漏极耦接于所述第一节点，用来依据所述每一移位缓存单元的前一个移位缓存单元的所述扫描信号脉冲，导通所述上拉电路；
    上升电路，耦接于所述第一节点和所述输出端之间，用来抬升所述第一节点的电位；
    下拉保持电路，耦接于所述第一节点、所述时钟信号以及第二电源电压，用来依据维持所述第一节点的低电平；以及
    下拉电路，耦接于所述第二电源电压、所述输出端以及所述每一移位缓存单元的下一个移位缓存单元的输出端，用来下拉所述第一节点的电位至所述第二电源电压。
  3. 根据权利要求2所述的栅极驱动基板，其中所述下拉电路包含：
    第三晶体管，其漏极电性连接于所述输出端，其源极电性连接于所述第二电源电压；以及
    第四晶体管，其漏极电性连接于所述第一节点，其源极电性连接于所述第二电源电压，其栅极电性连接于所述第三晶体管的栅极。
  4. 一种栅极驱动基板，其包含：
    数个呈矩阵排列的像素单元；
    数个晶体管，每一晶体管电性连接于其中一个像素单元；以及
    Ｎ个移位缓存单元，Ｎ个所述移位缓存单元以串联的方式耦接，每M个所述移位缓存单元由M个时钟信号控制，第一级移位缓存单元用来依据第一时钟信号以及起始信号，在输出端输出扫描信号脉冲，最后一级移位缓存单元用来依据第Ｍ个时钟信号以及所述起始信号，在输出端输出扫描信号脉冲，其中N、M皆为正整数，且N大于M，其中所述起始信号的脉宽起始于扫描第一帧画面时施加在所述最后一级移位缓存单元的所述第Ｍ个时钟信号的下降沿，并结束于扫描第二帧画面时施加在所述第一级移位缓存单元的所述第一个时钟信号的上升沿，所述第二帧画面是所述第一帧画面的下一帧画面。
  5. 如权利要求4所述的栅极驱动基板，其中所述起始信号的频率等于显示一帧画面的更新频率。
  6. 如权利要求4所述的栅极驱动基板，其中 M个所述时钟信号是依序轮流输出信号脉冲，且M个所述时钟信号的信号脉冲输出时间彼此不重叠。
  7. 如权利要求4所述的栅极驱动基板，其中每一移位缓存单元包含：
    上拉电路，其包含第一晶体管，其栅极耦接于第一节点，源极耦接于所述时钟信号，漏极耦接于所述输出端，用来依据所述时钟信号，由所述输出端提供所述扫描信号脉冲；
    上拉控制电路，其包含第二晶体管，其栅极耦接于所述每一移位缓存单元的前一个移位缓存单元的输出端，源极耦接于第一电源电压，漏极耦接于所述第一节点，用来依据所述每一移位缓存单元的前一个移位缓存单元的所述扫描信号脉冲，导通所述上拉电路；
    下拉保持电路，耦接于所述第一节点、所述时钟信号以及第二电源电压，用来依据维持所述第一节点的低电平；以及
    下拉电路，耦接于所述第二电源电压、所述输出端以及所述每一移位缓存单元的下一个移位缓存单元的输出端，用来下拉所述第一节点的电位至所述第二电源电压。
  8. 根据权利要求7所述的栅极驱动基板，其中所述移位缓存单元另包含上升电路，耦接于所述第一节点和所述输出端之间，用来抬升所述第一节点的电位。
  9. 根据权利要求8所述的栅极驱动基板，其中所述下拉电路包含：
    第三晶体管，其漏极电性连接于所述输出端，其源极电性连接于所述第二电源电压；以及
    第四晶体管，其漏极电性连接于所述第一节点，其源极电性连接于所述第二电源电压，其栅极电性连接于所述第三晶体管的栅极。
  10. 一种液晶显示器，其包含：
    源极驱动器，用来输出数据信号至数个像素单元使其显示灰阶；以及
    栅极驱动电路，用来输出扫描信号使得数个晶体管开启，所述栅极驱动电路包含：
    Ｎ个移位缓存单元，Ｎ个所述移位缓存单元以串联的方式耦接，每M个所述移位缓存单元由M个时钟信号控制，第一级移位缓存单元用来依据第一时钟信号以及起始信号，在输出端输出扫描信号脉冲，最后一级移位缓存单元用来依据第Ｍ个时钟信号以及所述起始信号，在输出端输出扫描信号脉冲，其中N、M皆为正整数，且N大于M，其中所述起始信号的脉宽起始于扫描第一帧画面时施加在所述最后一级移位缓存单元的所述第Ｍ个时钟信号的下降沿，并结束于扫描第二帧画面时施加在所述第一级移位缓存单元的所述第一个时钟信号的上升沿，所述第二帧画面是所述第一帧画面的下一帧画面。
  11. 如权利要求10所述的液晶显示器，其中所述起始信号的频率等于显示一帧画面的更新频率。
  12. 如权利要求10所述的液晶显示器，其中 M个所述时钟信号是依序轮流输出信号脉冲，且M个所述时钟信号的信号脉冲输出时间彼此不重叠。
  13. 如权利要求10所述的液晶显示器，其中每一移位缓存单元包含：
    上拉电路，其包含第一晶体管，其栅极耦接于第一节点，源极耦接于所述时钟信号，漏极耦接于所述输出端，用来依据所述时钟信号，由所述输出端提供所述扫描信号脉冲；
    上拉控制电路，其包含第二晶体管，其栅极耦接于所述每一移位缓存单元的前一个移位缓存单元的输出端，源极耦接于第一电源电压，漏极耦接于所述第一节点，用来依据所述每一移位缓存单元的前一个移位缓存单元的所述扫描信号脉冲，导通所述上拉电路；
    下拉保持电路，耦接于所述第一节点、所述时钟信号以及第二电源电压，用来依据维持所述第一节点的低电平；以及
    下拉电路，耦接于所述第二电源电压、所述输出端以及所述每一移位缓存单元的下一个移位缓存单元的输出端，用来下拉所述第一节点的电位至所述第二电源电压。
  14. 根据权利要求13所述的液晶显示器，其中所述移位缓存单元另包含上升电路，耦接于所述第一节点和所述输出端之间，用来抬升所述第一节点的电位。
  15. 根据权利要求14所述的液晶显示器，其中所述下拉电路包含：
    第三晶体管，其漏极电性连接于所述输出端，其源极电性连接于所述第二电源电压；以及
    第四晶体管，其漏极电性连接于所述第一节点，其源极电性连接于所述第二电源电压，其栅极电性连接于所述第三晶体管的栅极。
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