WO2017049662A1 - 扫描驱动电路及具有该电路的液晶显示装置 - Google Patents

扫描驱动电路及具有该电路的液晶显示装置 Download PDF

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Publication number
WO2017049662A1
WO2017049662A1 PCT/CN2015/091195 CN2015091195W WO2017049662A1 WO 2017049662 A1 WO2017049662 A1 WO 2017049662A1 CN 2015091195 W CN2015091195 W CN 2015091195W WO 2017049662 A1 WO2017049662 A1 WO 2017049662A1
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Prior art keywords
controllable switch
control
output
module
signal
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PCT/CN2015/091195
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English (en)
French (fr)
Inventor
王聪
杜鹏
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深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司, 武汉华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/888,698 priority Critical patent/US9805682B2/en
Publication of WO2017049662A1 publication Critical patent/WO2017049662A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a scan driving circuit and a liquid crystal display device having the same.
  • a scan driving circuit is used, that is, a conventional thin film transistor liquid crystal display array process is used to fabricate a scan driving circuit on an array substrate to realize a driving method for progressive scanning.
  • each scan driving circuit drives only one scanning line, and generally a plurality of scanning lines are arranged in the liquid crystal display device, which requires designing a plurality of scanning driving circuits, which inevitably makes the circuit design complicated and takes up space, Conducive to the narrow frame design of the liquid crystal display device.
  • the technical problem to be solved by the present invention is to provide a scan driving circuit and a liquid crystal display device having the same, which simplifies the circuit of the liquid crystal display device, saves space, and further facilitates the narrow bezel design of the liquid crystal display device.
  • the present invention adopts a technical solution to provide a scan driving circuit
  • the scan driving circuit includes a plurality of cascaded scan driving units, and each of the scan driving units includes:
  • An input module configured to output a low level signal according to the received first clock signal, the upper downlink signal, and the lower downlink signal of the current level
  • each driving circuit driving a corresponding one of the scanning lines, each of the driving circuits comprising:
  • control module configured to receive the low level signal output by the input module, and output a control signal according to the low level signal, the second clock signal, and the reset signal;
  • An output module configured to receive the control signal output by the control module and be turned on or off according to the control signal
  • a pull-down module is connected to the control module and the output module, and the pull-down module receives a control signal output by the control module and is turned on or off according to the control signal;
  • a scan line connecting the output module and the pull-down module for outputting a high level scan drive signal or a low level scan drive signal to the pixel unit;
  • the pull-down module When the output module is turned off, the pull-down module is turned on, so that the scan line outputs a scan driving signal of a low level to the pixel unit; when the output module is turned on, the pull-down module is turned off, thereby The scan line outputs a high level scan drive signal to the pixel unit.
  • the input module includes first to tenth controllable switches, and a control end of the first controllable switch is connected to the first clock signal, and an input end of the first controllable switch is connected to a high potential end.
  • An output end of the first controllable switch is connected to an output end of the second controllable switch, and a control end of the second controllable switch is connected to the first clock signal and a control end of the first controllable switch,
  • the input end of the second controllable switch is connected to the low-potential end
  • the control end of the third controllable switch is connected to the lower-level signal of the current control
  • the input end of the third controllable switch is connected to the low-potential end
  • the output end of the third controllable switch is connected to the input end of the fourth controllable switch, and the control end of the fourth controllable switch is connected to the output end of the first controllable switch
  • the fourth An output end of the control switch is connected to an output end of the fifth controllable switch,
  • the control module of each of the driving circuits includes eleventh to thirteenth controllable switches, and the control end of the eleventh controllable switch is connected to the second clock signal, the eleventh controllable switch The input end is connected to the output end of the input module, and the output end of the eleventh controllable switch is connected to the output ends of the twelfth controllable switch and the thirteenth controllable switch.
  • the input ends of the twelfth controllable switch and the thirteenth controllable switch are connected to the high potential end, and the control end of the twelfth controllable switch is connected to a third clock signal, the thirteenth a control end of the control switch is connected to the reset signal, and an output end of the twelfth controllable switch and the thirteenth controllable switch is connected as an output end of the control module, and an output end of the control module is connected The output module and the pull-down module.
  • the output module of each of the driving circuits includes a fourteenth to seventeenth controllable switch, and a control end of the fourteenth controllable switch is connected to a control end of the fifteenth controllable switch and the control An output end of the module, the input end of the fourteenth controllable switch is connected to the high potential end, and an output end of the fourteenth controllable switch is connected to an output end of the fifteenth controllable switch An input end of the fifteen controllable switch is connected to the low potential end, and a control end of the sixteenth controllable switch is connected to an output end of the fourteenth controllable switch, and an input end of the sixteenth controllable switch Connecting an input end of the seventeenth controllable switch and a fourth clock signal, wherein an output end of the sixteenth controllable switch is connected to the driving circuit to drive the scan line and the seventeenth controllable switch The output end of the seventeenth controllable switch is connected to the output end of the control module and the pull-down module.
  • the pull-down module of each of the driving circuits includes an eighteenth controllable switch, and a control end of the eighteenth controllable switch is connected to an output end of the control module, and an input end of the eighteenth controllable switch The low potential end is connected, and an output end of the eighteenth controllable switch is connected to the scan line and an output end of the seventeenth controllable switch.
  • the first controllable switch, the fifth controllable switch, the sixth controllable switch, the seventh controllable switch, the eighth controllable switch, and the fourteenth controllable switch And the seventeenth controllable switch is a PMOS type thin film transistor; the second controllable switch, the third controllable switch, the fourth controllable switch, the ninth controllable switch, the a tenth controllable switch, the eleventh controllable switch, the twelfth controllable switch, the thirteenth controllable switch, the fifteenth controllable switch, the sixteenth controllable switch And the eighteenth controllable switch is an NMOS type thin film transistor.
  • the time for the high level of the upper downlink signal, the lower downlink signal, and the fourth clock signal is increased to three times to ensure that the scan driving signal on time is constant.
  • the frequency of the high level and low level switching of a clock signal is reduced to 1/3.
  • the driving circuit outputs different scan driving signals to the scan lines corresponding to the driving circuit by the control of different second clock signals, and the first clock signal and the upper downlink signal are both For the low level signal, the lower stage signal and the fourth clock signal are both high level signals.
  • the plurality of driving circuits comprise three driving circuits.
  • another technical solution adopted by the present invention is to provide a liquid crystal display device comprising the scan driving circuit as described above.
  • the invention has the beneficial effects that the liquid crystal display device of the present invention is separately provided by the input module according to the received first clock signal, the upper-level downlink signal, and the lower-level signal of the lower-level signal outputted by the input module. And a control module of the plurality of driving circuits, so that the control module of each driving circuit controls the corresponding output module and the pull-down module to be turned on or off according to the received low level signal, the second clock signal, and the reset signal output control signal,
  • the scan driving signal is provided to the scan lines connecting each of the driving circuits, thereby simplifying the circuit of the liquid crystal display device, saving space, and thereby facilitating the narrow bezel design of the liquid crystal display device.
  • FIG. 1 is a schematic structural view of a scan driving circuit in the prior art
  • FIG. 3 is a schematic structural view of a scan driving circuit of the present invention.
  • Figure 4 is a waveform diagram of a scan driving circuit of the present invention.
  • Fig. 5 is a schematic view of a liquid crystal display device of the present invention.
  • FIG. 1 in the prior art, a plurality of scanning lines are disposed in a liquid crystal display device, and corresponding scanning driving circuits are required to be corresponding to the scanning lines, and each of the existing scanning driving circuits drives only one scanning line.
  • a scan driving circuit includes an input module 10, an output module 20, and a pull-down module 30, which will complicate the circuit design in the liquid crystal display device. Please continue to refer to FIG. 2.
  • FIG. 2 is a waveform diagram of a prior art scan driving circuit.
  • the input module 10 When the input module 10 receives the upper-level downlink signal ST(N-2) and the first clock signal CK are both low level, and the lower-level downlink signal ST(N) is at a high level,
  • the thin film transistor t1 converts the low level signal into a high level signal, so that the thin film transistors t3 and t4 are both turned on, the input module 10 outputs a low level signal, and the thin film transistors t13 and t14 in the output module 20
  • the second clock signal CK3 When the second clock signal CK3 is at a high level, a scan driving signal of a high level is output to a scan line corresponding to the scan driving circuit, and the principle of the next-stage scan driving circuit is the same.
  • FIG. 3 is a schematic structural diagram of a scan driving circuit of the present invention.
  • the scan driving circuit of the present invention includes a plurality of cascaded scan driving units 1.
  • Each scan driving unit 1 includes an input module 100 and a plurality of driving circuits 200.
  • Each driving circuit 200 drives a corresponding one of the scans. line.
  • the plurality of driving circuits 200 are three driving circuits for driving the scanning lines G(N-1), G(N), and G(N, respectively. +1)
  • the drive circuit 200 that drives the scanning line G(N-1) will be described as an example.
  • the input module 100 is configured to output a low level signal according to the received first clock signal, the upper downlink signal, and the lower downlink signal; each driving circuit 200 includes a control module 210, and is connected to the input module 100. Receiving a low level signal output by the input module 100, and outputting a control signal according to the low level signal, the second clock signal, and the reset signal; and the output module 220 is connected to the control module 210, for receiving the The control signal outputted by the control module 210 is turned on or off according to the control signal; the pull-down module 230 is connected to the control module 210 and the output module 220, and the pull-down module 230 receives the control signal output by the control module 210.
  • the input module 100 includes first to tenth controllable switches T1-T10, the control end of the first controllable switch T1 is connected to the first clock signal, and the input end of the first controllable switch T1 is connected high.
  • the output end of the first controllable switch T1 is connected to the output end of the second controllable switch T2, and the control end of the second controllable switch T2 is connected to the first clock signal and the first a control terminal of the controllable switch T1, the input end of the second controllable switch T2 is connected to the low potential end L, and the control end of the third controllable switch T3 is connected to the lower stage signal of the current level, the third
  • the input end of the controllable switch T3 is connected to the low potential end L
  • the output end of the third controllable switch T3 is connected to the input end of the fourth controllable switch T4, and the control end of the fourth controllable switch T4
  • An output end of the first controllable switch T1 is connected, an output end of the
  • the control end of the sixth controllable switch T6 is connected to the output end of the first controllable switch T1, the input end of the sixth controllable switch T6 is connected to the high potential end H, and the seventh controllable switch T7
  • the input end is connected to the input end of the sixth controllable switch T6 and the high potential end H
  • the control end of the seventh controllable switch T7 is connected to the first clock signal
  • the seventh controllable switch T7 The output end of the eighth controllable switch T8 is connected to the input end of the eighth controllable switch T8, and the output end of the eighth controllable switch T8 is connected to the output end.
  • An output end of the ninth controllable switch T9, the control end of the ninth controllable switch T9 is connected to the first clock signal, and an input end of the ninth controllable switch T9 is connected to the tenth controllable switch T10
  • the output end of the tenth controllable switch T10 is connected to the upper stage downlink signal, the input end of the tenth controllable switch T10 is connected to the low potential end L, the fourth controllable switch T4 and An output end of the ninth controllable switch T9 is connected as an output end of the input module 100, and the input module 10
  • the output of 0 is connected to each drive circuit 200.
  • the control module 210 of each of the driving circuits 200 includes eleventh to thirteenth controllable switches T11-T13, and the control end of the eleventh controllable switch T11 is connected to the second clock signal, the tenth An input end of the controllable switch T11 is connected to an output end of the input module 100, and an output end of the eleventh controllable switch T11 is connected to the twelfth controllable switch T12 and the thirteenth controllable switch T13 Output, An input end of the twelfth controllable switch T12 and the thirteenth controllable switch T13 is connected to the high potential end H, and a control end of the twelfth controllable switch T12 is connected to a third clock signal, The control end of the thirteenth controllable switch T13 is connected to the reset signal, and the output ends of the twelfth controllable switch T12 and the thirteenth controllable switch T13 are connected as an output end of the control module 210.
  • the output of the control module 210 is connected
  • the output module 220 of each driving circuit 200 includes fourteenth to seventeenth controllable switches T14-T17, and the control end of the fourteenth controllable switch T14 is connected to the control of the fifteenth controllable switch T15 And the output end of the control module 210, the input end of the fourteenth controllable switch T14 is connected to the high potential end H, and the output end of the fourteenth controllable switch T14 is connected to the fifteenth The output end of the fifteenth controllable switch T15 is connected to the low potential end L, and the control end of the sixteenth controllable switch T16 is connected to the fourteenth controllable switch T14 An output end of the sixteenth controllable switch T16 is connected to an input end of the seventeenth controllable switch T17 and a fourth clock signal, and an output end of the sixteenth controllable switch T16 is connected to the drive
  • the circuit 200 corresponds to the scan line (such as the scan line G(N-1)) and the output end of the seventeenth controllable switch T17, and the control end of
  • the pull-down module 230 of each of the driving circuits 200 includes an eighteen controllable switch T18, and a control end of the eighteenth controllable switch T18 is connected to an output end of the control module 210, and the eighteenth controllable switch The input end of the T18 is connected to the low potential end L, and the output end of the eighteenth controllable switch T18 is connected to the scan line and the output end of the seventeenth controllable switch T17.
  • the first controllable switch T1, the fifth controllable switch T5, the sixth controllable switch T6, the seventh controllable switch T7, the eighth controllable switch T8, the fourteenth The controllable switch T14 and the seventeenth controllable switch T17 are both PMOS type thin film transistors; the second controllable switch T2, the third controllable switch T3, the fourth controllable switch T4, the a ninth controllable switch T9, the tenth controllable switch T10, the eleventh controllable switch T11, the twelfth controllable switch T12, the thirteenth controllable switch T13, the tenth
  • the five controllable switches T15, the sixteenth controllable switch T16 and the eighteenth controllable switch T18 are all NMOS type thin film transistors.
  • the first clock signal is the first clock signal CK
  • the upper downlink signal is the upper downlink signal ST(N-2)
  • the downlink signal of the current level is the downlink signal of the current level.
  • the second clock signals are second clock signals CK01, CK02, and CK03, respectively
  • the third clock signals are third clock signals XCK01, XCK02, and XCK03, respectively
  • the reset signal is a reset signal Reset.
  • the fourth clock signal is a fourth clock signal CK3, and the scan lines are scan lines G(N-1), G(N), and G(N+1), wherein the corresponding scan lines G(N-1)
  • the second and third clock signals are CK01 and XCK01
  • the second and third clock signals corresponding to the scan line G(N) are CK02 and XCK02
  • the second and third clock signals corresponding to the scan line G(N+1) For CK03 and XCK03.
  • Each of the driving circuits 200 outputs different scan driving signals to the scan lines connected thereto by the control of different second clock signals, and the first clock signal and the upper downlink signals are low level signals.
  • the level down signal and the fourth clock signal are both high level signals.
  • the working principle of the scan driving circuit is as follows:
  • the first controllable switch T1 When the first clock signal CK and the upper downlink signal ST(N-2) received by the input module 100 are at a low level, and the received downlink signal ST(N) is at a high level,
  • the first controllable switch T1 is turned on, the output end thereof outputs a high level signal, the fourth controllable switch T4 is turned on, the sixth controllable switch T6 is turned off, and the third controllable switch T3 is turned on.
  • the control terminal receives the high level signal of the lower stage downlink signal ST(N) and is turned on, so that the output end of the fourth controllable switch T4 is due to the third and fourth controllable switches T3 and T4 Turning on is connected to the low potential terminal L, thereby outputting a low level signal to the control module 210 of each driving circuit 200.
  • the driving circuit 200 corresponding to the scanning line G(n-1) is taken as an example for description.
  • the working principle of the remaining driving circuit 200 is the same, and details are not described herein again.
  • the eleventh controllable switch T11 leads The twelveth and thirteenth controllable switches T12 and T13 are both turned off, and the output ends of the twelfth and thirteenth controllable switches T12 and T13, that is, the output end of the control module 210 A low level control signal is output to the output module 220 and the pull down module 230.
  • the output module 220 receives the low level signal output by the control module 210
  • the fifteenth and eighteenth controllable switches T15 and T18 are both turned off, and the fourteenth controllable switch T14 is turned on.
  • the high level signal outputted by the output terminal controls the sixteen controllable switch T16 to be turned on, and the control end of the seventeenth controllable switch T17 receives the low level control signal output by the control module 210.
  • the scan line G(n-1) receives a high level scan drive signal output by the drive circuit 200 and transmits the scan drive signal to the pixel unit.
  • the eleventh controllable switch T11 When the second clock signal CK01 received by the control module 210 of the driving circuit 200 is at a low level, and the reset signal Reset and the third clock signal XCK01 are both at a high level, the eleventh controllable switch T11 is turned off.
  • the twelfth and thirteenth controllable switches T12 and T13 are both turned on, and the output ends of the twelfth and thirteenth controllable switches T12 and T13, that is, the output end of the control module 210 A control signal of a high level is output to the output module 220 and the pull-down module 230.
  • the fourteenth controllable switch T14 When the output module 220 receives the high level signal output by the control module 210, the fourteenth controllable switch T14 is turned off, the fifteenth controllable switch T15 is turned on, and the output of the output terminal is low.
  • the level signal controls the sixteen controllable switch T16 to be turned off, and the control end of the seventeenth controllable switch T17 receives the high level signal output by the control module 210, and the eighteenth controllable
  • the control terminal of the switch T18 receives the high level signal output by the control module 210 and is turned on, thereby connecting the scan line G(n-1) to the low potential terminal L, thereby causing the scan line G (n-1) transmitting a scan driving signal of a low level to the pixel unit.
  • FIG. 4 is a waveform diagram of the scan driving circuit of the present invention.
  • the time of the upper level downlink signal, the lower level downlink signal, and the fourth clock signal high level is increased to three times, the first clock The frequency of the high and low switching of the signal is reduced to 1/3.
  • FIG. 5 is a schematic diagram of a liquid crystal display device of the present invention.
  • the liquid crystal display device includes the aforementioned scan driving circuit, and the scan driving circuit is disposed at both ends of the liquid crystal display device.
  • the scan driving circuit of the present invention is respectively supplied to the control module 210 of the plurality of driving circuits 200 according to the received first clock signal, the upper-level downlink signal, and the lower-level signal of the lower-level signal output by the input module 100, so that each The control module 210 of the driving circuit 200 controls the corresponding output module 220 and the pull-down module 230 to be turned on or off according to the received low level signal, the second clock signal, and the reset signal output control signal to correspond to each driving circuit 200.
  • the driven scan line provides a scan driving signal, thereby simplifying the circuit of the liquid crystal display device, saving space, and thereby facilitating the narrow bezel design of the liquid crystal display device.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
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Abstract

提供一种扫描驱动电路及液晶显示装置。所述扫描驱动电路包括多个级联的扫描驱动单元（1），每一扫描驱动单元（1）包括输出低电平信号的输入模块（100）及若干驱动电路（200），每一驱动电路（200）对应驱动一条扫描线。每一驱动电路（200）包括：控制模块（210），根据接收的低电平信号输出控制信号；输出模块（220）及下拉模块（230），根据接收的控制信号导通或截止；扫描线（G（N-1）、G（N）及G（N+1）），输出高或低电平的扫描驱动信号至像素单元。当输出模块（220）截止时，下拉模块（230）导通，扫描线（G（N-1）、G（N）及G（N+1））输出低电平的扫描驱动信号至像素单元；当输出模块（220）导通时，下拉模块（230）截止，扫描线（G（N-1）、G（N）及G（N+1））输出高电平的扫描驱动信号至所述像素单元。以此实现简化液晶显示装置的电路，节省空间，进而利于液晶显示装置的窄边框设计。

Description

扫描驱动电路及具有该电路的液晶显示装置
【技术领域】
本发明涉及显示技术领域，特别是涉及一种扫描驱动电路及具有该电路的液晶显示装置。
【背景技术】
目前的液晶显示装置中采用扫描驱动电路，也就是利用现有薄膜晶体管液晶显示器阵列制程将扫描驱动电路制作在阵列基板上，实现对逐行扫描的驱动方式。现有的液晶显示装置中每一扫描驱动电路仅驱动一条扫描线，而一般液晶显示装置中设置诸多条扫描线，这将需要设计诸多扫描驱动电路，势必使得电路设计复杂，且占用空间，不利于液晶显示装置的窄边框设计。
【发明内容】
本发明主要解决的技术问题是提供一种扫描驱动电路及具有该电路的液晶显示装置，以简化液晶显示装置的电路，节省空间，进而利于液晶显示装置的窄边框设计。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种扫描驱动电路，所述扫描驱动电路包括若干级联的扫描驱动单元，每一所述扫描驱动单元包括：
一输入模块，用于根据接收到的第一时钟信号、上级下传信号及本级下传信号输出低电平信号；及
若干驱动电路，每一驱动电路驱动对应的一条扫描线，每一所述驱动电路包括：
控制模块，连接所述输入模块，用于接收所述输入模块输出的低电平信号，并根据所述低电平信号、第二时钟信号及复位信号输出控制信号；
输出模块，连接所述控制模块，用于接收所述控制模块输出的控制信号并根据所述控制信号导通或截止；
下拉模块，连接所述控制模块及所述输出模块，所述下拉模块接收所述控制模块输出的控制信号并根据所述控制信号导通或截止；
扫描线，连接所述输出模块及所述下拉模块，用于输出高电平的扫描驱动信号或者低电平的扫描驱动信号至像素单元；
当所述输出模块截止时，所述下拉模块导通，从而所述扫描线输出低电平的扫描驱动信号至所述像素单元；当所述输出模块导通时，所述下拉模块截止，从而所述扫描线输出高电平的扫描驱动信号至所述像素单元。
其中，所述输入模块包括第一至第十可控开关，所述第一可控开关的控制端连接所述第一时钟信号，所述第一可控开关的输入端连接高电位端，所述第一可控开关的输出端连接所述第二可控开关的输出端，所述第二可控开关的控制端连接所述第一时钟信号及所述第一可控开关的控制端，所述第二可控开关的输入端连接低电位端，所述第三可控开关的控制端连接所述本级下传信号，所述第三可控开关的输入端连接所述低电位端，所述第三可控开关的输出端连接所述第四可控开关的输入端，所述第四可控开关的控制端连接所述第一可控开关的输出端，所述第四可控开关的输出端连接所述第五可控开关的输出端，所述第五可控开关的控制端连接所述上级下传信号，所述第五可控开关的输入端连接所述第六可控开关的输出端，所述第六可控开关的控制端连接所述第一可控开关的输出端，所述第六可控开关的输入端连接所述高电位端，所述第七可控开关的输入端连接所述第六可控开关的输入端及所述高电位端，所述第七可控开关的控制端连接所述第一时钟信号，所述第七可控开关的输出端连接所述第八可控开关的输入端，所述第八可控开关的控制端连接所述本级下传信号，所述第八可控开关的输出端连接所述第九可控开关的输出端，所述第九可控开关的控制端连接所述第一时钟信号，所述第九可控开关的输入端连接所述第十可控开关的输出端，所述第十可控开关的控制端连接所述上级下传信号，所述第十可控开关的输入端连接所述低电位端，所述第四可控开关及所述第九可控开关的输出端相连作为所述输入模块的输出端，所述输入模块的输出端连接每一驱动电路。
其中，所述每一驱动电路的控制模块包括第十一至第十三可控开关，所述第十一可控开关的控制端连接所述第二时钟信号，所述第十一可控开关的输入端连接所述输入模块的输出端，所述第十一可控开关的输出端连接所述第十二可控开关及所述第十三可控开关的输出端， 所述第十二可控开关及所述第十三可控开关的输入端连接所述高电位端，所述第十二可控开关的控制端连接第三时钟信号，所述第十三可控开关的控制端连接所述复位信号，所述第十二可控开关及所述第十三可控开关的输出端相连作为所述控制模块的输出端，所述控制模块的输出端连接所述输出模块及所述下拉模块。
其中，所述每一驱动电路的输出模块包括第十四至第十七可控开关，所述第十四可控开关的控制端连接所述第十五可控开关的控制端及所述控制模块的输出端，所述第十四可控开关的输入端连接所述高电位端，所述第十四可控开关的输出端连接所述第十五可控开关的输出端，所述第十五可控开关的输入端连接所述低电位端，所述第十六可控开关的控制端连接所述第十四可控开关的输出端，所述第十六可控开关的输入端连接所述第十七可控开关的输入端及第四时钟信号，所述第十六可控开关的输出端连接所述驱动电路对应驱动所述扫描线及所述第十七可控开关的输出端，所述第十七可控开关的控制端连接所述控制模块的输出端及所述下拉模块。
其中，所述每一驱动电路的下拉模块包括第十八可控开关，所述第十八可控开关的控制端连接所述控制模块的输出端，所述第十八可控开关的输入端连接所述低电位端，所述第十八可控开关的输出端连接所述扫描线及所述第十七可控开关的输出端。
其中，所述第一可控开关、所述第五可控开关、所述第六可控开关、所述第七可控开关、所述第八可控开关、所述第十四可控开关及所述第十七可控开关均为PMOS型薄膜晶体管；所述第二可控开关、所述第三可控开关、所述第四可控开关、所述第九可控开关、所述第十可控开关、所述第十一可控开关、所述第十二可控开关、所述第十三可控开关、所述第十五可控开关、所述第十六可控开关及所述第十八可控开关均为NMOS型薄膜晶体管。
其中，为保证所述扫描驱动信号开启时间不变，将所述上级下传信号、所述本级下传信号及所述第四时钟信号的高电平的时间增加至3倍，所述第一时钟信号的高电平与低电平切换的频率减少至1/3。
其中，所述每一驱动电路通过不同的第二时钟信号的控制对所述驱动电路对应驱动的所述扫描线输出不同的扫描驱动信号，所述第一时钟信号及所述上级下传信号均为低电平信号，所述本级下传信号及所述第四时钟信号均为高电平信号。
其中，所述若干驱动电路包括3个驱动电路。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示装置，包括如上所述任一所述的扫描驱动电路。
本发明的有益效果是：区别于现有技术的情况，本发明的液晶显示装置通过输入模块根据接收到的第一时钟信号、上级下传信号及本级下传信号输出低电平信号分别提供给多个驱动电路的控制模块，以使得每一驱动电路的控制模块根据接收到的低电平信号、第二时钟信号及复位信号输出控制信号控制对应的输出模块及下拉模块导通或截止，以对连接每一驱动电路的扫描线提供扫描驱动信号，以此实现简化液晶显示装置的电路，节省空间，进而利于液晶显示装置的窄边框设计。
【附图说明】
图1是现有技术中扫描驱动电路的结构示意图；
图2是现有技术中扫描驱动电路的波形图；
图3是本发明的扫描驱动电路的结构示意图；
图4是本发明的扫描驱动电路的波形图；
图5是本发明的液晶显示装置的示意图。
【具体实施方式】
请参阅图1，现有技术中液晶显示装置中设置有若干条扫描线，也就需要对应这些扫描线设置相应的扫描驱动电路，而现有的每一扫描驱动电路仅驱动一条扫描线，每一扫描驱动电路包括输入模块10、输出模块20及下拉模块30，这将使得液晶显示装置中的电路设计复杂。请继续参阅图2，图2为现有技术中扫描驱动电路的波形图。其中，当所述输入模块10接收到上级下传信号ST（N-2）及第一时钟信号CK均为低电平，且本级下传信号ST（N）为高电平时，通过所述薄膜晶体管t1将所述低电平信号转换为高电平信号，使得薄膜晶体管t3及t4均导通，所述输入模块10输出低电平信号，所述输出模块20中的薄膜晶体管t13及t14均导通，所述第二时钟信号CK3为高电平时输出高电平的扫描驱动信号给对应连接所述扫描驱动电路的扫描线，下一级扫描驱动电路原理相同。
请参阅图3，是本发明的扫描驱动电路的结构示意图。如图3所示，本发明的扫描驱动电路包括多个级联的扫描驱动单元1，每一扫描驱动单元1包括一输入模块100及若干驱动电路200，每一驱动电路200驱动对应的一条扫描线。在本实施方式中，仅以一个扫描驱动单元1为例进行说明，所述若干驱动电路200为3个驱动电路，以分别驱动扫描线G（N-1）、G（N）及G（N+1），在此仅以驱动扫描线G（N-1）的驱动电路200为例进行说明。
所述输入模块100用于根据接收到的第一时钟信号、上级下传信号及本级下传信号输出低电平信号；每一驱动电路200包括控制模块210，连接所述输入模块100，用于接收所述输入模块100输出的低电平信号，并根据所述低电平信号、第二时钟信号及复位信号输出控制信号；输出模块220，连接所述控制模块210，用于接收所述控制模块210输出的控制信号并根据所述控制信号导通或截止；下拉模块230，连接所述控制模块210及所述输出模块220，所述下拉模块230接收所述控制模块210输出的控制信号并根据所述控制信号导通或截止；扫描线，连接所述输出模块220及所述下拉模块230，用于输出高电平的扫描驱动信号或者低电平的扫描驱动信号至像素单元；当所述输出模块220截止时，所述下拉模块230导通，从而所述扫描线输出低电平的扫描驱动信号至所述像素单元；当所述输出模块220导通时，所述下拉模块230截止，从而所述扫描线输出高电平的扫描驱动信号至所述像素单元。
所述输入模块100包括第一至第十可控开关T1-T10，所述第一可控开关T1的控制端连接所述第一时钟信号，所述第一可控开关T1的输入端连接高电位端H，所述第一可控开关T1的输出端连接所述第二可控开关T2的输出端，所述第二可控开关T2的控制端连接所述第一时钟信号及所述第一可控开关T1的控制端，所述第二可控开关T2的输入端连接低电位端L，所述第三可控开关T3的控制端连接所述本级下传信号，所述第三可控开关T3的输入端连接所述低电位端L，所述第三可控开关T3的输出端连接所述第四可控开关T4的输入端，所述第四可控开关T4的控制端连接所述第一可控开关T1的输出端，所述第四可控开关T4的输出端连接所述第五可控开关T5的输出端，所述第五可控开关T5的控制端连接所述上级下传信号，所述第五可控开关T5的输入端连接所述第六可控开关T6的输出端，所述第六可控开关T6的控制端连接所述第一可控开关T1的输出端，所述第六可控开关T6的输入端连接所述高电位端H，所述第七可控开关T7的输入端连接所述第六可控开关T6的输入端及所述高电位端H，所述第七可控开关T7的控制端连接所述第一时钟信号，所述第七可控开关T7的输出端连接所述第八可控开关T8的输入端，所述第八可控开关T8的控制端连接所述本级下传信号，所述第八可控开关T8的输出端连接所述第九可控开关T9的输出端，所述第九可控开关T9的控制端连接所述第一时钟信号，所述第九可控开关T9的输入端连接所述第十可控开关T10的输出端，所述第十可控开关T10的控制端连接所述上级下传信号，所述第十可控开关T10的输入端连接所述低电位端L，所述第四可控开关T4及所述第九可控开关T9的输出端相连作为所述输入模块100的输出端，所述输入模块100的输出端连接每一驱动电路200。
所述每一驱动电路200的控制模块210包括第十一至第十三可控开关T11-T13，所述第十一可控开关T11的控制端连接所述第二时钟信号，所述第十一可控开关T11的输入端连接所述输入模块100的输出端，所述第十一可控开关T11的输出端连接所述第十二可控开关T12及所述第十三可控开关T13的输出端， 所述第十二可控开关T12及所述第十三可控开关T13的输入端连接所述高电位端H，所述第十二可控开关T12的控制端连接第三时钟信号，所述第十三可控开关T13的控制端连接所述复位信号，所述第十二可控开关T12及所述第十三可控开关T13的输出端相连作为所述控制模块210的输出端，所述控制模块210的输出端连接所述输出模块220及所述下拉模块230。
所述每一驱动电路200的输出模块220包括第十四至第十七可控开关T14-T17，所述第十四可控开关T14的控制端连接所述第十五可控开关T15的控制端及所述控制模块210的输出端，所述第十四可控开关T14的输入端连接所述高电位端H，所述第十四可控开关T14的输出端连接所述第十五可控开关T15的输出端，所述第十五可控开关T15的输入端连接所述低电位端L，所述第十六可控开关T16的控制端连接所述第十四可控开关T14的输出端，所述第十六可控开关T16的输入端连接所述第十七可控开关T17的输入端及第四时钟信号，所述第十六可控开关T16的输出端连接所述驱动电路200对应驱动的所述扫描线（如扫描线G（N-1））及所述第十七可控开关T17的输出端，所述第十七可控开关T17的控制端连接所述控制模块210的输出端及所述下拉模块230。
所述每一驱动电路200的下拉模块230包括第十八可控开关T18，所述第十八可控开关T18的控制端连接所述控制模块210的输出端，所述第十八可控开关T18的输入端连接所述低电位端L，所述第十八可控开关T18的输出端连接所述扫描线及所述第十七可控开关T17的输出端。
所述第一可控开关T1、所述第五可控开关T5、所述第六可控开关T6、所述第七可控开关T7、所述第八可控开关T8、所述第十四可控开关T14及所述第十七可控开关T17均为PMOS型薄膜晶体管；所述第二可控开关T2、所述第三可控开关T3、所述第四可控开关T4、所述第九可控开关T9、所述第十可控开关T10、所述第十一可控开关T11、所述第十二可控开关T12、所述第十三可控开关T13、所述第十五可控开关T15、所述第十六可控开关T16及所述第十八可控开关T18均为NMOS型薄膜晶体管。
在本实施例中，所述第一时钟信号为第一时钟信号CK，所述上级下传信号为上级下传信号ST（N-2），所述本级下传信号为本级下传信号ST（N），所述第二时钟信号分别为第二时钟信号CK01、CK02及CK03，所述第三时钟信号分别为第三时钟信号XCK01、XCK02及XCK03，所述复位信号为复位信号Reset，所述第四时钟信号为第四时钟信号CK3，所述扫描线为扫描线G（N-1）、G（N）及G（N+1），其中，对应扫描线G（N-1）的第二及第三时钟信号为CK01及XCK01，对应扫描线G（N）的第二及第三时钟信号为CK02及XCK02，对应扫描线G（N+1）的第二及第三时钟信号为CK03及XCK03。所述每一驱动电路200通过不同的第二时钟信号的控制对连接其的所述扫描线输出不同的扫描驱动信号，所述第一时钟信号及所述上级下传信号均为低电平信号，所述本级下传信号及所述第四时钟信号均为高电平信号。
所述扫描驱动电路的工作原理如下：
当所述输入模块100接收到的第一时钟信号CK及所述上级下传信号ST（N-2）为低电平，而接收到的本级下传信号ST（N）为高电平时，所述第一可控开关T1导通，其输出端输出高电平信号，所述第四可控开关T4导通，所述第六可控开关T6截止，所述第三可控开关T3的控制端接收所述本级下传信号ST（N）的高电平信号而导通，因此所述第四可控开关T4的输出端由于所述第三及第四可控开关T3及T4的导通而被连接至所述低电位端L，进而输出低电平信号给每一驱动电路200的控制模块210。在此仅以对应连接扫描线G（n-1）的驱动电路200为例进行说明，其余驱动电路200的工作原理相同，在此不再赘述。
当所述驱动电路200的控制模块210接收到的第二时钟信号CK01为高电平，所述复位信号Reset及第三时钟信号XCK01均为低电平时，所述第十一可控开关T11导通，所述第十二及第十三可控开关T12及T13均截止，此时所述第十二及第十三可控开关T12及T13的输出端，即所述控制模块210的输出端输出低电平的控制信号给所述输出模块220及所述下拉模块230。当所述输出模块220接收到所述控制模块210输出的低电平信号时，所述第十五及第十八可控开关T15及T18均截止，所述第十四可控开关T14导通，其输出端输出的高电平信号控制所述第十六可控开关T16导通，所述第十七可控开关T17的控制端接收所述控制模块210输出的低电平的控制信号而导通，当所述第四时钟信号CK3为高电平时，所述扫描线G（n-1）接收到所述驱动电路200输出的高电平的扫描驱动信号并传输给所述像素单元。
当所述驱动电路200的控制模块210接收到的第二时钟信号CK01为低电平，所述复位信号Reset及第三时钟信号XCK01均为高电平时，所述第十一可控开关T11截止，所述第十二及第十三可控开关T12及T13均导通，此时所述第十二及第十三可控开关T12及T13的输出端，即所述控制模块210的输出端输出高电平的控制信号给所述输出模块220及所述下拉模块230。当所述输出模块220接收到所述控制模块210输出的高电平信号时，所述第十四可控开关T14截止，所述第十五可控开关T15导通，其输出端输出的低电平信号控制所述第十六可控开关T16截止，所述第十七可控开关T17的控制端接收到所述控制模块210输出的高电平信号而截止，所述第十八可控开关T18的控制端接收到所述控制模块210输出的高电平信号而导通，从而将所述扫描线G（n-1）连接至所述低电位端L，进而使得所述扫描线G（n-1）传输低电平的扫描驱动信号给所述像素单元。
请参阅图4，图4是本发明扫描驱动电路的波形图。为保证所述扫描驱动信号开启时间不变，将所述上级下传信号、所述本级下传信号及所述第四时钟信号的高电平的时间增加至3倍，所述第一时钟信号的高电平与低电平切换的频率减少至1/3。
请参阅图5，为本发明一种液晶显示装置的示意图。所述液晶显示装置包括前述的扫描驱动电路，所述扫描驱动电路设置在所述液晶显示装置的两端。
本发明的扫描驱动电路通过输入模块100根据接收到的第一时钟信号、上级下传信号及本级下传信号输出低电平信号分别提供给多个驱动电路200的控制模块210，以使得每一驱动电路200的控制模块210根据接收到的低电平信号、第二时钟信号及复位信号输出控制信号控制对应的输出模块220及下拉模块230导通或截止，以对每一驱动电路200对应驱动的扫描线提供扫描驱动信号，以此实现简化液晶显示装置的电路，节省空间，进而利于液晶显示装置的窄边框设计。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种扫描驱动电路，其中，所述扫描驱动电路包括级联的多个扫描驱动单元，每一所述扫描驱动单元包括：
    一输入模块，用于根据接收到的第一时钟信号、上级下传信号及本级下传信号输出低电平信号；及
    若干驱动电路，每一驱动电路驱动对应的一条扫描线，每一所述驱动电路包括：
    控制模块，连接所述输入模块，用于接收所述输入模块输出的低电平信号，并根据所述低电平信号、第二时钟信号及复位信号输出控制信号；
    输出模块，连接所述控制模块，用于接收所述控制模块输出的控制信号并根据所述控制信号导通或截止；
    下拉模块，连接所述控制模块及所述输出模块，所述下拉模块接收所述控制模块输出的控制信号并根据所述控制信号导通或截止；
    扫描线，连接所述输出模块及所述下拉模块，用于输出高电平的扫描驱动信号或者低电平的扫描驱动信号至像素单元；
    当所述输出模块截止时，所述下拉模块导通，从而所述扫描线输出低电平的扫描驱动信号至所述像素单元；当所述输出模块导通时，所述下拉模块截止，从而所述扫描线输出高电平的扫描驱动信号至所述像素单元。
  2. 根据权利要求1所述的扫描驱动电路，其中，所述输入模块包括第一至第十可控开关，所述第一可控开关的控制端连接所述第一时钟信号，所述第一可控开关的输入端连接高电位端，所述第一可控开关的输出端连接所述第二可控开关的输出端，所述第二可控开关的控制端连接所述第一时钟信号及所述第一可控开关的控制端，所述第二可控开关的输入端连接低电位端，所述第三可控开关的控制端连接所述本级下传信号，所述第三可控开关的输入端连接所述低电位端，所述第三可控开关的输出端连接所述第四可控开关的输入端，所述第四可控开关的控制端连接所述第一可控开关的输出端，所述第四可控开关的输出端连接所述第五可控开关的输出端，所述第五可控开关的控制端连接所述上级下传信号，所述第五可控开关的输入端连接所述第六可控开关的输出端，所述第六可控开关的控制端连接所述第一可控开关的输出端，所述第六可控开关的输入端连接所述高电位端，所述第七可控开关的输入端连接所述第六可控开关的输入端及所述高电位端，所述第七可控开关的控制端连接所述第一时钟信号，所述第七可控开关的输出端连接所述第八可控开关的输入端，所述第八可控开关的控制端连接所述本级下传信号，所述第八可控开关的输出端连接所述第九可控开关的输出端，所述第九可控开关的控制端连接所述第一时钟信号，所述第九可控开关的输入端连接所述第十可控开关的输出端，所述第十可控开关的控制端连接所述上级下传信号，所述第十可控开关的输入端连接所述低电位端，所述第四可控开关及所述第九可控开关的输出端相连作为所述输入模块的输出端，所述输入模块的输出端连接每一驱动电路。
  3. 根据权利要求2所述的扫描驱动电路，其中，所述每一驱动电路的控制模块包括第十一至第十三可控开关，所述第十一可控开关的控制端连接所述第二时钟信号，所述第十一可控开关的输入端连接所述输入模块的输出端，所述第十一可控开关的输出端连接所述第十二可控开关及所述第十三可控开关的输出端， 所述第十二可控开关及所述第十三可控开关的输入端连接所述高电位端，所述第十二可控开关的控制端连接第三时钟信号，所述第十三可控开关的控制端连接所述复位信号，所述第十二可控开关及所述第十三可控开关的输出端相连作为所述控制模块的输出端，所述控制模块的输出端连接所述输出模块及所述下拉模块。
  4. 根据权利要求3所述的扫描驱动电路，其中，所述每一驱动电路的输出模块包括第十四至第十七可控开关，所述第十四可控开关的控制端连接所述第十五可控开关的控制端及所述控制模块的输出端，所述第十四可控开关的输入端连接所述高电位端，所述第十四可控开关的输出端连接所述第十五可控开关的输出端，所述第十五可控开关的输入端连接所述低电位端，所述第十六可控开关的控制端连接所述第十四可控开关的输出端，所述第十六可控开关的输入端连接所述第十七可控开关的输入端及第四时钟信号，所述第十六可控开关的输出端连接所述驱动电路对应驱动的所述扫描线及所述第十七可控开关的输出端，所述第十七可控开关的控制端连接所述控制模块的输出端及所述下拉模块。
  5. 根据权利要求4所述的扫描驱动电路，其中，所述每一驱动电路的下拉模块包括第十八可控开关，所述第十八可控开关的控制端连接所述控制模块的输出端，所述第十八可控开关的输入端连接所述低电位端，所述第十八可控开关的输出端连接所述扫描线及所述第十七可控开关的输出端。
  6. 根据权利要求5所述的扫描驱动电路，其中，所述第一可控开关、所述第五可控开关、所述第六可控开关、所述第七可控开关、所述第八可控开关、所述第十四可控开关及所述第十七可控开关均为PMOS型薄膜晶体管；所述第二可控开关、所述第三可控开关、所述第四可控开关、所述第九可控开关、所述第十可控开关、所述第十一可控开关、所述第十二可控开关、所述第十三可控开关、所述第十五可控开关、所述第十六可控开关及所述第十八可控开关均为NMOS型薄膜晶体管。
  7. 根据权利要求4所述的扫描驱动电路，其中，为保证所述扫描驱动信号开启时间不变，将所述上级下传信号、所述本级下传信号及所述第四时钟信号的高电平的时间增加至3倍，所述第一时钟信号的高电平与低电平切换的频率减少至1/3。
  8. 根据权利要求4所述的扫描驱动电路，其中，所述每一驱动电路通过不同的第二时钟信号的控制对所述驱动电路对应驱动的所述扫描线输出不同的扫描驱动信号，所述第一时钟信号及所述上级下传信号均为低电平信号，所述本级下传信号及所述第四时钟信号均为高电平信号。
  9. 根据权利要求1所述的扫描驱动电路，其中，所述若干驱动电路包括3个驱动电路。
  10. 一种液晶显示装置，其中，所述液晶显示装置包括扫描驱动电路，所述扫描驱动电路包括级联的多个扫描驱动单元，每一所述扫描驱动单元包括：
    一输入模块，用于根据接收到的第一时钟信号、上级下传信号及本级下传信号输出低电平信号；及
    若干驱动电路，每一驱动电路驱动对应的一条扫描线，每一所述驱动电路包括：
    控制模块，连接所述输入模块，用于接收所述输入模块输出的低电平信号，并根据所述低电平信号、第二时钟信号及复位信号输出控制信号；
    输出模块，连接所述控制模块，用于接收所述控制模块输出的控制信号并根据所述控制信号导通或截止；
    下拉模块，连接所述控制模块及所述输出模块，所述下拉模块接收所述控制模块输出的控制信号并根据所述控制信号导通或截止；
    扫描线，连接所述输出模块及所述下拉模块，用于输出高电平的扫描驱动信号或者低电平的扫描驱动信号至像素单元；
    当所述输出模块截止时，所述下拉模块导通，从而所述扫描线输出低电平的扫描驱动信号至所述像素单元；当所述输出模块导通时，所述下拉模块截止，从而所述扫描线输出高电平的扫描驱动信号至所述像素单元。
  11. 根据权利要求10所述的液晶显示装置，其中，所述输入模块包括第一至第十可控开关，所述第一可控开关的控制端连接所述第一时钟信号，所述第一可控开关的输入端连接高电位端，所述第一可控开关的输出端连接所述第二可控开关的输出端，所述第二可控开关的控制端连接所述第一时钟信号及所述第一可控开关的控制端，所述第二可控开关的输入端连接低电位端，所述第三可控开关的控制端连接所述本级下传信号，所述第三可控开关的输入端连接所述低电位端，所述第三可控开关的输出端连接所述第四可控开关的输入端，所述第四可控开关的控制端连接所述第一可控开关的输出端，所述第四可控开关的输出端连接所述第五可控开关的输出端，所述第五可控开关的控制端连接所述上级下传信号，所述第五可控开关的输入端连接所述第六可控开关的输出端，所述第六可控开关的控制端连接所述第一可控开关的输出端，所述第六可控开关的输入端连接所述高电位端，所述第七可控开关的输入端连接所述第六可控开关的输入端及所述高电位端，所述第七可控开关的控制端连接所述第一时钟信号，所述第七可控开关的输出端连接所述第八可控开关的输入端，所述第八可控开关的控制端连接所述本级下传信号，所述第八可控开关的输出端连接所述第九可控开关的输出端，所述第九可控开关的控制端连接所述第一时钟信号，所述第九可控开关的输入端连接所述第十可控开关的输出端，所述第十可控开关的控制端连接所述上级下传信号，所述第十可控开关的输入端连接所述低电位端，所述第四可控开关及所述第九可控开关的输出端相连作为所述输入模块的输出端，所述输入模块的输出端连接每一驱动电路。
  12. 根据权利要求11所述的液晶显示装置，其中，所述每一驱动电路的控制模块包括第十一至第十三可控开关，所述第十一可控开关的控制端连接所述第二时钟信号，所述第十一可控开关的输入端连接所述输入模块的输出端，所述第十一可控开关的输出端连接所述第十二可控开关及所述第十三可控开关的输出端， 所述第十二可控开关及所述第十三可控开关的输入端连接所述高电位端，所述第十二可控开关的控制端连接第三时钟信号，所述第十三可控开关的控制端连接所述复位信号，所述第十二可控开关及所述第十三可控开关的输出端相连作为所述控制模块的输出端，所述控制模块的输出端连接所述输出模块及所述下拉模块。
  13. 根据权利要求12所述的液晶显示装置，其中，所述每一驱动电路的输出模块包括第十四至第十七可控开关，所述第十四可控开关的控制端连接所述第十五可控开关的控制端及所述控制模块的输出端，所述第十四可控开关的输入端连接所述高电位端，所述第十四可控开关的输出端连接所述第十五可控开关的输出端，所述第十五可控开关的输入端连接所述低电位端，所述第十六可控开关的控制端连接所述第十四可控开关的输出端，所述第十六可控开关的输入端连接所述第十七可控开关的输入端及第四时钟信号，所述第十六可控开关的输出端连接所述驱动电路对应驱动的所述扫描线及所述第十七可控开关的输出端，所述第十七可控开关的控制端连接所述控制模块的输出端及所述下拉模块。
  14. 根据权利要求13所述的液晶显示装置，其中，所述每一驱动电路的下拉模块包括第十八可控开关，所述第十八可控开关的控制端连接所述控制模块的输出端，所述第十八可控开关的输入端连接所述低电位端，所述第十八可控开关的输出端连接所述扫描线及所述第十七可控开关的输出端。
  15. 根据权利要求14所述的液晶显示装置，其中，所述第一可控开关、所述第五可控开关、所述第六可控开关、所述第七可控开关、所述第八可控开关、所述第十四可控开关及所述第十七可控开关均为PMOS型薄膜晶体管；所述第二可控开关、所述第三可控开关、所述第四可控开关、所述第九可控开关、所述第十可控开关、所述第十一可控开关、所述第十二可控开关、所述第十三可控开关、所述第十五可控开关、所述第十六可控开关及所述第十八可控开关均为NMOS型薄膜晶体管。
  16. 根据权利要求13所述的液晶显示装置，其中，为保证所述扫描驱动信号开启时间不变，将所述上级下传信号、所述本级下传信号及所述第四时钟信号的高电平的时间增加至3倍，所述第一时钟信号的高电平与低电平切换的频率减少至1/3。
  17. 根据权利要求13所述的液晶显示装置，其中，所述每一驱动电路通过不同的第二时钟信号的控制对所述驱动电路对应驱动的所述扫描线输出不同的扫描驱动信号，所述第一时钟信号及所述上级下传信号均为低电平信号，所述本级下传信号及所述第四时钟信号均为高电平信号。
  18. 根据权利要求10所述的液晶显示装置，其中，所述若干驱动电路包括3个驱动电路。
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