WO2017036293A1 - 三电平单元的动态随机存取存储器及其读取方法 - Google Patents
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- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4099—Dummy cell treatment; Reference voltage generators
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/563—Multilevel memory reading aspects
- G11C2211/5634—Reference cells
Definitions
- This invention relates generally to memory devices, and more particularly to dynamic random access memory devices with multi-level cell storage.
- a multi-level cell dynamic random access memory can store more than two voltages on a memory cell such that each memory cell can store more than one bit.
- DRAM dynamic random access memory
- storing four or more voltages in the memory enables the memory to achieve higher efficiency, in practice, it is practical to set three voltages because if four or more voltages are set, the unit There is a half VDD reference voltage problem in memory and an inherent noise margin problem.
- the SA compares the three sub bit lines with three reference voltages and outputs corresponding 2 bit data. In this way, 2 bits of data can be read out at once.
- this solution has obvious drawbacks, such as the need for three sense amplifiers, the need to configure more switches and control circuits for the sub-bit lines.
- the biggest drawback is that it is sensitive to read errors, and the global reference voltage is unstable and the noise margin is small. More switching and decoding operations are required, which make the DRAM under this scheme slower than most conventional DRAMs.
- No. 5,283,761 to Gillingham discloses a method and circuit for forming two pairs of sub-bit lines, each pair having a sense amplifier, different from the parallel sensing method in the Furuyama scheme.
- the Gillingham program uses sequential sensing. In sequential sensing, the result of the first sense amplifier is used to generate a reference voltage for the second sense operation. An initial sensing operation compares VDD/2 to the multi-level cell voltage. If the cell voltage is above VDD/2, the second sensing operation will reference the 5VDD/6 reference voltage to the cell voltage (in the bit line) After charging sharing) compare. Conversely, if the first operation indicates that the cell voltage is below VDD/2, the second operation will compare the cell voltage with the reference voltage of VDD/6. The result of two sensing operations produces 2 bits of data.
- This scheme uses a locally generated reference voltage, thus reducing some of the noise generated by the global reference voltage used in Furayama.
- the disadvantage of this scheme is that two sense amplifiers are still used, and there are many control and switching circuits for the sub-bit lines. Compared to conventional DRAMs, there is a lower noise margin problem because of the higher reference voltage levels required. In addition, the speed is also slower than the Furuyama solution.
- a three-level (i.e., "three-state") unit of dynamic random access memory is designed for storing three voltage levels in a dynamic memory cell: 0, VDD/2, and VDD.
- the same and different signal voltages and reference voltages are efficiently sensed using an asymmetric sensing method.
- ASA asymmetric sense amplifier
- the ASA has two inputs, BLT and BLR.
- the ASA has an offset voltage deliberately introduced between the BLT and the BLR.
- the polarity of the offset voltage can be changed by switching the two control signals A, B.
- VDD/2 the offset voltage determines the sensed result, and when the offset voltage polarity changes, the opposite result is read.
- the difference between BLT and BLR will determine the sensing result, and when the offset voltage polarity changes, the readout result is the same.
- the write-back circuit controlled by the sensing result is capable of writing "0" and "VDD" voltages back to the memory cell.
- the VDD/2 precharge scheme can also write the "VDD/2" voltage back to the memory cell from the bit line precharge level.
- the connection of the BLT and BLR to the bit line pair can also be switched by selecting a transfer transistor.
- Asymmetric elements can be attached to the pmos side or the nmos side for offset voltage setting and polarity switching.
- the asymmetric components can also be shared by a plurality of conventional sense amplifiers, thus forming a plurality of asymmetric sense amplifiers.
- the sensing operation power consumption of the TLC-DRAM is smaller than that of a conventional DRAM. There are two reasons for this: 1. Two consecutive sensing operations sense the same physical memory location, so the bit line pair is only pre-charged once. 2. If the memory cell stores the voltage of VDD/2, the voltage of the bit line pair does not change. Of course, the bit line does not require much precharge current for the capacitor.
- Figure 1 shows a schematic diagram of an asymmetric sense amplifier (ASA) coupled to bit line pair, data input/output, and control signals A and B that control offset voltage switching.
- ASA asymmetric sense amplifier
- Fig. 2A shows a conventional latch type sense amplifier for a two-level DRAM.
- Fig. 2B shows another conventional differential type sense amplifier.
- Figure 3A shows a schematic diagram of a sense amplifier in combination with control signals A, B and asymmetrical components forming an asymmetric sense amplifier (ASA) with a positive offset voltage and a negative offset voltage.
- ASA asymmetric sense amplifier
- Fig. 3B shows a timing chart of the switching operations of the signals A and B.
- Figure 3C lists 3 different data in 3 storage instances.
- Figure 4A is another example of an ASA that differs from the use of a full logic level in that the ASA of this example directly uses analog voltages for signals A and B.
- Figure 4B is a timing diagram of signals A and B and the selected word line.
- Figure 5 shows a plurality of array structures with a plurality of asymmetric elements.
- 6A, 6B, and 6C are waveform diagrams of control signals and data outputs of a memory cell read operation in three different memory cell voltage examples.
- Figure 7A is a block diagram showing the interconnection of a memory unit to an ASA.
- Fig. 7B is a write back circuit of the example "0".
- Fig. 7C is a write back circuit of the example "1".
- Fig. 7D is a timing chart for charging and discharging a control signal.
- Figure 7E is the sensed data for the three voltage instances.
- Figure 8 is a waveform diagram of bit line voltage read/restore operations for three different voltages in a memory cell.
- 9A is a block diagram of a switchable interconnect between a bit line pair and a BLT/BLR input of the ASA.
- Figure 9B is a VDD/2 precharge circuit connected to the BLT.
- Figure 10 shows a block diagram of sensing a bit line pair using two sense amplifiers.
- Figure 11 shows a block diagram of the use of asymmetric components for supporting multiple bit line pairs for multiple conventional sense amplifiers.
- FIG. 12A is an example of a latch type ASA that switches the offset voltage polarity using a conventional SA and control signals A and B.
- Fig. 12B is a timing chart for switching of A and B signals.
- Figure 13 is a flow chart illustrating two consecutive sensing operations in accordance with one embodiment of the present invention.
- Figure 14 is a flow chart illustrating a single sensing operation and simultaneous reading of multiple data.
- FIG. 1 shows a highly simplified example of a TLC-DRAM in accordance with one embodiment.
- An asymmetric sense amplifier (ASA) is coupled to a signal bit line (BLT) and a reference bit line (BLR). When the word line is disconnected, the BLT is connected to the accessed memory location and the BLR is connected to the reference bit line.
- the ASA has two control signals, A and B, that are used to set the offset voltage and polarity switching of the ASA.
- Local IOs LIO/LIOB are used for data read and write operations.
- VDD/2 is typically used as the reference voltage for conventional sense amplifiers to judge from storage.
- the signal voltage in the cell to ground or "VDD” is higher or lower than the reference voltage.
- the conventional sense amplifier is designed to detect the difference between the two input voltages (BLT and BLR) and output the corresponding data ("1" or "0").
- 2A and 2B illustrate a conventional latch type sense amplifier (prior art). Conventional sense amplifiers are designed to detect the difference between two input voltages, but it does not detect voltage identity.
- a conventional sense amplifier In order to detect three different voltages of the DRAM, a conventional sense amplifier needs to use a reference voltage other than VDD/2 because the sense amplifier can neither detect VDD/2 nor the signal voltage and the reference voltage are at VDD/2. Make the correct judgment at the level.
- the present invention designs an asymmetric sense amplifier that has a positive bias between the two input voltages (BLT and BLR). Shift voltage and negative offset voltage.
- Figure 3A is a schematic diagram of a differential asymmetrical sense amplifier that can detect two input inputs Whether the pressure is the same or different.
- 301 is a conventional sense amplifier.
- the D and DB nodes are precharged to VDD through LIO and LIOB.
- 302 is an example of an asymmetrical element that uses control signals A and B to switch the pull-down strength on the BLT and BLR sides, by applying a voltage to C on the transfer gate.
- 303 is a variation of 302, and C is directly connected to VDD.
- A is turned on and B is grounded, the current of the BLT transistor flows directly to ground through transistor N4.
- the current of the BLR transistor flows to the ground through the transistors N6 and N4.
- the BLT transistor has a stronger pull-down force and the SA has a positive offset voltage.
- the BLR transistor has a stronger pull-down and SA has a negative offset. If the BLT and BLR voltages are the same, the read data for D or LIO will be different during these two consecutive sensitive amplification operations. So the ASA can detect if the voltage levels are the same.
- the corresponding bit line voltage on the BLT is also strong enough to cancel the offset voltage introduced by the asymmetric component, and always outputs "1" at node "D".
- offset voltage values can be adjusted by the control voltage levels on the gates of the asymmetric component transistors (N4, N5, N6), or by adjusting the width and length of these transistors.
- the offset voltage can be set at 50 mv, and the signal voltage difference can reach 100 mv or higher, depending on the ratio of the bit line capacitance to the cell capacitance. If the signal voltage and the reference voltage are the same, the offset voltage will determine the result of the sensing operation, and two opposite data "1” and "0” are read out in two operations as the offset polarity changes. Otherwise, the 100mv voltage difference will override the offset and read the "11" or "00" data if the memory cell stores "VDD" or "0".
- the timing diagram of Figure 3B shows the switching of A and B.
- C can be set to VDD or other voltage level for adjusting the offset voltage.
- Figure 3C lists three different data from a read operation in the case of three storage voltages.
- FIG. 4A is another embodiment of a design ASA that differs from the use of a full logic VDD or zero voltage for signals A and B, which directly uses analog voltages with different drive plating for signals A and B.
- Figure 4B shows a timing diagram of signals A, B and word line WL.
- a and B are that their voltage starts from VDD, so that the BLT and BLR transistors are initially turned off.
- a and B begin to discharge.
- the discharge intensity and speed of A are stronger than B.
- the sensing result is biased toward the BLT side and the output data.
- nodes D and DB of the ASA are reset to the VDD level.
- the word line voltage rises to the VCCP level
- nodes A and B begin to discharge.
- the Node B has a stronger and faster discharge than the Node A.
- the sensing results will facilitate the BLR side and output data.
- each memory array can contain a respective asymmetric component, and the offset voltage of a particular memory array data operation can be adjusted.
- Figure 5 shows a plurality of arrays with a plurality of asymmetric elements.
- component 500 can be set with a dV1 offset voltage and component 501 can be set with a dV2 offset voltage.
- Different offset voltages can be set by using different sized transistors and different metal connections to these asymmetric component transistors.
- 6A, 6B, and 6C are timing diagrams of three different voltage readout examples.
- 6A shows an example in which a memory cell stores a VDD/2 voltage during which time YSELn is activated and LIO/LIOB precharges nodes D and DB to a VDD voltage level.
- the control signal "A" is activated and the pulling force is tilted toward the BLT side. Since the voltages of BLT and BLR are both VDD/2, BLT will have more pulling force, D will remain at "VDD”, and DB will be discharged to "vss”.
- YSELn is turned on to output data from D to LIO.
- D and DB are precharged to the VDD level by LIO and LIOB.
- the control signal B is activated, and the pulling force is tilted to the BLR side. Since the BLT and BLR voltages are the same, when B is turned on, the BLR will have a greater tensile strength, DB will remain at "VDD”, and D will be discharged. To “vss”. At the time At an interval of 8-9, YSELn is turned on to output data from D to LIO. In these two-step sensing operations, the "VDD/2" instances read the "1" and "0" data, respectively.
- Fig. 6B shows an example in which the memory cell stores the VDD voltage
- YSELn is turned on
- LIO/LIOB precharges D and DB to the VDD level.
- the control signal "A" is turned on, and the pulling force is tilted toward the BLT side. Since the voltage of BLT is higher than ( ⁇ 100mv) the reference voltage of BLR at VDD/2, and BLT has a stronger pulling force when signal A is turned on, D will maintain the "VDD" voltage, and DB will be discharged to " VSS”.
- YSELn is turned on to output data from D to LIO.
- D and DB are precharged to the VDD level through LIO and LIOB.
- control signal B is turned on to tilt the pull force toward the BLR side because the voltage of BLT is higher ( ⁇ 100 mv) than the BLR reference voltage.
- B is turned on so that the ASA has a negative offset voltage, the voltage difference of BLT minus BLR can still cancel the offset voltage, and D will remain at "VDD" voltage, and DB will be discharged to "vss”. .
- YSELn is turned on to output data from D to LIO. In these two consecutive sensing operations, the "VDD" instances read data "1" and "1", respectively.
- FIG. 6C is an example of a memory cell storing a "0" voltage.
- the BLT voltage is below ( ⁇ 100mv) the BLR reference voltage at the VDD/2 level.
- the "0" instance reads out the "0" and "0" data, respectively.
- the dynamic memory cell stores an analog voltage on the capacitor, which has a stored charge leakage. Also in the read operation, the charge is also damaged when shared with the bit line capacitor. For DRAM cells, in order to maintain the charge on the cell capacitors, periodic refresh and read recovery circuits are required.
- FIG. 7A shows the interconnection between the memory unit and the ASA. Assuming that the BLT side is used to access the memory cells, the BLR side is used to reference the bit lines.
- the bit line is precharged to VDD/2.
- VDD/2 For cells storing VDD/2, there is no difference between the bit line voltage and the cell voltage, and the cell capacitor will remain at the VDD/2 voltage level. Therefore, it is not necessary to write back the VDD/2 voltage.
- the node DB can be used to discharge the bit line to "0" and write back "0" to the accessed memory location.
- Figure 7B is a write back circuit for a "0" storage instance.
- the DIS signal is turned off after the first sensing, however the bit line has been discharged to ground.
- Figure 7D is a timing diagram of the DIS control signal time with respect to signal "A" in the first sensing operation.
- Figure 7C is a write back circuit for the "VDD" storage instance.
- Figure 7D also has a timing diagram of the CHRn control signal with respect to the time of the B signal in the second sensing operation.
- Figure 7E is a table of three examples of sensing data results, but using only the node DB as an example.
- the analog timing diagram of Figure 8 shows the voltage levels of three bit lines in an example of storing three different voltages.
- the word line voltage timing is also shown in the waveform diagram. All three bit lines start at VDD/2 voltage.
- the bit line voltage for the "0" voltage instance is first generated.
- both the discharge and charge write-back circuits will be turned off and the bit line will remain at the VDD/2 voltage level.
- FIG. 9A shows the use of four transistors to connect the BLT and BLR to the corresponding bit line pair.
- EQ0 When EQ0 is turned on, BL0 is connected to BLT, and BL1 is connected to BLR.
- EQ1 When EQ1 is turned on, BL0 is connected to BLR, and BL1 is connected to BLT.
- Figure 7B shows a VDD/2 precharge circuit that precharges the BLT to a VDD/2 voltage. This VDD/2 level can be shared between bit lines.
- TLC_DRAM it is also possible to use two SAs for a pair of bit line sensing and to read out data in one sensing operation.
- the block diagram of Figure 10 shows the connection between two ASAs and bit line pairs.
- the two SAs have different pulldown connections.
- SA#1 the BLT is connected to the MA side;
- SA#2 the BLR is connected to the MA side.
- the pull-down force on the MA side is stronger than the MB side.
- FIG. 11 shows the use of an asymmetric component to support multiple conventional sense amplifiers such that all sense amplifiers can be considered as asymmetric sense amplifiers (ASA).
- ASA asymmetric sense amplifiers
- FIG. 12A depicts an ASA with a conventional sense amplifier, and the ASA connects the source side to two switchable signals A and B.
- a and B start from the VDD/2 voltage.
- the BLT and BLR are connected to the D and DB nodes through pass transistors.
- VDD/2 voltage
- the sensing operation starts, node A will discharge faster than node B, so node D will determine the sensing result; when the second sensing operation starts, node B will be more than node A. Discharge quickly so that the node DB will determine the sensing result.
- the signal voltage cancels the offset voltage and reads "00" and "11", respectively.
- the asymmetrical component was connected to the source side of the NFETs and the offset voltage of the sense amplifier was changed, it can still be inferred that the PFET side can also be connected to the asymmetrical component and produce a switchable bias to the conventional sense amplifier. Shift voltage.
- Figure 13 is a flow diagram for sensing a bit line pair using an ASA.
- the first sensing data is read out, the offset voltage polarity is switched, and the second sensing data is read out.
- Figure 14 is a flow diagram of directly sensing data from two ASAs in a single sensing operation using two ASAs simultaneously.
- TLC-DRAM of the present invention has been described herein by way of embodiments and various embodiments of interconnecting specific components, possible variations to these embodiments are also contemplated. Circuit variants are common in the field of circuit design. Therefore, the scope of the appended claims should not be limited by the description.
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Claims (11)
- 一种三电平单元的动态随机存取存储器,其特征在于,包括:多个存储单元阵列,其由存储单元构成,所述存储单元用于在单元电容器中储存VDD、VDD/2和对地电压来表示三种状态,或者所述存储单元的每个单元为1.58比特;不对称灵敏放大器,具有可控制并且极性可切换的正偏移电压和负偏移电压,尤其用于三电平单元动态随机存取存储器的感测操作,且偏移极性能够通过在不同的时间点激活的两个不同的控制信号或通过在不同时间点以不同模拟电压电平激活的两个不同的控制信号而进行切换;恢复和回写电路,其用于数据写入和恢复;以及在位线对和不对称灵敏放大器的电压输入之间的多个互连件。
- 如权利要求1所述的存储器,其中所述不对称灵敏放大器为具有可调节的偏移电压和可切换的正负极性的不对称元件的常规灵敏放大器。
- 如权利要求1所述的存储器,其中所述不对称灵敏放大器通过设置不同的不对称驱动强度来调节偏移电压大小。
- 如权利要求2所述的存储器,其中对于多个存储器阵列,多个常规灵敏放大器共享同一个不对称元件以形成多个不对称灵敏放大器。
- 如权利要求4所述的存储器,其中所述不对称灵敏放大器能够对相对应的存储器阵列改变其偏移电压的极性。
- 如权利要求1所述的存储器,其中所述不对称灵敏放大器通过偏移电压极性切换来检测两个输入电压是否不同和检测两个输入电压是否相同。
- 如权利要求1所述的存储器,其中所述回写电路使用不对称灵敏放大器的输出数据将电压电平写回到位线上并且写回到存储单元。
- 如权利要求1所述的存储器,其中所述不对称灵敏放大器通过在任何一个常规灵敏放大器电路上增加不对称元件来实现,且带有极性可切换的 偏移电压的所述不对称元件能够附加到灵敏放大器的P型晶体管一侧或N型晶体管一侧。
- 如权利要求1所述的存储器,其中当控制信号A和B被设置为完全相同的电压或强度时,所述不对称灵敏放大器在对称模式中运行。
- 一种读取三电平单元的动态随机存取存储器的方法,其特征在于,包括:在一个感测操作中,设置一个不对称灵敏放大器的偏移电压极性为正的步骤,以及在连续的下一个感测操作中,设置该不对称灵敏放大器的偏移电压极性为负;其中偏移极性通过在不同的时间点上激活的两个不同的控制信号或通过在不同时间点在不同的模拟电压电平下激活的两个不同的控制信号能够进行切换。
- 一种读取三电平单元的动态随机存取存储器的方法,其特征在于,包括:设置两个不对称灵敏放大器使它们的偏移电压极性相反,当所述两个不对称灵敏放大器的两个输入相同时,它们一起用于读出不同的数据;或当所述两个不对称灵敏放大器的输入不相同时,所述两个不对称灵敏放大器一起用于读出相同的数据;其中偏移极性通过在不同的时间点上激活的两个不同的控制信号或通过在不同时间点在不同的模拟电压电平下激活的两个不同的控制信号能够进行切换。
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DE112016004005.9T DE112016004005B4 (de) | 2015-09-03 | 2016-08-11 | Dynamischer Direktzugriffsspeicher für Dreipegelzelle und Verfahren zum Lesen desselben |
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US14/844,003 US9478277B1 (en) | 2015-09-03 | 2015-09-03 | Tri-level-cell DRAM and sense amplifier with alternating offset voltage |
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DE (1) | DE112016004005B4 (zh) |
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US9911501B2 (en) * | 2016-05-24 | 2018-03-06 | Silicon Storage Technology, Inc. | Sensing amplifier comprising a built-in sensing offset for flash memory devices |
US10622057B2 (en) * | 2017-04-27 | 2020-04-14 | Micron Technology, Inc. | Tri-level DRAM sense amplifer |
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DE102017127115A1 (de) | 2017-07-28 | 2019-01-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Statischer Direkzugriffspeicher mit einer Schreibunterstützungsschaltung |
US10269413B1 (en) | 2017-10-17 | 2019-04-23 | R&D 3 Llc | Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein |
US12014770B2 (en) | 2017-10-17 | 2024-06-18 | R&D3 Llc | Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein |
US11501826B2 (en) | 2017-10-17 | 2022-11-15 | R&D3 Llc | Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein |
KR20190073102A (ko) | 2017-12-18 | 2019-06-26 | 삼성전자주식회사 | 비트 라인 감지 증폭기, 반도체 메모리 장치, 그리고 그것의 멀티 비트 데이터의 센싱 방법 |
CN108133730B (zh) * | 2017-12-22 | 2020-09-11 | 联芸科技(杭州)有限公司 | 快闪存储器的读取控制方法、存储器读取装置和存储器系统 |
KR102424285B1 (ko) | 2018-02-01 | 2022-07-25 | 에스케이하이닉스 주식회사 | 멀티 레벨 센싱 회로 및 이를 포함하는 반도체 장치 |
US10706911B1 (en) | 2018-10-10 | 2020-07-07 | Samsung Electronics Co., Ltd. | Sense amplifier for sensing multi-level cell and memory device including the sense amplifier |
US11024364B2 (en) | 2018-11-07 | 2021-06-01 | Samsung Electronics Co., Ltd. | Sense amplifiers for sensing multilevel cells and memory devices including the same |
CA3030723C (en) * | 2019-01-21 | 2024-06-04 | Mitchell B. Miller | A system and method for bidirectionally based electrical information storage, processing and communication |
US10964357B2 (en) * | 2019-04-24 | 2021-03-30 | Marvell Asia Pte., Ltd. | Skewed sense amplifier for single-ended sensing |
CN112542185B (zh) | 2019-09-20 | 2024-05-14 | 长鑫存储技术有限公司 | 灵敏放大器及其控制方法、存储器读写电路以及存储器 |
CN110827868B (zh) * | 2019-10-31 | 2021-10-22 | 西安紫光国芯半导体有限公司 | 一种改善灵敏放大器读稳定性的回写电路及方法 |
US11024365B1 (en) | 2020-02-05 | 2021-06-01 | Samsung Electronics Co., Ltd. | Time interleaved sampling of sense amplifier circuits, memory devices and methods of operating memory devices |
CN111863053B (zh) * | 2020-07-27 | 2022-11-01 | 安徽大学 | 灵敏放大器、存储器和灵敏放大器的控制方法 |
CN112687311A (zh) * | 2020-12-30 | 2021-04-20 | 南京低功耗芯片技术研究院有限公司 | 一种高性能sram数据读出电路 |
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- 2016-08-11 WO PCT/CN2016/094693 patent/WO2017036293A1/zh active Application Filing
- 2016-08-12 CN CN201610665877.1A patent/CN106409328B/zh active Active
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US9478277B1 (en) | 2016-10-25 |
DE112016004005T5 (de) | 2018-07-12 |
DE112016004005B4 (de) | 2020-06-04 |
TW201711031A (zh) | 2017-03-16 |
KR101698155B1 (ko) | 2017-01-19 |
JP2018525765A (ja) | 2018-09-06 |
JP6374136B1 (ja) | 2018-08-15 |
TWI576840B (zh) | 2017-04-01 |
CN106409328B (zh) | 2018-05-18 |
CN106409328A (zh) | 2017-02-15 |
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