Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
  • H01L21/68778—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by supporting substrates others than wafers, e.g. chips
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
  • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67011—Apparatus for manufacture or treatment
  • H01L21/67098—Apparatus for thermal treatment
  • H01L21/67103—Apparatus for thermal treatment mainly by conduction
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67011—Apparatus for manufacture or treatment
  • H01L21/67098—Apparatus for thermal treatment
  • H01L21/67109—Apparatus for thermal treatment mainly by convection
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67242—Apparatus for monitoring, sorting or marking
  • H01L21/67248—Temperature monitoring
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
  • H01L21/68742—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a lifting arrangement, e.g. lift pins
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
  • H01L21/68785—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/10—Measuring as part of the manufacturing process
  • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Definitions

• the present disclosure applies broadly to the field of processing equipment. More specifically, systems and methods for providing spatially tailored processing of a workpiece are disclosed.
• Integrated circuits and other semiconductor products are often fabricated on surfaces of substrates called "wafers.” Sometimes processing is performed on groups of wafers held in a carrier, while other times processing and testing are performed on one wafer at a time. When single wafer processing or testing is performed, the wafer may be positioned on a wafer chuck. Other workpieces may also be processed on similar chucks. Chucks can be temperature controlled in order to control temperature of a workpiece for processing.
• a workpiece holder positions a workpiece for processing.
• the workpiece holder includes a substantially cylindrical puck that is characterized by a cylindrical axis, a puck radius about the cylindrical axis, and a puck thickness.
• the puck radius is at least four times the puck thickness, at least a top surface of the cylindrical puck is substantially planar, and the cylindrical puck defines one or more radial thermal breaks.
• Each thermal break is characterized as a radial recess that intersects at least one of the top surface and a bottom surface of the cylindrical puck.
• the radial recess is characterized by a thermal break depth that extends from the top surface or the bottom surface of the puck through at least half of the puck thickness, and a thermal break radius that is disposed symmetrically about the cylindrical axis, and is at least one-half of the puck radius.
• a method of processing a wafer includes processing the wafer with a first process that provides a first center-to-edge process variation; and subsequently, processing the wafer with a second process that provides a second center-to-edge process variation.
• the second center-to-edge process variation substantially compensates for the first center-to-edge process variation.
• a workpiece holder that positions a workpiece for processing.
• the workpiece holder includes a substantially cylindrical puck that is characterized by a cylindrical axis and a substantially planar top surface. The cylindrical puck defines two radial thermal breaks.
• a first one of the thermal breaks is characterized as a radial recess that intersects a bottom surface of the cylindrical puck at a first radius, and extends from the bottom surface through at least one-half of a thickness of the puck.
• a second one of the thermal breaks is characterized as a radial recess that intersects the top surface at a second radius that is greater than the first radius, and extends from the top surface through at least one-half of the thickness of the puck.
• a thermal sink extends substantially beneath the bottom surface of the puck, and includes a metal plate that flows a heat exchange fluid through channels defined therein, to maintain a reference temperature for the puck.
• a first heating device is disposed between the thermal sink and the puck.
• the first heating device is in thermal communication with the bottom surface of the puck and with the thermal sink, within the first radius.
• a second heating device is disposed between the thermal sink and the puck. The second heating device is in thermal communication with the bottom surface of the puck and with the thermal sink, outside the second radius.
• FIG. 1 schematically illustrates major elements of a processing system having a workpiece holder, according to an embodiment.
• FIG. 2 is a schematic cross sectional diagram illustrating exemplary construction details of the workpiece holder of FIG. 1.
• FIG. 3 is a schematic cross sectional diagram illustrating application of heaters and a thermal sink to inner and outer portions of a puck that forms part of the workpiece holder of FIG. 1, in accord with an embodiment.
• FIG. 4 is a schematic cross-sectional view that illustrates features of a puck, a resistive heater, and a thermal sink, in accord with an embodiment.
• FIG. 5 schematically illustrates a layout of heater trace within the inner resistive heater of FIG. 4, in accord with an embodiment.
• FIG. 6 schematically illustrates a lift pin mechanism disposed within a thermal break, in accord with an embodiment.
• FIG. 7 schematically illustrates, in a plan view, a three lift pin arrangement where lift pins are disposed within a thermal break, in accord with an embodiment.
• FIG. 8 is a flowchart of a method for processing a wafer or other workpiece, in accord with an embodiment.
• FIG. 9 is a flowchart of a method that includes, but is not limited to, one step of the method of FIG. 8.
• FIG. 10 is a flowchart of a method that includes, but is not limited to, another step of the method of FIG. 8.
• FIG. 1 schematically illustrates major elements of a wafer processing system 100.
• System 100 is depicted as a single wafer, semiconductor wafer plasma processing system, but it will be apparent to one skilled in the art that the techniques and principles herein are applicable to wafer processing systems of any type (e.g., systems that do not necessarily process wafers or semiconductors, and do not necessarily utilize plasmas for the processing).
• Processing system 100 includes a housing 110 for a wafer interface 115, a user interface 120, a plasma processing unit 130, a controller 140 and one or more power supplies 150.
• Processing system 100 is supported by various utilities that may include gas(es) 155, external power 170, vacuum 160 and optionally others. Internal plumbing and electrical connections within processing system 100 are not shown, for clarity of illustration.
• Processing system 100 is shown as a so-called indirect plasma processing system that generates a plasma in a first location and directs the plasma and/or plasma products (e.g., ions, molecular fragments, energized species and the like) to a second location where processing occurs.
• plasma processing unit 130 includes a plasma source 132 that supplies plasma and/or plasma products for a process chamber 134.
• Process chamber 134 includes one or more workpiece holders 135, upon which wafer interface 115 places a workpiece 50 (e.g., a semiconductor wafer, but could be a different type of workpiece) to be held for processing.
• workpiece holder 135 is often referred to as a wafer chuck.
• gas(es) 155 are introduced into plasma source 132 and a radio frequency generator (RF Gen) 165 supplies power to ignite a plasma within plasma source 132.
• Plasma and/or plasma products pass from plasma source 132 through a diffuser plate 137 to process chamber 134, where workpiece 50 is processed.
• a plasma may also be ignited within process chamber 134 for direct plasma processing of workpiece 50.
• Embodiments herein provide new and useful functionality for wafer processing systems. Semiconductor wafer sizes have increased while feature sizes have decreased significantly over the years, so that more integrated circuits with greater functionality can be harvested per wafer processed. Processing smaller features while wafers grow larger requires significant improvements in processing uniformity. Because chemical reaction rates are often temperature sensitive, temperature control across wafers during processing is often key to uniform processing.
• some types of processing can have radial effects (e.g., processing that varies from center to edge of a wafer). Some types of process equipment control these effects better than others, that is, some achieve high radial process uniformity while others do not.
• Embodiments herein recognize that not only are radial effects important to control, but it would be further advantageous to be able to provide radial processing control that can be tailored to compensate for processing that cannot achieve such control. For example, consider a case in which a layer is deposited on a wafer and then selectively etched off, as is common in semiconductor processing. If the deposition step is known to deposit a thicker layer at the wafer's edge than at its center, a compensating etch step would advantageously provide a higher etch rate at the wafer's edge than at its center, so that the deposited layer would be etched to completion at all parts of the wafer at the same time. Similarly, if an etch process were known to have a center-to-edge variation, a compensating deposition preceding the etch process could be adjusted to provide a corresponding variation.
• a compensating process can be provided by providing explicit center-to-edge temperature variation, because temperature often substantially influences reaction rates of processes.
• FIG. 2 is a schematic cross section that illustrates exemplary construction details of workpiece holder 135, FIG. 1.
• workpiece holder 135 includes a puck 200 that is substantially cylindrical, and is characterized in terms of having a puck radius rl in a radial direction R from a cylindrical axis Z.
• a workpiece 50 e.g., a wafer
• a bottom surface 204 of puck 200 is taken to be a median bottom surface height of puck 200; that is, a plane that defines the typical bottom surface height of puck 200 in the direction of axis Z exclusive of features such as edge rings or other protrusions 206, or indentations 208, that puck 200 may form as attachment points for other hardware.
• a top surface 202 is taken to be a planar surface configured to accommodate workpiece 50, irrespective of grooves that may be formed therein (e.g., as vacuum channels, see FIG. 4) and/or other features that retain workpiece 50.
• Puck 200 may also be characterized in terms of having a thickness t between bottom surface 204 and top surface 202, as shown.
• puck radius rl is at least four times puck thickness t, but this is not a requirement.
• Puck 200 defines one or more radial thermal breaks 210, as shown.
• Thermal breaks 210 are radial recesses defined in puck 200, that intersect at least one of top surface 202 or bottom surface 204 of puck 200.
• Thermal breaks 210 act as the term implies, that is, they provide thermal resistance, between a radially inner portion 212, and a radially outer portion 214, of puck 200. This facilitates explicit radial (e.g., center-to-edge) thermal control of the radially inner and outer portions of puck 200, which is advantageous in terms of either providing precise thermal matching of the inner and outer portions, or of providing deliberate temperature variation across the inner and outer portions.
• Thermal breaks 210 can be characterized in terms of having a thermal break depth and a thermal break radius.
• Depth of thermal breaks 210 can vary among embodiments, but the thermal break depth usually exceeds one-half of thickness t. Radial positioning of thermal breaks 210 can also vary among embodiments, but the thermal break radius r2 is usually at least one-half of puck radius rl, and in other embodiments r2 may be three-fourths, four-fifths, five sixths or more of puck radius rl . Certain embodiments may use a single thermal break 210, while other embodiments may use two thermal breaks 210 (as shown in FIG. 2) or more.
• a demarcation point between radially inner portion 212 and radially outer portion 214 is illustrated as a radially average position between two thermal breaks 210, but in embodiments having a single thermal break 210, such demarcation point can be considered to be the radial midpoint of the single thermal break 210.
• FIG. 3 is a schematic cross sectional diagram illustrating application of heaters and a thermal sink to inner and outer portions of puck 200. Some mechanical details of puck 200 are not shown in FIG. 3, for clarity of illustration.
• FIG. 3 illustrates a central channel 201 defined by puck 200 and an optional thermal sink 230. Central channel 201 is described in connection with FIG. 4.
• Inner heaters 220-1 and outer heaters 220-2 are disposed against, and are in thermal communication with, puck 200. It may be advantageous for heaters 220 to be spread across large portions of lower surface 204, but the distribution of heaters 220 across surface 204 can vary in embodiments.
• Heat provided by heaters 220 will substantially control the temperatures of inner portion 212 and outer portion 214 of puck 200; thermal breaks 210 assist in thermally isolating portions 212 and 214 from one another, to improve the precision of thermal control.
• Heaters 220 are typically resistive heaters, but other types of heaters (e.g., utilizing forced gas or liquid) may be implemented.
• Optional thermal sink 230 may also be provided.
• Thermal sink 230 may be controlled to present a lower temperature than typical operating temperatures, for example by flowing a heat exchange fluid therethrough, or by using a cooling device such as a Peltier cooler.
• thermal sink 230 provides several advantages.
• One such advantage is to provide a reference temperature to which all portions of puck 200 will have, in the absence of heat provided by heaters 220. That is, although heaters 220 can provide heat, such heat would ordinarily propagate, in all directions, throughout puck 200.
• Thermal sink 230 provides the ability to drive puck 200 to lower temperatures, such that if a heater 220 is located at a specific portion of puck 200, the heat generated by the heater does not simply diffuse throughout puck 200 in every direction, but heats a portion of puck 200 where the heat from the heater 220 locally exceeds the tendency of thermal sink 230 to remove the heat.
• thermal sink 230 can provide rapid thermal sinking capability such that when temperature settings of heaters 220 (e.g., current passing through resistive wires) decrease, adjacent portions of puck 200 respond with a relatively rapid temperature decrease.
• This provides the benefit of being able, for example, to load workpiece 50 onto puck 200, provide heat through heaters 220, and achieve rapid stabilization of temperatures on workpiece 50 so that processing can begin quickly, to maximize system throughput. Without thermal communication allowing some heat to dissipate to thermal sink 230, temperatures reached by portions of puck 200 would decrease only as fast as other heat dissipation paths would allow.
• heaters 220 are typically disposed in direct thermal
• thermal sink 230 is in indirect thermal communication with puck 200, through heaters 220.
• thermal sink 230 not be in direct thermal communication with puck 200, because such direct thermal communication can lead to thermal anomalies on the surface of puck 200 (e.g., puck 200 would have regions where temperature becomes close to the temperature of thermal sink 230, instead of being dominated by extra heat generated by heaters 220).
• heaters 220 have sufficient heat generation capability that heat applied by heaters 220 can overwhelm the indirect thermal coupling of puck 200 with thermal sink 230, so that heaters 220 can raise the temperature of inner portion 212 and outer portion 214 of puck 200, even while some of the heat generated by heaters 200 dissipates into thermal sink 230.
• heat provided by heaters 220 can, but does not immediately, dissipate through thermal sink 230.
• degrees of thermal coupling among puck 200, heaters 220 and thermal sink 230 may be adjusted according to principles herein, in order to balance
• thermal sink 230 is to confine heat generated by heaters 220 to the vicinity of puck 200. That is, thermal sink 230 can provide a thermal upper limit for adjacent system components to protect such components from high temperatures generated at puck 200. This may improve mechanical stability of the system and/or prevent damage to temperature sensitive components.
• Heaters 220 and thermal sink 230 may be implemented in various ways.
• heaters 220 include several layers coupled together as subassemblies, which can then be further coupled with a 200 and (optionally) thermal sink 230 to form a wafer chuck assembly.
• Embodiments designed, assembled and operated as disclosed herein allow explicit temperature control of workpiece (e.g., wafer) edge regions relative to center regions, and facilitate processing with explicit center to edge temperature control that is typically not achievable with prior art systems.
• FIG. 4 is a schematic cross-sectional view of a portion of a wafer chuck, that illustrates features of puck 200, a resistive heater acting as heater 220-1, and thermal sink 230.
• FIG. 4 represents a portion of a wafer chuck that is near a cylindrical axis Z thereof, and is not drawn to scale, for illustrative clarity of smaller features.
• Puck 200 is typically formed of an aluminum alloy, for example of the well-known "6061" alloy type.
• Puck 200 is shown as defining surface grooves or channels 205 that connect on upper surface 202 of puck 200, and with central channel 201 that is centered about axis Z.
• Vacuum may be supplied to central channel 201, reducing pressure within channels 205 so that atmospheric pressure (or gas pressure of relatively high pressure plasmas, or low pressure deposition systems, such as around 10-20 Torr) will urge workpiece 50 (see FIGS. 1, 2) against puck 200, providing good thermal communication between puck 200 and workpiece 50.
• atmospheric pressure or gas pressure of relatively high pressure plasmas, or low pressure deposition systems, such as around 10-20 Torr
• Inner resistive heater 220-1 is illustrated in FIG. 4, but it should be understood that the illustration and following description of inner resistive heater 220-1 apply equally to outer resistive heater 220-2.
• Resistive heater 220-1 includes a heater trace 264 and a buffer layer 266.
• Heater trace 264 is shown as a continuous layer in FIG. 4, but is understood to exist as a layer that forms a serpentine pattern, to distribute heat evenly along its length (that is, heater trace 264 falls along the cross-sectional plane shown in FIG. 4, but in other cross-sectional views, would appear intermittently cross the cross-sectional plane - see FIG. 5).
• Heater trace 264 may be formed, for example of Inconel of about 0.0005" to 0.005" thickness, although layers of about 0.0002" to 0.02" are also useful, as are other material choices.
• Buffer layer 266 is typically a polymer layer of about 0.025" to 0.10" thickness, although layers of about 0.01" to 0.15" are also useful.
• Buffer layer 266 may be formed of polyimide, but other polymers and other material choices may be useful.
• Buffer layer 266 is advantageously an electrical insulator (to avoid shorting heater trace 264) that is thermally stable. Buffer layer 266 is also
• buffer layer 266 increases thermal resistance between heater trace layer 264 and thermal sink 230, so that when heater trace layer 264 supplies heat, more of the heat transfers to puck 200 than to thermal sink 230.
• heater trace layer 264 and buffer layer 266 are coupled within thin metal layers 260, 268 that help spread heat from heater trace layer 264 evenly across surfaces of heater 220-1.
• a thin, electrically insulating layer 262 is included to keep metal layer 260 from shorting heater trace layer 264; insulating layer 262 or insulating layer 266 may also act as a substrate for fabrication of heater trace layer 264 (see FIG. 5).
• Insulating layer 262 is advantageously a thermally stable material, may be formed of ceramic or a polymer such as polyimide, and in embodiments has a thickness of about 0.001" to 0.040".
• Metal layers 260, 268 may be, for example, layers of Al 6061 of about 0.005" to 0.050".
• Metal layers 260, 268 also provide moderate protection for layers 262, 264 and 266, so that heater 220-1 can be fabricated and shipped as a subassembly for later integration with puck 200 and thermal sink 230.
• layers 260, 262, 264, 266, 268 and 270 that are shaped to the desired dimensions may be aligned into a stack in registration with one another, and bonded by compressing and/or heating the stack, to form heater 220-1 as a subassembly.
• heater subassemblies as disclosed herein will be roughly planar, and for wafer chuck applications will be roughly circular, but similarly fabricated subassemblies need not be circular, and could be fabricated to fit differently shaped surfaces (e.g., squares, rectangles, etc.) than the circular bottom surfaces of cylindrical pucks described herein.
• heater traces for cylindrical pucks may be arranged for azimuthal uniformity and uniform heating density, heater traces within such subassemblies could be arranged to form locally intense and less intense heating patterns.
• Heater 220-1 couples with puck 200 via an optional layer 250, and with thermal sink 230 via further optional layer 270, as shown.
• Layers 250 and 270 promote thermal transfer between heater 220-1 and both puck 200 and thermal sink 230; material choices of layers 250 and 270 include thermally stable polymers.
• optional layers 250, 270 are formed of layer of polymer having a bulk thermal conductivity of about 0.22 W/(m-K).
• Layers 250 and/or 270 may also be bondable to puck 200 and layer 260, and thermal sink 230 and layer 268 respectively, such that puck 200, thermal sink 230 may be bonded together with heaters 220- 1 and 220-1.
• puck 200, layer 250, heaters 220-1 and 220-2, layer 270 and thermal sink 230 may all be aligned in registration with one another, and bonded by compressing and/or heating.
• thermal sink 230 provides a reference temperature for puck 200, while still allowing inner and outer resistive heaters 220-1 and 220-2 to provide center-to-edge temperature control for puck 200. Temperature of optional thermal sink 230 may be actively controlled. For example, FIG. 4 shows thermal sink 230 defining fluid channels 280 through which a heat exchange fluid may be forced. Thermal sink 230 may also form thermal fins 290 to increase contact area and thus heat exchange efficiency of fluids within channels 280.
• heat exchange fluid does not require that the mixture always cool thermal sink 230; the heat exchange fluid could either add or take away heat. The heat exchange fluid may be provided at a controlled temperature.
• thermal sink 230 is formed of an aluminum alloy, such as the "6061" type, and the heat exchange fluid is a mix of 50% ethylene glycol and 50% water, although other materials may be used for thermal sink 230 and/or a heat exchange fluid.
• optional thermal sink 230 may be a passive thermal sink, e.g., thermal sink 230 may be a passive radiator, and may have heat fins and the like, to dissipate heat to a surrounding environment.
• FIG. 5 schematically illustrates a layout of heater trace 264 on insulating layer 262.
• the exact layout of heater trace 264 is not critical, but it is desirable that the layout be dense and azimuthally uniform.
• Heater trace 264 may terminate in a pair of bonding pads 274, as shown, for later connection with wires that deliver electrical power.
• heater trace 264 need not extend into a central region 269 of inner resistive heater 220-1.
• One reason for this is that the temperature reached within puck 200 in the area surrounding region 269 will rapidly spread across a corresponding region of puck 200.
• Another reason is that it may be desirable to leave region 269 open for other uses, such as to provide vacuum channel 201 (see FIGS. 3, 4), fluid connections for a heat exchange fluid, electrical contacts for heater trace 264, and/or other features.
• a further advantage of providing at least one thermal break 210 that intersects a top surface of puck 200 is that mechanical features may be disposed at least partially within the thermal break such that the features do not generate a thermal anomaly.
• a wafer chuck commonly provides lift pins that can be used to raise a wafer to a small distance off of the chuck to facilitate access by wafer handling tools (typically using a paddle or other device that, after the wafer is raised, is inserted between the wafer and the chuck).
• the lift pins typically retract into holes in the chuck, and such holes can locally affect wafer temperature during processing.
• FIG. 6 schematically illustrates a portion of a wafer chuck that has a lift pin mechanism 300 that controls a lift pin 310, disposed within a thermal break 210. Portions of heaters 220 and optional thermal sink 230 are also shown.
• the cross-sectional plane illustrated in FIG. 6 passes through a center of mechanism 300 such that the components thereof are within a lower portion of one thermal break 210.
• puck 200, thermal break 210 and thermal sink 230 may have profiles like those shown in FIGS. 3 and 4, so that the thermal break 210 in which mechanism 300 is disposed will continue along its arc through puck 200 (see FIG. 7).
• lift pin mechanism 300 is limited to a fairly small azimuthal angle relative to the central axis of puck 200 (again, see FIG. 7). That is, if a cross sectional plane were taken at a distance into or out of the plane shown in FIG. 6, the bottom surface of puck 200 would be continuous along the same plane where bottom surface 204 is indicated in FIG. 6, and thermal sink 230 would be continuous under puck 200.
• the small size of lift pin mechanism 300 limits thermal deviation of puck 200 in the area of lift pin mechanism 300.
• FIG. 6 shows lift pin 310 in a retracted position, wherein it will not create a thermal anomaly on the surface of puck 200.
• FIG. 7 schematically illustrates, in a plan view, a three lift pin arrangement where lift pins 310 are disposed within a thermal break 210.
• FIG. 7 is not drawn to scale, in particular, thermal break 210 is exaggerated so as to show lift pin mechanisms 300 and lift pins 310 clearly. Because lift pins 310 retract well below the average surface of puck 200 into thermal break 210, lift pins 310 do not generate a spatial thermal anomaly during processing, such that portions of a workpiece being processed at the locations of lift pins 310 (e.g., specific integrated circuits located at the corresponding locations of a semiconductor wafer) experience processing that is consistent with processing elsewhere on the workpiece.
• FIG. 8 is a flowchart of a method 400 for processing a wafer or other workpiece
• Method 400 may be uniquely enabled by the thermal management apparatus described in connection with FIGS. 2-8 that can be used to provide explicit center-to-edge thermal control, which in turn enables explicit center-to-edge process control.
• a first step 420 of method 400 processes the product wafer with a first center- to-edge process variation.
• a second step 440 of method 400 processes the product wafer with a second center-to-edge process variation that compensates for the first center-to-edge variation.
• one or the other of 420 or 440 will be carried out in equipment or in a process environment that unintentionally or uncontrollably generates the associated center-to-edge process variation (the "uncontrolled variation” hereinafter) but this is not required.
• the other is carried out in equipment such as that described herein, such that another center-to-edge process variation (the "controlled variation” hereinafter) is introduced through thermal management techniques that allow the center and edge portions of the product wafer to be explicitly controlled to provide a corresponding, inverse process variation.
• the uncontrolled variation and the controlled variation can occur in either order. That is, 420 may introduce either the uncontrolled or the controlled variation, and 440 may introduce the other of the uncontrolled and the controlled variation.
• FIGS. 9 and 10 provide additional guidance to those skilled in the art to enable useful exercise of method 400.
• FIG. 9 is a flowchart of a method 401 that includes, but is not limited to, step 420 of method 400. All of 410-418 and 422 shown in FIG. 9 are considered optional, but in embodiments may be helpful, in execution of method 400 to achieve useful wafer processing results.
• Step 410 sets up equipment characteristics that are related to the first center-to- edge process variation, which will be produced at 420.
• 410 may involve providing equipment parameters such as heater settings that will provide a controlled center-to-edge temperature variation.
• Equipment such as described in FIGS. 2-7 herein is useful in providing a controlled center-to-edge temperature variation.
• Step 412 measures equipment characteristics that are related to the first center-to-edge process variation. Process knowledge may be acquired over time about what equipment settings, or measured equipment characteristics, are successful in generating a known center-to-edge process variation (or at least providing a process variation that is stable, albeit unintentional).
• method 401 may optionally return from 412 to 410 to adjust equipment characteristics, if the equipment characteristics measured in 412 can likely be improved.
• Step 414 processes one or more test wafers that receive the first center-to-edge process variation.
• Step 416 measures one or more characteristics of the first center-to-edge process variation on the test wafer(s) processed in step 414.
• Method 401 may optionally return from 416 to 410 to adjust equipment characteristics in light of the center-to- edge process characteristics measured in 416.
• Any test wafers processed in 414 may optionally be saved in 418, for testing in the second process (e.g., the process to be executed later, in 440). Also, 414 may be performed in parallel with 420.
• test wafers may be processed at the same time as product wafers (for example, if the first process is a so-called "batch” process like dipping a cassette of wafers into a liquid bath, processing a set of wafers together in an ampoule, diffusion furnace or deposition chamber, or the like).
• Step 420 processes a product wafer with the first center-to-edge process variation.
• Step 422 measures one or more first center-to-edge characteristics on the product wafer, to generate data for equipment process control purposes, for correlation to yield or performance of the product wafer, and/or for use in correlating to information surrounding step 440, as described further below.
• FIG. 10 is a flowchart of a method 402 that includes, but is not limited to, step
• Step 430 sets up equipment characteristics that are related to the second center-to- edge process variation, which will be produced at step 440.
• 430 may involve providing equipment parameters such as heater settings that will provide a controlled center-to-edge temperature variation.
• Equipment such as described in FIGS. 2-7 herein is useful in providing a controlled center-to-edge temperature variation.
• Step 432 measures equipment characteristics that are related to the second center-to-edge process variation. In consideration of process knowledge, as discussed above, method 402 may optionally return from 432 to 430 to adjust equipment characteristics in light of the equipment characteristics measured in 432.
• Step 434 processes one or more test wafers that receive the second center-to-edge process variation; the test wafer(s) processed in 434 may include one or more test wafers saved from the first process step in 418, above.
• Step 436 measures one or more characteristics of the second center-to-edge process variation on the test wafer(s) processed in 434. In consideration of previously acquired process knowledge, method 402 may optionally return from 436 to 430 to adjust equipment characteristics in light of the center-to-edge process characteristics measured in 436.
• Step 440 processes a product wafer with the second center-to-edge process variation. Also, although not shown in method 402, additional test wafers could certainly be processed in parallel with the product wafer.
• Step 442 measures one or more first center-to-edge characteristics on the product wafer, to generate data for equipment process control purposes, for correlation to yield or performance of the product wafer, and/or for use in correlating to information surrounding 420, as described above. Such measurements could also be performed on any test wafer that was processed in parallel with the product wafer, but in any case 442 will generally not further alter any condition present on the product wafer. That is, the results of 420 and 440 will be fixed in the product wafer at the conclusion of 440 irrespective of any further testing done.

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