WO2017008368A1 - Tft基板的制作方法及制得的tft基板 - Google Patents

Tft基板的制作方法及制得的tft基板 Download PDF

Info

Publication number
WO2017008368A1
WO2017008368A1 PCT/CN2015/087720 CN2015087720W WO2017008368A1 WO 2017008368 A1 WO2017008368 A1 WO 2017008368A1 CN 2015087720 W CN2015087720 W CN 2015087720W WO 2017008368 A1 WO2017008368 A1 WO 2017008368A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
temperature polysilicon
low temperature
type doped
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/087720
Other languages
English (en)
French (fr)
Inventor
周星宇
吴元均
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/781,308 priority Critical patent/US9761447B2/en
Publication of WO2017008368A1 publication Critical patent/WO2017008368A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0229—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials characterised by control of the annealing or irradiation parameters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3454—Amorphous
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate and a TFT substrate produced.
  • LTPS Low Temperature Poly-Silicon
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • Emphasis is considered as an important material for achieving low-cost full-color flat panel display.
  • low temperature polysilicon material has the advantages of high resolution, fast reaction speed, high brightness, high aperture ratio, low energy consumption, etc.
  • low temperature polysilicon can be fabricated at low temperature and can be used to fabricate C-MOS (Complementary Metal Oxide).
  • C-MOS Complementary Metal Oxide
  • HTPS high temperature poly-Silicon
  • laser annealing High Temperature Oxidation Process
  • the temperature of the glass substrate will exceed 1000 degrees Celsius.
  • low-temperature polysilicon requires laser irradiation, but it generally uses an excimer laser as a heat source. After passing through the transmission system, the laser beam will be uniformly distributed and projected onto the amorphous silicon structure.
  • the glass substrate of the amorphous silicon structure absorbs the energy of the excimer laser, it is converted into a polysilicon structure. Since the entire process is basically completed below 600 degrees Celsius, generally ordinary glass substrates can withstand, which greatly reduces the manufacturing cost.
  • the advantages of low-temperature polysilicon are also reflected in: faster electron migration rate and higher stability.
  • the methods for producing low-temperature polycrystalline silicon include solid phase crystallization (SPC), metal-induced crystallography (MIC), and excimer laser annealing (ELA).
  • SPC solid phase crystallization
  • MIC metal-induced crystallography
  • ELA excimer laser annealing
  • the main process of this method is to first form a buffer layer on a glass substrate, then form an amorphous silicon layer on the buffer layer, and dehydrogenate at a high temperature.
  • the ELA laser beam is used to scan amorphous silicon for excimer laser annealing.
  • the amorphous silicon absorbs the energy of the laser and reaches a high temperature in a very short time and becomes molten.
  • the polycrystalline silicon is formed by cooling and recrystallization.
  • the current situation is that the low-temperature polysilicon thin film transistor fabricated by the ELA method has poor uniformity and high cost, and the SPC method can reduce the cost and improve the uniformity, but the on-current and subthreshold slopes are not as good as the ELA method.
  • the obtained low-temperature polysilicon thin film transistor has a large off current and thus has a poor driving ability.
  • An object of the present invention is to provide a method for fabricating a TFT substrate, which can increase the on-current of the thin film transistor, reduce the off current, suppress the warpage effect, lower the threshold voltage and the subthreshold slope, and reduce the groove while saving production cost. The occurrence of leakage caused by light.
  • the present invention provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step 1 Providing a substrate, after cleaning and pre-baking the substrate, depositing a buffer layer on the substrate;
  • Step 2 depositing a first metal layer on the buffer layer, and patterning the first metal layer to obtain a bottom gate;
  • Step 3 depositing a gate insulating layer on the bottom gate and the buffer layer, and depositing an amorphous silicon layer on the gate insulating layer;
  • Step 4 performing P-type doping on the amorphous silicon layer to obtain a P-type doped amorphous silicon layer located above and an undoped amorphous silicon layer under the P-type doped amorphous silicon layer ;
  • Step 5 converting the undoped amorphous silicon layer and the P-type doped amorphous silicon layer into an undoped low-temperature polysilicon layer and a P-type doped low-temperature polysilicon layer by a solid phase crystallization method, using a photolithography The process performs patterning treatment on the undoped low temperature polysilicon layer and the P type doped low temperature polysilicon layer to form a low temperature polysilicon island;
  • Step 6 Depositing a second metal layer over the low temperature polysilicon island and the gate insulating layer, and defining a channel region corresponding to the bottom gate on the undoped low temperature polysilicon layer of the low temperature polysilicon island And patterning the second metal layer and the low temperature polysilicon island by a lithography process to remove the P-type doped low temperature polysilicon layer and the second metal layer above the channel region, thereby forming corresponding a source and a drain on both sides of the channel region, and a first P-type doped low temperature polysilicon layer and a second P-type doped low temperature polysilicon layer;
  • the source and the drain are respectively in contact with the first and second P-type doped low-temperature polysilicon layers;
  • Step 7 depositing a passivation layer on the source, the drain, the channel region, and the gate insulating layer;
  • Step 8 Deposit a third metal layer on the passivation layer, and pattern the third metal layer to obtain a top gate corresponding to the bottom gate.
  • the amorphous silicon layer is doped with boron ions using diborane gas.
  • the undoped amorphous silicon layer and the P-type doped amorphous silicon layer are heated by a rapid thermal annealing method, and the heating temperature is 670-730 ° C.
  • the time is 10 to 30 minutes.
  • the bottom gate is a single-layer aluminum structure, a single-layer molybdenum structure, or a three-layer structure in which two layers of molybdenum are laminated with aluminum; the thickness of the bottom gate is 1500-2000A;
  • the top gate is a single-layer aluminum structure, a single-layer molybdenum structure, or a three-layer structure in which aluminum is sandwiched by two layers of molybdenum; the top gate has a thickness of 1500-2000A.
  • the top gate and the bottom gate are identical in size, thickness, and material.
  • the present invention also provides a TFT substrate, comprising: a substrate, a buffer layer disposed on the substrate, a bottom gate disposed on the buffer layer, and a gate insulating layer disposed on the buffer layer and the bottom gate a low-temperature polysilicon island disposed on the gate insulating layer, a source and a drain disposed on the low-temperature polysilicon island and the gate insulating layer, and disposed on the source, the drain, the low-temperature polysilicon island and the gate a passivation layer on the pole insulating layer, and a top gate disposed on the passivation layer and corresponding to the bottom gate;
  • the low temperature polysilicon island includes an undoped low temperature polysilicon layer and a P-type doped low temperature polysilicon layer disposed on the undoped low temperature polysilicon layer, and the undoped low temperature polysilicon layer is provided on the undoped low temperature polysilicon layer.
  • a channel region of the bottom gate and the top gate, the P-type doped low temperature polysilicon layer comprising a first P-type doped low temperature polysilicon layer corresponding to both sides of the channel region, and a second P-type doped low temperature polysilicon a layer; the source and the drain are respectively in contact with the first and second P-type doped low-temperature polysilicon layers.
  • the impurity doped in the first P-type doped low temperature polysilicon layer and the second P-type doped low temperature polysilicon layer is boron ion.
  • the substrate is a glass substrate;
  • the buffer layer is a single layer structure composed of silicon nitride, a single layer structure composed of silicon oxide, or a two-layer structure composed of a silicon nitride layer and a silicon oxide layer.
  • the bottom gate is a single-layer aluminum structure, a single-layer molybdenum structure, or a three-layer structure in which a layer of molybdenum is sandwiched by two layers of molybdenum; the thickness of the bottom gate is 1500-2000A;
  • the top gate is a single-layer aluminum structure, a single-layer molybdenum structure, or a three-layer structure in which a layer of molybdenum is sandwiched between two layers of molybdenum; the top gate has a thickness of 1500-2000A.
  • the top gate and the bottom gate are identical in size, thickness, and material.
  • the present invention also provides a TFT substrate, comprising: a substrate, a buffer layer disposed on the substrate, a bottom gate disposed on the buffer layer, and a gate insulating layer disposed on the buffer layer and the bottom gate a low temperature polysilicon island disposed on the gate insulating layer, disposed on the low temperature polysilicon island and the gate a source and a drain on the edge layer, a passivation layer disposed on the source, the drain, the low temperature polysilicon island, and the gate insulating layer, and a passivation layer disposed on the passivation layer and corresponding to the bottom gate Top gate
  • the low temperature polysilicon island includes an undoped low temperature polysilicon layer and a P-type doped low temperature polysilicon layer disposed on the undoped low temperature polysilicon layer, and the undoped low temperature polysilicon layer is provided on the undoped low temperature polysilicon layer.
  • the impurities doped in the first P-type doped low-temperature polysilicon layer and the second P-type doped low-temperature polysilicon layer are boron ions;
  • the substrate is a glass substrate
  • the buffer layer is a single layer structure composed of silicon nitride, a single layer structure composed of silicon oxide, or a double layer structure composed of a silicon nitride layer and a silicon oxide layer;
  • the bottom gate is a single-layer aluminum structure, a single-layer molybdenum structure, or a three-layer structure in which a layer of molybdenum is sandwiched by two layers of molybdenum; the thickness of the bottom gate is 1500-2000A;
  • the top gate is a single-layer aluminum structure, a single-layer molybdenum structure, or a three-layer structure in which a layer of molybdenum is sandwiched between two layers of molybdenum; the top gate has a thickness of 1500-2000A.
  • the present invention provides a TFT substrate manufacturing method and a TFT substrate produced by the method of solid phase crystallization to prepare a low temperature polysilicon layer, which is more cost effective than an excimer laser crystallization technique, and The formed grain uniformity is better; at the same time, the double gate structure is introduced, the gate-to-channel control is enhanced, the open current of the thin film transistor is increased, the off current is reduced, the warpage effect is suppressed, and the threshold voltage and the subthreshold are lowered.
  • the slope increases the driving ability of the thin film transistor, and the top gate can also function as a light blocking function to reduce the occurrence of channel light leakage.
  • the TFT substrate provided by the invention has the low-temperature polysilicon layer prepared by the solid phase crystallization method, and the production cost is low, and the TFT substrate also has a double-gate structure, so that the thin film transistor has better electric conductivity and strong driving capability, and Channel photo leakage is less likely to occur.
  • FIG. 1 is a schematic view showing a step 1 of a method of fabricating a TFT substrate of the present invention
  • FIG. 2 is a schematic view showing a step 2 of a method for fabricating a TFT substrate of the present invention
  • FIG. 3 is a schematic view showing a step 3 of a method of fabricating a TFT substrate of the present invention
  • FIG. 4 is a schematic view showing a step 4 of a method of fabricating a TFT substrate of the present invention
  • 5-6 is a schematic diagram of step 5 of the method for fabricating a TFT substrate of the present invention.
  • FIGS. 7-8 are schematic views showing a step 6 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 9 is a schematic view showing a step 7 of a method of fabricating a TFT substrate of the present invention.
  • Fig. 10 is a schematic view showing the step 8 of the method for fabricating the TFT substrate of the present invention and a schematic view of the TFT substrate of the present invention.
  • the invention firstly provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step 1 As shown in FIG. 1, a substrate 1 is provided. After the substrate 1 is cleaned and pre-baked, a buffer layer 2 is deposited on the substrate 1.
  • the substrate 1 may be a glass substrate.
  • the buffer layer 2 may be a single layer structure composed of silicon nitride, a single layer structure composed of silicon oxide, or a two-layer structure composed of a silicon nitride layer and a silicon oxide layer.
  • the buffer layer 2 has a thickness of 500 to 2000 ⁇ .
  • Step 2 As shown in FIG. 2, a first metal layer is deposited on the buffer layer 2, and the first metal layer is patterned to obtain a bottom gate 3.
  • the bottom gate 3 may be a single-layer aluminum structure, a single-layer molybdenum structure, or a three-layer structure in which a layer of aluminum is sandwiched between two layers of molybdenum.
  • the bottom gate 3 has a thickness of 1500 to 2000A.
  • Step 3 as shown in FIG. 3, a gate insulating layer 4 is deposited on the bottom gate 3 and the buffer layer 2, and an amorphous silicon layer 5 is deposited on the gate insulating layer 4.
  • the gate insulating layer 4 may be a single layer structure composed of silicon nitride, a single layer structure composed of silicon oxide, or a two-layer structure composed of a silicon nitride layer and a silicon oxide layer.
  • the gate insulating layer 4 has a thickness of 500 to 2000 ⁇ .
  • the amorphous silicon layer 5 has a thickness of 500 to 2000 ⁇ .
  • Step 4 as shown in FIG. 4, P-type doping the amorphous silicon layer 5 to obtain a P-type doped amorphous silicon layer 52 located above and a P-type doped amorphous silicon layer 52.
  • the amorphous silicon layer 5 is doped with boron ions (B + ) using diborane (B 2 H 6 ) gas.
  • Step 5 as shown in FIG. 5, the undoped amorphous silicon layer 51 and the P-type doped amorphous silicon layer 52 are converted into undoped low temperature by a solid phase crystallization method (SPC, Solid Phase Crystallization).
  • SPC Solid Phase Crystallization
  • the polysilicon layer 61 and the P-type doped low-temperature polysilicon layer 62, as shown in FIG. 6, the non-doped low-temperature polysilicon layer 61 and the P-type doped low-temperature polysilicon layer 62 are patterned by a photolithography process. A low temperature polysilicon island 6 is formed.
  • the undoped amorphous silicon layer 51 and the P-type doped amorphous silicon layer 52 are heated and heated by a rapid thermal annealing (RTA) method.
  • RTA rapid thermal annealing
  • Step 6 depositing a second metal layer 7 over the low temperature polysilicon island 6, and the gate insulating layer 4, as shown in FIG. 8, the undoped low temperature polysilicon in the low temperature polysilicon island 6.
  • a channel region 613 corresponding to the bottom gate 3 is defined on the layer 61, and the second metal layer 7 and the low temperature polysilicon island 6 are patterned by a photolithography process to remove the channel region.
  • the source and drain electrodes 71 and 72 are in contact with the first and second P-type doped low-temperature polysilicon layers 621 and 622, respectively.
  • the width of the channel region 613 is smaller than the width of the bottom gate 3.
  • the source and drain electrodes 71 and 72 may be a single-layer aluminum structure, a single-layer molybdenum structure, or a three-layer structure in which a layer of aluminum is sandwiched between two layers of molybdenum.
  • the source and drain electrodes 71 and 72 have a thickness of 1500 to 2000 A.
  • Step 7 As shown in FIG. 9, a passivation layer 8 is deposited on the source, drain electrodes 71, 72, the channel region 613, and the gate insulating layer 4.
  • the passivation layer 8 may be a single layer structure composed of silicon nitride, a single layer structure composed of silicon oxide, or a two-layer structure composed of a silicon nitride layer and a silicon oxide layer.
  • the passivation layer 8 has a thickness of 3000 to 4000A.
  • Step 8 As shown in FIG. 10, a third metal layer is deposited on the passivation layer 8, and the third metal layer is patterned to obtain a top gate 9 corresponding to the bottom gate 3.
  • the top gate 9 may be a single-layer aluminum structure, a single-layer molybdenum structure, or a three-layer structure in which a layer of aluminum is sandwiched between two layers of molybdenum.
  • the top gate 9 has a thickness of 1500 to 2000A.
  • the top gate 9 and the bottom gate 3 are identical in size, thickness, and material.
  • the present invention further provides a TFT substrate prepared by the above method, comprising: a substrate 1 , a buffer layer 2 disposed on the substrate 1 , and disposed on the buffer layer
  • the bottom gate 3 on 2 the gates provided on the buffer layer 2 and the bottom gate 3 a low-temperature polysilicon island 6 disposed on the gate insulating layer 4, a source 71 and a drain 72 disposed on the low-temperature polysilicon island 6 and the gate insulating layer 4, and disposed at the source, a drain layer 71, 72, a low temperature polysilicon island 6 and a passivation layer 8 on the gate insulating layer 4, and a top gate 9 provided on the passivation layer 8 and corresponding to the bottom gate 3;
  • the low temperature polysilicon island 6 includes an undoped low temperature polysilicon layer 61 and a P-type doped low temperature polysilicon layer 62 disposed on the undoped low temperature polysilicon layer 61.
  • the undoped low temperature polysilicon layer 61 is provided.
  • the P-type doped low temperature polysilicon layer 62 includes a first P-type doped low temperature polysilicon layer corresponding to both sides of the channel region 613. 621, and a second P-type doped low temperature polysilicon layer 622; the source and drain electrodes 71, 72 are in contact with the first and second P-type doped low temperature polysilicon layers 621, 622, respectively.
  • the substrate 1 may be a glass substrate.
  • the buffer layer 2 may be a single layer structure composed of silicon nitride, a single layer structure composed of silicon oxide, or a two-layer structure composed of a silicon nitride layer and a silicon oxide layer.
  • the buffer layer 2 has a thickness of 500 to 2000 ⁇ .
  • the bottom gate 3 may be a single-layer aluminum structure, a single-layer molybdenum structure, or a three-layer structure in which a layer of aluminum is sandwiched between two layers of molybdenum.
  • the bottom gate 3 has a thickness of 1500 to 2000A.
  • the gate insulating layer 4 may be a single layer structure composed of silicon nitride, a single layer structure composed of silicon oxide, or a two-layer structure composed of a silicon nitride layer and a silicon oxide layer.
  • the gate insulating layer 4 has a thickness of 500 to 2000 ⁇ .
  • the low temperature polysilicon island 6 has a thickness of 500 to 2000 A.
  • the width of the channel region 613 is smaller than the width of the bottom gate 3.
  • the impurity doped in the first P-type doped low-temperature polysilicon layer 621 and the second P-type doped low-temperature polysilicon layer 622 is boron ion (B + ).
  • the source and drain electrodes 71 and 72 may be a single-layer aluminum structure, a single-layer molybdenum structure, or a three-layer structure in which a layer of aluminum is sandwiched between two layers of molybdenum.
  • the source and drain electrodes 71 and 72 have a thickness of 1500 to 2000 A.
  • the passivation layer 8 may be a single layer structure composed of silicon nitride, a single layer structure composed of silicon oxide, or a two-layer structure composed of a silicon nitride layer and a silicon oxide layer.
  • the passivation layer 8 has a thickness of 3000 to 4000A.
  • the top gate 9 may be a single-layer aluminum structure, a single-layer molybdenum structure, or a three-layer structure in which a layer of aluminum is sandwiched between two layers of molybdenum.
  • the top gate 9 has a thickness of 1500 to 2000A.
  • the top gate 9 and the bottom gate 3 are identical in size, thickness, and material.
  • the present invention provides a method for fabricating a TFT substrate and a fabricated TFT substrate, which uses a solid phase crystallization technique to prepare a low temperature polysilicon layer, which is associated with an excimer laser crystallization technique. Compared, it is more cost-effective and has better grain uniformity. At the same time, it introduces a double-gate structure, which strengthens the gate-to-channel control, increases the open current of the thin film transistor, reduces the off current, and suppresses the warpage effect. The threshold voltage and the subthreshold slope are lowered to improve the driving capability of the thin film transistor, and the top gate can also function as a light blocking function to reduce the occurrence of channel light leakage.
  • the TFT substrate provided by the invention has the low-temperature polysilicon layer prepared by the solid phase crystallization method, and the production cost is low, and the TFT substrate also has a double-gate structure, so that the thin film transistor has better electric conductivity and strong driving capability, and Channel photo leakage is less likely to occur.

Landscapes

  • Thin Film Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

一种TFT基板的制作方法及制得的TFT基板，该方法采用固相结晶技术制备低温多晶硅层，与准分子激光晶化技术相比，更加节省成本，并且形成的晶粒均一性更好；同时引入双栅极结构，加强了栅极对沟道的控制，增大薄膜晶体管的开电流，减小关电流，抑制翘曲效应，降低阈值电压和亚阈值斜率，提高薄膜晶体管的驱动能力，同时顶栅极还可以起到遮光作用，减少沟道光致漏电现象的发生。TFT基板，其低温多晶硅层采用固相结晶方法制备，生产成本较低，并且该TFT基板还具有双栅极结构，使得薄膜晶体管的电性较好，驱动能力强，且不容易发生沟道光致漏电现象。

Description

TFT基板的制作方法及制得的TFT基板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板的制作方法及制得的TFT基板。
背景技术
随着平板显示的发展，高分辨率，低能耗的面板需求不断被提出。低温多晶硅(Low Temperature Poly-Silicon，LTPS)由于具有较高的电子迁移率，而在液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，OLED)技术中得到了业界的重视，被视为实现低成本全彩平板显示的重要材料。对平板显示而言，低温多晶硅材料具有高分辨率、反应速度快、高亮度、高开口率、低能耗等优点，而且低温多晶硅可在低温下制作，并可用于制作C-MOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)电路，因而被广泛研究，用以达到面板高分辨率，低能耗的需求。
在多晶硅技术发展的初期，为了将玻璃基板从非晶硅结构转变为多晶硅结构，就必须借助一道激光退火(Laser Anneal)的高温氧化工序，制得高温多晶硅(High Temperature Poly-Silicon，HTPS)，此时玻璃基板的温度将超过摄氏1000度。与传统的高温多晶硅相比，低温多晶硅虽然也需要激光照射，但它一般采用的是准分子激光作为热源，激光经过透射系统后，会产生能量均匀分布的激光束并被投射于非晶硅结构的玻璃基板上，当非晶硅结构的玻璃基板吸收准分子激光的能量后，就会转变成为多晶硅结构。由于整个处理过程基本是在600摄氏度以下完成，一般普通的玻璃基板均可承受，这就大大降低了制造成本。而除了制造成本降低外，低温多晶硅的优点还体现在：电子迁移速率更快、稳定性更高。
目前制作低温多晶硅的方法主要有：固相结晶(Solid Phase Crystallization，SPC)、金属诱导结晶(Metal-Induced Crystallization，MIC)、与准分子激光退火(Excimer Laser Annealing，ELA)等多种制作方法。其中，ELA是目前使用最为广泛、相对成熟的制作低温多晶硅的方法，该方法的主要过程为：首先在玻璃基板上形成缓冲层，然后在缓冲层上形成非晶硅层，高温去氢，再利用ELA激光束扫描非晶硅进行准分子激光退火，非晶硅吸收激光的能量，在极短的时间内达到高温并变成熔融状态，最后 经冷却重结晶形成多晶硅。目前的情况是：通过ELA方法制得的低温多晶硅薄膜晶体管的均一性不佳且成本较高，而采用SPC方法虽然能够降低成本，提高均一性，但其开电流以及亚阈值斜率又不如ELA方法制得的低温多晶硅薄膜晶体管，并且关电流较大，因此驱动能力较差。
发明内容
本发明的目的在于提供一种TFT基板的制作方法，能够在节省生产成本的同时增大薄膜晶体管的开电流，减小关电流，抑制翘曲效应，降低阈值电压和亚阈值斜率，并减少沟道光致漏电现象的发生。
本发明的目的还在于提供一种TFT基板，该TFT基板生产成本较低，同时还能够增大薄膜晶体管的开电流，减小关电流，抑制翘曲效应，降低阈值电压和亚阈值斜率，且不容易发生沟道光致漏电现象。
为实现上述目的，本发明提供一种TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板，对所述基板进行清洗与预烘烤后，在所述基板上沉积一缓冲层；
步骤2、在所述缓冲层上沉积第一金属层，并对该第一金属层进行图案化处理，得到底栅极；
步骤3、在所述底栅极、及缓冲层上沉积栅极绝缘层，在所述栅极绝缘层上沉积非晶硅层；
步骤4、对所述非晶硅层进行P型掺杂，得到位于上方的P型掺杂非晶硅层、及位于所述P型掺杂非晶硅层下方的未掺杂非晶硅层；
步骤5、采用固相结晶方法将所述未掺杂非晶硅层、及P型掺杂非晶硅层转化为未掺杂低温多晶硅层、及P型掺杂低温多晶硅层，采用一道光刻制程对所述未掺杂低温多晶硅层、及P型掺杂低温多晶硅层进行图案化处理，形成低温多晶硅岛；
步骤6、在所述低温多晶硅岛、及栅极绝缘层上方沉积第二金属层，在所述低温多晶硅岛的未掺杂低温多晶硅层上定义出对应于所述底栅极上方的沟道区，采用一道光刻制程对该第二金属层、及低温多晶硅岛进行图案化处理，去除位于所述沟道区上方的P型掺杂低温多晶硅层、及第二金属层，从而形成对应所述沟道区两侧的源极与漏极、及第一P型掺杂低温多晶硅层与第二P型掺杂低温多晶硅层；
所述源、漏极分别与所述第一、第二P型掺杂低温多晶硅层相接触；
步骤7、在所述源、漏极、沟道区、及栅极绝缘层上沉积钝化层；
步骤8、在所述钝化层上沉积第三金属层，并对该第三金属层进行图案化处理，得到对应所述底栅极的顶栅极。
所述步骤4中，采用乙硼烷气体对所述非晶硅层进行硼离子掺杂。
所述步骤5中，在固相结晶的过程中，采用快速热退火的方法对所述未掺杂非晶硅层、及P型掺杂非晶硅层进行加热，加热温度为670～730℃，时间为10～30min。
所述步骤2中，所述底栅极为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构；所述底栅极的厚度为1500～2000A；
所述步骤8中，所述顶栅极为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构；所述顶栅极的厚度为1500～2000A。
所述顶栅极与底栅极的大小、厚度、及材料完全相同。
本发明还提供一种TFT基板，包括：基板，设于所述基板上的缓冲层，设于所述缓冲层上的底栅极，设于所述缓冲层及底栅极上的栅极绝缘层，设于所述栅极绝缘层上的低温多晶硅岛，设于所述低温多晶硅岛及栅极绝缘层上的源极与漏极，设于所述源、漏极、低温多晶硅岛及栅极绝缘层上的钝化层，及设于所述钝化层上且对应所述底栅极的顶栅极；
其中，所述低温多晶硅岛包括未掺杂低温多晶硅层及设于所述未掺杂低温多晶硅层上的P型掺杂低温多晶硅层，所述未掺杂低温多晶硅层上设有对应于所述底栅极与顶栅极的沟道区，所述P型掺杂低温多晶硅层包括对应所述沟道区两侧的第一P型掺杂低温多晶硅层、及第二P型掺杂低温多晶硅层；所述源、漏极分别与所述第一、第二P型掺杂低温多晶硅层相接触。
所述第一P型掺杂低温多晶硅层、及第二P型掺杂低温多晶硅层中掺入的杂质为硼离子。
所述基板为玻璃基板；所述缓冲层为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构。
所述底栅极为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构；所述底栅极的厚度为1500～2000A；
所述顶栅极为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构；所述顶栅极的厚度为1500～2000A。
所述顶栅极与底栅极的大小、厚度、及材料完全相同。
本发明还提供一种TFT基板，包括：基板，设于所述基板上的缓冲层，设于所述缓冲层上的底栅极，设于所述缓冲层及底栅极上的栅极绝缘层，设于所述栅极绝缘层上的低温多晶硅岛，设于所述低温多晶硅岛及栅极绝 缘层上的源极与漏极，设于所述源、漏极、低温多晶硅岛及栅极绝缘层上的钝化层，及设于所述钝化层上且对应所述底栅极的顶栅极；
其中，所述低温多晶硅岛包括未掺杂低温多晶硅层及设于所述未掺杂低温多晶硅层上的P型掺杂低温多晶硅层，所述未掺杂低温多晶硅层上设有对应于所述底栅极与顶栅极的沟道区，所述P型掺杂低温多晶硅层包括对应所述沟道区两侧的第一P型掺杂低温多晶硅层、及第二P型掺杂低温多晶硅层；所述源、漏极分别与所述第一、第二P型掺杂低温多晶硅层相接触；
其中，所述第一P型掺杂低温多晶硅层、及第二P型掺杂低温多晶硅层中掺入的杂质为硼离子；
其中，所述基板为玻璃基板；所述缓冲层为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构；
其中，所述底栅极为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构；所述底栅极的厚度为1500～2000A；
所述顶栅极为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构；所述顶栅极的厚度为1500～2000A。
本发明的有益效果：本发明提供一种TFT基板的制作方法及制得的TFT基板，该方法采用固相结晶技术制备低温多晶硅层，与准分子激光晶化技术相比，更加节省成本，并且形成的晶粒均一性更好；同时引入双栅极结构，加强了栅极对沟道的控制，增大薄膜晶体管的开电流，减小关电流，抑制翘曲效应，降低阈值电压和亚阈值斜率，提高薄膜晶体管的驱动能力，同时顶栅极还可以起到遮光作用，减少沟道光致漏电现象的发生。本发明提供的一种TFT基板，其低温多晶硅层采用固相结晶方法制备，生产成本较低，并且该TFT基板还具有双栅极结构，使得薄膜晶体管的电性较好，驱动能力强，且不容易发生沟道光致漏电现象。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明的TFT基板的制作方法的步骤1的示意图；
图2为本发明的TFT基板的制作方法的步骤2的示意图；
图3为本发明的TFT基板的制作方法的步骤3的示意图；
图4为本发明的TFT基板的制作方法的步骤4的示意图；
图5-6为本发明的TFT基板的制作方法的步骤5的示意图；
图7-8为本发明的TFT基板的制作方法的步骤6的示意图；
图9为本发明的TFT基板的制作方法的步骤7的示意图；
图10为本发明的TFT基板的制作方法的步骤8的示意图暨本发明的TFT基板的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明首先提供一种TFT基板的制作方法，包括如下步骤：
步骤1、如图1所示，提供一基板1，对所述基板1进行清洗与预烘烤后，在所述基板1上沉积一缓冲层2。
具体的，所述基板1可以为玻璃基板。
具体的，所述缓冲层2可以为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构。优选的，所述缓冲层2的厚度为500～2000A。
步骤2、如图2所示，在所述缓冲层2上沉积第一金属层，并对该第一金属层进行图案化处理，得到底栅极3。
具体的，所述底栅极3可以为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构。优选的，所述底栅极3的厚度为1500～2000A。
步骤3、如图3所示，在所述底栅极3、及缓冲层2上沉积栅极绝缘层4，在所述栅极绝缘层4上沉积非晶硅层5。
具体的，所述栅极绝缘层4可以为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构。优选的，所述栅极绝缘层4的厚度为500～2000A。
优选的，所述非晶硅层5的厚度为500～2000A。
步骤4、如图4所示，对所述非晶硅层5进行P型掺杂，得到位于上方的P型掺杂非晶硅层52、及位于所述P型掺杂非晶硅层52下方的未掺杂非晶硅层51。
具体的，采用乙硼烷(B2H6)气体对所述非晶硅层5进行硼离子(B+)掺杂。
步骤5、如图5所示，采用固相结晶方法(SPC，Solid Phase Crystallization，)将所述未掺杂非晶硅层51、及P型掺杂非晶硅层52转化为未掺杂低温多晶硅层61、及P型掺杂低温多晶硅层62，如图6所示，采用一道光刻制程对所述未掺杂低温多晶硅层61、及P型掺杂低温多晶硅层62进行图案化处理，形成低温多晶硅岛6。
具体的，在固相结晶的过程中，采用快速热退火(RTA，Rapid Thermal Annealing)的方法对所述未掺杂非晶硅层51、及P型掺杂非晶硅层52进行加热，加热温度为670～730℃，时间为10～30min。
步骤6、如图7所示，在所述低温多晶硅岛6、及栅极绝缘层4上方沉积第二金属层7，如图8所示，在所述低温多晶硅岛6的未掺杂低温多晶硅层61上定义出对应于所述底栅极3上方的沟道区613，采用一道光刻制程对该第二金属层7、及低温多晶硅岛6进行图案化处理，去除位于所述沟道区613上方的P型掺杂低温多晶硅层62、及第二金属层7，从而形成对应所述沟道区613两侧的源极71与漏极72、及第一P型掺杂低温多晶硅层621与第二P型掺杂低温多晶硅层622；
所述源、漏极71、72分别与所述第一、第二P型掺杂低温多晶硅层621、622相接触。
具体的，所述沟道区613的宽度小于所述底栅极3的宽度。
具体的，所述源、漏极71、72可以为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构。优选的，所述源、漏极71、72的厚度为1500～2000A。
步骤7、如图9所示，在所述源、漏极71、72、沟道区613、及栅极绝缘层4上沉积钝化层8。
具体的，所述钝化层8可以为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构。优选的，所述钝化层8的厚度为3000～4000A。
步骤8、如图10所示，在所述钝化层8上沉积第三金属层，并对该第三金属层进行图案化处理，得到对应所述底栅极3的顶栅极9。
具体的，所述顶栅极9可以为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构。优选的，所述顶栅极9的厚度为1500～2000A。
优选的，所述顶栅极9与底栅极3的大小、厚度、及材料完全相同。
请参阅图10，基于上述TFT基板的制作方法，本发明还提供一种采用上述方法制备的TFT基板，包括：基板1，设于所述基板1上的缓冲层2，设于所述缓冲层2上的底栅极3，设于所述缓冲层2及底栅极3上的栅极绝 缘层4，设于所述栅极绝缘层4上的低温多晶硅岛6，设于所述低温多晶硅岛6及栅极绝缘层4上的源极71与漏极72，设于所述源、漏极71、72、低温多晶硅岛6及栅极绝缘层4上的钝化层8，及设于所述钝化层8上且对应所述底栅极3的顶栅极9；
其中，所述低温多晶硅岛6包括未掺杂低温多晶硅层61及设于所述未掺杂低温多晶硅层61上的P型掺杂低温多晶硅层62，所述未掺杂低温多晶硅层61上设有对应于所述底栅极3与顶栅极9的沟道区613，所述P型掺杂低温多晶硅层62包括对应所述沟道区613两侧的第一P型掺杂低温多晶硅层621、及第二P型掺杂低温多晶硅层622；所述源、漏极71、72分别与所述第一、第二P型掺杂低温多晶硅层621、622相接触。
具体的，所述基板1可以为玻璃基板。
具体的，所述缓冲层2可以为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构。优选的，所述缓冲层2的厚度为500～2000A。
具体的，所述底栅极3可以为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构。优选的，所述底栅极3的厚度为1500～2000A。
具体的，所述栅极绝缘层4可以为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构。优选的，所述栅极绝缘层4的厚度为500～2000A。
具体的，所述低温多晶硅岛6的厚度为500～2000A。
具体的，所述沟道区613的宽度小于所述底栅极3的宽度。
具体的，所述第一P型掺杂低温多晶硅层621、及第二P型掺杂低温多晶硅层622中掺入的杂质为硼离子(B+)。
具体的，所述源、漏极71、72可以为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构。优选的，所述源、漏极71、72的厚度为1500～2000A。
具体的，所述钝化层8可以为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构。优选的，所述钝化层8的厚度为3000～4000A。
具体的，所述顶栅极9可以为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构。优选的，所述顶栅极9的厚度为1500～2000A。
优选的，所述顶栅极9与底栅极3的大小、厚度、及材料完全相同。
综上所述，本发明提供一种TFT基板的制作方法及制得的TFT基板，该方法采用固相结晶技术制备低温多晶硅层，与准分子激光晶化技术相 比，更加节省成本，并且形成的晶粒均一性更好；同时引入双栅极结构，加强了栅极对沟道的控制，增大薄膜晶体管的开电流，减小关电流，抑制翘曲效应，降低阈值电压和亚阈值斜率，提高薄膜晶体管的驱动能力，同时顶栅极还可以起到遮光作用，减少沟道光致漏电现象的发生。本发明提供的一种TFT基板，其低温多晶硅层采用固相结晶方法制备，生产成本较低，并且该TFT基板还具有双栅极结构，使得薄膜晶体管的电性较好，驱动能力强，且不容易发生沟道光致漏电现象。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (12)

  1. 一种TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板，对所述基板进行清洗与预烘烤后，在所述基板上沉积一缓冲层；
    步骤2、在所述缓冲层上沉积第一金属层，并对该第一金属层进行图案化处理，得到底栅极；
    步骤3、在所述底栅极、及缓冲层上沉积栅极绝缘层，在所述栅极绝缘层上沉积非晶硅层；
    步骤4、对所述非晶硅层进行P型掺杂，得到位于上方的P型掺杂非晶硅层、及位于所述P型掺杂非晶硅层下方的未掺杂非晶硅层；
    步骤5、采用固相结晶方法将所述未掺杂非晶硅层、及P型掺杂非晶硅层转化为未掺杂低温多晶硅层、及P型掺杂低温多晶硅层，采用一道光刻制程对所述未掺杂低温多晶硅层、及P型掺杂低温多晶硅层进行图案化处理，形成低温多晶硅岛；
    步骤6、在所述低温多晶硅岛、及栅极绝缘层上方沉积第二金属层，在所述低温多晶硅岛的未掺杂低温多晶硅层上定义出对应于所述底栅极上方的沟道区，采用一道光刻制程对该第二金属层、及低温多晶硅岛进行图案化处理，去除位于所述沟道区上方的P型掺杂低温多晶硅层、及第二金属层，从而形成对应所述沟道区两侧的源极与漏极、及第一P型掺杂低温多晶硅层与第二P型掺杂低温多晶硅层；
    所述源、漏极分别与所述第一、第二P型掺杂低温多晶硅层相接触；
    步骤7、在所述源、漏极、沟道区、及栅极绝缘层上沉积钝化层；
    步骤8、在所述钝化层上沉积第三金属层，并对该第三金属层进行图案化处理，得到对应所述底栅极的顶栅极。
  2. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤4中，采用乙硼烷气体对所述非晶硅层进行硼离子掺杂。
  3. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤5中，在固相结晶的过程中，采用快速热退火的方法对所述未掺杂非晶硅层、及P型掺杂非晶硅层进行加热，加热温度为670～730℃，时间为10～30min。
  4. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤2中，所述底栅极为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构；所述底栅极的厚度为1500～2000A；
    所述步骤8中，所述顶栅极为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构；所述顶栅极的厚度为1500～2000A。
  5. 如权利要求4所述的TFT基板的制作方法，其中，所述顶栅极与底栅极的大小、厚度、及材料完全相同。
  6. 一种TFT基板，包括：基板，设于所述基板上的缓冲层，设于所述缓冲层上的底栅极，设于所述缓冲层及底栅极上的栅极绝缘层，设于所述栅极绝缘层上的低温多晶硅岛，设于所述低温多晶硅岛及栅极绝缘层上的源极与漏极，设于所述源、漏极、低温多晶硅岛及栅极绝缘层上的钝化层，及设于所述钝化层上且对应所述底栅极的顶栅极；
    其中，所述低温多晶硅岛包括未掺杂低温多晶硅层及设于所述未掺杂低温多晶硅层上的P型掺杂低温多晶硅层，所述未掺杂低温多晶硅层上设有对应于所述底栅极与顶栅极的沟道区，所述P型掺杂低温多晶硅层包括对应所述沟道区两侧的第一P型掺杂低温多晶硅层、及第二P型掺杂低温多晶硅层；所述源、漏极分别与所述第一、第二P型掺杂低温多晶硅层相接触。
  7. 如权利要求6所述的TFT基板，其中，所述第一P型掺杂低温多晶硅层、及第二P型掺杂低温多晶硅层中掺入的杂质为硼离子。
  8. 如权利要求6所述的TFT基板，其中，所述基板为玻璃基板；所述缓冲层为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构。
  9. 如权利要求6所述的TFT基板，其中，所述底栅极为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构；所述底栅极的厚度为1500～2000A；
    所述顶栅极为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构；所述顶栅极的厚度为1500～2000A。
  10. 如权利要求9所述的TFT基板，其中，所述顶栅极与底栅极的大小、厚度、及材料完全相同。
  11. 一种TFT基板，包括：基板，设于所述基板上的缓冲层，设于所述缓冲层上的底栅极，设于所述缓冲层及底栅极上的栅极绝缘层，设于所述栅极绝缘层上的低温多晶硅岛，设于所述低温多晶硅岛及栅极绝缘层上的源极与漏极，设于所述源、漏极、低温多晶硅岛及栅极绝缘层上的钝化层，及设于所述钝化层上且对应所述底栅极的顶栅极；
    其中，所述低温多晶硅岛包括未掺杂低温多晶硅层及设于所述未掺杂低温多晶硅层上的P型掺杂低温多晶硅层，所述未掺杂低温多晶硅层上设 有对应于所述底栅极与顶栅极的沟道区，所述P型掺杂低温多晶硅层包括对应所述沟道区两侧的第一P型掺杂低温多晶硅层、及第二P型掺杂低温多晶硅层；所述源、漏极分别与所述第一、第二P型掺杂低温多晶硅层相接触；
    其中，所述第一P型掺杂低温多晶硅层、及第二P型掺杂低温多晶硅层中掺入的杂质为硼离子；
    其中，所述基板为玻璃基板；所述缓冲层为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构；
    其中，所述底栅极为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构；所述底栅极的厚度为1500～2000A；
    所述顶栅极为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构；所述顶栅极的厚度为1500～2000A。
  12. 如权利要求11所述的TFT基板，其中，所述顶栅极与底栅极的大小、厚度、及材料完全相同。
PCT/CN2015/087720 2015-07-16 2015-08-21 Tft基板的制作方法及制得的tft基板 Ceased WO2017008368A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/781,308 US9761447B2 (en) 2015-07-16 2015-08-21 Method for manufacturing TFT substrate and TFT substrate manufactured thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510420705.3 2015-07-16
CN201510420705.3A CN105070724A (zh) 2015-07-16 2015-07-16 Tft基板的制作方法及制得的tft基板

Publications (1)

Publication Number Publication Date
WO2017008368A1 true WO2017008368A1 (zh) 2017-01-19

Family

ID=54500054

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/087720 Ceased WO2017008368A1 (zh) 2015-07-16 2015-08-21 Tft基板的制作方法及制得的tft基板

Country Status (3)

Country Link
US (1) US9761447B2 (zh)
CN (1) CN105070724A (zh)
WO (1) WO2017008368A1 (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105870198B (zh) * 2016-05-11 2020-03-31 京东方科技集团股份有限公司 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置
CN106098628B (zh) * 2016-06-07 2019-04-02 深圳市华星光电技术有限公司 Tft背板的制作方法及tft背板
WO2018043643A1 (ja) * 2016-09-02 2018-03-08 シャープ株式会社 アクティブマトリクス基板およびアクティブマトリクス基板を備えた表示装置
CN106910748A (zh) * 2017-04-10 2017-06-30 深圳市华星光电技术有限公司 一种阵列基板、显示装置及其制作方法
US10290665B2 (en) 2017-04-10 2019-05-14 Shenzhen China Star Optoelectronics Technology Co., Ltd Array substrates, display devices, and the manufacturing methods thereof
CN107039284A (zh) * 2017-04-17 2017-08-11 武汉华星光电技术有限公司 一种制作低温多晶硅薄膜晶体管的方法
CN107046003B (zh) * 2017-06-02 2019-05-03 武汉华星光电技术有限公司 低温多晶硅tft基板及其制作方法
CN107634011A (zh) 2017-09-20 2018-01-26 武汉华星光电半导体显示技术有限公司 一种阵列基板及其制造方法
CN109285782A (zh) * 2018-10-15 2019-01-29 深圳市华星光电技术有限公司 薄膜晶体管结构及其制作方法
CN109659370A (zh) * 2018-12-13 2019-04-19 武汉华星光电半导体显示技术有限公司 金属氧化物薄膜晶体管及其制作方法
CN109764983B (zh) * 2019-03-06 2021-01-22 京东方科技集团股份有限公司 双栅薄膜晶体管、传感器及制作方法
CN110581177A (zh) * 2019-08-13 2019-12-17 武汉华星光电半导体显示技术有限公司 阵列基板及其制备方法
CN110993697B (zh) * 2019-11-28 2022-08-05 深圳市华星光电半导体显示技术有限公司 薄膜晶体管及其制造方法、显示面板
CN113748521B (zh) * 2020-03-27 2024-09-13 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板、显示装置
CN112038288B (zh) * 2020-11-04 2021-02-02 成都中电熊猫显示科技有限公司 阵列基板的制作方法及阵列基板
CN115188831B (zh) * 2022-09-09 2022-12-23 惠科股份有限公司 薄膜晶体管结构、显示面板以及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1020899A2 (en) * 1999-01-11 2000-07-19 Hitachi, Ltd. TFT with large-grain polycrystalline active layer
CN1725510A (zh) * 2004-07-22 2006-01-25 广辉电子股份有限公司 低温多晶硅薄膜晶体管及其制造方法
CN103390592A (zh) * 2013-07-17 2013-11-13 京东方科技集团股份有限公司 阵列基板制备方法、阵列基板以及显示装置
CN104409512A (zh) * 2014-11-11 2015-03-11 深圳市华星光电技术有限公司 基于双栅极结构的低温多晶硅薄膜晶体管及其制备方法
CN104409350A (zh) * 2014-11-20 2015-03-11 深圳市华星光电技术有限公司 薄膜晶体管的制造方法
CN104576399A (zh) * 2014-12-29 2015-04-29 昆山国显光电有限公司 一种薄膜晶体管及其制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100379684B1 (ko) * 2001-04-20 2003-04-10 엘지.필립스 엘시디 주식회사 박막 트랜지스터 액정표시소자 제조방법
KR100797374B1 (ko) * 2001-06-05 2008-01-22 엘지.필립스 엘시디 주식회사 액정표시장치 및 그의 제조방법
CN1327530C (zh) * 2003-03-19 2007-07-18 鸿富锦精密工业（深圳）有限公司 薄膜晶体管及显示装置
KR100539623B1 (ko) * 2003-06-25 2005-12-28 엘지.필립스 엘시디 주식회사 버텀 게이트형 폴리 실리콘 박막트랜지스터 소자의 제조방법
KR100557730B1 (ko) * 2003-12-26 2006-03-06 엘지.필립스 엘시디 주식회사 듀얼패널타입 유기전계발광 소자 및 그 제조방법
US7507648B2 (en) * 2005-06-30 2009-03-24 Ramesh Kakkad Methods of fabricating crystalline silicon film and thin film transistors
US7700995B2 (en) * 2006-01-12 2010-04-20 Sharp Kabushiki Kaisha Semiconductor device and display device
CN100530605C (zh) * 2007-07-09 2009-08-19 友达光电股份有限公司 画素结构及其制作方法
KR101182232B1 (ko) * 2010-06-30 2012-09-12 삼성디스플레이 주식회사 유기전계발광 표시장치
KR101108176B1 (ko) * 2010-07-07 2012-01-31 삼성모바일디스플레이주식회사 더블 게이트형 박막 트랜지스터 및 이를 구비한 유기 발광 표시 장치

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1020899A2 (en) * 1999-01-11 2000-07-19 Hitachi, Ltd. TFT with large-grain polycrystalline active layer
CN1725510A (zh) * 2004-07-22 2006-01-25 广辉电子股份有限公司 低温多晶硅薄膜晶体管及其制造方法
CN103390592A (zh) * 2013-07-17 2013-11-13 京东方科技集团股份有限公司 阵列基板制备方法、阵列基板以及显示装置
CN104409512A (zh) * 2014-11-11 2015-03-11 深圳市华星光电技术有限公司 基于双栅极结构的低温多晶硅薄膜晶体管及其制备方法
CN104409350A (zh) * 2014-11-20 2015-03-11 深圳市华星光电技术有限公司 薄膜晶体管的制造方法
CN104576399A (zh) * 2014-12-29 2015-04-29 昆山国显光电有限公司 一种薄膜晶体管及其制造方法

Also Published As

Publication number Publication date
US9761447B2 (en) 2017-09-12
CN105070724A (zh) 2015-11-18
US20170154773A1 (en) 2017-06-01

Similar Documents

Publication Publication Date Title
WO2017008368A1 (zh) Tft基板的制作方法及制得的tft基板
CN106558593B (zh) 阵列基板、显示面板、显示装置及阵列基板的制备方法
CN105390451B (zh) 低温多晶硅tft基板的制作方法
TWI492315B (zh) 低溫多晶矽薄膜晶體管製造方法
CN103151388B (zh) 一种多晶硅薄膜晶体管及其制备方法、阵列基板
US8119465B1 (en) Thin film transistor and method for fabricating the same
CN106057735A (zh) Tft背板的制作方法及tft背板
WO2016070505A1 (zh) Amoled背板的制作方法
KR101498136B1 (ko) 폴리실리콘 활성층을 함유한 박막트랜지스터, 그 제조방법 및 어레이 기판
WO2016165187A1 (zh) 双栅极氧化物半导体tft基板的制作方法及其结构
WO2016101401A1 (zh) 低温多晶硅tft基板的制作方法及其结构
CN106601823A (zh) 一种薄膜晶体管的制作方法及薄膜晶体管
CN105576017A (zh) 一种基于氧化锌薄膜的薄膜晶体管
CN104716200B (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
WO2016101400A1 (zh) 低温多晶硅tft基板的制作方法及其结构
TWI593024B (zh) 薄膜電晶體的製造方法
WO2016201725A1 (zh) 低温多晶硅tft基板的制作方法及低温多晶硅tft基板
CN106952963B (zh) 一种薄膜晶体管及制作方法、阵列基板、显示装置
US10192903B2 (en) Method for manufacturing TFT substrate
CN104867983A (zh) 一种LDD/Offset结构薄膜晶体管及其制备方法
WO2019000508A1 (zh) 薄膜晶体管阵列基板及其制备方法、显示装置
US10516058B2 (en) Low temperature polysilicon thin film transistor and preparation method thereof
WO2022001468A1 (zh) 薄膜晶体管、显示基板及显示装置
WO2019028934A1 (zh) 低温多晶硅薄膜晶体管及其制备方法
WO2018119866A1 (zh) 一种低温多晶硅阵列基板及其制作方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14781308

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15898095

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15898095

Country of ref document: EP

Kind code of ref document: A1