WO2017004969A1 - 阵列基板和显示装置 - Google Patents

阵列基板和显示装置 Download PDF

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Publication number
WO2017004969A1
WO2017004969A1 PCT/CN2016/070097 CN2016070097W WO2017004969A1 WO 2017004969 A1 WO2017004969 A1 WO 2017004969A1 CN 2016070097 W CN2016070097 W CN 2016070097W WO 2017004969 A1 WO2017004969 A1 WO 2017004969A1
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Prior art keywords
chamfer
drain
source
film transistor
thin film
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Ceased
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PCT/CN2016/070097
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English (en)
French (fr)
Inventor
王静
贺伟
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to US15/110,565 priority Critical patent/US9923040B2/en
Publication of WO2017004969A1 publication Critical patent/WO2017004969A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to an array substrate and a display device.
  • a thin film transistor (TFT) arranged in a matrix and a driving chip for driving the thin film transistor are usually provided on the array substrate.
  • the thin film transistor is formed in the display area by a patterning process, and the driver chip is bonded in the non-display area.
  • a gate drive integrated GOA Gate On Array
  • the gate driving circuit is composed of a thin film transistor and can be formed by a patterning process like the thin film transistor of the display region.
  • the gate driver integrated chip portion is omitted, which not only saves cost, but also can be used for the tablet because the bonding process of the gate line direction can be omitted and the productivity is improved.
  • the non-display area thin film transistor of the display device.
  • the thin film transistor generally includes a gate G, a source S, a drain D, and a semiconductor layer.
  • the structure of the GOA thin film transistor in the non-display area and the structure of the pixel thin film transistor in the display area are different: the groove region between the source and the drain in the GOA thin film transistor shown in FIG. 1 is usually a U-shaped structure.
  • the trench region between the source and the drain in the pixel thin film transistor shown in FIG. 2 is a right angle structure.
  • the trench structure between the source and the drain of the GOA thin film transistor is more space-saving and is suitable for a limited space of a non-display area.
  • the same exposure direction is used for the entire substrate in the exposure step (depending on the typesetting of the thin film transistor on the substrate, It may be in the X direction or the Y direction), since the groove shape between the source and the drain of the GOA thin film transistor and the groove shape between the source and the drain of the pixel thin film transistor are inconsistent, it is easy to make There is a difference between the exposure of the GOA region and the exposure of the pixel region (such as unevenness, some regions in the trench are exposed and others are poorly exposed); in the development step after the exposure step, the source and the source are The groove region between the drains has residual photoresist due to the difference in exposure; further, the source region and the drain region between the source and the drain in the GOA region or the pixel region are caused by the photoresist residue. The extreme metal film etching is not clean. The uneven exposure of any of the GOA area and the pixel area causes the characteristics of the thin film transistor to be affected, which affects the display quality
  • the technical problem to be solved by the present invention is to provide an array substrate and a display device in which the non-display area and the display area thin film transistor have at least partially bent portions having the same shape, It has the same groove exposure performance between the source and the drain, and the display quality is better.
  • the array substrate is divided into a display area and a non-display area, the non-display area is provided with a first thin film transistor, and the display area is provided with a second thin film transistor, the first a region of the first active layer of the thin film transistor corresponding to the first source and the first drain forms a first trench, and a second active layer of the second thin film transistor corresponds to the second a region between the source and the second drain forms a second trench,
  • the first groove has at least one first bent portion
  • the second groove has a second bent portion
  • the first bent portion and the second bent portion have the same bending angle, or
  • the bending angles of the first bending portion and the second bending portion are set to each other (the sum of the angles is equal to 360 degrees).
  • each of the first bends includes a mirror image pair with respect to the first axis of symmetry
  • the first portion and the second portion of at least one of the first bent portions are alternately arranged;
  • the second bent portion includes mirror symmetry about the second axis of symmetry
  • the third portion and the fourth portion are disposed, and the first axis of symmetry is parallel to the second axis of symmetry.
  • the first axis of symmetry and the second axis of symmetry may be parallel to a gate of the second thin film transistor.
  • the first source is a U-shaped structure, and both sides of the U-shaped structure respectively have at least one first chamfer of the same number and shape, and the first drain is inserted into the U-shaped structure.
  • the second drain has a convex third angle
  • the second source has a concave fourth corner at a portion opposite to the third angle
  • a region between the third chamfer and the opposite fourth chamfer forms the second bend.
  • each of the first chamfers is composed of two intersecting first line segments, and each of the second chamfers is formed by two intersecting second line segments, and the first one of the first chamfers a region between a line segment and an opposite one of the second line segments constituting the second chamfer forms the first portion, and the other of the first line segments constituting the first chamfer is opposite thereto a region between another of the second line segments constituting the second chamfer forming the second portion;
  • Each of the third chamfers is composed of two intersecting third line segments, each of the fourth chamfers being composed of two intersecting second line segments, and the third line segment constituting the third chamfer is opposite thereto a region between the one of the fourth line segments constituting the fourth chamfer forming the third portion, a third line segment constituting the third chamfer and a piece constituting the fourth chamfer The area between the fourth line segments forms the fourth portion.
  • the first bent portion has a chamfer; and the second bent portion has a chamfered portion.
  • the first bending portion and the second bending portion have a bending angle ranging from 70 degrees to 110 degrees.
  • the first bending portion and the second bending portion have a bending angle of 90 degrees.
  • the first source, the first drain, the second source, and the second drain are made of the same material and formed in the same patterning process.
  • a display device comprising the above array substrate.
  • the beneficial effects of the present invention are: in the array substrate, since the trenches in the thin film transistors of the non-display area and the display area have at least partially bent portions, the lithography is performed when the source-drain electrodes are formed by a patterning process.
  • the exposure of the glue is more uniform, so that the problem of residual photoresist between the source and the drain due to poor exposure can be avoided; correspondingly, the subsequent etching process includes source and drain.
  • the pattern of the pole is formed in the process of forming a trench region between the source and the drain, thereby avoiding poor etching of the trench between the source and the drain due to residual photoresist, and ensuring the thin film transistor Performance improves the quality of array substrate products.
  • FIG. 1 is a schematic structural view of a thin film transistor of a GOA region in the prior art
  • FIG. 2 is a schematic structural view of a thin film transistor of a pixel region in the prior art
  • FIG. 3 is a schematic structural view of a thin film transistor of a GOA region according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic structural view of a thin film transistor of a pixel region according to Embodiment 1 of the present invention.
  • Figure 5 is a partial enlarged view of Figure 4.
  • Figure 6 is a schematic view showing the length and width of the groove in Figure 3;
  • Figure 7 is a schematic view showing the length and width of the groove in Figure 4.
  • the embodiment provides an array substrate, which greatly reduces the patterning process by setting the grooves between the source and the drain of the non-display area and the thin film transistor of the display area to at least partially the same shape.
  • the difference in exposure caused by the exposure step avoids uneven exposure, ensures the performance of the thin film transistor, and improves the yield and performance of the array substrate.
  • the inventive concept is not limited to the specific form illustrated in the embodiment, for example, the trench between the source and the drain of the thin film transistor of the non-display area and the display area may have any other shape than the fold line form.
  • the (first) groove in the non-display area has a geometrically similar shape to the (second) groove in the display area, it is possible to have the same or similar exposure performance.
  • the array substrate is divided into a display area shown in FIG. 4 and a non-display area shown in FIG. 3.
  • the non-display area is provided with a first thin film transistor
  • the display area is provided with a second thin film transistor.
  • a region of the first active layer 14 of the first thin film transistor corresponding to the first source 12 and the first drain 13 forms a first trench 15 and a second active layer 24 of the second thin film transistor
  • a second trench 25 is formed corresponding to a region between the second source 22 and the second drain 23, and the first trench 15 and the second trench 25 have bent portions of the same shape.
  • the display area may include respective pixel areas
  • the non-display area may include a GOA area.
  • the first thin film transistor is disposed in the non-display area, specifically in the GOA area, that is, integrated in the area for driving the gate line scanning; the second thin film transistor is disposed in the display area, specifically, corresponding to each display pixel. Area, so the display area can also be called a pixel area.
  • the first thin film transistor further includes a first gate 11 and the second thin film transistor further includes a second gate 21, which will not be described in detail herein.
  • the second gate 21 is electrically connected to the gate line 27, and the second source 22 and the data
  • the line 28 is electrically connected
  • the second drain 23 is electrically connected to the pixel electrode 26 to effect pixel display under the control of the thin film transistor.
  • the first source 12 of the first thin film transistor, the first drain 13 and the second source 22 and the second drain 23 of the second thin film transistor are made of the same material and are in the same composition. Formed in the process.
  • the first active layer 14 of the first thin film transistor and the second active layer 24 of the second thin film transistor are formed of the same material and are formed in the same patterning process.
  • the patterning process may include only a photolithography process, or a photolithography process and an etching process.
  • the photolithography process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like including a process of film formation, exposure, and development.
  • the channel is a very important structure for the thin film transistor, and the thin film transistor includes a semiconductor layer respectively connected to the source and the drain, and a part of the semiconductor layer formed between the separated source and the drain is at the gate Under the condition of applying an on-voltage, conduction in the longitudinal direction is caused by an electric field, and at this time, a portion of the semiconductor layer between the separated source and drain forms a channel.
  • the active layer of the above-described trench region having the bent portions of the same shape forms a channel of the thin film transistor during conduction.
  • a pattern of at least an active layer ie, a semiconductor layer
  • a source, a drain, and a gap region between the two is formed, and then is above the active layer pattern.
  • the gap is the trench in this embodiment, which forms a channel of the thin film transistor under the action of an applied electric field.
  • each of the first bent portions includes a first portion 151 and a second portion 152 that are mirror-symmetrically disposed with respect to the first axis of symmetry, and the first portion 151 and the first portion of the at least one first bent portion
  • the two parts 152 are alternately arranged, that is, when there are multiple first bends
  • a plurality of first bent portions are connected in series with each other, and the first portion and the second portion are alternately arranged; the second bent portion includes a third mirror-symmetrical arrangement with respect to the second symmetry axis.
  • the portion 251 and the fourth portion 252, the first axis of symmetry of the first bent portion is parallel to the second axis of symmetry of the second bent portion.
  • the first trench 15 has at least one first bent portion (the first trench 15 is on the left side in FIG. 3 with the sum of the first portion 151 and the second portion 152
  • the second trench 25 has a second bent portion (shown in the form of a sum of the third portion 251 and the fourth portion 252 in FIG. 4) .
  • mirror symmetry means that the corresponding points of the first portion 151 and the second portion 152 in the first groove 15 have an equal spacing with respect to the first axis of symmetry; the third portion of the second groove 25 The corresponding points of the 251 and the fourth portion 252 have an equal spacing with respect to the second axis of symmetry, so that the size and shape of the groove between the source and the drain can be ensured to be uniform, which is also advantageous for practical production.
  • the first symmetry axis and the second symmetry axis of the bent portion in the thin film transistor are both parallel with respect to the gate line.
  • the exposure process in the patterning process is performed by scanning in a direction parallel to the gate line or perpendicular to the gate line, and the thin film transistor structure in FIG. 3 or FIG. 4 is used to ensure the thin film transistor of the GOA region and the pixel region.
  • the photoresist has the same exposure performance when forming a trench region between the source and the drain, thereby ensuring that the subsequently formed trench regions have the same shape, thereby ensuring that the thin film transistors of the GOA region and the pixel region have The same performance.
  • the first source 12 and the first drain 13 are each formed in a fold line form, and each of the first bent portions includes a first portion 151 and a second portion 152, and the first portion 151 and the second portion
  • the portion 152 is composed of intersecting line segments and forms a fold line together;
  • the second source 22 and the second drain 23 form a fold line at least at the end or branch corner, and
  • the second bend portion includes a third portion 251 and a fourth portion 252.
  • the third portion 251 and the fourth portion 252 are composed of two line segments constituting the same folding angle.
  • polyline or “segment” is used to mean that a portion of a structure such as a source, a drain, or a trench of a transistor is formed in the form of a broken line or a line segment.
  • the first source is extremely a U-shaped structure (the portion of the first trench 15 corresponding to the bottom of the U-shaped source may be a straight portion), and the two sides of the U-shaped structure respectively have at least one first chamfer having the same number and the same angle, the first leak
  • the U-shaped structure recess is extremely inserted (ie, one end of the first drain 13 is disposed inside the U-shaped structure of the first source 12 and the other end extends inside the U-shaped structure), and has one side of the U-shaped structure a second folding angle having the same number of first angles and the same angle; a region between the first folding angle and the opposite second folding angle forms a first bending portion; and in the thin film transistor of the display region shown in FIG. 4, the second drain has a convex third angle, the second source has a concave fourth corner at a portion opposite to the third angle, and a region between the third angle and the opposite fourth angle forms Two bent parts.
  • each first chamfer is formed by two adjacent first line segments 1510
  • each second chamfer is formed by two adjacent second line segments 1520, forming a first line segment 1510 of the first chamfer. And a region between the second line segment 1520 and the second line segment 1520 constituting the second angle formed therebetween, the first portion 151, the other first line segment 1510 constituting the first chamfer, and the other portion opposite thereto forming the second chamfer
  • the area between the two line segments 1520 forms a second portion 152;
  • each third chamfer is formed by two adjacent third line segments 2510, each of which is formed by two adjacent fourth line segments 2520 a region between a third line segment 2510 constituting the third chamfer and a fourth line segment 2520 constituting the fourth chamfer formed therebetween forms a third portion 251, a third line segment 2510 constituting the third chamfer and a fourth portion
  • a region between a fourth line segment 2520 of the chamfer forms a fourth portion 252.
  • the shape of the first source 12 and the first drain 13 in the first thin film transistor in the vertical direction is a plurality of V-shaped at an angle
  • a first defined trench 15 forms a plurality of angled V-shapes
  • the first bent portion includes a first drain 13 formed Alternately arranged first portion 151 and second portion 152 on both sides formed by adjacent two broken lines of the first source 12 and adjacent two broken lines of the first drain 13 opposite thereto; in the second thin film transistor
  • the second source 22 and the second drain 23 are similarly designed to have a second trench 26 defined by the second source 22 and the second drain 23 (forming the source and side of the second thin film transistor)
  • the second bent portion includes a third portion 251 and a fourth portion 252 formed between the flanges adjacent to the second drain 23 and the second source 22.
  • the number of the first bent portions in each of the first thin film transistors may be different because the number of the first thin film transistors is large and the size is different (the shape of each of the first thin film transistors depends on In terms of its own size and size of the GOA area, but not limited to odd or even numbers, for example, it can be 3 or 4.
  • the more the bent portion the larger the size of the thin film transistor, and the larger the area occupied.
  • the second thin film transistor has substantially only one second bent portion.
  • the first bending portion and the second bending portion have the same bending angle, of course, if the first portion 151 of the first bending portion is regarded as the second of the adjacent bending portions The portion 152 of the adjacent bent portion is regarded as the first portion 151, and the bending angles of the first bent portion and the second bent portion are set to each other, that is, the first bent portion and the first portion The sum of the bending angles of the two bent portions is equal to 360 degrees.
  • the bending angle of the first bending portion and the second bending portion ranges from 70 degrees to 110 degrees. In order to obtain a more uniform exposure uniformity in two mutually perpendicular directions, it is preferred that the first bending portion and the second bending portion have a bending angle of 90 degrees.
  • the thin film transistor Since the axis of symmetry of the bent portion in the thin film transistor is parallel with respect to the gate line, whether the scanning process of the exposure process is performed in a direction parallel to the gate line or the scanning process of the exposure process is performed in a direction perpendicular to the gate line, It is ensured that the thin film transistor has the same exposure performance for the photoresist when forming a trench region between the source and the drain, thereby ensuring that the subsequently formed trench regions have the same shape, thereby ensuring the same performance.
  • the emphasis is on the bending angles of the first bent portion and the second bent portion being identical, and according to the actual effect of the patterning process, the reasonable bending of the groove region between the source and the drain can be flexibly set. Angle, here is not limited.
  • the first bent portion and the second bent portion have chamfers, that is, the bent portion defined by the first folded corner and the second folded corner of the first bent portion has And chamfering; and the bending region defined by the third corner and the fourth corner of the second bending portion has a chamfer.
  • a gentler angle is formed at the corner portion of the bend region to reduce the requirements for the patterning process.
  • the first bent portion and the second bent portion may also be directly disposed as a pointed corner structure, which is not limited herein.
  • the thin film transistor in the array substrate of the present embodiment has a larger aspect ratio than the thin film transistor of the prior art, and thus has better performance.
  • the width of a single trench between the source and the drain of the thin film transistor is W
  • the length of the trench between the source and the drain is L
  • the direction of W and L is perpendicular to each other.
  • width-to-length ratio W/L can be used to obtain the non-display in this embodiment.
  • the width-to-length ratio of the trench between the source and the drain of the thin film transistor of the region is larger than the width-to-length ratio of the trench between the source and the drain of the thin film transistor of the non-display region in the prior art.
  • the first thin film transistor of the non-display area passes through the source in this embodiment.
  • the increase in the width-to-length ratio W/L of the trench between the drain and the drain improves the on-current Ion of the thin film transistor, so that the characteristics of the thin film transistor are better.
  • the array substrate in this embodiment is applicable to a typical flat panel display device, such as an LCD display device and an OLED display device.
  • each pixel region of the LCD display device includes a second thin film transistor
  • each of the OLED display devices A pixel region includes a set of driving circuits composed of a plurality of second thin film transistors.
  • the exposure of the source and the drain of the thin film transistor is formed by a patterning process.
  • the step whether the scanning exposure is performed in the X direction or the Y direction, the GOA area and the pixel can be ensured.
  • the thin film transistor of the region has the same exposure effect for the photoresist when forming the trench region between the source and the drain, in other words, the light of the source/drain electrode is formed in the thin film transistor of the non-display region and the display region.
  • the exposure of the engraved glue is more uniform, so that the problem of residual photoresist between the source and the drain due to poor exposure can be avoided; correspondingly, the subsequent etching includes source and drain.
  • the pattern of the pole is formed in the process of forming the trench region between the source and the drain, and the etching of the trench between the source and the drain due to the residual of the photoresist is avoided, thereby ensuring The performance of thin film transistors improves the quality of array substrate products.
  • This embodiment provides a display device including the array substrate in Embodiment 1.
  • the display device can be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device employs the above array substrate, it has better display quality.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板和显示装置。该阵列基板，划分为显示区和非显示区，非显示区设置有第一薄膜晶体管，显示区设置有第二薄膜晶体管，第一薄膜晶体管中的第一有源层(14)的对应于第一源极(12)与第一漏极(13)之间的区域形成第一沟槽(15)，第二薄膜晶体管中的第二有源层(24)的对应于第二源极(22)与第二漏极(23)之间的区域形成第二沟槽(25)，第一沟槽(15)具有至少一个第一弯折部，第二沟槽(25)具有第二弯折部，第一弯折部和第二弯折部的弯折角度相同或者互为组角。该阵列基板中非显示区和显示区薄膜晶体管的沟槽具有至少局部形状相同的弯折部，因此具有相同的介于源极与漏极之间的沟槽区域的曝光性能，能够提高显示性能。

Description

阵列基板和显示装置 技术领域
本发明属于显示技术领域，具体涉及一种阵列基板和显示装置。
背景技术
在平板显示装置中，为了对各像素进行控制，通常在阵列基板上设置呈矩阵排列的薄膜晶体管(Thin Film Transistor，简称TFT)和对薄膜晶体管进行驱动的驱动芯片。通常情况下，薄膜晶体管通过构图工艺形成在显示区，驱动芯片绑定(bonding)在非显示区。
随着显示技术的发展，出现了栅极驱动集成GOA(Gate On Array)技术，即，将阵列基板中的栅极驱动电路集成在基板上，形成对像素的扫描驱动。其中的栅极驱动电路由薄膜晶体管组成，可以与显示区的薄膜晶体管一样采用构图工艺形成。相比传统的对驱动芯片的绑定工艺，省掉了栅极驱动集成芯片部分，不仅节省成本，同时由于可以省去栅线方向的绑定工艺，还有利于产能提升，因此广泛应用于平板显示装置的非显示区薄膜晶体管中。
薄膜晶体管通常包括栅极G、源极S、漏极D和半导体层。目前非显示区的GOA薄膜晶体管的结构和显示区的像素薄膜晶体管的结构不同：如图1所示的GOA薄膜晶体管中的介于源极与漏极之间的沟槽区通常为U型结构，而如图2所示的像素薄膜晶体管中的介于源极与漏极之间的沟槽区为直角结构。相对而言，GOA薄膜晶体管的介于源极与漏极之间的沟槽结构更节省空间，适合于非显示区的有限空间。
但是，在通过构图工艺形成阵列基板时，曝光步骤中对整张基板采用同一个曝光方向(根据薄膜晶体管在基板上的排版不同， 可以为X方向或Y方向)，由于GOA薄膜晶体管的介于源极与漏极之间的沟槽形状和像素薄膜晶体管的介于源极与漏极之间的沟槽形状不一致，因此容易使得GOA区的曝光与像素区的曝光之间存在差异(比如不均匀，沟槽中的一些区域曝光好而另一些区域曝光差)；在曝光步骤之后的显影步骤中，会导致介于源极与漏极之间的沟槽区域因曝光差而出现光刻胶残留；进而，导致GOA区或像素区中介于源极与漏极之间的沟槽区域因光刻胶残留而出现源极和漏极的金属薄膜刻蚀不干净。而GOA区和像素区中任一个出现曝光不均匀均会导致薄膜晶体管的特性受影响，影响产品的显示质量。
可见，规范非显示区和显示区薄膜晶体管的结构，保证构图工艺中上述两个区域中不同结构的薄膜晶体管中具有相同的介于源极与漏极之间的沟槽曝光性能成为目前亟待解决的技术问题。
发明内容
本发明所要解决的技术问题是针对现有技术中存在的上述不足，提供一种阵列基板和显示装置，该阵列基板中非显示区和显示区薄膜晶体管具有至少局部形状相同的弯折部，因此具有相同的介于源极与漏极之间的沟槽曝光性能，显示质量更好。
解决本发明技术问题所采用的技术方案是该阵列基板，划分为显示区和非显示区，所述非显示区设置有第一薄膜晶体管，所述显示区设置有第二薄膜晶体管，所述第一薄膜晶体管中的第一有源层的对应于第一源极与第一漏极之间的区域形成第一沟槽，所述第二薄膜晶体管中的第二有源层的对应于第二源极与第二漏极之间的区域形成第二沟槽，
所述第一沟槽具有至少一个第一弯折部，所述第二沟槽具有第二弯折部，所述第一弯折部和所述第二弯折部的弯折角度相同，或者，所述第一弯折部和所述第二弯折部的弯折角度互为组角(二者角度之和等于360度)。
优选的是，每一所述第一弯折部包括关于第一对称轴镜像对 称设置的第一部和第二部，至少一个所述第一弯折部的所述第一部和所述第二部交替排列；所述第二弯折部包括关于第二对称轴镜像对称设置的第三部和第四部，所述第一对称轴与所述第二对称轴平行。所述第一对称轴与所述第二对称轴可以与第二薄膜晶体管的栅极平行。
优选的是，所述第一源极为U型结构、且所述U型结构的两侧边分别具有数量相同、形状相同的至少一个第一折角，所述第一漏极为插入所述U型结构凹部、且具有与所述U型结构的一侧边的所述第一折角数量相同、形状相同的第二折角，所述第一折角与相对的所述第二折角之间的区域形成所述第一弯折部；
所述第二漏极具有外凸的第三折角，所述第二源极在与所述第三折角相对的部分具有与所述第三折角相匹配形状的内凹的第四折角，所述第三折角与相对的所述第四折角之间的区域形成所述第二弯折部。
优选的是，每一所述第一折角由相交的两条第一线段构成，每一所述第二折角由相交的两条第二线段构成，构成所述第一折角的一条所述第一线段和与其相对的、构成所述第二折角的一条所述第二线段之间的区域形成所述第一部，构成所述第一折角的另一条所述第一线段和与其相对的、构成所述第二折角的另一条所述第二线段之间的区域形成所述第二部；
每一所述第三折角由相交的两条第三线段构成，每一所述第四折角由相交的两条第四线段构成，构成所述第三折角的一条所述第三线段和与其相对的、构成所述第四折角的一条所述第四线段之间的区域形成所述第三部，构成所述第三折角的一条所述第三线段和构成所述第四折角的一条所述第四线段之间的区域形成所述第四部。
优选的是，所述第一弯折部具有倒角；且，所述第二弯折部具有倒角。
优选的是，所述第一弯折部和所述第二弯折部的弯折角度范围为70度-110度。
优选的是，所述第一弯折部和所述第二弯折部的弯折角度均为90度。
优选的是，所述第一源极、所述第一漏极、所述第二源极和所述第二漏极采用相同的材料、且在同一构图工艺中形成。
一种显示装置，包括上述的阵列基板。
本发明的有益效果是：该阵列基板中，由于非显示区和显示区的薄膜晶体管中的沟槽具有至少局部形状相同的弯折部，从而，在采用构图工艺形成源漏电极时对于光刻胶的曝光会更均匀，从而可以避免出现由于曝光不佳引起的介于源极与漏极之间的沟槽光刻胶残留的问题；相应的，在后续刻蚀工艺形成包括源极和漏极的图形以形成介于源极与漏极之间的沟槽区域的工艺中，避免因光刻胶残留而造成的介于源极与漏极之间的沟槽刻蚀不良，保证薄膜晶体管的性能，提高阵列基板产品的质量。
附图说明
图1为现有技术中GOA区薄膜晶体管结构示意图；
图2为现有技术中像素区薄膜晶体管的结构示意图；
图3为本发明实施例1中GOA区薄膜晶体管的结构示意图；
图4为本发明实施例1中像素区薄膜晶体管的结构示意图；
图5为图4的局部放大图；
图6为图3中标识了沟槽长宽的示意图；
图7为图4中标识了沟槽长宽的示意图；
图中：
11－第一栅极；12－第一源极；13－第一漏极；14－第一有源层；15－第一沟槽；151－第一部；1510－第一线段；152－第二部；1520－第二线段；
21－第二栅极；22－第二源极；23－第二漏极；24－第二有源层；25－第二沟槽；251－第三部；2510－第三线段；252－第四部；2520－第四线段；26－像素电极；27－栅线；28－数据线。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明阵列基板和显示装置作进一步详细描述。
实施例1：
本实施例提供一种阵列基板，该阵列基板通过将非显示区和显示区的薄膜晶体管的介于源极与漏极之间的沟槽设置为至少局部相同的形状，大大减轻了构图工艺中曝光步骤造成的曝光差异，避免出现曝光不均匀的情况，保证薄膜晶体管的性能，提高了阵列基板的良率和性能。
本发明的构思不限于实施例中所示例的具体形式，例如，上述非显示区和显示区的薄膜晶体管的介于源极与漏极之间的沟槽可以具有除了折线形式以外的任何其他形状，只要非显示区中的(第一)沟槽与显示区中的(第二)沟槽具有几何相似的形状，能够使得具有相同或相近的曝光性能即可。
如图3-图5所示，该阵列基板划分为图4所示的显示区和图3所示的非显示区，非显示区设置有第一薄膜晶体管，显示区设置有第二薄膜晶体管，第一薄膜晶体管中的第一有源层14的对应于第一源极12与第一漏极13之间的区域形成第一沟槽15，第二薄膜晶体管中的第二有源层24的对应于第二源极22与第二漏极23之间的区域形成第二沟槽25，第一沟槽15和第二沟槽25具有形状相同的弯折部分。在本发明构思中，所述显示区可以包括各个像素区，所述非显示区可以包括GOA区。
这里，第一薄膜晶体管设置在非显示区，具体是设置在GOA区，即集成在用于驱动栅线扫描的区域；第二薄膜晶体管设置在显示区，具体是设置在对应着各个显示像素的区域，因此显示区也可以称为像素区。当然，第一薄膜晶体管中还包括第一栅极11、第二薄膜晶体管中还包括第二栅极21，这里不再详述。在第二薄膜晶体管中，第二栅极21与栅线27电连接，第二源极22与数据 线28电连接，第二漏极23与像素电极26电连接，以在薄膜晶体管的控制下实现像素显示。
本实施例的阵列基板中，第一薄膜晶体管的第一源极12、第一漏极13和第二薄膜晶体管的第二源极22、第二漏极23采用相同的材料、且在同一构图工艺中形成。相应的，第一薄膜晶体管的第一有源层14和第二薄膜晶体管的第二有源层24采用相同的材料、且在同一构图工艺中形成。其中，构图工艺可只包括光刻工艺，或，包括光刻工艺以及刻蚀步骤。光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。
沟道对于薄膜晶体管而言是非常重要的结构，薄膜晶体管包括与源极和漏极均分别连接的一层半导体层，形成在分离的源极和漏极之间的部分半导体层在向栅极施加开启电压的条件下，在电场作用下引起沿长度方向的导电，此时介于分离的源极和漏极之间的半导体层部分即形成沟道。在本实施例中，上述具有形状相同的弯折部分的沟槽区域的有源层形成了薄膜晶体管在导通过程中的沟道。
具体的，薄膜晶体管在形成过程中，通常是先形成至少对应着源极、漏极和二者之间的间隙区域的有源层(即半导体层)的图形，然后在有源层图形的上方形成源极和漏极的金属薄膜，在该源极和漏极的金属薄膜的上方形成光刻胶层，然后通过曝光工艺对光刻胶层进行曝光，通过显影工艺仅保留对应于源极和漏极的区域的光刻胶，而去除对应于源极和漏极之间的间隙的光刻胶；进而通过刻蚀工艺刻蚀去除未被光刻胶覆盖的源极和漏极的金属薄膜，从而形成源极和漏极的图形以及二者之间的间隙，这里的间隙即本实施例中的沟槽，其在外加电场的作用下形成薄膜晶体管的沟道。
在本实施例的阵列基板中，每一第一弯折部包括关于第一对称轴镜像对称设置的第一部151和第二部152，至少一个第一弯折部的第一部151和第二部152交替排列，即，当存在多个第一弯 折部时，一种较优的实施方式是多个第一弯折部相互串联，并且第一部和第二部交替排列；第二弯折部包括关于第二对称轴镜像对称设置的第三部251和第四部252，第一弯折部的第一对称轴与第二弯折部的第二对称轴平行。如图3所示的第一薄膜晶体管中，第一沟槽15具有至少一个第一弯折部(第一沟槽15在图3中的左侧以第一部151和第二部152之和的形式示出)；如图4所示的第二薄膜晶体管中，第二沟槽25具有第二弯折部(图4中以第三部251和第四部252之和的形式示出)。在本文中，术语“镜像对称”即，第一沟槽15中的第一部151和第二部152的对应点相对第一对称轴具有相等的间距；第二沟槽25中的第三部251和第四部252的对应点相对第二对称轴具有相等的间距，从而可以保证介于源极与漏极之间的沟槽的大小、形状均匀，也利于实际生产运用。
优选的是，如图3和图4所示，其中的薄膜晶体管中的弯折部的第一对称轴和第二对称轴均相对于栅线平行。通常情况下，构图工艺中的曝光工艺采用平行于栅线的方向或垂直于栅线的方向进行扫描，采用图3或图4中的薄膜晶体管结构，有利于保证GOA区和像素区的薄膜晶体管在形成介于源极与漏极之间的沟槽区域时对于光刻胶具有相同的曝光性能，从而保证后续形成的沟槽区域具有相同的形状，从而保证GOA区和像素区的薄膜晶体管具有相同的性能。
本实施例的阵列基板中，第一源极12和第一漏极13均以折线形式形成，每一第一弯折部包括第一部151和第二部152，第一部151和第二部152由相交的线段构成并且一起形成折线；第二源极22和第二漏极23至少在端部或分支折角处形成折线，第二弯折部包括第三部251和第四部252，第三部251和第四部252由构成同一折角的两条线段构成。在本文中，“折线”或“线段”用于表示晶体管的源极、漏极或沟槽等结构中的形成为折线形式或线段形式的一部分。
具体的，图3所示的非显示区的薄膜晶体管中，第一源极为 U型结构(在对应着U型源极底部的第一沟槽15部分可以为直线部)、且U型结构的两侧边分别具有数量相同、角度相同的至少一个第一折角，第一漏极为插入U型结构凹部(即第一漏极13一端设置于第一源极12的U型结构的内侧、另一端延伸出U型结构的内侧)、且具有与U型结构的一侧边的第一折角数量相同、角度相同的第二折角，第一折角与相对的第二折角之间的区域形成第一弯折部；图4所示的显示区的薄膜晶体管中，第二漏极具有外凸的第三折角，第二源极在与第三折角相对的部分具有与第三折角相匹配形状的内凹的第四折角，第三折角与相对的第四折角之间的区域形成第二弯折部。
参考图6，每一第一折角由相邻的两条第一线段1510构成，每一第二折角由相邻的两条第二线段1520构成，构成第一折角的一条第一线段1510和与其相对的、构成第二折角的一条第二线段1520之间的区域形成第一部151，构成第一折角的另一条第一线段1510和与其相对的、构成第二折角的另一条第二线段1520之间的区域形成第二部152；参考图7，每一第三折角由相邻的两条第三线段2510构成，每一第四折角由相邻的两条第四线段2520构成，构成第三折角的一条第三线段2510和与其相对的、构成第四折角的一条第四线段2520之间的区域形成第三部251，构成第三折角的一条第三线段2510和构成第四折角的一条第四线段2520之间的区域形成第四部252。
简言之，第一薄膜晶体管中的第一源极12和第一漏极13在竖直方向上的形状为具有多个成一定角度的V形，由第一源极12和第一漏极13限定的第一沟槽15(形成第一薄膜晶体管的介于源极与漏极之间的沟槽)形成多个一定角度的V形，第一弯折部包括形成在第一漏极13两侧的、由第一源极12的相邻两折线和与之相对的第一漏极13的相邻两折线形成的交替排列的第一部151和第二部152；第二薄膜晶体管中的第二源极22和第二漏极23也采用类似的设计，使由第二源极22和第二漏极23限定的第二沟槽26(形成第二薄膜晶体管的介于源极与漏极之间的沟槽)也 形成一定角度的V形，第二弯折部包括形成在第二漏极23与第二源极22相邻的折边之间的第三部251和第四部252。
这里，非显示区因为第一薄膜晶体管的数量较多且尺寸大小不一，因此每个第一薄膜晶体管中的第一弯折部的数量可能不一样(每个第一薄膜晶体管的形状都取决于自身的尺寸大小和GOA区域大小)，但不限奇数或偶数，例如可以为3个或4个；通常情况下，弯折部越多，薄膜晶体管的尺寸越大，所占面积也越大，在像素区，受限于像素区的区域大小和开口率限制，第二薄膜晶体管基本只有一个第二弯折部。
在图3-图5中，第一弯折部和第二弯折部的弯折角度相同，当然，如果将第一弯折部中的第一部151视为相邻弯折部的第二部152，将相邻弯折部的第二部152视为第一部151，则第一弯折部和第二弯折部的弯折角度互为组角，即第一弯折部和第二弯折部的弯折角度相加之和等于360度。
其中，第一弯折部和第二弯折部的弯折角度范围为70度-110度。为了获得更一致的、在两个互相垂直的两个方向上的曝光一致性，优选第一弯折部和第二弯折部的弯折角度均为90度。由于薄膜晶体管中的弯折部的对称轴相对于栅线平行，因此不管是沿平行于栅线的方向进行曝光工艺的扫描，还是沿垂直于栅线的方向进行曝光工艺的扫描，此时均能保证薄膜晶体管在形成介于源极与漏极之间的沟槽区域时对于光刻胶具有相同的曝光性能，从而保证后续形成的沟槽区域具有相同的形状，从而保证相同的性能。这里，侧重在于第一弯折部和第二弯折部的弯折角度一致，而根据构图工艺的实际效果，可以灵活设置合理的介于源极与漏极之间的沟槽区域的弯折角度，这里不做限定。
通常情况下，图3和图4的薄膜晶体管中，第一弯折部和第二弯折部具有倒角，即第一弯折部的由第一折角和第二折角限定的弯折区域具有倒角；且，第二弯折部的由第三折角和第四折角限定的弯折区域具有倒角。优选的，在所述弯折区域的折角部分形成一个较缓和的角度，以降低对构图工艺的要求。当然，在工 艺条件允许的条件下，第一弯折部和第二弯折部也可以直接设置为尖角结构，这里不做限定。
本实施例阵列基板中的薄膜晶体管，相对现有技术中的薄膜晶体管的宽长比更大，因此性能更好。在图1中，薄膜晶体管的单个介于源极与漏极之间的沟槽的宽度为W，介于源极与漏极之间的沟槽长度为L，W与L的所在方向相互垂直；参考图6，图3中的第一薄膜晶体管介于源极与漏极之间的单边沟槽的宽度为|W1+W2+W3+W4|(即在竖直方向上的折线总长度)，其中W<|W1+W2+W3+W4|，介于源极与漏极之间的沟槽长度为L1(即构成弯折部的平行线之间的垂直距离)；同理，参考图7，图4中的第二薄膜晶体管介于源极与漏极之间的沟槽的宽度为|W5+W6|(即在竖直方向上的折线总长度)，其中W<|W5+W6|，介于源极与漏极之间的沟槽长度为L2(即构成弯折部的平行线之间的垂直距离)，由宽长比W/L可以得出本实施例中非显示区的薄膜晶体管的介于源极与漏极之间的沟槽的宽长比相对现有技术中非显示区的薄膜晶体管的介于源极与漏极之间的沟槽宽长比要大，而随着介于源极与漏极之间的沟槽宽长比的增大，薄膜晶体管的阈值电压Vth会减小，漏电流Id增大，导通电流Ion会增大，因此本实施例中非显示区的第一薄膜晶体管通过介于源极与漏极之间的沟槽的宽长比W/L的增大，提高了薄膜晶体管的导通电流Ion，使得薄膜晶体管的特性更好。
本实施例中的阵列基板，适用于典型的平板显示装置，例如LCD显示装置和OLED显示装置，通常情况下，LCD显示装置的每一像素区包括一个第二薄膜晶体管，而OLED显示装置的每一像素区包括由多个第二薄膜晶体管组成的一组驱动电路。而在非显示区的GOA区，二者均具有多个第一薄膜晶体管。
基于上述结构，该阵列基板中，由于非显示区和显示区的薄膜晶体管中的沟槽具有至少局部形状相同的弯折部，从而，在采用构图工艺形成薄膜晶体管的源极和漏极的曝光步骤中，不管是沿X方向还是沿Y方向进行扫描曝光，均能保证GOA区和像素 区的薄膜晶体管在形成介于源极与漏极之间的沟槽区域时对于光刻胶具有相同的曝光效果，换言之，即使得非显示区和显示区的薄膜晶体管中形成源漏电极的光刻胶的曝光会更均匀，从而可以避免出现由于曝光不佳引起的介于源极与漏极之间的沟槽光刻胶残留的问题；相应的，在后续刻蚀形成包括源极和漏极的图形以形成介于源极与漏极之间的沟槽区域的工艺中，由于避免因光刻胶残留而造成的介于源极与漏极之间的沟槽刻蚀不良，能够保证薄膜晶体管的性能，提高阵列基板产品的质量。
实施例2：
本实施例提供一种显示装置，包括实施例1中的阵列基板。
该显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
该显示装置由于采用上述的阵列基板，因此具有较好的显示品质。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (9)

  1. 一种阵列基板，划分为显示区和非显示区，所述非显示区设置有第一薄膜晶体管，所述显示区设置有第二薄膜晶体管，所述第一薄膜晶体管中的第一有源层的对应于第一源极与第一漏极之间的区域形成第一沟槽，所述第二薄膜晶体管中的第二有源层的对应于第二源极与第二漏极之间的区域形成第二沟槽，其特征在于，
    所述第一沟槽具有至少一个第一弯折部，所述第二沟槽具有第二弯折部，所述第一弯折部和所述第二弯折部的弯折角度相同或者互为组角。
  2. 根据权利要求1所述的阵列基板，其特征在于，每一所述第一弯折部包括关于第一对称轴镜像对称设置的第一部和第二部；所述第二弯折部包括关于第二对称轴镜像对称设置的第三部和第四部，所述第一对称轴与所述第二对称轴平行。
  3. 根据权利要求2所述的阵列基板，其特征在于，所述第一源极为U型结构、且所述U型结构的两侧边分别具有数量相同、形状相同的至少一个第一折角，所述第一漏极为插入所述U型结构凹部、且具有与所述U型结构的一侧边的所述第一折角数量相同、形状相同的第二折角，所述第一折角与相对的所述第二折角之间的区域形成所述第一弯折部；
    所述第二漏极具有外凸的第三折角，所述第二源极在与所述第三折角相对的部分具有与所述第三折角相匹配形状的内凹的第四折角，所述第三折角与相对的所述第四折角之间的区域形成所述第二弯折部。
  4. 根据权利要求3所述的阵列基板，其特征在于，每一所述第一折角由相交的两条第一线段构成，每一所述第二折角由相交 的两条第二线段构成，构成所述第一折角的一条所述第一线段和与其相对的、构成所述第二折角的一条所述第二线段之间的区域形成所述第一部，构成所述第一折角的另一条所述第一线段和与其相对的、构成所述第二折角的另一条所述第二线段之间的区域形成所述第二部；
    每一所述第三折角由相交的两条第三线段构成，每一所述第四折角由相交的两条第四线段构成，构成所述第三折角的一条所述第三线段和与其相对的、构成所述第四折角的一条所述第四线段之间的区域形成所述第三部，构成所述第三折角的一条所述第三线段和构成所述第四折角的一条所述第四线段之间的区域形成所述第四部。
  5. 根据权利要求3-4任一项所述的阵列基板，其特征在于，所述第一弯折部具有倒角；且，所述第二弯折部具有倒角。
  6. 根据权利要求1-4任一项所述的阵列基板，其特征在于，所述第一弯折部和所述第二弯折部的弯折角度范围为70度-110度。
  7. 根据权利要求6所述的阵列基板，其特征在于，所述第一弯折部和所述第二弯折部的弯折角度均为90度。
  8. 根据权利要求1-4任一项所述的阵列基板，其特征在于，所述第一源极、所述第一漏极、所述第二源极和所述第二漏极采用相同的材料、且在同一构图工艺中形成。
  9. 一种显示装置，其特征在于，包括权利要求1-8任一项所述的阵列基板。
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