WO2016197404A1 - Tft基板结构的制作方法及tft基板结构 - Google Patents

Tft基板结构的制作方法及tft基板结构 Download PDF

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WO2016197404A1
WO2016197404A1 PCT/CN2015/082163 CN2015082163W WO2016197404A1 WO 2016197404 A1 WO2016197404 A1 WO 2016197404A1 CN 2015082163 W CN2015082163 W CN 2015082163W WO 2016197404 A1 WO2016197404 A1 WO 2016197404A1
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gate
tft substrate
type
polysilicon layer
substrate structure
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PCT/CN2015/082163
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English (en)
French (fr)
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郭文帅
明星
申智渊
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武汉华星光电技术有限公司
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Priority to US14/778,606 priority Critical patent/US20170170202A1/en
Publication of WO2016197404A1 publication Critical patent/WO2016197404A1/zh

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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate structure and a TFT substrate structure.
  • Liquid crystal display has many advantages such as thin body, power saving, no radiation, etc., and is widely used, such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptops. Screen, etc.
  • a liquid crystal display device includes a housing, a liquid crystal panel disposed in the housing, and a backlight module disposed in the housing.
  • the structure of the liquid crystal panel is mainly composed of a Thin Film Transistor Array Substrate (TFT Array Substrate), a color filter substrate (Color Filter, CF), and a liquid crystal layer disposed between the two substrates (Liquid).
  • the crystal layer is constructed by controlling the rotation of the liquid crystal molecules of the liquid crystal layer by applying a driving voltage on the two glass substrates, and refracting the light of the backlight module to produce a picture.
  • hot carriers are injected into the oxide layer across the insulating layer, accumulating, changing the threshold voltage, affecting the life of the device;
  • the depletion region near the drain collides with the crystal lattice to generate a new electron-hole pair.
  • MOS metal oxide semiconductor
  • the electrons generated by the collision form an additional leakage current.
  • the holes are collected by the substrate to form a substrate current such that the total current becomes the sum of the saturated leakage current and the substrate current.
  • the hot carrier effect is one of the fundamental factors limiting the maximum operating voltage of the device.
  • FIG. 1 is a schematic diagram of a method for fabricating a conventional TFT substrate structure.
  • the TFT substrate structure includes a substrate 100, a buffer layer 200 disposed on the substrate 100, and a polysilicon layer 300 disposed on the buffer layer 200.
  • the method uses the photoresist layer 600 as a mask to perform ion implantation on the polysilicon layer 300.
  • Both sides of the pole, in the polysilicon layer 300 A symmetric two n-type lightly doped regions (LDD) 320 are formed between the channel region 330 and the n-type heavily doped regions 310 on both sides to disperse a strong electric field near the electrodes and reduce the generation of hot carriers.
  • LDD lightly doped regions
  • An object of the present invention is to provide a method for fabricating a TFT substrate structure, which can simultaneously form an n-type heavily doped region and an n-type lightly doped region in a polysilicon layer to increase the resistance value, disperse a strong electric field near the electrode, and avoid localized
  • the hot carrier effect that occurs in the presence of a strong electric field affects device characteristics.
  • the present invention provides a method for fabricating a TFT substrate structure, including the following steps:
  • Step 1 providing a substrate, depositing a buffer layer on the substrate;
  • Step 2 depositing a polysilicon layer on the buffer layer, and depositing a gate insulating layer on the polysilicon layer;
  • Step 3 depositing a metal layer on the gate insulating layer, and patterning the metal layer to form a gate corresponding to a middle portion of the polysilicon layer;
  • the gate is a trapezoidal structure, and includes an upper bottom surface, a lower bottom surface, and a first inclined surface and a second inclined surface connected between the upper bottom surface and the lower bottom surface; the upper bottom surface has an area smaller than the lower bottom surface area;
  • Step 4 using the gate as a photomask, performing an n-type doping on the polysilicon layer by an ion implantation process, and forming an n-type heavily doped region in a region not covered by the gate on both sides of the polysilicon layer.
  • a region of the polysilicon layer corresponding to the first slope and the second slope of the gate forming a first n-type lightly doped region and a second n-type lightly doped region, corresponding to the gate in a middle portion of the polysilicon layer
  • the region of the upper bottom surface of the pole forms an undoped channel region.
  • the thickness of the gate is the thickness of the gate.
  • the step 3 forms a first slope and a second slope by dry etching or wet etching.
  • An angle formed between the first inclined surface and the lower bottom surface is 10° to 60°; an angle formed between the second inclined surface and the lower bottom surface is 10° to 60°.
  • the n-type ion concentration in the first and second n-type lightly doped regions is linearly decreasing from the outer side to the inner side.
  • the material of the buffer layer and the gate insulating layer is silicon oxide, silicon nitride, or a combination of the two; the material of the gate is a stack combination of one or more of molybdenum, titanium, aluminum, and copper. .
  • the present invention also provides a TFT substrate structure including a substrate, a buffer layer disposed on the substrate, a polysilicon layer disposed on the buffer layer, a gate insulating layer disposed on the polysilicon layer, and a a gate on the gate insulating layer and corresponding to a middle portion of the polysilicon layer;
  • the gate is a trapezoidal structure, and includes an upper bottom surface, a lower bottom surface, and a first inclined surface and a second inclined surface connected between the upper bottom surface and the lower bottom surface; the upper bottom surface has an area smaller than the lower bottom surface area;
  • the polysilicon layer includes an undoped channel region located at a middle portion and corresponding to the upper bottom surface, and a first n-type light located on both sides of the channel region and respectively corresponding to the first slope and the second slope a doped region, a second n-type lightly doped region, and two n-type heavily doped regions respectively located outside the first n-type lightly doped region and the second n-type lightly doped region.
  • the thickness of the gate is An angle formed between the first inclined surface and the lower bottom surface is 10° to 60°; an angle formed between the second inclined surface and the lower bottom surface is 10° to 60°.
  • the n-type ion concentration in the first and second n-type lightly doped regions is linearly decreasing from the outer side to the inner side.
  • the material of the buffer layer and the gate insulating layer is silicon oxide, silicon nitride, or a combination of the two; the material of the gate is a stack combination of one or more of molybdenum, titanium, aluminum, and copper. .
  • the present invention also provides a TFT substrate structure including a substrate, a buffer layer disposed on the substrate, a polysilicon layer disposed on the buffer layer, a gate insulating layer disposed on the polysilicon layer, and a a gate on the gate insulating layer and corresponding to a middle portion of the polysilicon layer;
  • the gate is a trapezoidal structure, and includes an upper bottom surface, a lower bottom surface, and a first inclined surface and a second inclined surface connected between the upper bottom surface and the lower bottom surface; the upper bottom surface has an area smaller than the lower bottom surface area;
  • the polysilicon layer includes an undoped channel region located at a middle portion and corresponding to the upper bottom surface, and a first n-type light located on both sides of the channel region and respectively corresponding to the first slope and the second slope a doped region, a second n-type lightly doped region, and two n-type heavily doped regions respectively located outside the first n-type lightly doped region and the second n-type lightly doped region;
  • the thickness of the gate is The angle formed between the first inclined surface and the lower bottom surface is 10 ° ⁇ 60 °; the angle formed between the second inclined surface and the lower bottom surface is 10 ° ⁇ 60 °;
  • n-type ion concentration in the first and second n-type lightly doped regions is linearly decreasing from the outer side to the inner side;
  • the material of the buffer layer and the gate insulating layer is silicon oxide, silicon nitride, or a combination of the two; the material of the gate is one or more of molybdenum, titanium, aluminum, and copper. Stack combination.
  • the invention has the beneficial effects of the TFT substrate structure of the present invention.
  • the etching parameters are adjusted to form a slope on both sides of the gate, and the gate is used as a mask to ion-implant the polysilicon layer.
  • an n-type heavily doped region and an n-type lightly doped region are formed in the polysilicon layer, which increases the resistance value, disperses the strong electric field near the electrode, and avoids the hot carrier effect on the device due to the existence of a local strong electric field.
  • the effect of the characteristics and other effects of the asymmetry of the lightly doped region on the device saves the process of separately forming the n-type lightly doped region, improves the generation efficiency, and reduces the production cost.
  • the polysilicon layer includes an n-type heavily doped region on both sides and an n-type lightly doped region between the channel region of the polysilicon layer and the n-type heavily doped region, thereby avoiding local strong
  • the generation of an electric field eliminates the effect of hot carriers on device characteristics.
  • FIG. 1 is a schematic view showing a manufacturing method of a conventional TFT substrate structure
  • FIG. 2 is a flow chart showing a method of fabricating a TFT substrate structure of the present invention
  • FIG. 3 is a schematic view showing the first step of the method for fabricating the TFT substrate structure of the present invention.
  • FIG. 4 is a schematic view showing a step 2 of a method for fabricating a TFT substrate structure according to the present invention
  • step 3 is a schematic diagram of step 3 of a method for fabricating a TFT substrate structure according to the present invention.
  • FIG. 6 is a schematic diagram of step 4 of a method for fabricating a TFT substrate structure according to the present invention.
  • Fig. 7 is a schematic cross-sectional view showing the structure of a TFT substrate of the present invention.
  • the present invention first provides a method for fabricating a TFT substrate structure, including the following steps:
  • Step 1 As shown in FIG. 3, a substrate 1 is provided on which a buffer layer 2 is deposited.
  • the substrate 1 may be a glass substrate or a plastic substrate
  • the material of the buffer layer 2 may be silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.
  • Step 2 depositing a polysilicon (Poly-Si) layer 3 on the buffer layer 2, And a gate insulating layer 4 is deposited on the polysilicon layer 3.
  • a polysilicon (Poly-Si) layer 3 depositing a polysilicon (Poly-Si) layer 3 on the buffer layer 2
  • a gate insulating layer 4 is deposited on the polysilicon layer 3.
  • the material of the gate insulating layer 4 may be silicon oxide, silicon nitride, or a combination of the two.
  • Step 3 As shown in FIG. 5, a metal layer is deposited on the gate insulating layer 4, and the metal layer is patterned to form a gate 5 corresponding to a middle portion of the polysilicon layer 3.
  • the gate 5 is a trapezoidal structure, and includes an upper bottom surface 51, a lower bottom surface 52, and a first inclined surface 53 and a second inclined surface 54 connected between the upper bottom surface 51 and the lower bottom surface 52.
  • the area of 51 is smaller than the area of the lower bottom surface 52.
  • an angle formed between the first inclined surface 53 and the lower bottom surface 52 is 10° to 60°; an angle formed between the second inclined surface 54 and the lower bottom surface 52 is 10° ⁇ 60°.
  • the angle formed by the first inclined surface 53 and the second inclined surface 54 and the lower bottom surface 52 is the same.
  • the material of the gate 5 may be a stack combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • first inclined surface 53 and the second inclined surface 54 are formed by dry etching (Dry Etch) or wet etching (Wet Etch), and the first inclined surface 53 and the second are adjusted by adjusting parameters of the etching process.
  • the thickness of the gate 5 is the thickness of the gate 5
  • Step 4 as shown in FIG. 6, using the gate 5 as a photomask, the polysilicon layer 3 is doped n-type by an ion implantation process, and the polysilicon layer 3 is not covered by the gate 5 on both sides.
  • the two n-type lightly doped regions 33 form an undoped channel region 34 in a region of the polysilicon layer 3 corresponding to the upper bottom surface 51 of the gate electrode 5.
  • an n-type heavily doped region is formed in a region not covered by the gate 5. 31. Since the thickness of the gate 5 is located at the first slope 53 and the second slope 54, the n-type ions can pass through the gate 5, and the gate 5 is on the polysilicon layer 3. A region covered by a slope 53 and a second slope 54 forms first and second n-type lightly doped regions 32, 33 having a linear distribution of n-type ion concentrations. The first and second n-type lightly doped regions 32, 33 increase the resistance value, disperse the strong electric field near the electrode, and avoid the hot carrier effect caused by the local strong electric field on the device characteristics. influences.
  • the thickness of the gate 5 between the first inclined surface 53 and the lower bottom surface 52 increases linearly from the outer side to the inner side, the difficulty of n-type ion implantation is also performed when performing n-type doping.
  • the outward inward is gradually increased, so that the n-type ion concentration in the finally obtained first n-type lightly doped region 32 is linearly decreasing from the outer side to the inner side.
  • the thickness of the gate 5 between the second slope 54 and the lower surface 52 increases linearly from the outside to the inside, the difficulty of the n-type ion implantation is gradually increased from the outside to the inside when performing n-type doping. Therefore, the n-type ion concentration in the finally obtained second n-type lightly doped region 33 is linearly decreasing from the outer side to the inner side.
  • the n-type ion concentration C n+ in the n-type heavily doped region 31 obtained in the step 4 ranges from 10 14 to 10 15 ions/cm 3 ; the first n-type lightly doped region 32, The n-type ion concentration C n- in the two n-type lightly doped regions 33 ranges from C n+ >C n- >0.
  • the parameters of the etching process are adjusted to form a slope on both sides of the gate, and the gate is used as a mask to ion-implant the polysilicon layer through a process simultaneously in the polysilicon layer.
  • Forming an n-type heavily doped region and an n-type lightly doped region with a linear ion concentration increases the resistance, disperses the strong electric field near the electrode, and avoids the hot carrier effect on the device due to the presence of a local strong electric field.
  • the effect of the characteristics and other effects of the asymmetry of the lightly doped region on the device saves the process of separately forming the n-type lightly doped region, improves the generation efficiency, and reduces the production cost.
  • the present invention further provides a TFT substrate structure, including a substrate 1 , a buffer layer 2 disposed on the substrate 1 , a polysilicon layer 3 disposed on the buffer layer 2 , and a polysilicon layer disposed on the polysilicon layer. a gate insulating layer 4 on the third surface, and a gate electrode 5 disposed on the gate insulating layer 4 and corresponding to the middle portion of the polysilicon layer 3.
  • the gate 5 is a trapezoidal structure, and includes an upper bottom surface 51, a lower bottom surface 52, and a first inclined surface 53 and a second inclined surface 54 connected between the upper bottom surface 51 and the lower bottom surface 52.
  • the area of 51 is smaller than the area of the lower bottom surface 52.
  • the polysilicon layer 3 includes an undoped channel region 34 located at a middle portion and corresponding to the upper bottom surface 51, located on both sides of the channel region 34 and corresponding to the first slope 53 and the second slope 54 respectively. a first n-type lightly doped region 32, a second n-type lightly doped region 33, and two n-types respectively located outside the first n-type lightly doped region 32 and the second n-type lightly doped region 33 Heavy doped region 31.
  • the thickness of the gate 5 is the thickness of the gate 5
  • an angle formed between the first inclined surface 53 and the lower bottom surface 52 is 10° to 60°; an angle formed between the second inclined surface 54 and the lower bottom surface 52 is 10° ⁇ 60°.
  • the angle formed by the first inclined surface 53 and the second inclined surface 54 and the lower bottom surface 52 is the same.
  • the n-type ion concentration in the first and second n-type lightly doped regions 32, 33 is linearly distributed.
  • the n-type ion concentration in the first and second n-type lightly doped regions 32, 33 is linearly decreasing from the outer side to the inner side.
  • the n-type ion concentration C n+ in the n-type heavily doped region 31 ranges from 10 14 to 10 15 ions/cm 3 ; the first n-type lightly doped region 32 and the second n-type light are The range of the n-type ion concentration C n- in the doped region 33 is C n+ >C n- >0.
  • the material of the buffer layer 2 and the gate insulating layer 4 is silicon oxide, silicon nitride, or a combination of the two; the material of the gate 5 is one of molybdenum, titanium, aluminum, and copper. Or a variety of stack combinations.
  • the polysilicon layer includes an n-type heavily doped region on both sides and an n-type lightly doped region between the channel region of the polysilicon layer and the n-type heavily doped region, thereby avoiding a local strong electric field. Generated, eliminating the effects of hot carriers on device characteristics.
  • the method for fabricating the TFT substrate structure of the present invention by adjusting the parameters of the etching when the gate is formed, a slope is formed on both sides of the gate, and the gate is used as a mask to ion-implant the polysilicon layer.
  • a process simultaneously forms an n-type heavily doped region and an n-type lightly doped region on the polysilicon layer, increasing the resistance value, dispersing a strong electric field near the electrode, and avoiding hot carriers occurring due to the presence of a local strong electric field.
  • the polysilicon layer includes an n-type heavily doped region on both sides and an n-type lightly doped region between the channel region of the polysilicon layer and the n-type heavily doped region, thereby avoiding local strong
  • the generation of an electric field eliminates the effect of hot carriers on device characteristics.

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Abstract

一种TFT基板结构的制作方法及TFT基板结构。TFT基板结构的制作方法，在制作栅极（5）时通过调整蚀刻的参数，使栅极（5）两侧形成斜面，并以栅极（5）作为光罩，对多晶硅层（3）进行离子注入，同时在多晶硅层（3）形成n型重掺杂区（31）和n型轻掺杂区（32），增加了阻值，分散了电极附近的强电场，避免了因局部强电场的存在而发生的热载流子效应对器件特性造成的影响，节省了单独形成n型轻掺杂区的制程，提升了生成效率，降低了生产成本。TFT基板结构，多晶硅层（3）包括位于两侧的n型重掺杂区（31）及位于多晶硅层的沟道区（34）与n型重掺杂区（31）之间的n型轻掺杂区（32），避免了局部强电场的产生，消除了热载流子对器件特性的影响。

Description

TFT基板结构的制作方法及TFT基板结构 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板结构的制作方法及TFT基板结构。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等。
通常液晶显示装置包括壳体、设于壳体内的液晶面板及设于壳体内的背光模组(Backlight module)。其中，液晶面板的结构主要是由一薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)、一彩色滤光片基板(Color Filter，CF)、以及配置于两基板间的液晶层(Liquid Crystal Layer)所构成，其工作原理是通过在两片玻璃基板上施加驱动电压来控制液晶层的液晶分子的旋转，将背光模组的光线折射出来产生画面。
随着移动显示技术在生活中的应用起到的作用越来越大，移动显示技术向更高画质、更高精细程度、更轻薄和更低功耗的方向发展，在器件上就要求尺寸越来越小，器件内部局部区域的电场强度也因此而增强，特别是在漏极附近存在强电场。载流子在强电场的作用下获得较高的能量成为热载流子。热载流子对器件性能的影响主要表现在以下两个方面：
(1)热载流子越过绝缘层注入到氧化层，不断积累，改变阈值电压，影响器件寿命；
(2)在漏极附近的耗尽区与晶格碰撞产生新的电子空穴对，以金属氧化物半导体(Metal Oxid Semiconductor，MOS)场效应晶体管为例，碰撞产生的电子形成附加的漏电流，空穴则被衬底收集，形成衬底电流，使总电流成为饱和漏电流与衬底电流之和。热载流子效应是限制器件最高工作电压的基本因素之一。
为了解决热载流子的出现对器件特性的影响，技术人员想出了各种办法来避免局部强电场的产生。请参阅图1，为一种现有的TFT基板结构的制作方法的示意图。该TFT基板结构包括基板100、设于基板100上的缓冲层200、设于缓冲层200上的多晶硅层300，该方法利用光阻层600为掩模，对多晶硅层300进行离子注入，对应栅极的两侧，在多晶硅层300的 沟道区330与位于两侧的n型重掺杂区310之间形成对称的两n型轻掺杂区(LDD)320，以分散电极附近的强电场，减少热载流子的产生。但这样就意味着需要针对所述n型轻掺杂区320的制作进行单独的光罩设计及一次光刻制程，需要花费大量的成本。
发明内容
本发明的目的在于提供一种TFT基板结构的制作方法，可同时在多晶硅层形成n型重掺杂区和n型轻掺杂区，以增加阻值，分散电极附近的强电场，避免因局部强电场的存在而发生的热载流子效应对器件特性造成影响。
本发明的目的还在于提供一种TFT基板结构，多晶硅层中包括位于两侧的n型重掺杂区及位于多晶硅层的沟道区与n型重掺杂区之间的n型轻掺杂区，可避免局部强电场的产生，消除热载流子对器件特性的影响。
为实现上述目的，本发明提供一种TFT基板结构的制作方法，包括如下步骤：
步骤1、提供基板，在所述基板上沉积缓冲层；
步骤2、在所述缓冲层上沉积多晶硅层，并在所述多晶硅层上沉积栅极绝缘层；
步骤3、在所述栅极绝缘层上沉积金属层，并对所述金属层进行图案化处理，形成对应于所述多晶硅层中部的栅极；
所述栅极为梯形体结构，包括上底面、下底面、连接于所述上底面与下底面之间且相对设置的第一斜面与第二斜面；所述上底面的面积小于所述下底面的面积；
步骤4、以所述栅极为光罩，采用离子注入工艺对所述多晶硅层进行n型掺杂，在所述多晶硅层两侧没有被栅极覆盖的区域形成n型重掺杂区，在所述多晶硅层上对应于所述栅极的第一斜面、第二斜面的区域形成第一n型轻掺杂区、第二n型轻掺杂区，在所述多晶硅层中部对应于所述栅极的上底面的区域形成未掺杂的沟道区。
所述栅极的厚度为
Figure PCTCN2015082163-appb-000001
所述步骤3通过干法蚀刻或湿法蚀刻形成第一斜面与第二斜面。
所述第一斜面与下底面之间形成的夹角的角度为10°～60°；所述第二斜面与下底面之间形成的夹角的角度为10°～60°。
所述第一、第二n型轻掺杂区中的n型离子浓度为从外侧向内侧呈线性递减分布。
所述缓冲层、及栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合；所述栅极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明还提供一种TFT基板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的多晶硅层、设于所述多晶硅层上的栅极绝缘层、及设于所述栅极绝缘层上且对应于所述多晶硅层中部的栅极；
所述栅极为梯形体结构，包括上底面、下底面、连接于所述上底面与下底面之间且相对设置的第一斜面与第二斜面；所述上底面的面积小于所述下底面的面积；
所述多晶硅层包括位于中部且对应于所述上底面的未掺杂的沟道区，位于所述沟道区两侧且分别对应于所述第一斜面、第二斜面的第一n型轻掺杂区、第二n型轻掺杂区，及分别位于所述第一n型轻掺杂区与第二n型轻掺杂区外侧的两n型重掺杂区。
所述栅极的厚度为
Figure PCTCN2015082163-appb-000002
所述第一斜面与下底面之间形成的夹角的角度为10°～60°；所述第二斜面与下底面之间形成的夹角的角度为10°～60°。
所述第一、第二n型轻掺杂区中的n型离子浓度为从外侧向内侧呈线性递减分布。
所述缓冲层、及栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合；所述栅极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明还提供一种TFT基板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的多晶硅层、设于所述多晶硅层上的栅极绝缘层、及设于所述栅极绝缘层上且对应于所述多晶硅层中部的栅极；
所述栅极为梯形体结构，包括上底面、下底面、连接于所述上底面与下底面之间且相对设置的第一斜面与第二斜面；所述上底面的面积小于所述下底面的面积；
所述多晶硅层包括位于中部且对应于所述上底面的未掺杂的沟道区，位于所述沟道区两侧且分别对应于所述第一斜面、第二斜面的第一n型轻掺杂区、第二n型轻掺杂区，及分别位于所述第一n型轻掺杂区与第二n型轻掺杂区外侧的两n型重掺杂区；
其中，所述栅极的厚度为
Figure PCTCN2015082163-appb-000003
所述第一斜面与下底面之间形成的夹角的角度为10°～60°；所述第二斜面与下底面之间形成的夹角的角度为10°～60°；
其中，所述第一、第二n型轻掺杂区中的n型离子浓度为从外侧向内侧呈线性递减分布；
其中，所述缓冲层、及栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合；所述栅极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明的有益效果：本发明的TFT基板结构的制作方法，在制作栅极时通过调整蚀刻的参数，使栅极两侧形成斜面，并以栅极作为光罩，对多晶硅层进行离子注入，同时在多晶硅层形成n型重掺杂区和n型轻掺杂区，增加了阻值，分散了电极附近的强电场，避免了因局部强电场的存在而发生的热载流子效应对器件特性造成的影响，以及轻掺杂区不对称对器件的造成的其他影响，节省了单独形成n型轻掺杂区的制程，提升了生成效率，降低了生产成本。本发明的TFT基板结构，多晶硅层中包括位于两侧的n型重掺杂区及位于多晶硅层的沟道区与n型重掺杂区之间的n型轻掺杂区，避免了局部强电场的产生，消除了热载流子对器件特性的影响。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为一种现有的TFT基板结构的制作方法的示意图；
图2为本发明的TFT基板结构的制作方法的流程图；
图3为本发明的TFT基板结构的制作方法的步骤1的示意图；
图4为本发明的TFT基板结构的制作方法的步骤2的示意图；
图5为本发明的TFT基板结构的制作方法的步骤3的示意图；
图6为本发明的TFT基板结构的制作方法的步骤4的示意图；
图7为本发明的TFT基板结构的剖面示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明首先提供一种TFT基板结构的制作方法，包括如下步骤：
步骤1、如图3所示，提供基板1，在所述基板1上沉积缓冲层2。
具体的，所述基板1可以是玻璃基板或塑料基板，所述缓冲层2的材料可以是氧化硅(SiOx)、氮化硅(SiNx)、或二者的组合。
步骤2、如图4所示，在所述缓冲层2上沉积多晶硅(Poly-Si)层3， 并在所述多晶硅层3上沉积栅极绝缘层4。
具体的，所述栅极绝缘层4的材料可以是氧化硅、氮化硅、或二者的组合。
步骤3、如图5所示，在所述栅极绝缘层4上沉积金属层，并对所述金属层进行图案化处理，形成对应于所述多晶硅层3中部的栅极5。
所述栅极5为梯形体结构，包括上底面51、下底面52、连接于所述上底面51与下底面52之间且相对设置的第一斜面53与第二斜面54；所述上底面51的面积小于所述下底面52的面积。
具体的，所述第一斜面53与下底面52之间形成的夹角的角度为10°～60°；所述第二斜面54与下底面52之间形成的夹角的角度为10°～60°。
优选的，所述第一斜面53、第二斜面54与下底面52之间形成的夹角的角度相同。
具体的，所述栅极5的材料可以是钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
具体的，通过干法蚀刻(Dry Etch)或湿法蚀刻(Wet Etch)形成所述第一斜面53与第二斜面54，并通过调整蚀刻工艺的参数来调整所述第一斜面53、第二斜面54与所述下底面52之间形成的夹角的角度。
优选的，所述栅极5的厚度为
Figure PCTCN2015082163-appb-000004
步骤4、如图6所示，以所述栅极5为光罩，采用离子注入工艺对所述多晶硅层3进行n型掺杂，在所述多晶硅层3两侧没有被栅极5覆盖的区域上形成n型重掺杂区31，在所述多晶硅层3上对应于所述栅极5的第一斜面53、第二斜面54的区域形成第一n型轻掺杂区32、及第二n型轻掺杂区33，在所述多晶硅层3中部对应于所述栅极5的上底面51的区域形成未掺杂的沟道区34。
由于所述栅极5的两侧为平缓的斜面，因此在采用离子注入工艺对所述多晶硅层3进行n型掺杂的过程中，在没有栅极5覆盖的区域形成n型重掺杂区31，由于所述栅极5位于第一斜面53与第二斜面54处的厚度较薄，从而n型离子可以穿过所述栅极5，在所述多晶硅层3上被栅极5的第一斜面53、第二斜面54覆盖的区域形成n型离子浓度呈线性分布的第一、第二n型轻掺杂区32、33。所述第一、第二n型轻掺杂区32、33增加了阻值，分散了电极附近的强电场，避免了因局部强电场的存在而发生的热载流子效应对器件特性造成的影响。
进一步的，由于所述栅极5位于第一斜面53与下底面52之间的厚度从外侧向内侧呈线性递增，因此进行n型掺杂时，n型离子注入的难度也从 外向内逐渐递增，从而最终得到的第一n型轻掺杂区32中的n型离子浓度为从外侧向内侧呈线性递减分布。
同理，由于所述栅极5位于第二斜面54与下底面52之间的厚度从外侧向内侧呈线性递增，因此进行n型掺杂时，n型离子注入的难度也从外向内逐渐递增，从而最终得到的第二n型轻掺杂区33中的n型离子浓度为从外侧向内侧呈线性递减分布。
具体的，所述步骤4得到的n型重掺杂区31中的n型离子浓度Cn+的范围为1014～1015ions/cm3；所述第一n型轻掺杂区32、第二n型轻掺杂区33中的n型离子浓度Cn-的范围为Cn+＞Cn-＞0。
本发明的TFT基板结构的制作方法，通过在沟道的两侧分别设置两个n型轻掺杂区，避免了轻掺杂区不对称对器件的造成的其他影响。
上述TFT基板结构的制作方法，在制作栅极时通过调整蚀刻工艺的参数，使栅极两侧形成斜面，并以栅极作为光罩，对多晶硅层进行离子注入，通过一道制程同时在多晶硅层形成n型重掺杂区和线性离子浓度的n型轻掺杂区，增加了阻值，分散了电极附近的强电场，避免了因局部强电场的存在而发生的热载流子效应对器件特性造成的影响，以及轻掺杂区不对称对器件的造成的其他影响，节省了单独形成n型轻掺杂区的制程，提升了生成效率，降低了生产成本。
请参阅图7，本发明还提供一种TFT基板结构，包括基板1、设于所述基板1上的缓冲层2、设于所述缓冲层2上的多晶硅层3、设于所述多晶硅层3上的栅极绝缘层4、及设于所述栅极绝缘层4上且对应于所述多晶硅层3中部的栅极5。
所述栅极5为梯形体结构，包括上底面51、下底面52、连接于所述上底面51与下底面52之间且相对设置的第一斜面53与第二斜面54；所述上底面51的面积小于所述下底面52的面积。
所述多晶硅层3包括位于中部且对应于所述上底面51的未掺杂的沟道区34，位于所述沟道区34两侧且分别对应于所述第一斜面53、第二斜面54的第一n型轻掺杂区32、第二n型轻掺杂区33，及分别位于所述第一n型轻掺杂区32与第二n型轻掺杂区33外侧的两n型重掺杂区31。
优选的，所述栅极5的厚度为
Figure PCTCN2015082163-appb-000005
具体的，所述第一斜面53与下底面52之间形成的夹角的角度为10°～60°；所述第二斜面54与下底面52之间形成的夹角的角度为10°～60°。
优选的，所述第一斜面53、第二斜面54与下底面52之间形成的夹角的角度相同。
具体的，所述第一、第二n型轻掺杂区32、33中的n型离子浓度呈线性分布。
进一步的，所述第一、第二n型轻掺杂区32、33中的n型离子浓度为从外侧向内侧呈线性递减分布。
具体的，所述n型重掺杂区31中的n型离子浓度Cn+的范围为1014～1015ions/cm3；所述第一n型轻掺杂区32、第二n型轻掺杂区33中的n型离子浓度Cn-的范围为Cn+＞Cn-＞0。
具体的，所述缓冲层2、及栅极绝缘层4的材料为氧化硅、氮化硅、或二者的组合；所述栅极5的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
上述TFT基板结构，多晶硅层中包括位于两侧的n型重掺杂区及位于多晶硅层的沟道区与n型重掺杂区之间的n型轻掺杂区，避免了局部强电场的产生，消除了热载流子对器件特性的影响。
综上所述，本发明的TFT基板结构的制作方法，在制作栅极时通过调整蚀刻的参数，使栅极两侧形成斜面，并以栅极作为光罩，对多晶硅层进行离子注入，通过一道制程同时在多晶硅层上形成n型重掺杂区和n型轻掺杂区，增加了阻值，分散了电极附近的强电场，避免了因局部强电场的存在而发生的热载流子效应对器件特性造成的影响，以及轻掺杂区不对称对器件的造成的其他影响；节省了单独形成n型轻掺杂区的制程，提升了生成效率，降低了生产成本。本发明的TFT基板结构，多晶硅层中包括位于两侧的n型重掺杂区及位于多晶硅层的沟道区与n型重掺杂区之间的n型轻掺杂区，避免了局部强电场的产生，消除了热载流子对器件特性的影响。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (11)

  1. 一种TFT基板结构的制作方法，包括如下步骤：
    步骤1、提供基板，在所述基板上沉积缓冲层；
    步骤2、在所述缓冲层上沉积多晶硅层，并在所述多晶硅层上沉积栅极绝缘层；
    步骤3、在所述栅极绝缘层上沉积金属层，并对所述金属层进行图案化处理，形成对应于所述多晶硅层中部的栅极；
    所述栅极为梯形体结构，包括上底面、下底面、连接于所述上底面与下底面之间且相对设置的第一斜面与第二斜面；所述上底面的面积小于所述下底面的面积；
    步骤4、以所述栅极为光罩，采用离子注入工艺对所述多晶硅层进行n型掺杂，在所述多晶硅层两侧没有被栅极覆盖的区域形成n型重掺杂区，在所述多晶硅层上对应于所述栅极的第一斜面、第二斜面的区域形成第一n型轻掺杂区、第二n型轻掺杂区，在所述多晶硅层中部对应于所述栅极的上底面的区域形成未掺杂的沟道区。
  2. 如权利要求1所述的TFT基板结构的制作方法，其中，所述栅极的厚度为
    Figure PCTCN2015082163-appb-100001
  3. 如权利要求1所述的TFT基板结构的制作方法，其中，所述步骤3通过干法蚀刻或湿法蚀刻形成第一斜面与第二斜面。
  4. 如权利要求1所述的TFT基板结构的制作方法，其中，所述第一斜面与下底面之间形成的夹角的角度为10°～60°；所述第二斜面与下底面之间形成的夹角的角度为10°～60°。
  5. 如权利要求1所述的TFT基板结构的制作方法，其中，所述第一、第二n型轻掺杂区中的n型离子浓度为从外侧向内侧呈线性递减分布。
  6. 如权利要求1所述的TFT基板结构的制作方法，其中，所述缓冲层、及栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合；所述栅极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  7. 一种TFT基板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的多晶硅层、设于所述多晶硅层上的栅极绝缘层、及设于所述栅极绝缘层上且对应于所述多晶硅层中部的栅极；
    所述栅极为梯形体结构，包括上底面、下底面、连接于所述上底面与下底面之间且相对设置的第一斜面与第二斜面；所述上底面的面积小于所 述下底面的面积；
    所述多晶硅层包括位于中部且对应于所述上底面的未掺杂的沟道区，位于所述沟道区两侧且分别对应于所述第一斜面、第二斜面的第一n型轻掺杂区、第二n型轻掺杂区，及分别位于所述第一n型轻掺杂区与第二n型轻掺杂区外侧的两n型重掺杂区。
  8. 如权利要求7所述的TFT基板结构，其中，所述栅极的厚度为
    Figure PCTCN2015082163-appb-100002
    所述第一斜面与下底面之间形成的夹角的角度为10°～60°；所述第二斜面与下底面之间形成的夹角的角度为10°～60°。
  9. 如权利要求7所述的TFT基板结构的制作方法，其中，所述第一、第二n型轻掺杂区中的n型离子浓度为从外侧向内侧呈线性递减分布。
  10. 如权利要求7所述的TFT基板结构，其中，所述缓冲层、及栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合；所述栅极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  11. 一种TFT基板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的多晶硅层、设于所述多晶硅层上的栅极绝缘层、及设于所述栅极绝缘层上且对应于所述多晶硅层中部的栅极；
    所述栅极为梯形体结构，包括上底面、下底面、连接于所述上底面与下底面之间且相对设置的第一斜面与第二斜面；所述上底面的面积小于所述下底面的面积；
    所述多晶硅层包括位于中部且对应于所述上底面的未掺杂的沟道区，位于所述沟道区两侧且分别对应于所述第一斜面、第二斜面的第一n型轻掺杂区、第二n型轻掺杂区，及分别位于所述第一n型轻掺杂区与第二n型轻掺杂区外侧的两n型重掺杂区；
    其中，所述栅极的厚度为
    Figure PCTCN2015082163-appb-100003
    所述第一斜面与下底面之间形成的夹角的角度为10°～60°；所述第二斜面与下底面之间形成的夹角的角度为10°～60°；
    其中，所述第一、第二n型轻掺杂区中的n型离子浓度为从外侧向内侧呈线性递减分布；
    其中，所述缓冲层、及栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合；所述栅极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
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