WO2016192364A1 - 狭缝电极的制造方法、狭缝电极及显示面板 - Google Patents

狭缝电极的制造方法、狭缝电极及显示面板 Download PDF

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WO2016192364A1
WO2016192364A1 PCT/CN2015/097002 CN2015097002W WO2016192364A1 WO 2016192364 A1 WO2016192364 A1 WO 2016192364A1 CN 2015097002 W CN2015097002 W CN 2015097002W WO 2016192364 A1 WO2016192364 A1 WO 2016192364A1
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Prior art keywords
photoresist
pattern
layer
slit electrode
passivation layer
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PCT/CN2015/097002
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English (en)
French (fr)
Inventor
安杨
彭志龙
代伍坤
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US15/303,043 priority Critical patent/US10345658B2/en
Publication of WO2016192364A1 publication Critical patent/WO2016192364A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/042—Coating on selected surface areas, e.g. using masks using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/0605—Carbon
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
    • C23C14/086—Oxides of zinc, germanium, cadmium, indium, tin, thallium or bismuth
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a method of manufacturing a slit electrode, a slit electrode, and a display panel.
  • the liquid crystal panel can be divided into: twisted nematic (English full name: Twisted Nematic, referred to as: TN) type, plane conversion (English full name: In Plane Switching, referred to as: IPS) type and advanced super-dimensional field switch (English) Full name: Advanced Super Dimension Switch, referred to as: ADS).
  • twisted nematic English full name: Twisted Nematic, referred to as: TN
  • plane conversion English full name: In Plane Switching, referred to as: IPS
  • advanced super-dimensional field switch English
  • ADS Advanced Super Dimension Switch
  • the liquid crystal panel of the ADS display mode forms a multi-dimensional electric field by an electric field generated by a slit electrode in the same plane and an electric field generated between the surface electrodes, so that all liquid crystal molecules between the electrodes and directly above the electrodes are rotated, as opposed to
  • the liquid crystal panel of the IPS display mode can improve the working efficiency of the liquid crystal and increase the light transmission efficiency.
  • the LCD panel of ADS display mode is
  • the steps of coating, coating, exposing, developing, etching and stripping are generally included, wherein one of the most commonly used processes in the etching process is Wet chemical etching process.
  • wet chemical etching process etches the slit electrode, the etching at the slit is often unclean, and even the electrode short circuit may occur, which may cause uneven brightness of the array substrate of the display device. :Mura), the transmittance is lowered, and the liquid crystal guiding film (for example, Cell polyimide, referred to as Cell PI) is uneven. Therefore, how to avoid etching residue at the slit of the slit electrode is a problem to be solved by those skilled in the art.
  • Embodiments of the present disclosure provide a method for manufacturing a slit electrode, a slit electrode, and a display panel, which are used to solve the problem that the etching is not clean when the slit electrode is fabricated in the prior art.
  • a method of manufacturing a slit electrode comprising:
  • a slit electrode pattern on the passivation layer formed with the first photoresist pattern, the slit electrode pattern being covered with a second photoresist pattern, the shape of the second photoresist pattern and the narrow The shape of the slit electrode corresponds;
  • the forming a first photoresist pattern on the passivation layer comprises:
  • the exposed first photoresist layer is developed to form a first photoresist pattern.
  • the forming a slit electrode pattern on the passivation layer formed with the first photoresist pattern comprises:
  • the electrode material film layer covered with the second photoresist pattern is etched to form the slit electrode pattern.
  • the forming a layer of the electrode material film on the passivation layer formed with the first photoresist pattern comprises:
  • a layer of the electrode material film layer is formed on the passivation layer on which the first photoresist pattern is formed by sputtering.
  • the electrode pattern comprises an indium tin oxide pattern.
  • the electrode pattern comprises a graphene pattern.
  • the photoresist coating process includes a static gluing process and a dynamic gluing process.
  • the static gluing process includes the following steps:
  • the photoresist is uniformly coated by rotating the passivation layer.
  • the dynamic gluing process comprises the following steps:
  • the passivation layer is rotated while the photoresist is sprayed onto the passivation layer, so that the photoresist begins to diffuse upon contact with the passivation layer, thereby forming a uniform photoresist film layer.
  • the mask is made of an opaque material, and after exposing the photoresist to the unmasked portion of the mask, the photoresist irradiated by the light on the photoresist layer is polymerized to form a polymer.
  • a slit electrode produced by the method of manufacturing a slit electrode according to any of the first aspects.
  • a display panel comprising the slit electrode of the second aspect.
  • the display panel comprises: an advanced super-dimensional field switch type display panel, wherein the slit electrode is a pixel electrode of the display panel.
  • a method for fabricating a slit electrode firstly forms a first photoresist pattern on a passivation layer, the shape of the first photoresist pattern corresponding to the shape of the slit of the slit electrode; a slit electrode pattern is formed on the passivation layer on which the first photoresist pattern is formed, and the slit electrode pattern is covered with a second photoresist pattern, and the shape of the second photoresist pattern corresponds to the shape of the slit electrode Finally, the first photoresist pattern and the second photoresist pattern are stripped; since the slit of the slit electrode can be simultaneously peeled off while peeling off the first photoresist pattern and the second photoresist pattern The electrode material is completely etched away, so the embodiment of the present disclosure can solve the problem that the etching is not clean when the slit electrode is fabricated in the prior art.
  • FIG. 1 is a flow chart of steps of a method for manufacturing a slit electrode according to an embodiment of the present disclosure
  • FIG. 2 is a flow chart showing the steps of a method for manufacturing a slit electrode according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a passivation layer and a first photoresist layer according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of a first mask provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a first photoresist pattern according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of an electrode material layer according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a second photoresist layer according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a second mask provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a second photoresist pattern according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a slit electrode pattern according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a slit electrode after peeling off a first photoresist pattern and a second photoresist pattern according to an embodiment of the present disclosure.
  • Electrode material layer -60
  • Second photoresist layer -70 Second photoresist layer -70
  • Second photoresist pattern -90 Second photoresist pattern -90
  • the “upper” and “lower” in the embodiments of the present disclosure are used in the order of manufacturing the slit electrodes.
  • the pattern on the upper refers to the pattern formed later
  • the pattern on the lower refers to the pattern formed on the opposite side.
  • the thickness ratio of each layer structure is selected in an easy-to-view thickness ratio, but the thickness ratio of each layer structure in the drawing does not represent an actual display device.
  • the thickness ratio of each layer structure is also not a limitation of the present disclosure.
  • An embodiment of the present disclosure provides a method for manufacturing a slit electrode. Specifically, referring to FIG. 1, the method includes:
  • a method for fabricating a slit electrode firstly forms a first photoresist pattern on a passivation layer, the shape of the first photoresist pattern corresponding to the shape of the slit of the slit electrode; a slit electrode pattern is formed on the passivation layer on which the first photoresist pattern is formed, and the slit electrode pattern is covered with a second photoresist pattern, and the shape of the second photoresist pattern corresponds to the shape of the slit electrode Finally, the first photoresist pattern and the second photoresist pattern are stripped; since the first photoresist pattern and the second photoresist pattern are stripped, the slit electrode slit can be simultaneously peeled off The electrode material is not completely etched, so the embodiment of the present disclosure can solve the problem that the etching is not clean when the slit electrode is fabricated in the prior art.
  • Another embodiment of the present disclosure provides a method for manufacturing a slit electrode. Specifically, referring to FIG. 2, the method includes:
  • the passivation layer is also called a protective layer, which is used to isolate adjacent layer structures or to protect other layer structures.
  • a protective layer for example: a gate insulating layer of an array substrate.
  • the photoresist generally comprises: a polymer, a solvent, a sensitizer, an additive, etc., and the photoresist can be polymerized under specific conditions to form a polymer.
  • a photoresist undergoes polymerization to form a polymer when exposed to light, and another photoresist undergoes polymerization to form a polymer when not exposed to light.
  • the photoresist is subjected to The polymerization reaction to form a polymer upon irradiation with light will be described as an example.
  • a first photoresist layer 31 is coated on the passivation layer 30.
  • Typical photoresist coating processes include static gluing processes and dynamic gluing processes.
  • the static coating process is as follows: first, the photoresist is deposited in the center of the passivation layer through a pipe, and the measurement is determined by the size of the passivation layer and the type of the photoresist, and then the deposited photoresist is spread out, and then The photoresist is uniformly coated by rotating the passivation layer; and the dynamic gluing process is: rotating the passivation layer while spraying the photoresist to the passivation layer, thereby causing the photoresist to contact the passivation layer upon contact Diffusion begins, and a more uniform photoresist layer can be formed with less photoresist using a dynamic gluing process.
  • the process of applying the photoresist is not limited in the embodiment of the present disclosure as long as a uniform photoresist film layer can be formed.
  • a first mask is disposed over the first photoresist layer, and the photoresist of the unmasked portion of the first mask is exposed.
  • a first mask 40 is disposed above the first photoresist layer formed in the above step S201, and the mask 40 is made of an opaque material, and the photoresist is not blocked on the mask. After exposure, the photoresist irradiated with light on the first photoresist layer is polymerized to form a polymer.
  • the developing process generally includes a wet developing process and a dry developing process, wherein the wet developing process is further divided into a process of immersion development, spray development, coagulation development, and the like; dry development refers to a plasma etching process.
  • the above development processes are all existing processes, and are not described in detail herein to avoid a brief description of the present disclosure. Specifically, referring to FIG. 5, a first photoresist pattern 50 is formed on the passivation layer 30.
  • the principle of sputter coating is a technique in which a high-energy electron is bombarded on a surface of a target in a vacuum chamber to deposit a bombarded particle on a substrate to form a film.
  • the sputtering process generally does not occur in a chemical reaction, and belongs to a physical vapor deposition method (English name: physical vapor deposition, English abbreviation: PVD), which is generally used to form a metal electrode.
  • the electrode material may be: indium tin oxide (English name: Indium Tin Oxide, Abbreviation: ITO) or graphene.
  • ITO Indium Tin Oxide
  • the formed slit electrode pattern is an ITO pattern or a graphene pattern.
  • ITO is the most commonly used material in transparent electrodes, including indium oxide and tin oxide, indium oxide has high transmittance, and tin oxide has strong conductivity, so ITO is a kind of conductive with high transmittance. material.
  • Graphene is a new carbonaceous material that is closely packed into a two-dimensional honeycomb structure by a single layer of carbon atoms. It has a mobility of 200,000 cm2/Vs, which is 100 times higher than that of silicon.
  • Graphene as a motor material can not only increase the transmittance and conductivity of the slit electrode, but also increase the strength of the slit electrode.
  • a layer of the electrode material film layer 60 is formed on the passivation layer 30 on which the first photoresist pattern 50 is formed.
  • the method of coating the second photoresist layer on the electrode material film layer in step S205 is similar to the method of applying the first photoresist layer on the passivation layer in step S201, and details are not described herein again. Specifically, referring to FIG. 7, a second photoresist layer 70 is coated on the electrode material film layer 60.
  • a second mask is disposed over the second photoresist layer, and the photoresist of the unmasked portion of the second mask is exposed.
  • step S206 a second mask is disposed over the second photoresist layer, and the photoresist is exposed to the unmasked portion of the second mask, and the step S202 is above the first photoresist layer.
  • the method of setting the first mask and exposing the photoresist of the unmasked portion of the first mask is similar. The difference is that the shape of the light-transmitting region of the first mask used in step S202 is different from the shape of the light-transmitting region of the second mask used in step S206.
  • the shape of the non-transmissive region of the first mask used in step S202 is the same as the shape of the slit of the slit electrode, and the shape of the non-transparent region of the second mask used in step S206 is opposite to the shape of the slit electrode.
  • the shape is the same.
  • a second mask 80 is disposed over the second photoresist layer 70 , and the photoresist of the unmasked portion of the second mask 80 is exposed.
  • step S207 is similar to that in step S203, and is not described herein again. Specifically, referring to FIG. 9, the exposed second photoresist layer 70 is developed to form a second photoresist pattern 90.
  • the etching process generally includes dry etching and wet etching, wherein the dry method is mainly used for etching of a non-metal film.
  • the dry method is mainly used for etching of a non-metal film.
  • plasma etching English name: plasma etching, referred to as: PE,
  • reactive ion etching (refer to the full name: reactive ion etching, referred to as: RIE).
  • Wet etching is mainly used for the etching of metal films.
  • the essential process is the process of dissolving and redoxing the metal film by a strong acid solution.
  • the method of etching is also not limited in the embodiment of the present disclosure as long as the slit electrode pattern can be etched. Referring to FIG. 10, the electrode material film layer 60 covered with the second photoresist 70 pattern is etched to form the slit electrode pattern 100.
  • the purpose of the stripping is to remove the photoresist of the etched slit electrode.
  • the commonly used photoresist stripping method is to strip the photoresist by the photoresist stripping solution. That is, the etched slit electrode pattern, the passivation layer, the first photoresist pattern, and the second photoresist pattern are entirely placed in the photoresist stripping solution to dissolve the photoresist, and at the same time, attached to the first
  • the unetched electrode material on the second photoresist pattern also peels off the slit electrode pattern along with the second photoresist. Therefore, the embodiment of the present disclosure can solve the problem that the etching is not clean when the slit electrode is fabricated in the prior art. Referring to FIG. 11, in FIG. 11, 100 is a slit electrode pattern after peeling off the first photoresist pattern and the second photoresist pattern.
  • a further embodiment of the present disclosure provides a slit electrode fabricated by the method for fabricating the slit electrode provided in any of the above embodiments. Since the slit electrode of the present disclosure is obtained by the method for fabricating the slit electrode provided in any of the above embodiments, the slit electrode provided by the present disclosure can solve the problem that the etching is not clean when the slit electrode is fabricated in the prior art. .
  • An embodiment of the present disclosure is a display panel including the slit electrode provided in the above embodiment.
  • the display panel can be: electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator and the like with any display product or component.
  • the display panel comprises: an advanced super-dimensional field switch type display panel, and the slit electrode is a pixel electrode of the display panel.
  • the display panel can also be a flat panel conversion (English name: In Plane Switching, IPS for short) mode display panel and fringe field switch (English full name: Fringe Field Switching, referred to as: FFS) mode display panel, this disclosure does not do this It is to be limited as long as the display panel includes the slit electrode provided in the above embodiment.
  • IPS In Plane Switching
  • FFS Fringe Field Switching

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Abstract

一种狭缝电极的制造方法、狭缝电极及显示面板。该制造方法包括，在钝化层(30)上形成第一光刻胶图案(50)，第一光刻胶图案(50)的形状与狭缝电极的狭缝的形状相对应；在形成有第一光刻胶图案(50)的钝化层(30)上形成狭缝电极图案(100)，狭缝电极图案(100)上覆盖有第二光刻胶图案(90)，第二光刻胶图案(90)的形状与狭缝电极的形状相对应；对第一光刻胶图案(50)和第二光刻胶图案(90)进行剥离。

Description

狭缝电极的制造方法、狭缝电极及显示面板
相关申请的交叉引用
本申请主张在2015年6月3日在中国提交的中国专利申请号No.201510300844.2的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示器技术领域，尤其涉及一种狭缝电极的制造方法、狭缝电极及显示面板。
背景技术
目前，液晶面板按照显示模式可以分为：扭曲向列(英文全称：Twisted Nematic，简称：TN)型、平面转换(英文全称：In Plane Switching，简称：IPS)型和高级超维场开关(英文全称：Advanced Super Dimension Switch，简称：ADS)型等。其中，ADS显示模式的液晶面板是通过同一平面内的狭缝电极所产生的电场和面电极间产生的电场形成多维电场，使在电极之间和电极正上方的所有液晶分子发生旋转，相对于IPS显示模式的液晶面板，能够提高液晶的工作效率且增加了透光效率。由于ADS显示模式的液晶面板具有高画面品质、高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无水波纹(引文名称：push Mura)等优点所以被广泛应用。
现有技术中，在制作ADS显示模式的液晶面板的狭缝电极时通常依次包括：镀膜、涂胶、曝光、显影、刻蚀和剥离等工序，其中刻蚀工艺中最常用的一种工艺是湿法化学刻蚀工艺。然而，湿法化学刻蚀工艺在刻蚀狭缝电极时，常常会出现狭缝处刻蚀不干净，甚至于会出现电极短路的现象，进而导致显示装置的阵列基板出现亮度不均匀(英文名称：Mura)、透过率降低、液晶导向膜(例如Cell polyimide，简称：Cell PI)不均匀等问题。所以，如何避免狭缝电极的狭缝处刻蚀残留是本领域技术人员亟待解决的问题。
发明内容
本公开的实施例提供一种狭缝电极的制造方法、狭缝电极及显示面板，用于解决现有技术中制作狭缝电极时刻蚀不干净的问题。
为达到上述目的，本公开的实施例采用如下技术方案：
第一方面，提供一种狭缝电极的制造方法，包括：
在钝化层上形成第一光刻胶图案，所述第一光刻胶图案的形状与所述狭缝电极的狭缝的形状相对应；
在形成有第一光刻胶图案的钝化层上形成狭缝电极图案，所述狭缝电极图案上覆盖有第二光刻胶图案，所述第二光刻胶图案的形状与所述狭缝电极的形状相对应；
对所述第一光刻胶图案和所述第二光刻胶图案进行剥离。
可选的，所述在钝化层上形成第一光刻胶图案，包括：
在钝化层上涂覆第一层光刻胶层；
在所述第一光刻胶层上方设置第一掩膜板，并对所述第一掩膜板未遮挡部位的光刻胶进行曝光；
对曝光后的所述第一光刻胶层进行显影形成第一光刻胶图案。
可选的，所述在形成有第一光刻胶图案的钝化层上形成狭缝电极图案，包括：
在形成有第一光刻胶图案的钝化层上形成一层电极材料膜层；
在所述电极材料膜层上涂覆第二层光刻胶层；
在所述第二光刻胶层上方设置第二掩膜板，并对所述第二掩膜板未遮挡部位的光刻胶进行曝光；
对曝光后的第二光刻胶进行显影形成第二光刻胶图案；
对覆盖有第二光刻胶图案的电极材料膜层进行刻蚀形成所述狭缝电极图案。
可选的，所述在形成有第一光刻胶图案的钝化层上形成一层电极材料膜层，包括：
通过溅射镀膜在形成有第一光刻胶图案的钝化层上形成一层电极材料膜层。
可选的，所述电极图案包括铟锡氧化物图案。
可选的，所述电极图案包括石墨烯图案。
可选的，涂覆光刻胶的工艺包括静态涂胶工艺和动态涂胶工艺。
可选的，静态涂胶工艺包括以下步骤：
将光刻胶通过管道堆积在钝化层的中心，其计量由钝化层的大小和光刻胶的类型确定；
将堆积的光刻胶铺展开来；
通过旋转对钝化层使光刻胶涂覆均匀。
可选的，动态涂胶工艺包括以下步骤：
在向钝化层喷洒光刻胶的同时使钝化层旋转，从而使光刻胶在一接触到钝化层时就开始扩散，进而形成均匀的光刻胶膜层。
可选的，所述掩膜板为不透光材料制作，对掩膜板未遮挡部位的光刻胶进行曝光后，光刻胶层上受到光线照射的光刻胶发生聚合反应形成聚合物。
第二方面，提供一种狭缝电极，所述狭缝电极由第一方面任一项所述的狭缝电极制造方法制作获得。
第三方面，提供一种显示面板，包括第二方面所述的狭缝电极。
可选的，所述显示面板包括：高级超维场开关型显示面板，所述狭缝电极为所述显示面板的像素电极。
本公开实施例提供的狭缝电极的制作方法，首先在在钝化层上形成第一光刻胶图案，第一光刻胶图案的形状与狭缝电极的狭缝的形状相对应；然后在形成有第一光刻胶图案的钝化层上形成狭缝电极图案，且狭缝电极图案上覆盖有第二光刻胶图案，第二光刻胶图案的形状与狭缝电极的形状相对应；最后对第一光刻胶图案和第二光刻胶图案进行剥离；因为在对第一光刻胶图案和第二光刻胶图案进行剥离的同时能够同时剥离掉狭缝电极狭缝内未完全刻蚀掉的电极材料，所以本公开的实施例能够解决现有技术中制作狭缝电极时刻蚀不干净的问题。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种狭缝电极制造方法的步骤流程图；
图2为本公开实施例提供的另一种狭缝电极制造方法的步骤流程图；
图3为本公开实施例提供的钝化层和第一光刻胶层的示意性结构图；
图4为本公开实施例提供的第一掩膜板的示意性结构图
图5为本公开实施例提供的第一光刻胶图案的示意性结构图；
图6为本公开实施例提供的电极材料层的示意性结构图；
图7为本公开实施例提供的第二光刻胶层的示意性结构图；
图8为本公开实施例提供的第二掩膜板的示意性结构图；
图9为本公开实施例提供的第二光刻胶图案的示意性结构图；
图10为本公开实施例提供的狭缝电极图案的示意性结构图；
图11为本公开实施例提供的剥离第一光刻胶图案和第二光刻胶图案后的狭缝电极的示意性结构图。
附图标记：
钝化层-30；
第一光刻胶层-31；
第一掩膜板-40；
第一光刻胶图案-50；
电极材料层-60；
第二光刻胶层-70；
第二掩膜板-80；
第二光刻胶图案-90；
狭缝电极图案-100。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
需要说明的是，本申请中的“第一”、“第二”等字样仅仅是为了对功能和作用基本相同的相同项或相似项进行区分，“第一”、“第二”等字样并不是在对数量和执行次序进行限定。
此外，本公开实施例中的“上”、“下”以制造狭缝电极时的先后顺序为 准，例如，在上的图案是指相对在后形成的图案，在下的图案是指相对在先形成的图案。另一方面，为了更清楚地说明本公开实施例的技术方案，附图中对各层结构的厚度选取了易于观察的厚度比例，但附图中各个层结构的厚度比例并不代表实际显示装置中各层结构的厚度比例，也不能作为对本公开的限制。
本公开的实施例提供一种狭缝电极的制造方法，具体的，参照图1所示，该方法包括：
S101、在钝化层上形成第一光刻胶图案，第一光刻胶图案的形状与狭缝电极的狭缝的形状相对应。
S102、在形成有第一光刻胶图案的钝化层上形成狭缝电极图案，狭缝电极图案上覆盖有第二光刻胶图案，第二光刻胶图案的形状与狭缝电极的形状相对应。
S103、对第一光刻胶图案和第二光刻胶图案进行剥离。
本公开实施例提供的狭缝电极的制作方法，首先在在钝化层上形成第一光刻胶图案，第一光刻胶图案的形状与狭缝电极的狭缝的形状相对应；然后在形成有第一光刻胶图案的钝化层上形成狭缝电极图案，且狭缝电极图案上覆盖有第二光刻胶图案，第二光刻胶图案的形状与狭缝电极的形状相对应；最后对第一光刻胶图案和第二光刻胶图案进行剥离；因为在对第一光刻胶图案和第二光刻胶图案进行剥离的同时，能够同时剥离掉狭缝电极狭缝内未完全刻蚀掉的电极材料，所以本公开的实施例能够解决现有技术中制作狭缝电极时刻蚀不干净的问题。
本公开另一实施例提供一种狭缝电极的制造方法，具体的，参照图2所示，该方法包括：
S201、在钝化层上涂覆第一光刻胶层。
其中，钝化层又称为保护层，用于隔离相邻的层结构或者保护其他层结构。例如：阵列基板的栅绝缘层。光刻胶通常包括：聚合物、溶剂、感光剂、添加剂等成分，光刻胶在特定条件下可以发生聚合反应形成聚合物。一种光刻胶在受到光线照射时会发生聚合反应形成聚合物，而另一种光刻胶在未受到光线照射时会发生聚合反应形成聚合物。本公开的实施例中均以光刻胶受 到光线照射时会发生聚合反应形成聚合物为例进行说明。
参照图3所示，在钝化层30上涂覆第一光刻胶层31。通常涂覆光刻胶的工艺包括静态涂胶工艺和动态涂胶工艺。其中，静态涂胶工艺为：首先将光刻胶通过管道堆积在钝化层的中心，计量由钝化层的大小和光刻胶的类型确定，然后将堆积的光刻胶铺展开来，再通过旋转钝化层使光刻胶涂覆均匀；而动态涂胶工艺为：在向钝化层喷洒光刻胶的同时使钝化层旋转，从而使光刻胶在一接触到钝化层时就开始扩散，用动态涂胶工艺可以用较少的光刻胶而形成更均匀的光刻胶膜层。本公开的实施例中不限定涂覆光刻胶的工艺，只要可以形成均匀的光刻胶膜层即可。
S202、在第一光刻胶层上方设置第一掩膜板，并对第一掩膜板未遮挡部位的光刻胶进行曝光。
参照图4所示，在上述步骤S201形成的第一光刻胶层的上方设置第一掩膜板40，掩膜板40为不透光材料制作，对掩膜板未遮挡部位的光刻胶进行曝光后，第一光刻胶层上受到光线照射的光刻胶发生聚合反应形成聚合物。
S203、对曝光后的第一光刻胶层进行显影形成第一光刻胶图案。
第一光刻胶层进过曝光后，第一光刻胶图案的形状记录在光刻胶膜层上，然后通过对未发生聚合反应的光刻胶的化学分解、去除来时使第一光刻胶图案显影。即，通过显影完成掩膜板的图形到光刻胶层上的转移。显影工艺通常包括：湿法显影工艺和干法显影工艺，其中，湿法显影工艺又分为沉浸显影、喷射显影、混凝显影等工艺；干法显影是指使用等离子体刻蚀工艺。以上显影工艺均为现有工艺，为避免赘述本公开在此不做详细介绍。具体的，参照图5所示，在钝化层30上形成第一光刻胶图案50。
S204、通过溅射镀膜在形成有第一光刻胶图案的钝化层上形成一层电极材料膜层。
溅射镀膜的原理为：在真空室中，利用高能量电子轰击靶材表面，使被轰击出的粒子在基板上沉积成膜的技术。溅射过程一般不发生化学反应，属于物理气相沉积法(英文全称：physical vapor deposition，英文简称：PVD)的一种，一般用来形成金属电极。
示例性的，该电极材料可以为：铟锡氧化物(英文全称：Indium Tin Oxide， 简称：ITO)或石墨烯。从而使形成的狭缝电极图案为ITO图案或石墨烯图案。其中，ITO是透明电极中最常用的一种材料，其包括氧化铟和氧化锡，氧化铟具有高透过率，氧化锡具有很强导电能力，因此ITO是一种具有高透过率的导电材料。石墨烯是一种由单层碳原子紧密堆积成二维蜂窝状结构的碳质新材料。其具有200,000cm2/Vs的迁移率，比硅高出100倍，其导电性与铜相接近，光透射率可达97.7％，远高于一般导电薄膜，同时石墨烯还具有高柔性，所以选用石墨烯作为电机材料不但可以增加狭缝电极的透过率、导电率，而且还可以增加狭缝电极的强度。具体的，参照图6所示，在形成有第一光刻胶图案50的钝化层30上形成一层电极材料膜层60。
S205、在电极材料膜层上涂覆第二光刻胶层。
步骤S205中在电极材料膜层上涂覆第二光刻胶层的方法与步骤S201中在钝化层上涂覆第一光刻胶层的方法类似，此处不再赘述。具体的，参照图7所示，在电极材料膜层60上涂覆第二光刻胶层70。
S206、在第二光刻胶层上方设置第二掩膜板，并对第二掩膜板未遮挡部位的光刻胶进行曝光。
同样，步骤S206中在第二光刻胶层上方设置第二掩膜板，并对第二掩膜板未遮挡部位的光刻胶进行曝光的方法与步骤S202中在第一光刻胶层上方设置第一掩膜板，并对第一掩膜板未遮挡部位的光刻胶进行曝光的方法类似。不同之处在于步骤S202中使用的第一掩膜板的透光区域的形状与步骤S206中使用的第二掩膜板的透光区域的形状不同。步骤S202中使用的第一掩膜板的非透光区域的形状与狭缝电极的狭缝形状相同，而步骤S206中使用的第二掩膜板的非透光区域的形状与狭缝电极的形状相同。具体的，参照图8所示，在第二光刻胶层70上方设置第二掩膜板80，并对第二掩膜板80未遮挡部位的光刻胶进行曝光。
S207、对曝光后的第二光刻胶层进行显影形成第二光刻胶图案。
步骤S207中显影方法与步骤S203中类似，此处不再赘述，具体的，参照见图9所示，曝光后的第二光刻胶层70进行显影形成第二光刻胶图案90。
S208、对覆盖有第二光刻胶图案的电极材料膜层进行刻蚀形成狭缝电极图案。
刻蚀工艺通常包括干法刻蚀和湿法刻蚀，其中，干法主要用于非金属膜的刻蚀。包括：等离子刻蚀(英文全称：plasma etching，简称：PE，)反应性离子刻蚀(引文全称：reactive ion etching，简称：RIE)。湿法刻蚀主要用于金属膜的刻蚀，其实质过程为强酸溶液对金属膜进行溶解和氧化还原的过程。本公开实施例中同样不限定刻蚀的方法，只要能够刻蚀形成狭缝电极图案即可。参照图10所示，对覆盖有第二光刻胶70图案的电极材料膜层60进行刻蚀形成狭缝电极图案100。
S209、对第一光刻胶图案和第二光刻胶图案进行剥离。
剥离的目的是将经过蚀刻的狭缝电极的光刻胶去除干净，目前普遍使用的光刻胶剥离方法为通过光刻胶剥离液对光刻胶进行剥离。即，将刻蚀后的狭缝电极图案、钝化层、第一光刻胶图案、第二光刻胶图案整体放入光刻胶剥离液中对光刻胶进行溶解，同时，附着于第二光刻胶图案上未刻蚀干净的电极材料也会随着第二光刻胶剥离狭缝电极图案。所以本公开的实施例可以解决现有技术中制作狭缝电极时刻蚀不干净的问题。参照图11所示，图11中100为剥离第一光刻胶图案和第二光刻胶图案后的狭缝电极图案。
本公开再一实施例提供一种狭缝电极，该狭缝电极由上述任一实施例提供的狭缝电极的制作方法制作获得。由于本公开的狭缝电极，由上述任一实施例的提供的狭缝电极制作方法制作获得，所以本公开提供的狭缝电极可以能够解决现有技术中制作狭缝电极时刻蚀不干净的问题。
本公开一实施例，一种显示面板，该显示面板包括上述实施例提供的狭缝电极。
另外，显示面板可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
示例性的，显示面板包括：高级超维场开关型显示面板，狭缝电极为显示面板的像素电极。
当然，显示面板还可以为平面转换(英文全称：In Plane Switching，简称：IPS)模式显示面板和边缘场开关(英文全称：Fringe Field Switching，简称：FFS)模式显示面板，本公开对此不做限定，只要显示面板包括上述实施例提供狭缝电极即可。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (13)

  1. 一种狭缝电极的制造方法，包括：
    在钝化层上形成第一光刻胶图案，所述第一光刻胶图案的形状与所述狭缝电极的狭缝的形状相对应；
    在形成有第一光刻胶图案的钝化层上形成狭缝电极图案，所述狭缝电极图案上覆盖有第二光刻胶图案，所述第二光刻胶图案的形状与所述狭缝电极的形状相对应；
    对所述第一光刻胶图案和所述第二光刻胶图案进行剥离。
  2. 根据权利要求1所述的方法，其中，所述在钝化层上形成第一光刻胶图案，包括：
    在钝化层上涂覆第一层光刻胶层；
    在所述第一光刻胶层上方设置第一掩膜板，并对所述第一掩膜板未遮挡部位的光刻胶进行曝光；
    对曝光后的所述第一光刻胶层进行显影形成第一光刻胶图案。
  3. 根据权利要求1所述的方法，其中，所述在形成有第一光刻胶图案的钝化层上形成狭缝电极图案，包括：
    在形成有第一光刻胶图案的钝化层上形成一层电极材料膜层；
    在所述电极材料膜层上涂覆第二层光刻胶层；
    在所述第二光刻胶层上方设置第二掩膜板，并对所述第二掩膜板未遮挡部位的光刻胶进行曝光；
    对曝光后的第二光刻胶进行显影形成第二光刻胶图案；
    对覆盖有第二光刻胶图案的电极材料膜层进行刻蚀形成所述狭缝电极图案。
  4. 根据权利要求3所述的方法，其中，所述在形成有第一光刻胶图案的钝化层上形成一层电极材料膜层，包括：
    通过溅射镀膜在形成有第一光刻胶图案的钝化层上形成一层电极材料膜层。
  5. 根据权利要求1所述的方法，其中，所述电极图案包括铟锡氧化物图 案。
  6. 根据权利要求1所述的方法，其中，所述电极图案包括石墨烯图案。
  7. 根据权利要求2或3所述的方法，其中，涂覆光刻胶的工艺包括静态涂胶工艺和动态涂胶工艺。
  8. 根据权利要求7所述的方法，其中，静态涂胶工艺包括以下步骤：
    将光刻胶通过管道堆积在钝化层的中心，其计量由钝化层的大小和光刻胶的类型确定；
    将堆积的光刻胶铺展开来；
    通过旋转对钝化层使光刻胶涂覆均匀。
  9. 根据权利要求7所述的方法，其中，动态涂胶工艺包括以下步骤：
    在向钝化层喷洒光刻胶的同时使钝化层旋转，从而使光刻胶在一接触到钝化层时就开始扩散，进而形成均匀的光刻胶膜层。
  10. 根据权利要求2或3所述的方法，其中，所述掩膜板为不透光材料制作，对掩膜板未遮挡部位的光刻胶进行曝光后，光刻胶层上受到光线照射的光刻胶发生聚合反应形成聚合物。
  11. 一种狭缝电极，其中，所述狭缝电极由权利要求1-10任一项所述的狭缝电极的制造方法制作获得，所述狭缝电极的狭缝内不存在未完全刻蚀掉的电极材料。
  12. 一种显示面板，包括权利要求11所述的狭缝电极。
  13. 根据权利要求12所述的显示面板，其中，所述显示面板包括：高级超维场开关型显示面板，所述狭缝电极为所述显示面板的像素电极。
PCT/CN2015/097002 2015-06-03 2015-12-10 狭缝电极的制造方法、狭缝电极及显示面板 WO2016192364A1 (zh)

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