WO2016191993A1 - Système et procédé de correction de pré-distorsion analogique (apd) - Google Patents

Système et procédé de correction de pré-distorsion analogique (apd) Download PDF

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Publication number
WO2016191993A1
WO2016191993A1 PCT/CN2015/080442 CN2015080442W WO2016191993A1 WO 2016191993 A1 WO2016191993 A1 WO 2016191993A1 CN 2015080442 W CN2015080442 W CN 2015080442W WO 2016191993 A1 WO2016191993 A1 WO 2016191993A1
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WO
WIPO (PCT)
Prior art keywords
signal
coefficient
error
apd
delay
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PCT/CN2015/080442
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English (en)
Chinese (zh)
Inventor
叶四清
尤览
曹斌
朱尔霓
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201580000955.XA priority Critical patent/CN106664269B/zh
Priority to PCT/CN2015/080442 priority patent/WO2016191993A1/fr
Publication of WO2016191993A1 publication Critical patent/WO2016191993A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

Definitions

  • the present invention relates to the field of communications, and in particular, to an analog predistortion correction system and method.
  • PA Power Amplifier
  • PA Power Amplifier
  • PA is an amplifier that amplifies signal power and is often used in the field of communications.
  • the power of the PA to be transmitted is often amplified by the PA.
  • the signal to be transmitted after being amplified by the PA is distorted, which affects the communication quality.
  • the DPD Digital Pre-Distortion
  • APD Analog Pre-Distortion
  • the prior art APD correction system includes a pass-through/delay module 101, a core module 102, a feedforward receiver 103, a feedback receiver 104, and a training module 105, wherein:
  • the through/delay module 101 receives the system input signal, directly outputs the system input signal, or delays the system input signal to obtain a delay signal output;
  • the core module 102 receives the system input signal and the APD coefficient output by the training module 105, and generates a predistortion signal output according to the system input signal and the APD coefficient; a mixed signal of the output signal of the through/delay module 101 and the output signal of the core module 102. That is, the input signal of the PA, and the PA performs power amplification on the mixed signal and outputs it;
  • the feedforward receiver 103 receives the system input signal, performs down-conversion, analog-to-digital conversion processing, and obtains a feedforward digital signal output to the training module 105;
  • the feedback receiver 104 receives the output signal of the PA, performs down-conversion, analog-to-digital conversion processing, and obtains a feedback digital signal output to the training module 105;
  • the training module 105 receives the feedforward digital signal output from the feedforward receiver 103 and the feedback receiver 104.
  • the output feedback digital signal determines the APD coefficient based on the feedforward digital signal and the feedback digital signal, and outputs to the core module 102.
  • Embodiments of the present invention provide an APD correction system and method, which are easier to implement.
  • an APD correction system including a core unit, a gain adjustment unit, an error generation unit, and a training unit, wherein:
  • the core unit is configured to receive a system input signal and an APD coefficient output by the training unit; delaying the input signal of the system to obtain N delay signals with different delays, wherein one delay signal is used as a feedforward a signal is output to the error generating unit, N is an integer not less than 1; and an input signal of the power amplifier PA is obtained according to the system input signal, the N-channel delayed delay signal, and the APD coefficient, A part of the output signal of the PA is coupled as a feedback signal;
  • the gain adjustment unit is configured to receive the feedback signal, adjust a gain of the feedback signal, obtain a feedback adjustment signal, and output the feedback adjustment signal to the error generation unit;
  • the error generating unit is configured to receive a feedforward signal output by the core unit and a feedback adjustment signal output by the gain adjustment unit, generate an error signal of the feedforward signal and the feedback adjustment signal, and output the An error signal to the training unit;
  • the training unit is configured to receive an error signal output by the error generating unit, determine the APD coefficient according to the error signal, and output the APD coefficient to the core unit.
  • the training unit includes a variable gain amplifier, a power detector, an analog-to-digital converter, and a coefficient training module, where:
  • variable gain amplifier is configured to adjust a gain of the error signal to obtain an error adjustment signal
  • the power detector is configured to detect an average power of the error adjustment signal, and obtain Error power signal
  • the analog-to-digital converter is configured to perform analog-to-digital conversion on the error power signal to obtain an error power digital signal
  • the coefficient training module is configured to determine the APD coefficient according to the error power digital signal.
  • the training unit includes a receiver and a coefficient training module, where:
  • the receiver is configured to perform down-conversion and analog-to-digital conversion processing on the error signal to obtain an error digital signal
  • the coefficient training module is configured to determine the APD coefficient according to the error digital signal.
  • the core unit includes N delays , a nonlinear module, M digital vector modulators, and an adder, the APD coefficients including a nonlinear coefficient and M linear coefficients, 1 ⁇ M ⁇ N +1, wherein:
  • the N delay devices are connected in series for delaying the input signals of the system to obtain delay signals of N different delays;
  • the non-linear module is configured to generate a nonlinear pre-distortion signal according to the system input signal, the N-channel delay signal with different delays, and the nonlinear coefficient;
  • the M digital vector modulators wherein one digital vector modulator is used as a post digital vector modulator, and the other M-1 digital vector modulators are used as front digital vector modulators; the system input signal and the N path are different.
  • the N+1 signals composed of the delayed signals one signal is used as the center delay signal, and the other N signals are used as the non-center delay signal;
  • the M linear coefficients one linear coefficient and the adder Corresponding to the output signal, the other M-1 linear coefficients and the M-1 non-central delay signals in the N non-central delay signals are in one-to-one correspondence; each pre-digital vector modulator performs the M-1 path non-center Multiplication of a non-central delay signal in the delayed signal with a corresponding linear coefficient;
  • the adder performs the nonlinear predistortion signal, the center delay signal, and M-1 Addition of the output signal of the former digital vector modulator;
  • the post digital vector modulator performs multiplication of the output signal of the adder with a corresponding linear coefficient to obtain an input signal of the PA.
  • the core unit includes N delays , a nonlinear module, M digital vector modulators, and an adder, the APD coefficients including a nonlinear coefficient and M linear coefficients, 1 ⁇ M ⁇ N +1, wherein:
  • the N delay devices are connected in series for delaying the input signals of the system to obtain delay signals of N different delays;
  • the non-linear module is configured to generate a nonlinear pre-distortion signal according to the system input signal, the N-channel delay signal with different delays, and the nonlinear coefficient;
  • the M digital vector modulators wherein one digital vector modulator acts as a central digital vector modulator, and the other M-1 digital vector modulators act as non-center digital vector modulators;
  • the system input signal is different from the N path Among the N+1 signals composed of the delayed delay signals, one signal is used as the center delay signal, and the other N signals are used as the non-center delay signal;
  • the central digital vector modulator performs the central delay signal and corresponding a multiplication operation of a linear coefficient, each non-central digital vector modulator performing a multiplication operation of a non-central delay signal of the M-1 way non-center delay signal and a corresponding linear coefficient;
  • the adder performs addition of the nonlinear predistortion signal and the output signals of the M digital vector modulators to obtain an input signal of the PA.
  • an APD correction method including:
  • N is an integer not less than 1;
  • a part of the output signal of the PA is coupled as a feedback signal, and the gain of the feedback signal is adjusted to obtain a feedback adjustment signal; one of the N delay signals is used as a feedforward signal to generate the feedforward And an error signal of the feedback adjustment signal; determining the APD coefficient based on the error signal.
  • determining the APD coefficient according to the error signal includes:
  • the APD coefficient is determined based on the error power digital signal.
  • determining the APD coefficient according to the error signal includes:
  • the APD coefficient is determined based on the error digital signal.
  • the APD coefficient includes a nonlinear coefficient and an M Linear coefficients, 1 ⁇ M ⁇ N+1;
  • an input signal of the PA according to the input signal of the system, the delay signal of the N different delays, and the APD coefficient, specifically including:
  • one linear coefficient other than the M-1 linear coefficients corresponds to the output signal of the addition; the multiplication of the output signal of the addition and the corresponding linear coefficient is performed to obtain a PA Input signal.
  • the APD coefficient includes a nonlinear coefficient and an M Linear coefficients, 1 ⁇ M ⁇ N+1;
  • an input signal of the PA according to the input signal of the system, the delay signal of the N different delays, and the APD coefficient, specifically including:
  • the addition of the nonlinear predistortion signal and the M multiplication output signals is performed to obtain an input signal of the PA.
  • an APD correction system including a core unit, a gain adjustment unit, an error generation unit, and a training unit, wherein:
  • the core unit is configured to receive a system input signal and an APD coefficient output by the training unit, and obtain an input signal of the power amplifier PA according to the system input signal and the APD coefficient, and a part of the PA output signal is coupled as a Feedback signal;
  • the gain adjustment unit is configured to receive the feedback signal, adjust a gain of the feedback signal, obtain a feedback adjustment signal, and output the feedback adjustment signal to the error generation unit;
  • the error generating unit is configured to receive the system input signal and the gain adjusting unit Outputting a feedback adjustment signal, the system input signal as a feedforward signal, generating an error signal of the feedforward signal and the feedback adjustment signal, and outputting the error signal to the training unit;
  • the training unit is configured to receive an error signal output by the error generating unit, determine the APD coefficient according to the error signal, and output the APD coefficient to the core unit.
  • the training unit includes a variable gain amplifier, a power detector, an analog-to-digital converter, and a coefficient training module, where:
  • variable gain amplifier is configured to adjust a gain of the error signal to obtain an error adjustment signal
  • the power detector is configured to detect an average power of the error adjustment signal to obtain an error power signal
  • the analog-to-digital converter is configured to perform analog-to-digital conversion on the error power signal to obtain an error power digital signal
  • the coefficient training module is configured to determine the APD coefficient according to the error power digital signal.
  • the training unit includes a receiver and a coefficient training module, where:
  • the receiver is configured to perform down-conversion and analog-to-digital conversion processing on the error signal to obtain an error digital signal
  • the coefficient training module is configured to determine the APD coefficient according to the error digital signal.
  • the core unit includes a nonlinear module, A digital vector modulator and an adder, the APD coefficients comprising a nonlinear coefficient and a linear coefficient, wherein:
  • the non-linear module is configured to generate a nonlinear pre-distortion signal according to the system input signal and the nonlinear coefficient;
  • the adder performs an addition operation of the nonlinear predistortion signal and the system input signal
  • the digital vector modulator performs multiplication of the output signal of the adder with the linear coefficient to obtain an input signal of the PA.
  • the core unit includes a nonlinear module, A digital vector modulator and an adder, the APD coefficients comprising a nonlinear coefficient and a linear coefficient, wherein:
  • the non-linear module is configured to generate a nonlinear pre-distortion signal according to the system input signal and the nonlinear coefficient;
  • the digital vector modulator performing a multiplication operation of the system input signal and the linear coefficient
  • the adder performs addition of the nonlinear predistortion signal and an output signal of the digital vector modulator to obtain an input signal of the PA.
  • an APD correction method including:
  • a part of the output signal of the power amplifier PA is coupled as a feedback signal, and the gain of the feedback signal is adjusted to obtain a feedback adjustment signal;
  • the system input signal is used as a feedforward signal to generate an error signal of the feedforward signal and the feedback adjustment signal;
  • An input signal of the PA is obtained based on the system input signal and the APD coefficient.
  • determining the APD coefficient according to the error signal includes:
  • the APD coefficient is determined based on the error power digital signal.
  • determining the APD coefficient according to the error signal includes:
  • the APD coefficient is determined based on the error digital signal.
  • the APD coefficient includes a nonlinear coefficient and a linear coefficient
  • the output signal of the addition is multiplied by the linear coefficient to obtain an input signal of the PA.
  • the APD coefficient includes a nonlinear coefficient and a linear coefficient
  • the nonlinear predistortion signal and the addition of the multiplied output signal are performed to obtain an input signal of the PA.
  • the core unit receiving system input signal, and the APD coefficient output by the training unit Delaying the input signal of the system to obtain delay signals of N different delays, wherein one delay signal is output as a feedforward signal to the error generating unit, and according to the system input signal, N different delayed delay signals And the APD coefficient, the input signal of the PA is obtained, and a part of the output signal of the PA is coupled as a feedback signal;
  • the gain adjustment unit receives the feedback signal, adjusts the gain of the feedback signal, and obtains a feedback adjustment signal, and And outputting the feedback adjustment signal to the error generation unit;
  • the error generation unit receives the delay signal output by the core unit and the feedback adjustment signal output by the gain adjustment unit, generates an error signal of the feedforward signal and the feedback adjustment signal, and outputs the error signal to the training a unit;
  • the training unit receives an error signal output by
  • FIG. 1 is a schematic structural view of an APD correction system in the prior art
  • FIG. 2 is a schematic structural diagram of an APD correction system according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a core unit in an APD correction system according to an embodiment of the present disclosure
  • FIG. 4 is a second schematic structural diagram of a core unit in an APD correction system according to an embodiment of the present invention.
  • FIG. 5 is a third schematic structural diagram of a core unit in an APD correction system according to an embodiment of the present disclosure.
  • FIG. 6 is a fourth schematic structural diagram of a core unit in an APD correction system according to an embodiment of the present disclosure.
  • FIG. 7 is a fifth schematic structural diagram of a core unit in an APD correction system according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a nonlinear module in a core unit of an APD correction system according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of a digital vector modulator in a core unit of an APD correction system according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of an APD correction system according to Embodiment 1 of the present invention.
  • FIG. 11 is a schematic structural diagram of an APD correction system according to Embodiment 2 of the present invention.
  • FIG. 12 is a schematic structural diagram of a quadrature demodulator in a training unit of an APD correction system according to Embodiment 2 of the present invention.
  • FIG. 13 is a schematic flowchart of an APD correction method according to an embodiment of the present disclosure.
  • FIG. 14 is a second schematic structural diagram of an APD correction system according to an embodiment of the present disclosure.
  • FIG. 15 is a sixth structural diagram of a core unit in an APD correction system according to an embodiment of the present invention.
  • FIG. 16 is a second schematic flowchart of an APD correction method according to an embodiment of the present invention.
  • an embodiment of the present invention provides an APD correction system and method.
  • the preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used. The invention is illustrated and described, and is not intended to limit the invention. And in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.
  • An embodiment of the present invention provides an APD correction system, as shown in FIG. 2, which may include a core unit 201, a gain adjustment unit 202, an error generation unit 203, and a training unit 204, where:
  • the core unit 201 is configured to receive the system input signal and the APD coefficient output by the training unit 204; delay the system input signal to obtain N delay signals of different delays, wherein one of the delay signals is output as a feedforward signal to the error
  • the generating unit 203, N is an integer not less than 1; and according to the system input signal, the N-channel delay signal and the APD coefficient, the PA input signal is obtained, the PA amplifies the input signal, and the PA output signal is coupled. Part of it as a feedback signal;
  • the gain adjustment unit 202 is configured to receive a feedback signal, adjust the gain of the feedback signal, obtain a feedback adjustment signal, that is, the adjusted feedback signal, and output the feedback adjustment signal to the error generation unit 203;
  • the error generating unit 203 is configured to receive the feedforward signal output by the core unit 201 and the feedback adjustment signal output by the gain adjustment unit 202, and generate an error signal of the feedforward signal and the feedback adjustment signal. And outputting the error signal to the training unit 204;
  • the training unit 204 is configured to receive an error signal output by the error generating unit 203, determine an APD coefficient according to the error signal, and output the APD coefficient to the core unit 201.
  • the training unit 204 adjusts the linear characteristic and the nonlinear characteristic of the core unit 201 by adjusting the APD coefficient, so that the error signal is as close as possible to zero, that is, the feedback adjustment signal is consistent with the feedforward signal, that is, the PA output signal is made.
  • the PA phase predistortion is achieved by the amplitude and phase modulation information of the input signal of the system, that is, the amplitude and phase of the signal change with time.
  • the core unit 201 has multiple implementation manners, for example:
  • the core unit 201 includes N delays, nonlinear modules, M DVM (Digital Vector Modulator) and adder, and the APD coefficients include nonlinear coefficients and M linear coefficients, 1 ⁇ M ⁇ N+ 1, where:
  • N delay devices are connected in series for delaying the input signal of the system to obtain delayed signals of N different delays;
  • a nonlinear module for generating a nonlinear predistortion signal according to a system input signal, N delay signals of different delays, and nonlinear coefficients;
  • M DVMs one of which is the central DVM, and the other M-1 DVMs are used as non-central digital vector modulators; one of the N+1 signals consisting of the system input signal and the N delay signals with different delays The center delay signal, the other N signals are used as the non-center delay signal; among the M linear coefficients, one linear coefficient corresponds to the center delay signal, and the other M-1 linear coefficients and N of the N non-central delay signals -1 way non-center delay signal one-to-one correspondence; central DVM multiplies the center delay signal and corresponding linear coefficient, and each non-center DVM performs one non-center delay signal in the M-1 non-center delay signal Multiplication with corresponding linear coefficients;
  • the adder performs addition of the nonlinear predistortion signal and the output signals of the M DVMs to obtain an input signal of the PA.
  • the core unit 201 implemented by the mode 1 is as shown in FIG. 3, At this time, the delay signal with the largest delay relative to the input signal of the system can be selected as the feedforward signal.
  • the core unit 201 can also use two adders, a first adder and a second adder, the first adder performs the addition of the output signals of the M DVMs, and the second adder performs the nonlinear predistortion signal,
  • the addition of the output signal of the first adder, and the connection between the first adder and the second adder via the buffer amplifier Buf, can prevent the interference of the feedforward signal caused by the forward leakage of the output signal of the core unit 201.
  • the feedback adjustment signal is consistent with the feedforward signal by adjusting the APD coefficient. Therefore, the feedforward signal is substantially a learning template signal of the feedback adjustment signal, and the feedforward signal is deteriorated by the interference. System performance.
  • the core unit 201 shown in FIG. 3 is as shown in FIG.
  • the core unit 201 includes N delays, nonlinear modules, M DVMs, and adders.
  • the APD coefficients include nonlinear coefficients and M linear coefficients, 1 ⁇ M ⁇ N +1, where:
  • N delay devices are connected in series for delaying the input signal of the system to obtain delayed signals of N different delays;
  • a nonlinear module for generating a nonlinear predistortion signal according to a system input signal, N delay signals of different delays, and nonlinear coefficients;
  • M DVMs one of which is the latter DVM, the other M-1 DVMs are used as the front DVM; among the N+1 signals consisting of the system input signal and the N delay signals with different delays, one signal is used as the center delay signal.
  • the other N signals are used as non-center delay signals; among the M linear coefficients, one linear coefficient corresponds to the output signal of the adder, and the other M-1 linear coefficients and the M-1 road in the N non-central delay signals
  • the non-central delay signals are in one-to-one correspondence; each pre-DVM performs multiplication of a non-central delay signal in the M-1 way non-center delay signal with a corresponding linear coefficient;
  • An adder that performs addition of a nonlinear predistortion signal, a center delay signal, and an output signal of M-1 pre-DVMs;
  • the post DVM performs multiplication of the output signal of the adder with the corresponding linear coefficient to obtain an input signal of the PA.
  • the DVM at the output end can adjust the power level of the signal, so that the output signal of the core unit 201 is adapted to the power level requirements of the input signals of different PAs.
  • the selection of the center delay signal and the feedforward signal may follow the following principle: the sum of the delay length of the center delay signal relative to the system input signal and the delay length of the PA is approximately equal to the former The length of the delay of the feed signal relative to the system input signal.
  • the delay length of the center delay signal relative to the system input signal may be approximately half of the delay length of the delay signal with the largest delay relative to the system input signal; after selecting the center delay signal, The above principle determines which delay signal is selected as the feedforward signal.
  • the feedforward signal can be determined first and then the center delay signal is determined, which is not limited herein.
  • the core unit 201 implemented by the second method includes two delays, a nonlinear module, three DVMs, and an adder, as shown in FIG. 5;
  • the delay length of the device 1 is equal to the delay length of the delay device 2 equal to the delay length of the PA, and the two delay devices are connected in series to delay the input signal of the system to obtain two delay signals with different delays;
  • the delay signal outputted by the delay device 1 is used as the center delay signal, and the delay signal outputted by the delay device 2 is used as the feedforward signal and also as the non-central delay signal;
  • the nonlinear module is different according to the system input signal and the 2 way.
  • the delayed delay signal and the nonlinear coefficient generate a nonlinear predistortion signal; in 3 DVMs, DVM0 is used as the post DVM, DVM1 and DVM2 are used as the front DVM; DVM1 is used to multiply the system input signal and the linear coefficient 1, and DVM2 is extended.
  • the delay signal output by the timer 2 is multiplied by the linear coefficient 2; the adder performs the addition of the nonlinear predistortion signal, the delay signal outputted by the delayer 1, the output signal of the DVM1, and the output signal of the DVM2; DVM3 Perform the output signal of the adder with a linear coefficient of 3 Calculation method, the input signal to obtain the PA.
  • the core unit 201 can also use two adders, a first adder and a second adder, the first adder performs the addition of the center delay signal and the output signals of the N pre-DVMs, and the second adder performs the second adder.
  • the nonlinear predistortion signal, the addition of the output signal of the first adder, and the first adder and the second adder are connected by the buffer amplifier Buf, which can prevent the output signal of the core unit 201 from leaking forward. The interference of the feedforward signal.
  • the core unit 201 shown in FIG. 5 is as shown in FIG. 6.
  • the core unit 201 implemented by the second method is as shown in FIG. 7, and includes one delay device, a nonlinear module, two DVMs, and an adder;
  • the delay signal output by the timer is used as the feedforward signal, and the system input signal is used as the center delay signal, and the delay signal output by the delay device is used as the non-center delay signal.
  • the specific structure and modified structure are not described in detail herein.
  • the number N of delay devices may be an odd number or an even number; the delay lengths of the N delay devices may be different or the same.
  • the number of specific delays and the length of the delay can be set based on actual needs, which is not limited herein.
  • N delay devices may also be connected in other manners, as long as N delay signals with different delays can be obtained, N delay devices Any connection method can be used. For example, multiple delays can be used in series to obtain multiple delay signals with different delays. One of the delay signals is used as the center delay signal, and a special delay device is used to delay the input signal of the system to generate feedforward. The signal, or a dedicated delayer, delays one of the multiple delayed signals of different delays to generate a feedforward signal.
  • the non-linear module may specifically include the envelope submodule 801 and the action matrix submodule 802, as shown in FIG.
  • the envelope sub-module 801 is configured to receive the input signal of the system, perform envelope detection on the input signal of the system, obtain an input envelope signal of different delays of the L channel, and output the input envelope signal of the L delay with different delays to the function.
  • the matrix sub-module 802; L is an integer not less than 1, and may be equal to N or may be equal to N;
  • the action matrix sub-module 802 is configured to receive N delay signals of different delays, input envelope signals of different delays of L channels, and nonlinear coefficients, according to different delayed delay signals of the N channels, and different delays of the L paths
  • the input envelope signal and the nonlinear coefficient form a nonlinear predistortion signal.
  • envelope sub-module 801 and the action matrix sub-module 802 are prior art and will not be described in detail herein.
  • the DVM may be implemented by using the structure shown in FIG. 9, including a QPS (Quadrature Phase Splitter), a subtractor, and
  • QPS Quadrature Phase Splitter
  • each of the above linear coefficients is a complex coefficient
  • the real part of the complex coefficient is the in-phase coefficient shown in FIG. 9
  • the imaginary part of the complex coefficient is the orthogonal coefficient shown in FIG. 9, specifically:
  • One multiplier of the two multipliers performs multiplication of the in-phase signal and the in-phase coefficient of the QPS output; the other multiplier performs multiplication of the orthogonal signal of the QPS output and the orthogonal coefficient;
  • the subtracter performs a subtraction of the output signals of the two multipliers; the output signal of the subtractor is the output signal of the DVM.
  • the gain adjustment unit 202 can be implemented by a VGA (Variable Gain Amplifier), and the gain of the VGA is related to the gain of the output signal of the system input signal to the PA, so the actual implementation
  • the gain of the VGA can be configured according to the gain requirement of the system input signal to the output signal of the PA.
  • the error generating unit 203 may be implemented by a subtractor that performs a subtraction operation of the feedforward signal and the feedback adjustment signal, that is, an error signal of the feedforward signal and the feedback adjustment signal.
  • the training unit 204 also has various implementation manners, which will be described in detail below with reference to the accompanying drawings.
  • the core unit 201 may be implemented in the foregoing manner, or may be implemented in the foregoing manner; the gain adjustment unit 202 may be implemented by using a VGA; and the error generation unit 203 may be implemented.
  • the subtraction unit is implemented; the training unit 204 determines the APD coefficient according to the power of the error signal output by the error generating unit 203.
  • the training unit 204 may include a VGA, a PDET (Power Detector), and an ADC (Analog to Digital). Converter, analog to digital converter) and coefficient training module, where:
  • VGA for receiving an error signal, adjusting the gain of the error signal to obtain an error adjustment signal, and outputting the error adjustment signal to the PDET;
  • the PDET is configured to receive an error adjustment signal of the VGA output, detect an average power of the error adjustment signal, obtain an error power signal, and output the error power signal to the ADC;
  • the ADC is configured to receive an error power signal output by the PDET, perform analog-to-digital conversion on the error power signal, obtain an error power digital signal, and output the error power digital signal to the coefficient training module;
  • the coefficient training module is configured to receive an error power digital signal output by the ADC, and determine an APD coefficient according to the error power digital signal, so that the error power digital signal approaches 0.
  • the coefficient training module can perform AGC (Automatic Gain Control) on the VGA to control the gain of the VGA, thereby controlling the adjustment range of the gain of the error signal, so that the error power signal input by the ADC is always close to the ADC.
  • AGC Automatic Gain Control
  • the size of the signal is good for coefficient training.
  • the APD correction system provided by Embodiment 1 of the present invention does not require a receiver; the ADC in the training unit 204 performs analog-to-digital conversion on the error power signal, and since the error power signal is a signal that changes slowly with time, the ADC is Low performance requirements are not only easy to implement, but also greatly reduce system cost.
  • the core unit 201 may be implemented in the foregoing manner, or may be implemented in the foregoing manner; the gain adjustment unit 202 may be implemented by using a VGA; and the error generation unit 203 may be implemented.
  • a subtractor implementation; training unit 204 which can include a receiver and a coefficient training module, wherein:
  • the receiver is configured to receive an error signal, perform down-conversion and analog-to-digital conversion processing on the error signal, obtain an error digital signal, and output the error digital signal to the coefficient training module;
  • the coefficient training module is configured to receive an error digital signal output by the receiver, and determine an APD coefficient according to the error digital signal, so that the error digital signal approaches 0.
  • the above receiver may specifically be in the form shown in FIG. 11, including a VGA, a QDM (Quadrature Demodulator), and two ADCs, and the coefficient training module performs AGC on the VGA in the receiver; wherein:
  • VGA adjusts the gain of the input signal of the receiver
  • QDM performs down-conversion processing on the output signal of the VGA
  • the two ADCs respectively perform analog-to-digital conversion processing on the two output signals of the QDM; the output signals of the two ADCs are the output signals of the receiver.
  • the QDM structure in Figure 11 is shown in Figure 12, including a -90° phase shifter, two multipliers, and two LPFs (Low-Pass Filters), where:
  • the -90° phase shifter performs a -90° phase shift on the local oscillator signal to obtain a local oscillator signal after phase shifting;
  • One of the two multipliers performs multiplication of the QDM input signal and the local oscillator signal; the other multiplier performs multiplication of the QDM input signal and the phase-shifted local oscillator signal;
  • the two LPFs respectively filter the output signals of the two multipliers; the output signals of the two LPFs are the output signals of the QDM.
  • receivers may also be other types of receivers in the prior art, which are not limited by the present invention.
  • Embodiment 2 of the present invention With the APD correction system provided by Embodiment 2 of the present invention, only one receiver is needed, which is easier to implement and lowers the system cost than the prior art.
  • the APD correction system according to the above embodiment of the present invention, correspondingly, the embodiment of the present invention further provides an APD correction method, which is shown in FIG.
  • Step 1301 delaying the input signal of the system to obtain a delay signal of N different delays, where N is an integer not less than 1;
  • Step 1302 Obtain an input signal of the power amplifier PA according to the input signal of the system, the delayed signal of the N different delays, and the APD coefficient; wherein the APD coefficient is determined as follows:
  • a part of the output signal of the PA is coupled as a feedback signal, and the gain of the feedback signal is adjusted to obtain a feedback adjustment signal; a delay signal in the N-way delay signal is used as a feedforward signal to generate a feedforward signal and a feedback adjustment signal.
  • the error signal based on the error signal, the APD coefficient is determined.
  • generating an error signal of the feedforward signal and the feedback adjustment signal that is, performing a feedforward signal And the feedback adjustment signal is subtracted, and the obtained signal is the error signal of the feedforward signal and the feedback adjustment signal.
  • determining the APD coefficient according to the error signal may specifically include:
  • the APD coefficient is determined based on the power of the error signal.
  • determining the APD coefficient according to the power of the error signal may specifically include:
  • Adjusting the gain of the error signal to obtain an error adjustment signal ; detecting an average power of the error adjustment signal to obtain an error power signal; performing analog-to-digital conversion on the error power signal to obtain an error power digital signal; A digital signal that determines the APD coefficient.
  • determining the APD coefficient according to the error signal may specifically include:
  • the error signal is subjected to down-conversion and analog-to-digital conversion processing to obtain an error digital signal; and the APD coefficient is determined according to the error digital signal.
  • the APD coefficient includes a nonlinear coefficient and M linear coefficients, 1 ⁇ M ⁇ N+1; and step 1302 is based on the system input signal, the N-channel delayed delay signal, and the APD.
  • the coefficient obtains the input signal of the PA, and specifically includes:
  • a nonlinear predistortion signal according to the input signal of the system, the delay signal of the N different delays, and the nonlinear coefficient; the N+1 path formed by the input signal of the system and the delay signal of the N different delays In the signal, one signal is used as the center delay signal, and the other N signals are used as the non-central delay signal; among the M linear coefficients, M-1 linear coefficients and M-1 non-center delay signals
  • the central delay signals are in one-to-one correspondence; performing multiplication of each non-central delay signal in the M-1 way non-center delay signal with a corresponding linear coefficient; performing the nonlinear predistortion signal, the center delay signal, Addition of output signals of M-1 multiplication operations; among the M linear coefficients, a linear coefficient other than the M-1 linear coefficients corresponds to an output signal of the addition; an output signal of the addition operation is performed Corresponding to the multiplication of the linear coefficients, the input signal of the PA is obtained.
  • the APD coefficient includes a nonlinear coefficient and M linear coefficients, 1 ⁇ M ⁇ N+1; and step 1302 is based on the input signal of the system and the delay of the N different delays.
  • the time signal and the APD coefficient are used to obtain an input signal of the PA, which may specifically include:
  • N ⁇ 2 the sum of the delay length of the center delay signal relative to the system input signal and the delay length of the PA is substantially equal to the delay length of the feedforward signal relative to the system input signal.
  • processing steps in the above process may correspond to the functions of the corresponding units shown in FIG. 2 to FIG. 12, and details are not described herein again.
  • an embodiment of the present invention further provides an APD correction system, as shown in FIG. 14, which may include a core unit 1401, a gain adjustment unit 1402, an error generation unit 1403, and a training unit 1404, where:
  • the core unit 1401 is configured to receive a system input signal and an APD coefficient output by the training unit 1404, and obtain an input signal of the power amplifier PA according to the system input signal and the APD coefficient, and a part of the PA output signal is coupled as a feedback signal;
  • the gain adjustment unit 1402 is configured to receive a feedback signal, adjust the gain of the feedback signal, obtain a feedback adjustment signal, and output the feedback adjustment signal to the error generation unit 1403;
  • the error generating unit 1403 is configured to receive the system input signal and the feedback adjustment signal output by the gain adjustment unit 1402, and the system input signal is used as a feedforward signal to generate an error signal of the feedforward signal and the feedback adjustment signal, and output the error signal to the training unit 1404. ;
  • the training unit 1404 is configured to receive an error signal output by the error generating unit 1403, determine an APD coefficient according to the error signal, and output the APD coefficient to the core unit 1401.
  • the training unit 1404 which can be seen in FIG. 10, includes Variable gain amplifier, power detector, analog to digital converter and coefficient training module, wherein:
  • variable gain amplifier for adjusting the gain of the error signal to obtain an error adjustment signal
  • a power detector for detecting an average power of the error adjustment signal to obtain an error power signal
  • An analog-to-digital converter for performing analog-to-digital conversion on the error power signal to obtain an error power digital signal
  • a coefficient training module for determining an APD coefficient based on the error power digital signal.
  • the training unit 1404 includes a receiver and a coefficient training module, wherein:
  • a receiver for performing down-conversion and analog-to-digital conversion processing on the error signal to obtain an error digital signal
  • a coefficient training module for determining an APD coefficient based on the error digital signal.
  • the core unit 1401 has various implementation manners, for example:
  • the core unit 1401 includes a nonlinear module, a digital vector modulator, and an adder, and the APD coefficients include a nonlinear coefficient and a linear coefficient, wherein:
  • a nonlinear module for generating a nonlinear predistortion signal based on a system input signal and a nonlinear coefficient
  • An adder for performing addition of a nonlinear predistortion signal and a system input signal
  • the digital vector modulator performs multiplication of the output signal of the adder and the linear coefficient to obtain an input signal of the PA.
  • the core unit 1401 includes a nonlinear module, a digital vector modulator and an adder, and the APD coefficients include a nonlinear coefficient and a linear coefficient, wherein:
  • a nonlinear module for generating a nonlinear predistortion signal based on a system input signal and a nonlinear coefficient
  • the adder performs addition of the nonlinear predistortion signal and the output signal of the digital vector modulator to obtain an input signal of the PA.
  • the gain adjustment unit 1402 can be implemented by a VGA.
  • the error generating unit 1403 may be implemented by a subtractor that performs a subtraction operation of the feedforward signal and the feedback adjustment signal, that is, obtains an error of the feedforward signal and the feedback adjustment signal. signal.
  • the embodiment of the present invention further provides an APD correction method, which is shown in FIG.
  • Step 1601 A part of the output signal of the power amplifier PA is coupled as a feedback signal, and the gain of the feedback signal is adjusted to obtain a feedback adjustment signal.
  • Step 1602 The system input signal is used as a feedforward signal, and the error signal of the feedforward signal and the feedback adjustment signal is generated.
  • Step 1603 determining the APD coefficient according to the error signal
  • Step 1604 Obtain an input signal of the PA according to the system input signal and the APD coefficient.
  • Step 1602 generates an error signal of the feedforward signal and the feedback adjustment signal, that is, performs subtraction of the feedforward signal and the feedback adjustment signal, and the obtained signal is an error signal of the feedforward signal and the feedback adjustment signal.
  • the step 1603 determines the APD coefficient according to the error signal, which may specifically include:
  • Adjusting the gain of the error signal to obtain an error adjustment signal adjusting the signal for the error
  • the average power is detected to obtain an error power signal; the error power signal is subjected to analog-to-digital conversion to obtain an error power digital signal; and the APD coefficient is determined according to the error power digital signal.
  • the step 1603 determines the APD coefficient according to the error signal, which may specifically include:
  • the error signal is subjected to down-conversion and analog-to-digital conversion processing to obtain an error digital signal; and the APD coefficient is determined according to the error digital signal.
  • the APD coefficient includes a nonlinear coefficient and a linear coefficient; and the step 1604 obtains an input signal of the PA according to the input signal of the system and the APD coefficient, which may specifically include:
  • the APD coefficient includes a non-linear coefficient and a linear coefficient.
  • the input signal of the PA is obtained according to the input signal of the system and the APD coefficient, which may specifically include:
  • processing steps in the above process may correspond to the functions of the corresponding units shown in FIG. 14 to FIG. 15, and details are not described herein again.
  • the APD correction scheme provided by the embodiment of the present invention is easier to implement and has lower cost.
  • the coefficient training module of the training unit can be implemented by a digital circuit (including an optional AGC part), and other parts are implemented by using an analog circuit.
  • the APD correction scheme provided in any of the above embodiments may be applied to a system that requires APD, such as a mobile communication system, a wireless transmission system, or a radar system.
  • APD correction The scheme can be, but is not limited to, applied to a base station in a mobile communication system.
  • the embodiment of the invention further provides a base station, including any one of the above APD correction systems.
  • the signal to be transmitted that needs to be power amplified is used as the system input signal of the APD correction system, and the APD correction system generates the input signal of the PA. Since the distortion generated by the PA is corrected by the APD correction system, the output signal of the PA is relatively The input signal of the system has no distortion, that is, the signal to be transmitted after power amplification has no distortion, and the communication quality is ensured.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in a block or blocks of a flow or a flow and/or a block diagram of a flowchart Step.

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  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Amplifiers (AREA)

Abstract

L'invention concerne un système et un procédé de correction de pré-distorsion analogique (APD), facile à mettre en œuvre. Le système comprend une unité de noyau, une unité de réglage de gain, une unité de génération d'erreur, et une unité d'entraînement, l'unité de noyau retardant un signal d'entrée de système de façon à obtenir N signaux de retard pour différents retards, et l'un des signaux de retard, servant de signal de couplage vers l'avant, est délivré à l'unité de génération d'erreur, N étant un nombre entier qui n'est pas inférieur à 1 ; obtenir, selon le signal d'entrée de système, les N signaux de retard pour différents retards, et un coefficient d'APD, un signal d'entrée d'un amplificateur de puissance (PA), certains des signaux de sortie du PA étant couplés en tant que signaux de rétroaction ; l'unité de réglage de gain règle des gains des signaux de rétroaction de manière à obtenir un signal de réglage de rétroaction, et délivre en sortie le signal de réglage de rétroaction à l'unité de génération d'erreur ; l'unité de génération d'erreurs génère des signaux d'erreur du signal de couplage vers l'avant et du signal de réglage de rétroaction, et délivre en sortie les signaux d'erreur à l'unité d'entraînement ; et l'unité d'entraînement détermine, selon les signaux d'erreur, un coefficient d'APD, et délivre en sortie le coefficient d'APD à l'unité de noyau.
PCT/CN2015/080442 2015-05-30 2015-05-30 Système et procédé de correction de pré-distorsion analogique (apd) WO2016191993A1 (fr)

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