WO2016166834A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2016166834A1
WO2016166834A1 PCT/JP2015/061573 JP2015061573W WO2016166834A1 WO 2016166834 A1 WO2016166834 A1 WO 2016166834A1 JP 2015061573 W JP2015061573 W JP 2015061573W WO 2016166834 A1 WO2016166834 A1 WO 2016166834A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
mold resin
lead frame
resin
frame
Prior art date
Application number
PCT/JP2015/061573
Other languages
English (en)
French (fr)
Inventor
孝信 梶原
大前　勝彦
俊祐 伏江
椋田　宗明
中島　大輔
誠裕 元岡
宏幸 宮西
有紀 仲松
淳也 鈴木
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2015/061573 priority Critical patent/WO2016166834A1/ja
Priority to JP2017512118A priority patent/JP6266168B2/ja
Priority to EP15889172.1A priority patent/EP3285288B1/en
Priority to US15/536,192 priority patent/US10262912B2/en
Publication of WO2016166834A1 publication Critical patent/WO2016166834A1/ja

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    • H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • the present invention relates to a resin mold type semiconductor device, and more particularly to a semiconductor device sealed entirely with a mold resin.
  • Semiconductor devices for power are semiconductor elements after die-bonding semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal-Oxide-Semiconductors, Field-Effect Transistors), IC chips, LSI chips to lead frames for external terminals.
  • IGBTs Insulated Gate Bipolar Transistors
  • MOSFETs Metal-Oxide-Semiconductors, Field-Effect Transistors
  • IC chips LSI chips to lead frames for external terminals.
  • the electrodes and the external terminals are electrically connected with wires or inner leads to input / output signals from / to the outside.
  • the surface (mounting surface) of the lead frame on which the semiconductor element is mounted and the heat radiation surface on the opposite side are sealed with mold resin. Since a power semiconductor device includes a high heat generating element therein, the mold resin is required to have high heat dissipation.
  • the mounting surface of the lead frame is sealed with a low-stress resin used as a mold resin for a general integrated circuit, and the heat dissipation surface has a thermal conductivity of 4 to 10 W / m ⁇ Sealed with K high heat dissipation resin.
  • Patent Document 1 when sealing is performed using two types of resins, a high heat dissipation resin and a low stress resin, as in Patent Document 1, there is a problem that the adhesion between the resins is poor.
  • a method for sufficiently adhering the high heat dissipation resin and the low stress resin in Patent Document 1, the outer peripheral end portion of the high heat dissipation resin covering the heat dissipation surface of the lead frame is positioned inside the outer peripheral end portion of the lead frame, and semi-cured. The high heat dissipation resin in the state is sealed with a low stress resin.
  • Patent Document 1 When two types of resins are used as in Patent Document 1, a mold resin having a large amount of filler and a high viscosity is used as the high heat dissipation resin. For this reason, when the molding is performed by the transfer method, the fluidity of the resin is poor, and it is difficult to get wet with the low stress resin or the lead frame. As a result, the molded high heat dissipation resin has low adhesion to the low stress resin and the lead frame, and when discharged from the molding die, the interface between the two types of mold resin or the interface between the lead frame and the high heat dissipation resin. Stress acted, and initial peeling sometimes occurred at the interface immediately after transfer molding.
  • the resin remaining in the gate which is the resin path in the mold used for transfer molding, is called a runner, but after transfer molding, the gate break that separates the runner from the semiconductor device immediately after removing the semiconductor device from the mold. As a result, a gate break remains in the semiconductor device.
  • the present invention has been made in view of the above circumstances, and in a semiconductor device using two types of mold resin, the adhesion between the two types of mold resin or the adhesion between the lead frame and the mold resin is improved, and the gate portion is formed. It is an object of the present invention to obtain a semiconductor device excellent in heat dissipation and insulation, which is less likely to cause peeling or chipping of a thin molded portion of a mold resin on the heat dissipation surface even when transfer molding is performed with a mold having the same.
  • a semiconductor device includes a lead frame on which a semiconductor element is mounted, a first mold resin that seals a mounting surface that is a surface on which the semiconductor element of the lead frame is mounted, and a surface opposite to the mounting surface of the lead frame.
  • a second mold resin that seals the heat dissipating surface that is the side surface, and a frame-shaped projection formed by the first mold resin and the second mold resin at the outer peripheral end of the heat dissipating surface of the lead frame.
  • the two opposite sides of the frame-shaped protrusion and the thin molded part that covers the two sides are formed integrally with the second mold resin, and the other two opposite sides of the frame-shaped protrusion are the first mold. It is molded from resin.
  • the two opposite sides of the frame-shaped protrusion and the thin molded portion covering the two sides are integrally formed with the second mold resin, and the other two opposite sides of the frame-shaped protrusion are the first. Since the molding is performed with one molding resin, the fluidity of the second molding resin to the thin molded portion is improved compared to the case where all four sides of the frame-shaped protrusion are molded in one transfer molding process. The second mold resin is easily wetted and the adhesion to the lead frame is increased.
  • FIG. 1 is a cross-sectional view showing a configuration of a resin mold type semiconductor device according to the first embodiment
  • FIG. 2 is a plan view of the semiconductor device after the first transfer molding process, as viewed from the heat radiation surface side
  • FIG. These are the top views which looked at the semiconductor device after the 2nd transfer molding process from the heat sinking side.
  • the same or corresponding parts are denoted by the same reference numerals.
  • a semiconductor device 100 includes a semiconductor element 1, a lead frame 2, external terminals 4, wires 5, inner leads 6, and the like.
  • a semiconductor element 1 such as an IGBT, a MOSFET, an IC chip, or an LSI chip is placed on an upper surface (hereinafter referred to as a mounting surface 2a) of a lead frame 2 via a bonding member 3 such as solder or silver.
  • the lead frame 2 is a copper plate or a copper alloy plate, and the surface thereof is coated with metal plating (not shown) such as gold, silver, nickel, tin or the like.
  • the electrode pad of the semiconductor element 1 is electrically connected to the external terminal 4 via the wire 5 connected by wire bonding or the inner lead 6 made of a copper plate or copper alloy plate material, I / O is performed.
  • the wire 5 and the inner lead 6 can be replaced with each other.
  • the wire 5 is made of gold, silver, aluminum, copper or the like, and the wire diameter is about 20 ⁇ m to 500 ⁇ m.
  • the lead frame 2 has a mounting surface 2a sealed with a first mold resin 7 and a heat radiating surface 2b opposite to the mounting surface 2a sealed with a second mold resin 8.
  • the first mold resin 7 is disposed between two spaced apart regions of the lead frame 2 (hereinafter referred to as “die pad 10”).
  • the heat radiating surface 2b of the lead frame 2 has a thickness of about 0.3 mm to 2 mm formed by the first mold resin 7 and the second mold resin 8 at the outer peripheral end thereof.
  • a skirt portion which is a frame-like projection is provided.
  • the skirt portion is composed of a first skirt portion 7 a formed from the first mold resin 7 and a second skirt portion 8 a formed from the second mold resin 8.
  • the first skirt portion 7a and the second skirt portion 8a have a rectangular, square, or trapezoidal cross-sectional shape cut in a direction orthogonal to their respective sides.
  • a thin molded portion 8b having a thickness of about 0.02 mm to 0.3 mm is integrally formed with the second skirt portion 8a by the second mold resin 8 between the second skirt portions 8a. Yes.
  • the first skirt portion 7a and the second skirt portion 8a are joined by four resin joint portions 9 to form a skirt portion surrounding the thin molded portion 8b.
  • the thin molded portion 8b is joined to a heat sink made of copper or aluminum via a heat radiating member such as grease.
  • the first mold resin 7 and the second mold resin 8 are both thermosetting epoxy resins. However, a high heat dissipation resin having higher thermal conductivity than the first mold resin 7 is used for the second mold resin 8 on the heat dissipation surface 2b side.
  • the thermal conductivity of the second mold resin 8 is 3 W / m ⁇ K to 12 W / m ⁇ K.
  • a low stress resin which is a mold resin of a general integrated circuit is used.
  • FIGS. 4 and 5 are cross-sectional views at the position indicated by AA in FIG.
  • the first mold resin 7 is melted by heat and pressure applied by the first molding die 20, and the lead frame 2 is installed through the upper gate 22.
  • the cavity 21 is injected.
  • the first mold resin 7 flows to the mounting surface 2a side of the lead frame 2 and fills the cavity 21, and also flows into the cavity corresponding to the first skirt portion 7a to mold the first skirt portion 7a.
  • the first molding resin 7 remaining inside the upper gate 22 of the first molding die 20 is called a runner 7b.
  • the upper gate break trace 7c (see FIG. 1) remains in the semiconductor device 100.
  • the first skirt portion that is two sides parallel to the upper gate 22 is formed on the heat radiating surface 2 b of the lead frame 2 after the first transfer molding process by the first mold resin 7. 7a is formed and the space 10 between the die pads is embedded.
  • a second transfer molding process is performed.
  • the first mold resin 7 may be subjected to UV treatment or plasma treatment after the first transfer molding step.
  • the lead frame 2 in which the mounting surface 2a is sealed after the first transfer molding process is completed.
  • a cavity 31 is formed on the heat dissipating surface 2 b side of the lead frame 2.
  • the second molding resin 8 is melted by the heat and pressure applied by the second molding die 30, passes through the cavity 31 corresponding to the second skirt portion 8a near the lower gate 32, and corresponds to the thin molding portion 8b. It flows into the cavity 31 that does. At this time, since the second mold resin 8 once accumulates in the second skirt portion 8a near the lower gate 32, it can flow uniformly to the thin molded portion 8b. The second mold resin 8 that has passed through the thin molded portion 8b further flows into the cavity 31 corresponding to the second skirt portion 8a on the opposite side farthest from the lower gate 32 serving as the final filling portion.
  • the second mold resin 8 is hardened and has a high viscosity, but the second skirt portion 8a, which is the final filling portion, is thicker than the thin molded portion 8b, and therefore has a low flow resistance.
  • the mold resin 8 is easy to flow.
  • the second skirt portion 8a and the thin molded portion 8b are molded by the second mold resin 8, and immediately after the molded product is taken out from the second molding die 30, the molded product is removed.
  • a gate break process is performed to separate the runner. After the gate break, the lower gate break mark 8c (see FIG. 1) remains in the semiconductor device 100.
  • the second skirt portion 8a including the side closest to the lower gate 32 and the thin-wall molding covering the two sides are provided.
  • the portion 8 b is integrally formed with the second mold resin 8.
  • the position of the upper gate break mark 7c (that is, the position of the upper gate 22 of the first molding die 20 used in the first transfer molding step) is limited to the position shown in FIG.
  • the number is not limited to one, and a plurality of them may exist. For example, as shown in FIG. 6, you may have the three upper gate break traces 7c in the position near the 1st skirt part 7a.
  • the first skirt portion 7 a formed by the first mold resin 7 is located on the long side, and the second side
  • the second skirt portion 8a formed by the mold resin 8 is located on the short side, but the reverse may be possible depending on the position of the gate of the molding die used.
  • the surface of the lead frame 2 is coated with metal plating such as gold, silver, nickel, tin, etc., but it may not be coated.
  • the lead frame 2 having a uniform thickness is used.
  • a lead frame having a partially different thickness may be used.
  • the cost becomes high.
  • the heat sink is joined to the thin molded portion 8b via a heat radiating member such as grease.
  • the heat radiating member may not be used.
  • the surface opposite to the mounting surface 2a is the heat dissipation surface, but the mounting surface 2b may have the same heat dissipation property.
  • the first mold resin 7 may be a high heat dissipation resin having a thermal conductivity of 3 W / m ⁇ K to 12 W / m ⁇ K, similar to the second mold resin 8.
  • the first skirt portion 7a is formed with the first mold resin 7 in the first transfer molding step, and the second skirt portion 8a and the thin-walled molded portion are formed in the second transfer molding step.
  • the flow of the second mold resin 8 to the thin molded portion 8b is compared with the case where all four sides of the skirt portion are molded in a single transfer molding process. Since the second mold resin 8 is easily wetted, the adhesion between the thin molded portion 8b and the lead frame 2 is improved.
  • the adhesion between the first mold resin 7 and the second mold resin 8 and the adhesion between the lead frame 2 and the second mold resin 8 can be improved.
  • the thin molded part 8b is hardly peeled off or chipped, and the highly reliable semiconductor device 100 having excellent heat dissipation and insulation can be obtained.
  • FIG. FIG. 7 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment of the present invention.
  • the semiconductor device 101 according to the second embodiment is a modification of the semiconductor device 100 according to the first embodiment, and since the overall configuration is the same, only the differences will be described.
  • the skirt portion of the semiconductor device 100 has a rectangular, square, or trapezoidal cross-sectional shape cut in a direction orthogonal to each side (see FIG. 1).
  • the skirt portion of the semiconductor device 101 according to the second embodiment has a tip portion whose cross-sectional shape cut in a direction orthogonal to each side thereof is an arc shape.
  • FIG. 7 only the second skirt portion 8d is shown, but the first skirt portion similarly has a tip portion having an arcuate cross section cut in a direction perpendicular to each side thereof. is doing.
  • a manufacturing process of the semiconductor device 101 according to the second embodiment will be described with reference to FIG.
  • the semiconductor device 101 is manufactured including two molding steps, and the first transfer molding step similar to that of the first embodiment is performed (see FIG. 4).
  • the second time the compression molding process shown in FIG. 8 is performed.
  • compression molding a tablet-like or granule-like second molding resin 8 is previously installed in a cavity 41 inside the third molding die 40, and the third molding die 40 has a lower gate. Absent.
  • the lower part (movable part) of the third molding die 40 moves in the direction of arrow A, and pressurizes the cavity 41 in a predetermined manner. Stop at the position. Thereby, the thin molding part 8b and the second skirt part 8d are molded by the second mold resin 8.
  • the molten second mold resin 8 is obtained by adsorbing a film made of thermoplastic fluororesin having a thickness of about 40 ⁇ m to 100 ⁇ m to the inner surface of the third molding die 40. Intrusion into the movable part of the third molding die 40 is prevented.
  • the film 42 follows the internal shape of the third molding die 40 when the movable part of the third molding die 40 pressurizes the second molding resin 8. Therefore, if there is an edge portion in the internal shape of the third molding die 40, the film 42 hits the edge portion and is broken, and the second mold resin 8 enters the movable portion of the third molding die 40 from the damaged portion. It will be.
  • the cross-sectional shape of the tip portion of the skirt portion is made arcuate to eliminate the edge portion.
  • the tip of the skirt may have a cross-sectional shape that does not damage the film 42 in compression molding. Therefore, the cross-sectional shape cut
  • the cross-sectional shape of the tip of the skirt portion is rounded at the corners of an arc or a rectangle. It is possible to employ compression molding in the second molding process for sealing the surface 2b. Thereby, the installation cost of a metal mold
  • the semiconductor device 101 according to the second embodiment can also be manufactured by two transfer molding steps similar to those in the first embodiment.
  • FIG. 9 is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment of the present invention.
  • the semiconductor device 102 according to the third embodiment is a modification of the semiconductor device 100 according to the first embodiment, and since the overall configuration is the same, only the differences will be described.
  • the first mold resin 7 is disposed between the die pads 10 of the lead frame 2.
  • the semiconductor device 102 according to the third embodiment among the plurality of die pads 10 existing in the lead frame 2, at least some of the die pads 10 are formed by the second mold resin 8.
  • An inter-frame filling portion (hereinafter referred to as inter-die pad filling portions 8e and 8f) is disposed. In the example shown in FIG. 9, inter-die pad filling portions 8 e and 8 f are arranged between two die pads 10.
  • the burrs 2c may be provided on a part of the side surface of the lead frame 2 where the inter-die pad filling portion 8e is disposed. By forming the burrs 2c on the side surfaces of the lead frame 2 by pressing, the adhesion with the inter-die pad filling portion 8e is further improved by the anchor effect.
  • the thin molded portion 8b is partially thickened by the inter-die pad filling portions 8e and 8f, the strength of the thin molded portion 8b is improved, and chipping and cracking are less likely to occur. Furthermore, the heat dissipation is improved by increasing the area where the lead frame 2 serving as a heat dissipation path and the second mold resin 8 which is a high heat dissipation resin are in close contact with each other. In the third embodiment, the heat dissipation is further improved by covering the side surface of the lead frame 2 with the second mold resin 8 which is a high heat dissipation resin.
  • the semiconductor device 102 according to the third embodiment is manufactured by including two transfer molding steps as in the first embodiment. However, as shown in FIG. 11, in the first transfer molding process, the pins 23 are inserted from the first molding die 20 so that the first molding resin 7 is not filled between some die pads 10. Yes.
  • the second mold resin 8 is filled into a part of the die pads 10 not filled with the first mold resin 7, and the inter-die pad filling parts 8e and 8f, the thin-walled molding part. 8b and the second skirt portion 8a are integrally formed.
  • the inter-die pad filling portion 8e integrally formed with the thin molded portion 8b is formed between some die pads 10 of the lead frame 2.
  • the adhesion between the thin molded portion 8b and the lead frame 2 is improved.
  • the burrs 2c on the side surface of the lead frame 2 in which the inter-die pad filling portion 8e is disposed the adhesion is further improved by the anchor effect.
  • FIG. 12 is a cross-sectional view showing the configuration of the semiconductor device according to the fourth embodiment of the present invention.
  • the semiconductor device 103 according to the fourth embodiment is a modification of the semiconductor device 100 according to the first embodiment, and since the overall configuration is the same, only the differences will be described.
  • the semiconductor device 103 includes an electronic component (hereinafter referred to as a bridge mounted product 11) that is bridge-mounted so as to straddle the die pads 10 of the lead frame 2.
  • a bridge mounted product 11 an electronic component that is bridge-mounted so as to straddle the die pads 10 of the lead frame 2.
  • a recess 8g is provided in the second mold resin 8 corresponding to a position directly below the bridge mounted product 11, the mounting surface 2a of the lead frame 2 is sealed by the first mold resin 7, and the first mold resin 7 is sealed in the first recess 8g.
  • the mold resin 7 is filled.
  • FIG. 13 shows the first transfer molding step.
  • the first transfer molding process is performed before mounting the parts such as the semiconductor element 1 on the lead frame 2, and the second mold resin 8 is used to radiate the heat radiation surface 2 b of the lead frame 2.
  • a second skirt portion 8a and a thin-walled molded portion 8b are formed.
  • the fourth molding die 50 used in the first transfer molding process in the fourth embodiment has a convex portion 53 at a position where the bridge mounted product 11 between the die pads 10 is arranged. is doing.
  • the second molding resin 8 is melted by heat and pressure applied by the fourth molding die 50 and injected through the lower gate 52 into the cavity 51 where the lead frame 2 is installed.
  • the second molding resin 8 integrally molds the thin molded portion 8b having a recess 8g at a position corresponding to a position directly below the bridge mounted product 11 and the second skirt portion 8a.
  • the melted first mold resin 7 flows on the mounting surface 2a of the lead frame 2, fills the periphery 8b of the bridge mounted product 11 and the recess 8g immediately below, and The skirt portion 7a is formed.
  • FIG. 14 shows a second transfer molding step when the second mold resin 8 immediately below the bridge mounted product 11 has no depression 8g as a comparative example of the fourth embodiment.
  • the first mold resin 7 injected into the cavity 61 of the molding die 60 shown in FIG. 14 flows on the mounting surface 2 a of the lead frame 2 and fills the periphery of the bridge mounted product 11.
  • the first mold resin 7 is easy to flow, and the periphery of the bridge mounted product 11 is When the first mold resin 7 flows, it can flow simultaneously to the upper surface of the bridge mounted product 11 and directly below. Therefore, the first mold resin 7 is filled immediately below the bridge mounted product 11, and damage to the bridge mounted product 11 due to the molding pressure of the first mold resin 7 can be reduced.
  • the heat dissipation is improved by covering the side surface of the lead frame 2 with the second mold resin 8 which is a high heat dissipation resin.
  • a recess 8g is provided in the second mold resin 8 immediately below the bridge mounted product 11, and the first mold resin 7 is provided in the recess 8g. In this way, damage to the bridge mounted product 11 can be reduced, and a highly reliable semiconductor device 103 can be obtained.
  • FIG. FIG. 15 is a scanning electron micrograph showing the surface state of the lead frame of the semiconductor device according to the fifth embodiment of the present invention.
  • the overall configuration of the semiconductor device according to the fifth embodiment is the same as that of the first embodiment, and the description of each element is omitted (see FIG. 1).
  • the method for manufacturing the semiconductor device according to the fifth embodiment is the same as that in the first embodiment, and a description thereof will be omitted.
  • the semiconductor device uses a rough metal plating lead frame 12 instead of the lead frame 2 used in the first embodiment.
  • the roughened metal plating lead frame 12 is a surface of a lead frame 13 made of copper or copper alloy formed by roughening metal plating 14 such as nickel, tin, silver or gold having a surface roughness Ra of about 0.06 to 0.2. It is a coating.
  • the first mold resin 7 and the second resin can be obtained by the anchor effect of the rough metal plating 14. Adhesion with the second mold resin 8 is improved. Further, since the rough metal plating lead frame 12 has a larger surface area than the normal lead frame 2, heat dissipation is improved.
  • FIG. FIG. 16 is a cross-sectional view showing the configuration of the semiconductor device according to the sixth embodiment of the present invention.
  • the semiconductor device 104 according to the sixth embodiment is a modification of the semiconductor device 100 according to the first embodiment, and since the overall configuration is the same, only the differences will be described.
  • the method for manufacturing the semiconductor device 104 according to the sixth embodiment is the same as that in the first embodiment, and a description thereof will be omitted.
  • the lead frame 2 of the semiconductor device 104 is coated with metal plating (not shown), and has a scale portion 15 obtained by deforming the surface shape of the metal plating into a scale shape.
  • the scale portion 15 is disposed on the outer peripheral portion of the heat radiating surface 2 b of the lead frame 2. Due to the anchor effect of the scale-like portions 15, the second mold resin 8 is prevented from peeling from the lead frame 2.
  • a recess 16 is provided in the first mold resin 7 between the die pads 10.
  • the recess 16 is formed by irradiating the first mold resin 7 between the die pads 10 with a laser after sealing the mounting surface 2a with the first mold resin 7 in the first transfer molding process. It is formed by partially melting the mold resin 7.
  • the number and shape of the recessed part 16 are not specifically limited.
  • the second mold resin 8 disposed between the die pads 10 may be provided with a recess.
  • the second skirt portion 8a, the thin molded portion 8b, and the inter-die pad filling portion 8e are molded by the second mold resin 8 in the first transfer molding step.
  • the inter-die pad filling portion 8e can be irradiated with a laser to form a recess. In this way, by providing a recess in any resin between the die pads 10 that serve as a joint between the first mold resin 7 and the second mold resin 8, the anchor effect of the recess makes the first mold resin 7 and The adhesion of the second mold resin 8 is improved.
  • FIGS. 17 and 18 are scanning electron micrographs showing the form of the scaly portion, and FIG. 18 is a top perspective view of the cross section indicated by BB in FIG.
  • the scaly portion 15 is obtained by melting the metal plating that coats the lead frame 2 by, for example, continuously performing spot irradiation with a laser and deforming it into a scaly shape.
  • the scaly portion 15 has scaly projections continuously arranged, and both sides thereof are raised.
  • the scaly portion 15 is formed by laser irradiation, an arbitrary portion of the lead frame 2, for example, a portion or mold resin where stress is easily generated when a semiconductor device is discharged from a molding die or when a gate break occurs and initial peeling is likely to occur. Can be selectively placed at a location where the adhesiveness is low.
  • the width and height of the scale portion 15 can be adjusted by the output of the laser, the scanning speed, and the like.
  • the width of the scale portion 15 is desirably 60 ⁇ m or more, and the adhesiveness is further improved by increasing the width according to the area of the place where the scale portion 15 is disposed.
  • FIG. 19 is a perspective view of a scanning electron micrograph showing the shape of the recess.
  • the recess 16 is formed by melting resin by laser irradiation.
  • the width and height difference of the recess 16 can be adjusted by the laser output, the scanning speed, and the like.
  • the scaly portion 15 is arranged in the vicinity of the lower gate break mark 8 c of the lead frame 2, that is, in a position close to the lower gate 32 (see FIG. 5) of the second molding die 30. Thereby, it is possible to improve the adhesion between the lead frame 2 and the second mold resin 8 in the vicinity of the lower gate break mark 8c where initial peeling is likely to occur.
  • the scale portion 15 is disposed on the outer peripheral portion of the heat radiation surface 2 b of the lead frame 2.
  • initial peeling due to stress when the semiconductor device 104 is discharged from the second molding die 30 and peeling due to other external stress can be suppressed, and the inside of the second mold resin 8 can be suppressed. It has the effect of preventing moisture and contaminants from entering.
  • the arrangement examples of the scale portions 15 are not limited to those shown in FIG. 20 and FIG.
  • the lead frame 2 and the first mold resin 7 or the second molding resin 7 can be obtained by providing the scale portion 15 at an arbitrary position of the lead frame 2.
  • the adhesion with the mold resin 8 is improved.
  • the recess 16 in the first mold resin 7 or the second mold resin 8 between the die pads 10 the adhesion between the first mold resin 7 and the second mold resin 8 is improved.
  • FIG. FIG. 22 is an enlarged cross-sectional view showing the thin molded portion after the second transfer molding step in the semiconductor device according to the seventh embodiment of the present invention.
  • the overall configuration of the semiconductor device according to the seventh embodiment is the same as that of the first embodiment, and the description of each element is omitted (see FIG. 1).
  • the method for manufacturing the semiconductor device according to the seventh embodiment is the same as that in the first embodiment, and a description thereof will be omitted.
  • a skin layer 17 is formed on the surface in contact with the second molding die 30 (see FIG. 5) and the lead frame 2 by the flow of molten resin.
  • This skin layer 17 has a small amount of filler and a large amount of epoxy, and has a lower thermal conductivity than other portions. Therefore, in the seventh embodiment, after the second transfer molding process, the skin layer 17 on the surface of the thin molded portion 8b in contact with the heat sink is shaved and removed by laser processing or mechanical polishing.
  • the skin layer 17 on the surface of the thin molded portion 8b is removed, so that a semiconductor device with further excellent heat dissipation can be obtained.
  • FIG. FIG. 23 is an enlarged cross-sectional view showing a thin molded portion of the semiconductor device according to Embodiment 8 of the present invention.
  • the overall configuration of the semiconductor device according to the eighth embodiment is the same as that of the first embodiment, and thus description of each element is omitted (see FIG. 1).
  • the method for manufacturing the semiconductor device according to the eighth embodiment is the same as that in the first embodiment, and a description thereof will be omitted.
  • a high heat dissipation resin having a thermal conductivity of silica or alumina and containing a filler 18 less than boron nitride is used as the second mold resin 8.
  • the filler cut point (maximum filler diameter) of the filler 18 is 0.02 mm to 0.15 mm, and the thickness of the thin molded portion 8b is 0.022 mm to 0, which is 1.1 to 2 times the filler cut point size. .3 mm.
  • the eighth embodiment in addition to the same effects as those of the first embodiment, it is possible to improve the heat dissipation property of the thin molded portion 8b without using expensive boron nitride as a filler, which is inexpensive. A semiconductor device is obtained.
  • FIG. FIG. 24 is a cross-sectional view showing a semiconductor device according to the ninth embodiment of the present invention
  • FIG. 25 is a cross-sectional view showing a second transfer molding process of the semiconductor device according to the ninth embodiment.
  • the semiconductor device 105 according to the ninth embodiment is a modification of the semiconductor device 100 according to the first embodiment, and since the overall configuration is the same, only the differences will be described.
  • the heat sink 19 is installed inside the molding die 70, and the heat radiating surface 2 b of the lead frame 2 is attached by the second molding resin 8. While sealing, the heat sink 19 is joined to the thin molded part 8b.
  • a heat radiating member such as grease for bonding the heat sink 19 becomes unnecessary.
  • the heat dissipation is further improved. Further, after the second transfer molding step, the step of joining the heat sink 19 to the thin molded portion 8b via a heat radiating member such as grease can be omitted.
  • the lead frame 2 has the mounting surface 2a and the heat radiating surface 2b opposite to the mounting surface 2a.
  • a heat radiating portion is also provided on the mounting surface 2a side, and the lead frame 2 It is good also as a structure which has a thermal radiation part on both surfaces.
  • the mounting portion on which the semiconductor element 1 is mounted can be covered with the first mold resin 7, and the heat radiating portion can be covered with the second mold resin 8.
  • each component of the semiconductor device according to the first to ninth embodiments for example, the semiconductor element 1, the external terminal 4, the wire 5, the inner lead 6, and the bridge mounted product 11 are as follows. However, it is not particularly limited, and is appropriately selected according to a required function. Further, within the scope of the invention, the present invention can be freely combined with each other, or can be appropriately modified or omitted.

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Abstract

半導体装置（１００）において、リードフレーム（２）の放熱面（２ｂ）に、第一のモールド樹脂（７）により成形された第一のスカート部（７ａ）と、第二のモールド樹脂（８）により成形された第二のスカート部（８ａ）を設けた。また、薄肉成形部（８ｂ）は、第二のモールド樹脂（８）により第二のスカート部（８ａ）と一体的に成形される。このような構成により、薄肉成形部（８ｂ）とリードフレーム（２）との密着性が高く、放熱性と絶縁性に優れた半導体装置（１００）が得られる。

Description

半導体装置
　本発明は、樹脂モールド型の半導体装置に関し、特にモールド樹脂で全体を封止した半導体装置に関するものである。
　パワー用の半導体装置は、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）、ＭＯＳＦＥＴ（Ｍｅｔａｌ－ｏｘｉｄｅ－ｓｅｍｉｃｏｎｄｕｃｔｏｒ　ｆｉｅｌｄ－ｅｆｆｅｃｔ　ｔｒａｎｓｉｓｔｏｒ）、ＩＣチップ、ＬＳＩチップ等の半導体素子を外部端子用リードフレームにダイボンドした後、半導体素子の電極と外部端子をワイヤまたはインナーリードで電気的に接続し、外部との信号の入出力を行っている。
　また、樹脂モールド型の半導体装置は、モールド成形工程において、リードフレームの半導体素子が実装された側の面（実装面）とその反対側の放熱面を、モールド樹脂で封止される。パワー用の半導体装置は、内部に高発熱素子を備えているため、モールド樹脂には高放熱性が要求される。例えば特許文献１に提示された半導体装置は、リードフレームの実装面は一般的な集積回路のモールド樹脂として用いられる低応力樹脂で封止し、放熱面は熱伝導率が４～１０Ｗ／ｍ・Ｋの高放熱樹脂で封止している。
　一方、特許文献１のように高放熱樹脂と低応力樹脂の二種類の樹脂を用いて封止する場合、樹脂同士の密着性が悪いという課題があった。高放熱樹脂と低応力樹脂を十分に密着させる方法として、特許文献１では、リードフレームの放熱面を覆う高放熱樹脂の外周端部をリードフレームの外周端部よりも内側に位置させ、半硬化状態の高放熱樹脂を低応力樹脂で封止するようにしている。
特許第５４１５８２３号公報
　特許文献１のように二種類の樹脂を用いる場合、高放熱樹脂としてフィラー量が多く粘度が高いモールド樹脂が用いられる。このため、トランスファー法で成形する際に樹脂の流動性が悪く、低応力樹脂やリードフレームに対して濡れにくい。その結果、成形された高放熱樹脂は、低応力樹脂やリードフレームとの密着性が低く、成形金型から排出する際に二種類のモールド樹脂の界面、またはリードフレームと高放熱樹脂の界面に応力が働き、トランスファー成形の直後にそれらの界面で初期的な剥離が生じることがあった。
　また、トランスファー成形に用いられる金型における樹脂の通り道であるゲート内に残った樹脂はランナーと呼ばれるが、トランスファー成形後、金型から半導体装置を取り出した直後に、ランナーと半導体装置を切り離すゲートブレイクが実施され、半導体装置にはゲートブレイク跡が残る。
　ゲートブレイク時には、リードフレームを変形させる力が加わること、また、ゲートブレイク跡付近は粘度が高くなっている樹脂が流れる箇所であり、リードフレームとの密着性が他の箇所よりも劣ることから、ゲートブレイク跡付近で初期的な剥離が発生しやすい。また、初期的な剥離がなかったとしても、使用環境下での繰り返しの熱応力により、ゲートブレイク跡付近の二種類のモールド樹脂の界面、またはリードフレームとモールド樹脂の界面において剥離が発生しやすい。
　また、放熱面側のモールド樹脂は、放熱性向上のためには薄く形成することが望ましいが、薄肉化により金型の空洞部が狭くなるため、金型内での樹脂の流動性がさらに悪くなり、リードフレームと樹脂との密着性が低下する。さらに、薄肉化により沿面距離が短くなり絶縁性が低下するという問題や、強度の低下によりゲートブレイク時に欠けが発生するという問題が発生する。これらのことから、特許文献１では、高粘度の高放熱樹脂の成形には、ゲート部を持たない金型を用いたコンプレッション成形を採用している。
　本発明は上記の事情に鑑みてなされたもので、二種類のモールド樹脂を用いた半導体装置において、二種類のモールド樹脂の密着性またはリードフレームとモールド樹脂の密着性を向上させ、ゲート部を持つ金型でトランスファー成形した場合でも放熱面側のモールド樹脂の薄肉成形部の剥離や欠けが発生しにくく、放熱性と絶縁性に優れた半導体装置を得ることを目的とする。
　本発明に係る半導体装置は、半導体素子が実装されたリードフレームと、リードフレームの半導体素子が実装された面である実装面を封止する第一のモールド樹脂と、リードフレームの実装面と反対側の面である放熱面を封止する第二のモールド樹脂を備え、リードフレームの放熱面の外周端部には、第一のモールド樹脂と第二のモールド樹脂により成形された枠状突起が設けられ、枠状突起の対向する二辺と該二辺の間を覆う薄肉成形部は第二のモールド樹脂により一体的に成形され、枠状突起の他の対向する二辺は第一のモールド樹脂により成形されたものである。
　本発明によれば、枠状突起の対向する二辺と該二辺の間を覆う薄肉成形部を第二のモールド樹脂により一体的に成形し、枠状突起の他の対向する二辺を第一のモールド樹脂により成形するようにしたので、枠状突起の四辺全てを一回のトランスファー成形工程で成形する場合に比べ、薄肉成形部への第二のモールド樹脂の流動性が向上し、第二のモールド樹脂が濡れ易くなり、リードフレームとの密着性が高くなる。このため、ゲート部を持つ金型でトランスファー成形した場合でも、放熱面側の第二のモールド樹脂の薄肉成形部の剥離や欠けが発生しにくく、放熱性と絶縁性に優れた半導体装置が得られる。
　この発明の上記以外の目的、特徴、観点及び効果は、図面を参照する以下のこの発明の詳細な説明から、さらに明らかになるであろう。
本発明の実施の形態１に係る半導体装置を示す断面図である。 本発明の実施の形態１における一回目のトランスファー成形工程後の半導体装置を放熱面側から見た平面図である。 本発明の実施の形態１における二回目のトランスファー成形工程後の半導体装置を放熱面側から見た平面図である。 本発明の実施の形態１に係る半導体装置の一回目のトランスファー成形工程を示す断面図である。 本発明の実施の形態１に係る半導体装置の二回目のトランスファー成形工程を示す断面図である。 本発明の実施の形態１における一回目のトランスファー成形工程後の別の半導体装置を放熱面側から見た平面図である。 本発明の実施の形態２に係る半導体装置を示す断面図である。 本発明の実施の形態２に係る半導体装置のコンプレッション成形工程を示す断面図である。 本発明の実施の形態３に係る半導体装置を示す断面図である。 本発明の実施の形態３に係る半導体装置を示す部分断面図である。 本発明の実施の形態３に係る半導体装置の一回目のトランスファー成形工程を示す断面図である。 本発明の実施の形態４に係る半導体装置を示す断面図である。 本発明の実施の形態４に係る半導体装置の一回目のトランスファー成形工程を示す断面図である。 本発明の実施の形態４の比較例である半導体装置の二回目のトランスファー成形工程を示す断面図である。 本発明の実施の形態５に係る半導体装置のリードフレームの表面状態を示す走査電子顕微鏡写真による図である。 本発明の実施の形態６に係る半導体装置を示す断面図である。 本発明の実施の形態６に係る半導体装置における鱗状部の形態を示す走査電子顕微鏡写真による図である。 本発明の実施の形態６に係る半導体装置における鱗状部の形態を示す走査電子顕微鏡写真による図である。 本発明の実施の形態６に係る半導体装置における凹部の形態を示す走査電子顕微鏡写真による図である。 本発明の実施の形態６に係る半導体装置における鱗状部の配置例を示す図である。 本発明の実施の形態６に係る半導体装置における鱗状部の配置例を示す図である。 本発明の実施の形態７に係る半導体装置における二回目のトランスファー成形工程後の薄肉成形部を示す拡大断面図である。 本発明の実施の形態８に係る半導体装置の薄肉成形部を示す拡大断面図である。 本発明の実施の形態９に係る半導体装置を示す断面図である。 本発明の実施の形態９に係る半導体装置の二回目のトランスファー成形工程を示す断面図である。
実施の形態１．
　以下に、本発明の実施の形態１に係る半導体装置について、図面に基づいて説明する。図１は、本実施の形態１に係る樹脂モールド型の半導体装置の構成を示す断面図、図２は、一回目のトランスファー成形工程後の半導体装置を放熱面側から見た平面図、図３は、二回目のトランスファー成形工程後の半導体装置を放熱面側から見た平面図である。なお、各図において、図中、同一または相当部分には同一符号を付している。
　図１に示すように、本実施の形態１に係る半導体装置１００は、半導体素子１、リードフレーム２、外部端子４、ワイヤ５、インナーリード６等を含んで構成される。図１において、リードフレーム２の上側の面（以下、実装面２ａと称す）には、例えばＩＧＢＴ、ＭＯＳＦＥＴ、ＩＣチップ、ＬＳＩチップ等の半導体素子１が、はんだ、銀等の接合部材３を介して実装されている。リードフレーム２は、銅板または銅合金板であり、その表面を、金、銀、ニッケル、スズ等の金属めっき（図示省略）で被膜されている。
　半導体素子１の電極パッドは、ワイヤボンディングで接続されたワイヤ５、もしくは、銅板や銅合金板の材料で作成されたインナーリード６を介して外部端子４と電気的に接続され、外部と信号の入出力を行っている。ワイヤ５とインナーリード６は互いに置き換えが可能である。ワイヤ５は、金、銀、アルミ、銅等からなり、ワイヤ線径は２０μｍから５００μｍ程度である。
　リードフレーム２は、その実装面２ａを第一のモールド樹脂７により封止され、実装面２ａと反対側の面である放熱面２ｂを第二のモールド樹脂８により封止されている。また、本実施の形態１では、リードフレーム２の離間された二つの領域の間（以下、ダイパッド間１０と称す）には、第一のモールド樹脂７が配置されている。
　さらに、図３に示すように、リードフレーム２の放熱面２ｂには、その外周端部に、第一のモールド樹脂７と第二のモールド樹脂８により成形された厚さ０．３ｍｍ～２ｍｍ程度の枠状突起であるスカート部が設けられている。このスカート部は、第一のモールド樹脂７により成形された第一のスカート部７ａと、第二のモールド樹脂８により成形された第二のスカート部８ａから構成されている。
　このようなスカート部を設けることにより、高圧がかかるリードフレーム２の外周端部の強度を確保することができる。また、沿面距離が長くなり絶縁性が向上するため、半導体素子１としてＩＧＢＴを使用する高圧モジュールには有利となる。なお、本実施の形態１では、第一のスカート部７ａ及び第二のスカート部８ａは、その各辺と直交する方向に切断した断面形状が、長方形または正方形または台形である。
　また、第二のスカート部８ａの間には、厚さ０．０２ｍｍ～０．３ｍｍ程度の薄肉成形部８ｂが、第二のモールド樹脂８により第二のスカート部８ａと一体的に成形されている。第一のスカート部７ａと第二のスカート部８ａは、四箇所の樹脂接合部９で接合され、薄肉成形部８ｂを囲むスカート部を形成している。薄肉成形部８ｂは、グリース等の放熱部材を介して銅、アルミ製のヒートシンクと接合される。
　第一のモールド樹脂７と第二のモールド樹脂８は、いずれも熱硬化性のエポキシ樹脂等である。ただし、放熱面２ｂ側の第二のモールド樹脂８には、第一のモールド樹脂７よりも熱伝導率が高い高放熱樹脂が用いられる。第二のモールド樹脂８の熱伝導率は、３Ｗ／ｍ・Ｋ～１２Ｗ／ｍ・Ｋである。実装面２ａ側の第一のモールド樹脂７には、一般的な集積回路のモールド樹脂である低応力樹脂が用いられる。
　次に、本実施の形態１に係る半導体装置１００のモールド成形工程について、図４及び図５を用いて説明する。半導体装置１００は、二回のトランスファー成形工程を含んで製造され、図４は一回目のトランスファー成形工程、図５は二回目のトランスファー成形工程を示している。なお、図４及び図５は、図２中Ａ－Ａで示す位置における断面図である。
　図４に示すように、一回目のトランスファー成形工程において、第一のモールド樹脂７は、第一の成形金型２０で加える熱と圧力により溶融され、上ゲート２２を通ってリードフレーム２が設置された空洞２１に注入される。第一のモールド樹脂７は、リードフレーム２の実装面２ａ側に流動し空洞２１を充填すると共に、第一のスカート部７ａに該当する空洞に流動し第一のスカート部７ａを成形する。第一の成形金型２０の上ゲート２２の内部に残った第一のモールド樹脂７は、ランナー７ｂと呼ばれる。
　一回目のトランスファー成形後、第一の成形金型２０から成形品を取り出した直後に、成形品からランナー７ｂを切り離すゲートブレイク工程が実施される。ゲートブレイク後は、半導体装置１００に上ゲートブレイク跡７ｃ（図１参照）が残る。また、図２に示すように、一回目のトランスファー成形工程後のリードフレーム２の放熱面２ｂには、第一のモールド樹脂７により、上ゲート２２と平行な二辺である第一のスカート部７ａが成形されると共に、ダイパッド間１０が埋め込まれている。
　続いて、二回目のトランスファー成形工程が実施される。なお、第一のモールド樹脂７と第二のモールド樹脂８の密着性を高めるため、一回目のトランスファー成形工程後、第一のモールド樹脂７にＵＶ処理やプラズマ処理を実施しても良い。図５に示すように、二回目のトランスファー成形工程で用いられる第二の成形金型３０の内部には、前述の一回目のトランスファー成形工程を終えて実装面２ａが封止されたリードフレーム２が設置され、リードフレーム２の放熱面２ｂ側が空洞３１となっている。
　第二のモールド樹脂８は、第二の成形金型３０で加える熱と圧力により溶融され、下ゲート３２付近にある第二のスカート部８ａに該当する空洞３１を通り、薄肉成形部８ｂに該当する空洞３１へ流動する。この時、第二のモールド樹脂８は、一旦、下ゲート３２付近の第二のスカート部８ａに溜まるため、薄肉成形部８ｂへ均一に流動することができる。薄肉成形部８ｂを通った第二のモールド樹脂８は、さらに、最終充填部となる下ゲート３２から最も遠い対辺の第二のスカート部８ａに該当する空洞３１に流動する。
　この時、第二のモールド樹脂８は、硬化が進み粘度が高くなっているが、最終充填部である第二のスカート部８ａは薄肉成形部８ｂより厚みが大きいため流動抵抗が小さく、第二のモールド樹脂８が流動しやすい。この二回目のトランスファー成形工程において、第二のモールド樹脂８により第二のスカート部８ａと薄肉成形部８ｂを成形し、第二の成形金型３０から成形品を取り出した直後に、成形品からランナーを切り離すゲートブレイク工程が実施される。ゲートブレイク後は、半導体装置１００に下ゲートブレイク跡８ｃ（図１参照）が残る。
　図３に示すように、二回目のトランスファー成形工程後の放熱面２ｂには、下ゲート３２に最も近い辺を含む二辺の第二のスカート部８ａと、該二辺の間を覆う薄肉成形部８ｂが、第二のモールド樹脂８により一体的に成形されている。
　本実施の形態１の比較例として、スカート部の四辺全てと薄肉成形部を一回のトランスファー成形工程で同時に成形する場合について説明する。成形金型内において、スカート部の厚みは薄肉成形部よりも大きく流動抵抗が小さいため、溶融樹脂はスカート部の四辺に先に流動し、薄肉成形部が最終充填部となる。最終充填部には、硬化が進み粘度が高くなった樹脂が流動するため、流動抵抗の大きい薄肉成形部へ均一に流動することが難しい。また、先にスカート部の四辺に流動した樹脂が薄肉成形部で合流するため、強度や絶縁性が劣るウェルドラインが形成される。
　この比較例に対し、本実施の形態１のように二回のトランスファー成形工程を経てスカート部を成型した場合、第二のモールド樹脂８の薄肉成形部８ｂへの流動性が向上し、第一のモールド樹脂７及びリードフレーム２に対し濡れ易くなり密着性が向上する。
　なお、本実施の形態１において、上ゲートブレイク跡７ｃの位置（すなわち一回目のトランスファー成形工程で用いられる第一の成形金型２０の上ゲート２２の位置）は、図２に示す位置に限定されるものではなく、また、その数も１つに限らず複数存在しても良い。例えば図６に示すように、第一のスカート部７ａに近い位置に、三個の上ゲートブレイク跡７ｃを有していても良い。
　また、本実施の形態１では、図３に示すように、長方形の半導体装置１００において、第一のモールド樹脂７により成形された第一のスカート部７ａが長辺側に位置し、第二のモールド樹脂８により成形された第二のスカート部８ａが短辺側に位置しているが、使用される成形金型のゲートの位置によって、逆の場合も有り得る。
　また、本実施の形態１では、リードフレーム２の表面は、金、銀、ニッケル、スズ等の金属めっきで被膜されているが、被膜されていない場合もある。また、本実施の形態１では、厚さが均一のリードフレーム２を用いたが、部分的に厚さが異なるリードフレームを用いても良い。ただしその場合、コストが高くなる。また、本実施の形態１では、薄肉成形部８ｂにグリース等の放熱部材を介してヒートシンクを接合するが、放熱部材を用いない場合もある。
　また、本実施の形態１では、実装面２ａと反対側の面を放熱面としたが、実装面２ｂも同様の放熱性を有するようにしても良い。例えば第一のモールド樹脂７として、第二のモールド樹脂８と同様の、熱伝導率が３Ｗ／ｍ・Ｋ～１２Ｗ／ｍ・Ｋの高放熱樹脂を用いても良い。発熱部品である半導体素子１の周りを高放熱樹脂で封止することにより、半導体素子１の全周囲から放熱されるため、放熱性が向上する。
　本実施の形態１によれば、一回目のトランスファー成形工程で第一のスカート部７ａを第一のモールド樹脂７により成形し、二回目のトランスファー成形工程で第二のスカート部８ａと薄肉成形部８ｂを第二のモールド樹脂８により一体的に成形することにより、スカート部の四辺全てを一回のトランスファー成形工程で成形する場合に比べ、薄肉成形部８ｂへの第二のモールド樹脂８の流動性が向上し、第二のモールド樹脂８が濡れ易くなるため、薄肉成形部８ｂとリードフレーム２の密着性が高くなる。
　また、二回目のトランスファー成形工程における下ゲートブレイク跡８ｃ付近の第二のモールド樹脂８とリードフレーム２との密着性も向上することから、下ゲートブレイク跡８ｃ付近での初期的な剥離を抑制することができる。
　これらのことから、本実施の形態１によれば、第一のモールド樹脂７と第二のモールド樹脂８の密着性、及びリードフレーム２と第二のモールド樹脂８の密着性を向上させることが可能となり、二回目のトランスファー成形工程後のゲートブレイク工程においても薄肉成形部８ｂの剥離や欠けが発生しにくく、放熱性と絶縁性に優れた信頼性の高い半導体装置１００が得られる。
実施の形態２．
　図７は、本発明の実施の形態２に係る半導体装置の構成を示す断面図である。本実施の形態２に係る半導体装置１０１は、上記実施の形態１に係る半導体装置１００の変形例であり、全体的な構成は同じであるため、相違点のみを説明する。
　上記実施の形態１では、半導体装置１００のスカート部は、その各辺と直交する方向に切断した断面形状が長方形または正方形または台形であった（図１参照）。本実施の形態２に係る半導体装置１０１のスカート部は、その各辺と直交する方向に切断した断面形状が円弧状の先端部を有するものである。なお、図７には、第二のスカート部８ｄのみを図示しているが、第一のスカート部も同様に、その各辺と直交する方向に切断した断面形状が円弧状の先端部を有している。
　本実施の形態２に係る半導体装置１０１の製造工程について、図８を用いて説明する。半導体装置１０１は、二回のモールド成形工程を含んで製造され、一回目は上記実施の形態１と同様のトランスファー成形工程を実施し（図４参照）。二回目は、図８に示すコンプレッション成形工程を実施する。コンプレッション成形では、予め第三の成形金型４０内部の空洞４１に、タブレット状または顆粒状の第二のモールド樹脂８が設置されており、第三の成形金型４０は下ゲートを有していない。
　空洞４１に設置された第二のモールド樹脂８の溶融が開始されると同時に、第三の成形金型４０の下部（可動部）が矢印Ａの方向に移動し、空洞４１を加圧しながら所定の位置で停止する。これにより、第二のモールド樹脂８により薄肉成形部８ｂと第二のスカート部８ｄが成形される。なお、成形前に第三の成形金型４０の内部表面に、厚さ４０μｍ～１００μｍ程度の熱可塑性フッ素樹脂製のフィルム４２を吸着させておくことにより、溶融した第二のモールド樹脂８が第三の成形金型４０の可動部に侵入するのを防止している。
　このフィルム４２は、第三の成形金型４０の可動部が第二のモールド樹脂８を加圧する際に、第三の成形金型４０の内部形状に倣う。そのため、第三の成形金型４０の内部形状にエッジ部があると、フィルム４２がエッジ部に当たって破れ、破損部から第二のモールド樹脂８が第三の成形金型４０の可動部に侵入することになる。これを防ぐために、本実施の形態２に係る半導体装置１０１は、スカート部の先端部の断面形状を円弧状にしてエッジ部をなくしている。
　なお、本実施の形態２において、スカート部の先端は、コンプレッション成形においてフィルム４２が破損しない断面形状であれば良い。従って、その各辺と直交する方向に切断した断面形状が矩形であり、その角部が丸みを帯びているものであっても良い。
　本実施の形態２によれば、上記実施の形態１と同様の効果に加え、スカート部の先端部の断面形状を円弧状または矩形の角部が丸みを帯びているものとすることにより、放熱面２ｂを封止する二回目のモールド成形工程にコンプレッション成形を採用することが可能である。これにより、金型の設備費が抑制され、樹脂材料の損失が少なく、二回目のゲートブレイク工程を省略することができる。ただし、本実施の形態２に係る半導体装置１０１は、上記実施の形態１と同様の二回のトランスファー成形工程によっても製造することができる。
実施の形態３．
　図９は、本発明の実施の形態３に係る半導体装置の構成を示す断面図である。本実施の形態３に係る半導体装置１０２は、上記実施の形態１に係る半導体装置１００の変形例であり、全体的な構成は同じであるため、相違点のみを説明する。
　上記実施の形態１に係る半導体装置１００は、リードフレーム２のダイパッド間１０には、第一のモールド樹脂７が配置されている。これに対し、本実施の形態３に係る半導体装置１０２は、リードフレーム２に存在する複数のダイパッド間１０のうち、少なくとも一部のダイパッド間１０に、第二のモールド樹脂８により成形されたリードフレーム間充填部（以下、ダイパッド間充填部８ｅ、８ｆと称す）を配置する。図９に示す例では、二箇所のダイパッド間１０に、ダイパッド間充填部８ｅ、８ｆが配置されている。
　これらのダイパッド間充填部８ｅ、８ｆがリードフレーム２の側面と密着することにより、第二のモールド樹脂８がリードフレーム２と密着する面積が拡大し、薄肉成形部８ｂとリードフレーム２の密着性が向上する。また、図１０に示すように、ダイパッド間充填部８ｅが配置されたリードフレーム２の側面の一部に、カエリ２ｃを有するようにしてもよい。リードフレーム２の側面にプレスでカエリ２ｃを形成することにより、アンカー効果でダイパッド間充填部８ｅとの密着力がさらに向上する。
　また、ダイパッド間充填部８ｅ、８ｆにより薄肉成形部８ｂが部分的に厚くなるため、薄肉成形部８ｂの強度が向上し、欠けや割れが発生しにくくなる。さらに、放熱経路となっているリードフレーム２と高放熱樹脂である第二のモールド樹脂８が密着する面積が拡大することにより、放熱性が向上する。なお、本実施の形態３において、リードフレーム２の側面を高放熱樹脂である第二のモールド樹脂８で覆うことにより、放熱性がさらに向上する。
　本実施の形態３に係る半導体装置１０２は、上記実施の形態１と同様に二回のトランスファー成形工程を含んで製造される。ただし、図１１に示すように、一回目のトランスファー成形工程において、一部のダイパッド間１０に第一のモールド樹脂７が充填されないように、第一の成形金型２０からピン２３が挿入されている。
　その後、二回目のトランスファー成形工程において、第一のモールド樹脂７が充填されなかった一部のダイパッド間１０に、第二のモールド樹脂８が充填され、ダイパッド間充填部８ｅ、８ｆ、薄肉成形部８ｂ、及び第二のスカート部８ａが一体的に成形される。
　本実施の形態３によれば、上記実施の形態１と同様の効果に加え、リードフレーム２の一部のダイパッド間１０に、薄肉成形部８ｂと一体的に成形されたダイパッド間充填部８ｅ、８ｆを配置することにより、薄肉成形部８ｂとリードフレーム２の密着性が向上する。また、ダイパッド間充填部８ｅが配置されたリードフレーム２の側面にカエリ２ｃを形成することにより、アンカー効果により密着性がさらに向上する。
実施の形態４．
　図１２は、本発明の実施の形態４に係る半導体装置の構成を示す断面図である。本実施の形態４に係る半導体装置１０３は、上記実施の形態１に係る半導体装置１００の変形例であり、全体的な構成は同じであるため、相違点のみを説明する。
　半導体装置１０３は、リードフレーム２のダイパッド間１０を跨ぐようにブリッジ実装された電子部品（以下、ブリッジ実装品１１という）を備えている。ブリッジ実装品１１の直下に相当する第二のモールド樹脂８には窪み８ｇが設けられ、第一のモールド樹脂７によりリードフレーム２の実装面２ａが封止されると共に、窪み８ｇに第一のモールド樹脂７が充填される。
　本実施の形態４に係る半導体装置１０３の製造工程について、図１３を用いて説明する。半導体装置１０３は、二回のトランスファー成形工程を含んで製造され、図１３は一回目のトランスファー成形工程を示している。本実施の形態４では、一回目のトランスファー成形工程は、半導体素子１等の部品をリードフレーム２に実装する前に実施され、リードフレーム２の放熱面２ｂに、第二のモールド樹脂８により第二のスカート部８ａと薄肉成形部８ｂが成形される。
　図１３に示すように、本実施の形態４において一回目のトランスファー成形工程に用いられる第四の成形金型５０は、ダイパッド間１０のブリッジ実装品１１が配置される位置に凸部５３を有している。一回目のトランスファー成形工程において、第二のモールド樹脂８は、第四の成形金型５０で加える熱と圧力により溶融され、下ゲート５２を通ってリードフレーム２が設置された空洞５１に注入される。この一回目のトランスファー成形工程において、第二のモールド樹脂８により、ブリッジ実装品１１の直下に相当する位置に窪み８ｇを有する薄肉成形部８ｂと、第二のスカート部８ａが一体的に成形される。
　一回目のトランスファー成形工程の後、リードフレーム２の実装面２ａに半導体素子１やブリッジ実装品１１等の部品を実装する。続いて、二回目のトランスファー成形工程において、溶融された第一のモールド樹脂７はリードフレーム２の実装面２ａを流動し、ブリッジ実装品１１の周囲及び直下の窪み８ｇを充填すると共に、第一のスカート部７ａを成形する。
　図１４は、本実施の形態４の比較例として、ブリッジ実装品１１の直下の第二のモールド樹脂８に窪み８ｇがない場合の二回目のトランスファー成形工程を示している。図１４に示す成形金型６０の空洞６１に注入された第一のモールド樹脂７は、リードフレーム２の実装面２ａを流動し、ブリッジ実装品１１の周囲を充填する。
　しかし、ブリッジ実装品１１の直下には、はんだ厚分の５０μｍ～１００μｍの非常に狭い隙間しかないため、第一のモールド樹脂７の流動抵抗が大きく、流動しにくい。このため、ブリッジ実装品１１の周囲を第一のモールド樹脂７が流動する際に、ブリッジ実装品１１の直下が空洞のまま、上面から第一のモールド樹脂７による成形圧力がかかり、ブリッジ実装品１１が破損する要因となる。
　これに対し、本実施の形態４では、ブリッジ実装品１１の直下の第二のモールド樹脂８に窪み８ｇを設けているため、第一のモールド樹脂７が流動しやすく、ブリッジ実装品１１の周囲を第一のモールド樹脂７が流動する際に、ブリッジ実装品１１の上面と直下へ同時に流動することができる。よって、ブリッジ実装品１１の直下に第一のモールド樹脂７が充填され、第一のモールド樹脂７の成形圧力によるブリッジ実装品１１の破損を低減することができる。なお、本実施の形態４において、リードフレーム２の側面を高放熱樹脂である第二のモールド樹脂８で覆うことにより、放熱性が向上する。
　本実施の形態４によれば、上記実施の形態１と同様の効果に加え、ブリッジ実装品１１の直下の第二のモールド樹脂８に窪み８ｇを設け、この窪み８ｇに第一のモールド樹脂７を充填することにより、ブリッジ実装品１１の破損を低減することができ、信頼性の高い半導体装置１０３が得られる。
実施の形態５．
　図１５は、本発明の実施の形態５に係る半導体装置のリードフレームの表面状態を示す走査電子顕微鏡写真による図である。なお、本実施の形態５に係る半導体装置の全体構成は、上記実施の形態１と同様であるので、各要素の説明を省略する（図１参照）。また、本実施の形態５に係る半導体装置の製造方法は、上記実施の形態１と同様であるので説明を省略する。
　本実施の形態５に係る半導体装置は、上記実施の形態１で用いたリードフレーム２の代わりに、粗化金属めっきリードフレーム１２を用いたものである。粗化金属めっきリードフレーム１２とは、銅または銅合金製のリードフレーム１３の表面を、表面粗さＲａ０．０６～０．２程度のニッケル、すず、銀、金等の粗化金属めっき１４により被膜したものである。
　本実施の形態５によれば、上記実施の形態１と同様の効果に加え、粗化金属めっきリードフレーム１２を用いることにより、粗化金属めっき１４のアンカー効果で第一のモールド樹脂７及び第二のモールド樹脂８との密着力が向上する。さらに、粗化金属めっきリードフレーム１２は、通常のリードフレーム２に比べ表面積が大きいことから、放熱性が向上する。
実施の形態６．
　図１６は、本発明の実施の形態６に係る半導体装置の構成を示す断面図である。本実施の形態６に係る半導体装置１０４は、上記実施の形態１に係る半導体装置１００の変形例であり、全体的な構成は同じであるため、相違点のみを説明する。また、本実施の形態６に係る半導体装置１０４の製造方法は、上記実施の形態１と同様であるので説明を省略する。
　半導体装置１０４のリードフレーム２は、金属めっき（図示省略）により被膜されており、金属めっきの表面形状を鱗状に変形させた鱗状部１５を有している。図１６に示す例では、鱗状部１５は、リードフレーム２の放熱面２ｂの外周部に配置されている。この鱗状部１５のアンカー効果により、第二のモールド樹脂８がリードフレーム２から剥離するのを抑制している。
　また、ダイパッド間１０の第一のモールド樹脂７には、凹部１６が設けられている。この凹部１６は、一回目のトラスファー成形工程において第一のモールド樹脂７で実装面２ａを封止した後、ダイパッド間１０の第一のモールド樹脂７にレーザーを照射することにより、第一のモールド樹脂７を部分的に溶融させて形成したものである。なお、凹部１６の数及び形状は、特に限定されるものではない。
　また、ダイパッド間１０に配置された第二のモールド樹脂８に凹部を設けてもよい。例えば上記実施の形態４（図１２参照）のように、一回目のトランスファー成形工程で第二のモールド樹脂８により第二のスカート部８ａ、薄肉成形部８ｂ、及びダイパッド間充填部８ｅを成形する場合には、ダイパッド間充填部８ｅにレーザーを照射し、凹部を形成することができる。このように、第一のモールド樹脂７と第二のモールド樹脂８の接合部となるダイパッド間１０において、いずれかの樹脂に凹部を設けることにより、凹部のアンカー効果で第一のモールド樹脂７と第二のモールド樹脂８の密着性が向上する。
　図１７及び図１８は、鱗状部の形態を示す走査電子顕微鏡写真による図であり、図１８は、図１７中、Ｂ－Ｂで示す断面の上面斜視図である。鱗状部１５は、例えばレーザーによるスポット照射を連続的に行うことにより、リードフレーム２を被膜する金属めっきを溶融させ、鱗状に変形させたものである。鱗状部１５は、鱗片状の突起が連続的に配置されており、その両側が高く盛り上がっている。
　鱗状部１５は、レーザー照射により形成されるため、リードフレーム２の任意の箇所、例えば半導体装置を成形金型から排出する際やゲートブレイク時に応力がかかり初期的な剥離が生じやすい箇所やモールド樹脂との密着性が低い箇所に、選択的に配置することができる。また、鱗状部１５の幅や高さは、レーザーの出力や走査スピード等により調整することができる。鱗状部１５の幅は６０μｍ以上が望ましく、配置される箇所の面積に応じて幅を大きくすることにより、密着性がさらに向上する。
　また、図１９は、凹部の形態を示す走査電子顕微鏡写真による斜視図である。凹部１６は、レーザー照射により樹脂を溶融させて凹ませたものである。凹部１６の幅や高低差はレーザーの出力や走査スピード等により調整することができる。
　鱗状部１５の配置例とその効果について、図２０及び図２１を用いて説明する。図２０に示す例では、鱗状部１５は、リードフレーム２の下ゲートブレイク跡８ｃ付近、すなわち第二の成形金型３０の下ゲート３２（図５参照）に近接する箇所に配置されている。これにより、初期的な剥離が生じやすい下ゲートブレイク跡８ｃ付近のリードフレーム２と第二のモールド樹脂８の密着力を向上させることができる。
　また、図２１に示す例では、鱗状部１５は、リードフレーム２の放熱面２ｂの外周部に配置されている。これにより、半導体装置１０４を第二の成形金型３０から排出する際の応力による初期的な剥離や、その他の外部からの応力による剥離を抑制することができ、第二のモールド樹脂８内部への水分や汚染物質の侵入を防止する効果がある。なお、鱗状部１５の配置例は、図２０及び図２１に限定されるものではなく、リードフレーム２の実装面２ａの外周部や上ゲートブレイク跡７ｃ付近等に設けても良い。
　本実施の形態６によれば、上記実施の形態１と同様の効果に加え、リードフレーム２の任意の箇所に鱗状部１５を設けることにより、リードフレーム２と第一のモールド樹脂７または第二のモールド樹脂８との密着性が向上する。また、ダイパッド間１０の第一のモールド樹脂７または第二のモールド樹脂８に凹部１６を設けることにより、第一のモールド樹脂７と第二のモールド樹脂８の密着性が向上する。
実施の形態７．
　図２２は、本発明の実施の形態７に係る半導体装置における二回目のトランスファー成形工程後の薄肉成形部を示す拡大断面図である。なお、本実施の形態７に係る半導体装置の全体構成は、上記実施の形態１と同様であるので、各要素の説明を省略する（図１参照）。また、本実施の形態７に係る半導体装置の製造方法は、上記実施の形態１と同様であるので説明を省略する。
　二回目のトランスファー成形工程後の薄肉成形部８ｂは、第二の成形金型３０（図５参照）やリードフレーム２と接する面に、溶融樹脂の流動によるスキン層１７が形成される。このスキン層１７は、フィラーが少なくエポキシが多く存在し、他の部分より熱伝導率が低い。そこで、本実施の形態７では、二回目のトランスファー成形工程後に、ヒートシンクに接する薄肉成形部８ｂの表面のスキン層１７を、レーザー処理や機械研磨により削り、除去するものである。
　本実施の形態７によれば、上記実施の形態１と同様の効果に加え、薄肉成形部８ｂの表面のスキン層１７を除去するようにしたので、さらに放熱性に優れた半導体装置が得られる。
実施の形態８．
　図２３は、本発明の実施の形態８に係る半導体装置の薄肉成形部を示す拡大断面図である。なお、本実施の形態８に係る半導体装置の全体構成は、上記実施の形態１と同様であるので、各要素の説明を省略する（図１参照）。また、本実施の形態８に係る半導体装置の製造方法は、上記実施の形態１と同様であるので説明を省略する。
　本実施の形態８では、第二のモールド樹脂８として、熱伝導率がシリカ、アルミナ以上であり、ボロンナイトライド未満のフィラー１８を含有する高放熱樹脂を用いている。また、フィラー１８のフィラーカットポイント（最大フィラー径）を０．０２ｍｍ～０．１５ｍｍとし、薄肉成形部８ｂの厚さをフィラーカットポイントサイズの１．１倍～２倍である０．０２２ｍｍ～０．３ｍｍとしたものである。
　本実施の形態８によれば、上記実施の形態１と同様の効果に加え、フィラーとして高価なボロンナイトライドを用いずに、薄肉成形部８ｂの放熱性を向上させることが可能となり、安価な半導体装置が得られる。
実施の形態９．
　図２４は、本発明の実施の形態９に係る半導体装置を示す断面図、図２５は、本実施の形態９に係る半導体装置の二回目のトランスファー成形工程を示す断面図である。本実施の形態９に係る半導体装置１０５は、上記実施の形態１に係る半導体装置１００の変形例であり、全体的な構成は同じであるため、相違点のみを説明する。
　本実施の形態９では、図２５に示すように、二回目のトランスファー成形工程において、成形金型７０の内部にヒートシンク１９を設置し、第二のモールド樹脂８でリードフレーム２の放熱面２ｂを封止すると共に、薄肉成形部８ｂにヒートシンク１９を接合する。この時、薄肉成形部８ｂに該当する空洞７１へ流動した硬化前の第二のモールド樹脂８が接着剤を兼ねるため、ヒートシンク１９を接着するためのグリース等の放熱部材が不要となる。
　本実施の形態９によれば、上記実施の形態１と同様の効果に加え、薄肉成形部８ｂがヒートシンク１９と直接接合されるため、放熱性がさらに向上する。また、二回目のトランスファー成形工程後、薄肉成形部８ｂにグリース等の放熱部材を介してヒートシンク１９を接合する工程を省略することができる。
　なお、上記実施の形態１～実施の形態７では、リードフレーム２が実装面２ａとこれに対向する放熱面２ｂを有する構成としたが、実装面２ａ側にも放熱部を設け、リードフレーム２の両面に放熱部を有する構成としても良い。その場合、リードフレーム２の同じ面において、半導体素子１が実装された実装部を第一のモールド樹脂７により覆い、放熱部を第二のモールド樹脂８により覆うことも可能である。
　なお、上記実施の形態１～実施の形態９に係る半導体装置の各構成要素、例えば半導体素子１、外部端子４、ワイヤ５、インナーリード６、ブリッジ実装品１１等の形状、個数、及び配置は、特に限定されるものではなく、求められる機能に応じて適宜選択される。また、本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。

Claims (19)

  1. 　半導体素子が実装されたリードフレーム、前記リードフレームの前記半導体素子が実装された面である実装面を封止する第一のモールド樹脂、前記リードフレームの前記実装面と反対側の面である放熱面を封止する第二のモールド樹脂を備え、
    前記リードフレームの前記放熱面の外周端部には、前記第一のモールド樹脂と前記第二のモールド樹脂により成形された枠状突起が設けられ、
    前記枠状突起の対向する二辺と該二辺の間を覆う薄肉成形部は前記第二のモールド樹脂により一体的に成形され、前記枠状突起の他の対向する二辺は前記第一のモールド樹脂により成形されたことを特徴とする半導体装置。
  2. 　前記第二のモールド樹脂は、トランスファー成形工程で用いられた成形金型のゲート内に残った樹脂の痕跡であるゲートブレイク跡を有し、前記枠状突起の前記ゲートブレイク跡に最も近い辺を含む二辺と該二辺の間を覆う前記薄肉成形部が、前記第二のモールド樹脂により成形されたことを特徴とする請求項１記載の半導体装置。
  3. 　前記枠状突起は、その各辺と直交する方向に切断した断面形状が、円弧状の先端部を有することを特徴とする請求項１または請求項２に記載の半導体装置。
  4. 　前記枠状突起は、その各辺と直交する方向に切断した断面形状が矩形であり、その角部が丸みを帯びていることを特徴とする請求項１または請求項２に記載の半導体装置。
  5. 　前記リードフレームの離間された二つの領域の間の少なくとも一部に、前記第一のモールド樹脂が配置され、前記二つの領域の間に配置された前記第一のモールド樹脂は、前記第二のモールド樹脂との接合面に凹部を有することを特徴とする請求項１から請求項４のいずれか一項に記載の半導体装置。
  6. 　前記リードフレームの離間された二つの領域の間の少なくとも一部に、前記第二のモールド樹脂により成形されたリードフレーム間充填部が配置されることを特徴とする請求項１から請求項５のいずれか一項に記載の半導体装置。
  7. 　前記リードフレーム間充填部が配置された前記リードフレームの側面の一部に、カエリを有することを特徴とする請求項６記載の半導体装置。
  8. 　前記リードフレーム間充填部は、前記第一のモールド樹脂との接合部に凹部を有することを特徴とする請求項６記載の半導体装置。
  9. 　前記リードフレームの離間された二つの領域を跨ぐように前記実装面にブリッジ実装された電子部品を備え、前記電子部品の直下に相当する前記第二のモールド樹脂に窪みが設けられ、前記窪みに前記第一のモールド樹脂が充填されたことを特徴とする請求項１から請求項８のいずれか一項に記載の半導体装置。
  10. 　前記リードフレームとして、表面が粗化された金属めっきにより被膜された粗化金属めっきリードフレームを用いたことを特徴とする請求項１から請求項９のいずれか一項に記載の半導体装置。
  11. 　前記リードフレームは、金属めっきにより被膜され、前記金属めっきの表面形状を鱗状に変形させた鱗状部を有することを特徴とする請求項１から請求項１０のいずれか一項に記載の半導体装置。
  12. 　前記第一のモールド樹脂は、トランスファー成形工程で用いられた成形金型のゲート内に残った樹脂の痕跡であるゲートブレイク跡を有し、前記鱗状部は、前記リードフレームの前記実装面の前記ゲートブレイク跡に近接する箇所に配置されることを特徴とする請求項１１記載の半導体装置。
  13. 　前記第二のモールド樹脂は、トランスファー成形工程で用いられた成形金型のゲート内に残った樹脂の痕跡であるゲートブレイク跡を有し、前記鱗状部は、前記リードフレームの前記放熱面の前記ゲートブレイク跡に近接する箇所に配置されることを特徴とする請求項１１または請求項１２に記載の半導体装置。
  14. 　前記鱗状部は、前記リードフレームの前記実装面及び前記放熱面のいずれか一方または両方の外周部に配置されることを特徴とする請求項１１から請求項１３のいずれか一項に記載の半導体装置。
  15. 　前記第二のモールド樹脂には、前記第一のモールド樹脂よりも熱伝導率が高い高放熱樹脂が用いられることを特徴とする請求項１から請求項１４のいずれか一項に記載の半導体装置。
  16. 　前記第一のモールド樹脂及び前記第二のモールド樹脂には、熱伝導率が３Ｗ／ｍ・Ｋ～１２Ｗ／ｍ・Ｋの高放熱樹脂が用いられることを特徴とする請求項１から請求項１４のいずれか一項に記載の半導体装置。
  17. 　前記第二のモールド樹脂は、最大径が０．０２ｍｍ～０．１５ｍｍのフィラーを含有し、前記薄肉成形部の厚さは、０．０２２ｍｍ～０．３ｍｍであることを特徴とする請求項１から請求項１６のいずれか一項に記載の半導体装置。
  18. 　前記薄肉成形部は、表面のスキン層が除去されていることを特徴とする請求項１から請求項１７のいずれか一項に記載の半導体装置。
  19. 　前記リードフレームの前記放熱面を覆う前記薄肉成形部に、ヒートシンクが直接接合されたことを特徴とする請求項１から請求項１８のいずれか一項に記載の半導体装置。
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