WO2016161840A1 - 横向扩散金属氧化物半导体场效应管及其制造方法 - Google Patents

横向扩散金属氧化物半导体场效应管及其制造方法 Download PDF

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WO2016161840A1
WO2016161840A1 PCT/CN2016/072839 CN2016072839W WO2016161840A1 WO 2016161840 A1 WO2016161840 A1 WO 2016161840A1 CN 2016072839 W CN2016072839 W CN 2016072839W WO 2016161840 A1 WO2016161840 A1 WO 2016161840A1
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well
plug
region
substrate
drain
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French (fr)
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祁树坤
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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Priority to US15/564,727 priority Critical patent/US10249707B2/en
Priority to JP2017551034A priority patent/JP6538190B2/ja
Publication of WO2016161840A1 publication Critical patent/WO2016161840A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H10D30/655—Lateral DMOS [LDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform

Definitions

  • the present invention relates to semiconductor processes, and more particularly to a laterally diffused metal oxide semiconductor field effect transistor, and to a method of fabricating a laterally diffused metal oxide semiconductor field effect transistor.
  • the basic structure using the RESURF (Reduced Surface Electric Field) principle consists of a low doped P-type substrate and a low doped N-type epitaxial layer.
  • a P well is formed on the epitaxial layer and N+, P+ are implanted to form a lateral P-well/N-epi (P-well-N-type epitaxial layer) junction and a longitudinal P-sub/N-epi (P-type substrate).
  • -N type epitaxial layer) junction Due to the higher doping concentration at both ends of the lateral junction, the breakdown voltage is lower than the longitudinal junction.
  • RESURF The basic principle of RESURF is to make the epitaxial layer completely depleted before the lateral junction reaches the critical avalanche breakdown electric field by using the interaction of the lateral junction and the longitudinal junction. By reasonably optimizing the device parameters, the breakdown of the device occurs in the longitudinal junction, thereby To reduce the effect of the surface electric field.
  • the lighter deep well is easily depleted, and the breakdown is likely to occur on the surface of the drain region, and the on-resistance is high, thereby affecting reliability and product application.
  • a laterally diffused metal oxide semiconductor field effect transistor comprising a substrate, a source, a drain, a body region and a well region on the substrate, the well region comprising: a plug-in well, the doping type being P-type, An N-well is disposed on the two sides of the plug-in well; a P-well is disposed adjacent to the N-well and connected to the N-well; the source and The body region is disposed in the P well.
  • a method for fabricating a laterally diffused metal oxide semiconductor field effect transistor comprising the steps of: providing a substrate; photolithographically forming an N-well implantation window; and implanting N-type ions into the substrate through the implantation window; The photoresist overlying the substrate is separated to retain the position of the plug-in well; the hot push well forms an N-well; the P-type ions are implanted and the well is thermally pushed to form the plug-in well inserted into the N-well, and formed a P-well adjacent to the N-well and connected to the N-well; forming an active region and field oxide; forming a source and a drain; the drain is formed over the plug-in well and is in contact with the plug-in well.
  • Another method of fabricating a laterally diffused metal oxide semiconductor field effect transistor comprising the steps of: providing a substrate; photolithographically forming a first N well implant window; and implanting N-type ions into the substrate through the implant window;
  • the implantation window is separated by a photoresist overlying the substrate to retain the position of the first plug-in well;
  • the hot push well forms a first N-well;
  • the P-type ions are implanted and the well is thermally pushed to form the first N-well
  • the laterally diffused metal oxide semiconductor field effect transistor is formed by a plug-in well to form a triple
  • the RESURF structure helps to increase the doping concentration of the N-well and lower the on-resistance of the device, and helps to improve the breakdown characteristics of the device.
  • FIG. 1 is a schematic structural view of a laterally diffused metal oxide semiconductor field effect transistor in an embodiment
  • FIG. 2 is a schematic structural view of a laterally diffused metal oxide semiconductor field effect transistor in another embodiment
  • FIG. 3 is a flow chart showing a method of manufacturing a laterally diffused metal oxide semiconductor field effect transistor in the embodiment shown in FIG. 1;
  • FIG. 4 is a flow chart showing a method of fabricating a laterally diffused metal oxide semiconductor field effect transistor in the embodiment shown in FIG. 2.
  • the present invention provides a laterally diffused metal oxide semiconductor field effect transistor having a reduced surface electric field (RESURF) structure including a substrate, a source, a drain, a body region, and a well region on the substrate.
  • the well region specifically includes an N well, a P well, and a plug-in well inserted into the N well.
  • the doped type of the plug-in well is P-type, disposed under the drain and connected to the drain and the substrate.
  • N wells are provided on both sides of the plug-in well.
  • the P well is placed beside the N well and connected to the N well.
  • the source and body regions are disposed in the P well.
  • LDMOS laterally diffused metal oxide semiconductor field effect transistor
  • RESURF structure in an embodiment, which is a left-right symmetric structure including a substrate 110, a well region on the substrate, a drain 140, and a source.
  • the substrate is P-doped
  • the drain 140 is N-doped
  • the source 150 is N-doped
  • the body region 160 is P-doped.
  • the well region includes a P-type doped plug well 122, an N well 124 as a drift region, and a P well 126 as a channel region.
  • the field oxide region 170 is disposed on the surface of the N well 124 of the drift region, the two field oxygen regions 170 structure sandwich the drain 140, and the polysilicon structure 180 is composed of a polysilicon gate and a field portion, which is overlapped from the surface of the field oxygen region 170 to Source 150 surface.
  • the P well 126 is inserted by splitting the N well 124 to a certain width to form a triple.
  • the RESURF structure allows the interposer well 122, the N well 124, the P well 126, and the substrate 110 to be depleted from each other, and the breakdown point is transferred into the device body, and the device is longitudinally broken down.
  • the width of the plug-in well 122 is 10% to 40% of the width of the active region of the drain.
  • the width of the plug-in well 122 is not too wide, and it is necessary to ensure that the two N-wells 124 under the drain 140 are still connected to the drain 140 (ie, the width of the plug-in well 122 is at least narrower than the drain 140), such that the drift region
  • the N-well 124 concentration is improved over the prior art to contribute to a reduction in on-resistance. This is because when an extra charge is added to the depletion region, the opposite type of charge density is correspondingly increased to achieve the charge balance requirement.
  • the plug-in well 122 cannot be too narrow. A certain width of the plug-in well 122 can effectively control the occurrence of breakdown in the device body. If the width is too narrow, the plug-in well 122 has less influence on the depletion region of the N-wells 124 on both sides, and the breakdown position is still in the prior art. When the breakdown position of the drift region N well 124 is not set when the plug-in well 122 is not provided, the insertion of the plug-in well 122 does not function to adjust the breakdown.
  • the intervening well 122 and the N well 124 of the drift region on both sides are depleted until the depletion layer formed by the N wells 124 on both sides gradually expands to overlap.
  • the potential lines on both sides are connected, and then depleted from the top to the bottom in the substrate 110, and the electric field peak is weakened, thereby effectively improving the breakdown voltage.
  • drain 140 is N+ drain
  • source 150 is N+ source
  • body region 160 is P+ body region.
  • the LDMOS includes a substrate 210, a first well region on the substrate and a second well region on the first well region, a drain 240, a source 250, a body region 260, a field oxide region 270, and a polysilicon structure 280.
  • the first well region includes a P-type doped first plug-in well 222, a first N-well 224, and a first P-well 226;
  • the second well region includes a second plug-in well 232, a second N-well 234, and a third P-P
  • the well 236, the second plug-in well 232, the second N-well 234, and the third P-well 236 are respectively connected to the first plug-in well 222, the first N-well 224, and the first P-well 226; the first N-well 224 and The second N wells 234 collectively function as a drift region.
  • the source 250 and the body region 260 are disposed in the second P well 236.
  • the LDMOS further includes a floating layer P-well 235 disposed in the second N-well 234 below the field oxide region 270.
  • the doping concentration is lighter than that of the second N-well 234, which can slow down the concentration gradient and increase the withstand voltage of the device.
  • the N-well including the first N-well 224 and the second N-well 234.
  • the N+ between the plug-in wells still has a certain effective width, at least 30% of the active area of the drain 240. Therefore, the width of the first plug-in well 222 and the second plug-in well 232 should not exceed 40% of the width of the active region of the drain 240. In embodiments where the active region is 10 microns wide, the aforementioned effective width is at least 3 microns, i.e., the width of the first plug-in well 222 and the second plug-in well 232 does not exceed 2 microns.
  • drain 240 is N+ drain
  • source 250 is N+ source
  • body region 260 is P+ body region.
  • the present invention also provides a method of fabricating a laterally diffused metal oxide semiconductor field effect transistor having a RESURF structure for forming the LDMOS shown in FIG. 3 is a flow chart of the method in an embodiment, including the following steps:
  • a P-type doped silicon substrate is provided.
  • the hot push well forms an N well.
  • the N well is oxidized while the well is being pushed, and an oxide layer is formed on the surface of the N well.
  • the oxide layer can provide a self-aligned implant structure for the P implant of step S340, omitting a lithographic plate. Note that the photoresist is also removed before performing the next step.
  • the formed plug-in well is sandwiched by the N-well, and the P-well is formed outside the N-well and is in contact therewith.
  • gate oxide and polysilicon gates are generated.
  • a drain is formed over the plug-in well and is in contact with the plug-in well.
  • the present invention also provides another method of fabricating a laterally diffused metal oxide semiconductor field effect transistor having a RESURF structure for forming the LDMOS shown in FIG. 4 is a flow chart of the method in an embodiment, including the following steps:
  • photolithography forms a first N-well implantation window, and implants N-type ions into the substrate through the implantation window.
  • the hot push well forms a first N well.
  • Oxidation of the first N well is performed while the well is thermally pushed, and an oxide layer is formed on the surface of the first N well.
  • the photoresist is also removed before the next step is performed.
  • the photoresist pattern is the same as that in step S420.
  • the implanted N-type ions are pushed down to the first N-well by a hot push trap.
  • the second N well is oxidized while the well is being pushed, and an oxide layer is formed on the surface of the second N well as a self-aligned implant structure.
  • the photoresist is also removed before the next step is performed.
  • gate oxide and polysilicon gates are generated.
  • a drain is formed over and in contact with the second plug-in well.

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  • Chemical & Material Sciences (AREA)
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Abstract

一种横向扩散金属氧化物半导体场效应管，包括衬底（110）、源极（150）、漏极（140）、体区（160）及衬底上的阱区，阱区包括：插入式阱（122），掺杂类型为P型，设于漏极的下方并与漏极相接；N阱（124），设于插入式阱的两侧；P阱（126），设于N阱的旁边并与N阱连接；源极和体区设于P阱内。

Description

横向扩散金属氧化物半导体场效应管及其制造方法
【技术领域】
本发明涉及半导体工艺，特别是涉及一种横向扩散金属氧化物半导体场效应管，还涉及一种横向扩散金属氧化物半导体场效应管的制造方法。
【背景技术】
采用RESURF（降低表面电场）原理的基本结构由低掺杂的P型衬底和低掺杂的N型外延层组成。在外延层上形成P阱并注入N+、P+，形成一个横向的P-well/N-epi（P阱-N型外延层）结和一个纵向的P-sub/N-epi（P型衬底-N型外延层）结。由于横向结两端有着更高的掺杂浓度，因此击穿电压比纵向结更低。RESURF的基本原理是利用横向结和纵向结的相互作用，使外延层在横向结达到临界雪崩击穿电场前完全耗尽，通过合理优化器件参数，使得器件的击穿发生在纵向结，从而起到降低表面电场的作用。
传统的RESURF结构，较淡的深阱易被耗尽，击穿易发生于漏端区域表面，且导通电阻偏高，从而影响可靠性及产品应用。
【发明内容】
基于此，有必要针对背景技术中提到的传统RESURF结构导通电阻偏高、易击穿的问题，提供一种低导通电阻、且能够改善击穿特性的横向扩散金属氧化物半导体场效应管。
一种横向扩散金属氧化物半导体场效应管，包括衬底、源极、漏极、体区及衬底上的阱区，所述阱区包括：插入式阱，掺杂类型为P型，设于所述漏极的下方并与漏极相接；N阱，设于所述插入式阱的两侧；P阱，设于所述N阱的旁边并与N阱连接；所述源极和体区设于所述P阱内。
一种横向扩散金属氧化物半导体场效应管的制造方法，包括步骤：提供衬底；光刻形成N阱注入窗口，并通过所述注入窗口向衬底内注入N型离子；所述注入窗口被覆盖在衬底上的光刻胶分隔而保留出插入式阱的位置；热推阱形成N阱；注入P型离子并热推阱，形成插入所述N阱的所述插入式阱，以及形成于N阱旁边并与N阱相接的P阱；形成有源区和场氧；形成源极和漏极；所述漏极形成于所述插入式阱上方并与插入式阱相接。
另一种横向扩散金属氧化物半导体场效应管的制造方法，包括步骤：提供衬底；光刻形成第一N阱注入窗口，并通过所述注入窗口向衬底内注入N型离子；所述注入窗口被覆盖在衬底上的光刻胶分隔而保留出第一插入式阱的位置；热推阱形成第一N阱；注入P型离子并热推阱，形成插入所述第一N阱的所述第一插入式阱，以及形成于第一N阱旁边并与第一N阱相接的第一P阱；在所述衬底上形成第一外延层；光刻并向所述外延层中注入N型离子，推阱后在第一N阱上方形成与第一N阱相接的第二N阱；注入P型离子并热推阱，形成插入第二N阱的第二插入式阱，以及第二N阱旁的第二P阱；所述第二插入式阱形成于第一插入式阱上方并与第一插入式阱相接，所述第二P阱形成于所属第一P阱上方并与第一P阱相接；形成有源区和场氧；形成源极和漏极；所述漏极形成于所述第二插入式阱上方并与第二插入式阱相接。
上述横向扩散金属氧化物半导体场效应管，通过插入式阱形成triple RESURF结构，有助于提高N阱的掺杂浓度，并降低器件的导通电阻，并且有助于改善器件的击穿特性。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是一实施例中横向扩散金属氧化物半导体场效应管的结构示意图；
图2是另一实施例中横向扩散金属氧化物半导体场效应管的结构示意图；
图3是图1所示实施例中横向扩散金属氧化物半导体场效应管的制造方法的流程图；
图4是图2所示实施例中横向扩散金属氧化物半导体场效应管的制造方法的流程图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及／或”包括一个或多个相关的所列项目的任意的和所有的组合。
本发明提供一种具有降低表面电场（RESURF）结构的横向扩散金属氧化物半导体场效应管，包括衬底、源极、漏极、体区及衬底上的阱区。阱区具体包括N阱、P阱以及插入N阱中的插入式阱，其中插入式阱的掺杂类型为P型，设于漏极的下方并与漏极和衬底相接。N阱设于插入式阱的两侧。P阱设于N阱的旁边并与N阱连接。源极和体区设于P阱内。
图1是一实施例中具有RESURF结构的横向扩散金属氧化物半导体场效应管（LDMOS）的结构示意图，其为左右对称结构，包括衬底110，衬底上的阱区，漏极140，源极150，体区160，场氧区170以及多晶硅结构180。其中，衬底为P型掺杂，漏极140为N型掺杂，源极150为N型掺杂，体区160为P型掺杂。阱区包括P型掺杂的插入式阱122、作为漂移区的N阱124以及作为沟道区的P阱126。场氧区170设于漂移区的N阱124表面，两块场氧区170结构将漏极140夹于中间，多晶硅结构180由多晶硅栅和搭场部分组成，从场氧区170表面搭接至源极150表面。
如图1所示，在现有结构的漏端N+结下方，通过将N阱124裂开一定宽度，插入P阱126，形成triple RESURF结构，使得插入式阱122、N阱124、P阱126及衬底110之间相互耗尽，击穿点向器件体内转移，器件得以纵向击穿。
在其中一个实施例中，插入式阱122的宽度为漏极的有源区宽度的10%~40%。
插入式阱122的宽度不能太宽，需要保证漏极140下方的两侧N阱124仍然与漏极140相接（即插入式阱122的宽度至少要比漏极140窄），这样漂移区的N阱124浓度相较现有技术得以提高，有助于导通电阻的降低。这是因为当耗尽区中加入额外的电荷后，相反类型的电荷密度也会相应提高，以达到电荷平衡的要求。
插入式阱122不能太窄。一定宽度的插入式阱122可以有效控制器件体内击穿发生的先后，如宽度过窄，插入式阱122对两侧N阱124的耗尽区影响较小，击穿位置仍与现有技术中漂移区N阱124不设置插入式阱122时的击穿位置接近，那么插入式阱122的插入就起不到对于击穿的调整作用了。
当漏极140外接较高电位，耗尽至漏极140时，插入式阱122与两侧漂移区的N阱124相互耗尽，直至两侧N阱124形成的耗尽层逐渐扩大至交叠于P阱126中，两侧电势线相接，之后由上而下向衬底110中耗尽，电场峰值被削弱，进而有效改善击穿电压。
在图1所示实施例中，漏极140为N+漏极，源极150为N+源极，体区160为P+体区。
图2是另一实施例中具有RESURF结构的横向扩散金属氧化物半导体场效应管的结构示意图，其与图1所示实施例的区别在于阱区由一层用于与高压器件配合的高压阱、和一层用于与低压器件配合的低压阱组成。即LDMOS包括衬底210，衬底上的第一阱区和第一阱区上的第二阱区，漏极240，源极250，体区260，场氧区270以及多晶硅结构280。第一阱区包括P型掺杂的第一插入式阱222、第一N阱224以及第一P阱226；第二阱区包括第二插入式阱232、第二N阱234以及第三P阱236，第二插入式阱232、第二N阱234以及第三P阱236分别与第一插入式阱222、第一N阱224以及第一P阱226相接；第一N阱224和第二N阱234共同作为漂移区。其中源极250和体区260设于第二P阱236内。
在图2所示实施例中，LDMOS还包括设于第二N阱234内、场氧区270下方的浮层P阱235。其掺杂浓度比第二N阱234要淡，可以减缓浓度梯度、提高器件耐压。
为了确保漂移区耗尽至漏极240的有源区（DTO）时，仍有较高浓度的N型杂质，必须保证此时N阱（包括第一N阱224和第二N阱234）与插入式阱（包括第一插入式阱222和第二插入式阱232）间的N+的仍有一定的有效宽度，至少为漏极240的有源区的30%。因此，第一插入式阱222和第二插入式阱232的宽度不应超过漏极240的有源区宽度的40%。在有源区宽10微米的实施例中，前述有效宽度至少为3微米，即第一插入式阱222和第二插入式阱232的宽度不超过2微米。
在图2所示实施例中，漏极240为N+漏极，源极250为N+源极，体区260为P+体区。
本发明还提供一种具有RESURF结构的横向扩散金属氧化物半导体场效应管的制造方法，用于形成图1所示的LDMOS。图3是一实施例中该方法的流程图，包括下列步骤：
S310，提供衬底。
本实施例中是提供P型掺杂的硅衬底。
S320，光刻形成N阱注入窗口，并通过注入窗口向衬底内注入N型离子。
由于要在N阱中插入一个P阱，因此在需要插入的位置形成光刻胶，保留出位置供后续形成插入式阱。光刻之前可以先进行初始氧化。
S330，热推阱形成N阱。
热推阱的同时进行N阱的氧化，在N阱表面形成氧化层。该氧化层可以为步骤S340的P注入提供自对准注入结构，省去一块光刻版。注意执行下一步骤之前还要去除光刻胶。
S340，注入P型离子并热推阱，形成插入N阱的插入式阱，以及N阱旁边的P阱。
形成的插入式阱被N阱夹在中间，P阱形成于N阱外侧并与其相接。
S350，形成有源区和场氧。
在本实施例中，形成有源区和场氧后，生成栅氧和多晶硅栅极。
S360，形成源极和漏极。
漏极形成于插入式阱上方并与插入式阱相接。
本发明还提供另一种具有RESURF结构的横向扩散金属氧化物半导体场效应管的制造方法，用于形成图2所示的LDMOS。图4是一实施例中该方法的流程图，包括下列步骤：
S410，提供衬底。
S420，光刻形成第一N阱注入窗口，并通过注入窗口向衬底内注入N型离子。
S430，热推阱形成第一N阱。
热推阱的同时进行第一N阱的氧化，在第一N阱表面形成氧化层。执行下一步骤之前还要去除光刻胶。
S440，注入P型离子并热推阱，形成插入第一N阱的第一插入式阱，以及第一N阱旁的第一P阱。
S450，在衬底上形成外延层。
外延之前去除多余的氧化层。
S460，光刻并向外延层中注入N型离子，热推阱后形成与第一N阱相接的第二N阱。
光刻胶图案与步骤S420中的相同。通过热推阱将注入的N型离子向下推至与第一N阱相接。热推阱的同时进行第二N阱的氧化，在第二N阱表面形成氧化层，作为自对准注入结构。执行下一步骤之前还要去除光刻胶。
S470，注入P型离子并热推阱，形成插入第二N阱的第二插入式阱，以及第二N阱旁的第二P阱。
S480，形成有源区和场氧。
在本实施例中，形成有源区和场氧后，生成栅氧和多晶硅栅极。
S490，形成源极和漏极。
漏极形成于第二插入式阱上方并与其相接。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (14)

  1. 一种横向扩散金属氧化物半导体场效应管，包括衬底、源极、漏极、体区及衬底上的阱区，其特征在于，所述阱区包括：
    插入式阱，掺杂类型为P型，设于所述漏极的下方并与所述漏极相接；
    N阱，设于所述插入式阱的两侧；及
    P阱，设于所述N阱的旁边并与所述N阱相接；所述源极和所述体区设于所述P阱内。
  2. 根据权利要求1所述的横向扩散金属氧化物半导体场效应管，其特征在于，所述阱区包括所述衬底上的第一阱区和第一阱区上的第二阱区，所述插入式阱包括所述第一阱区内的第一插入式阱和所述第二阱区内的第二插入式阱，所述N阱包括所述第一阱区内的第一N阱和所述第二阱区内的第二N阱，所述P阱包括所述第一阱区内的第一P阱和所述第二阱区内的第二P阱。
  3. 根据权利要求2所述的横向扩散金属氧化物半导体场效应管，其特征在于，所述第一N阱的掺杂浓度低于所述第二N阱的掺杂浓度，所述第一P阱的掺杂浓度低于所述第二P阱的掺杂浓度，所述第一插入式阱的掺杂浓度低于所述第二插入式阱的掺杂浓度。
  4. 根据权利要求1所述的横向扩散金属氧化物半导体场效应管，其特征在于，还包括场氧区和多晶硅结构，所述场氧区设于所述N阱表面，两块所述场氧区结构将所述漏极夹于中间，所述多晶硅结构从所述场氧区表面搭接至所述源极表面。
  5. 根据权利要求4所述的横向扩散金属氧化物半导体场效应管，其特征在于，还包括设于所述N阱内、场氧区下方的浮层P阱。
  6. 根据权利要求1所述的横向扩散金属氧化物半导体场效应管，其特征在于，所述插入式阱的宽度不超过所述漏极的有源区宽度的40%。
  7. 根据权利要求6所述的横向扩散金属氧化物半导体场效应管，其特征在于，所述插入式阱的宽度为所述漏极的有源区宽度的10%~40%。
  8. 根据权利要求2所述的横向扩散金属氧化物半导体场效应管，其特征在于，所述漏极的有源区宽度为10微米，所述第一插入式阱和所述第二插入式阱的宽度不超过2微米。
  9. 根据权利要求1所述的横向扩散金属氧化物半导体场效应管，其特征在于，所述阱区的掺杂浓度低于所述漏极的掺杂浓度。
  10. 根据权利要求1所述的横向扩散金属氧化物半导体场效应管，其特征在于，所述衬底为P掺杂衬底，所述漏极为N掺杂漏极，所述源极为N掺杂源极，所述体区为P掺杂体区。
  11. 一种横向扩散金属氧化物半导体场效应管的制造方法，包括步骤：
    提供衬底；
    通过光刻在所述衬底上形成N阱注入窗口，并通过所述N阱注入窗口向所述衬底内注入N型离子；所述N阱注入窗口被覆盖在所述衬底上的光刻胶分隔而保留出插入式阱的位置；
    热推阱形成N阱；
    向所述衬底内注入P型离子并热推阱，形成插入所述N阱的所述插入式阱，以及形成于所述N阱旁边并与所述N阱相接的P阱；
    形成有源区和场氧；及
    形成源极和漏极；所述漏极形成于所述插入式阱上方，并与所述插入式阱相接。
  12. 根据权利要求11所述的方法，其特征在于，所述热推阱形成N阱的步骤包括在所述N阱表面形成氧化层，作为所述向衬底内注入P型离子步骤的自对准注入结构。
  13. 一种横向扩散金属氧化物半导体场效应管的制造方法，包括步骤：
    提供衬底；
    通过光刻在所述衬底上形成第一N阱注入窗口，并通过所述第一N阱注入窗口向衬底内注入N型离子；所述第一N阱注入窗口被覆盖在所述衬底上的光刻胶分隔而保留出第一插入式阱的位置；
    热推阱形成第一N阱；
    向所述衬底内注入P型离子并热推阱，形成插入所述第一N阱的所述第一插入式阱，以及形成于所述第一N阱旁边并与所述第一N阱相接的第一P阱；
    在所述衬底上形成第一外延层；
    光刻并向所述第一外延层中注入N型离子，热推阱后在所述第一N阱上方形成与所述第一N阱相接的第二N阱；
    向所述第二N阱内注入P型离子并热推阱，形成插入第二N阱的第二插入式阱，以及第二N阱旁的第二P阱；所述第二插入式阱形成于第一插入式阱上方，并与所述第一插入式阱相接，所述第二P阱形成于所述第一P阱上方，并与所述第一P阱相接；
    形成有源区和场氧；及
    形成源极和漏极；所述漏极形成于所述第二插入式阱上方，并与所述第二插入式阱相接。
  14. 根据权利要求13所述的方法，其特征在于，所述热推阱形成第一N阱的步骤包括在所述第一N阱表面形成氧化层，作为所述向衬底内注入P型离子步骤的自对准注入结构。
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