WO2016155149A1 - 多晶硅薄膜制备方法、半导体器件、显示基板及显示装置 - Google Patents

多晶硅薄膜制备方法、半导体器件、显示基板及显示装置 Download PDF

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WO2016155149A1
WO2016155149A1 PCT/CN2015/084215 CN2015084215W WO2016155149A1 WO 2016155149 A1 WO2016155149 A1 WO 2016155149A1 CN 2015084215 W CN2015084215 W CN 2015084215W WO 2016155149 A1 WO2016155149 A1 WO 2016155149A1
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buffer layer
buffer
polysilicon film
silicon film
amorphous silicon
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PCT/CN2015/084215
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English (en)
French (fr)
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徐文清
龙春平
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京东方科技集团股份有限公司
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Priority to US14/894,908 priority Critical patent/US10062566B2/en
Publication of WO2016155149A1 publication Critical patent/WO2016155149A1/zh

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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1277—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using a crystallisation promoting species, e.g. local introduction of Ni catalyst
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a method for fabricating a polysilicon film, a semiconductor device, a display substrate, and a display device.
  • the existing amorphous silicon itself has many unavoidable disadvantages such as low mobility, low stability, and the like.
  • Low temperature polysilicon has higher mobility and stability than amorphous silicon. Therefore, low temperature polysilicon technology has developed rapidly.
  • the unevenness of the grain size of the polycrystalline silicon and the irregular arrangement of the crystal grains may cause unevenness of the threshold voltage, thereby affecting the display quality of the display panel using the polycrystalline silicon film.
  • Embodiments of the present invention provide a method for manufacturing a polysilicon film for solving the problem of uneven grain size of polycrystalline silicon and irregular grain arrangement in a polycrystalline silicon film produced by a method for manufacturing a polycrystalline silicon film of the prior art.
  • Embodiments of the present invention also provide a semiconductor device including the polysilicon film, a display substrate, and a display device.
  • Embodiments of the present invention provide a method of fabricating a polysilicon film, comprising: forming a buffer layer on a substrate; forming a regularly arranged first groove on a surface of the buffer layer; forming the first groove Forming an amorphous silicon film on the buffer layer; and crystallizing the amorphous silicon film by an optical annealing process to form a polysilicon film.
  • the optical annealing process comprises an excimer laser annealing process.
  • the buffer layer includes at least one first buffer sublayer and at least one second buffer sublayer disposed in a stack, and the first buffer sublayer and the second buffer sublayer are alternately arranged.
  • the material of the first buffer sublayer is silicon dioxide
  • the material of the second buffer sublayer is silicon nitride
  • the distance between the first grooves ranges from 300 nm to 400 nm.
  • the shape of the first groove is circular or square.
  • the method before the step of performing crystallization treatment on the amorphous silicon film by using an optical annealing process, the method further comprises: performing dehydrogenation treatment on the amorphous silicon film.
  • the material of the buffer layer is silicon dioxide.
  • the thickness of the buffer layer ranges from 100 nm to 600 nm.
  • Embodiments of the present invention also provide a semiconductor device including a substrate, a buffer layer, and a polysilicon film which are sequentially stacked, wherein a surface of the buffer layer that is in contact with the polysilicon film is provided with a regularly arranged first concave And a polysilicon film formed by crystallization treatment of an amorphous silicon film formed on the buffer layer provided with the regularly arranged first grooves by an optical annealing process.
  • Embodiments of the present invention also provide a display substrate including a substrate, a buffer layer, and a polysilicon film which are sequentially stacked, wherein a surface of the buffer layer that is in contact with the polysilicon film is provided with a regularly arranged first concave And a polysilicon film formed by crystallization treatment of an amorphous silicon film formed on the buffer layer provided with the regularly arranged first grooves by an optical annealing process.
  • the buffer layer comprises at least one first buffer sublayer and at least one second buffer sublayer disposed in a stack.
  • the first buffer sublayer and the second buffer sublayer are alternately arranged, the material of the first buffer sublayer is silicon dioxide, and the material of the second buffer sublayer is silicon nitride.
  • the distance between the first grooves ranges from 300 nm to 400 nm.
  • the thickness of the buffer layer ranges from 100 nm to 600 nm.
  • Embodiments of the present invention also provide a display device including any of the above display substrates.
  • a method of preparing a polysilicon film according to the present invention includes: forming a buffer layer on a substrate; forming a regularly arranged first groove on a surface of the buffer layer; forming a non-deposit on the buffer layer on which the first groove is formed a crystalline silicon film; and crystallization treatment of the amorphous silicon film by an optical annealing process to form a polysilicon film.
  • an amorphous silicon film is formed after forming a regularly arranged first groove on the buffer layer, and then the amorphous silicon film is subjected to crystallization treatment by an optical annealing process.
  • the semiconductor device, display substrate and display device according to the present invention comprise a polycrystalline silicon film produced by the above-described method for producing a polycrystalline silicon film of the present invention, and thus have improved performance.
  • FIG. 1 is a flow chart of a method for preparing a polysilicon film according to a first embodiment of the present invention.
  • FIG 2 is a cross-sectional view of a buffer layer formed in accordance with the method of the first embodiment of the present invention.
  • Fig. 3 is a cross-sectional view taken along line A-A of the buffer layer shown in Fig. 2;
  • FIG. 4 is a cross-sectional view of an amorphous silicon film formed by the method according to the first embodiment of the present invention.
  • Fig. 5 is a schematic view showing the annealing treatment of the amorphous silicon film shown in Fig. 4.
  • Figure 6 is a cross-sectional view showing a polycrystalline silicon film formed by the method according to the first embodiment of the present invention.
  • Fig. 7 is a cross-sectional view taken along line B-B of the polycrystalline silicon film shown in Fig. 6.
  • FIG. 1 is a flow chart of a method for preparing a polysilicon film according to a first embodiment of the present invention. As shown in FIG. 1, the method for preparing the polysilicon film includes the following steps 1001 to 1004.
  • Step 1001 forming a buffer layer on the substrate.
  • FIG. 2 is a cross-sectional view of a buffer layer formed by the method according to the first embodiment of the present invention
  • FIG. 3 is a cross-sectional view taken along line A-A of the buffer layer shown in FIG. 2.
  • a buffer layer 101 is formed on a substrate (not shown).
  • the material of the buffer layer 101 may be silicon dioxide.
  • the buffer layer 101 includes a first buffer sublayer and a second buffer sublayer (not shown) disposed in a stack.
  • the buffer layer 101 may include a plurality of first buffer sublayers and a plurality of second buffer sublayers disposed in a stack, and the first buffer sublayer and the second buffer sublayer are alternately arranged.
  • the material of the first buffer sublayer is silicon dioxide
  • the material of the second buffer sublayer is silicon nitride.
  • the thickness of the buffer layer ranges from 100 nm to 600 nm.
  • the buffer layer serves to smooth the substrate and serves to prevent impurities in the substrate from penetrating into the polysilicon film during the formation of the polysilicon film.
  • Step 1002 forming a regularly arranged first groove on the surface of the buffer layer.
  • a regularly arranged first groove 102 is formed on the surface of the buffer layer 101 (i.e., the surface opposite to the surface contacting the substrate).
  • a photoresist is coated on the buffer layer, and the photoresist is exposed and developed using a mask to form a photoresist retention region and a photoresist removal region.
  • the removal area corresponds to a pattern area forming a first groove
  • the photoresist retention area corresponds to other areas outside the pattern area.
  • the buffer layer is etched to form a first recess.
  • the distance between the first grooves 102 ranges from 300 nm to 400 nm, and the shape of the first grooves 102 is circular or square.
  • Step 1003 forming an amorphous silicon film on the buffer layer on which the first recess is formed.
  • FIG. 4 is a cross-sectional view of an amorphous silicon film formed by the method according to the first embodiment of the present invention.
  • an amorphous silicon film 103 is formed on the buffer layer 101. Since the surface of the buffer layer 101 is provided with the first recess 102, the surface of the amorphous silicon film 103 also forms a second recess 104 corresponding to the first recess 102. Since the first grooves 102 are regularly arranged, the second grooves 104 are also regularly arranged.
  • the amorphous silicon film is subjected to a dehydrogenation treatment.
  • Step 1004 The amorphous silicon film is subjected to crystallization treatment by an optical annealing process to form a polysilicon film.
  • Fig. 5 is a schematic view showing the annealing treatment of the amorphous silicon film shown in Fig. 4.
  • Figure 5 the amorphous silicon film 103 can be crystallized by an excimer laser annealing process. Since the amorphous silicon film 103 is provided with the regularly arranged second grooves 104, when the excimer laser annealing process is performed, in the case where the laser light 108 is focused on the upper surface of the amorphous silicon film 103, the laser The focus of 108 does not reach the depth at which the amorphous silicon material corresponding to the second recess 104 is located.
  • the amorphous silicon material corresponding to the second recess 104 receives less energy from the laser than the amorphous silicon material corresponding to the region outside the second recess 104.
  • the amorphous silicon material corresponding to the region other than the second recess 104 may still be incapable of melting, thereby forming the crystal seed 105 (for example, The crystal seed 105 is formed in the amorphous silicon material in the first groove corresponding to the second groove 104, as shown in FIG.
  • the regularly arranged second grooves 104 form a regularly arranged crystal seed 105, thereby forming a polycrystalline silicon film having a uniform grain size and regular grain arrangement.
  • FIG. 6 is a cross-sectional view showing a polycrystalline silicon film formed by the method according to the first embodiment of the present invention
  • FIG. 7 is a cross-sectional view taken along line B-B of the polycrystalline silicon thin film shown in FIG.
  • a crystal seed 105 is formed in the first groove 102
  • a crystal grain 107 is formed with the crystal seed 105 as a core. Since the first grooves 102 are regularly arranged, the size of the formed crystal grains 107 is uniform, and the crystal grains 107 are regularly arranged.
  • the method for preparing a polysilicon film includes: forming a buffer layer on a substrate; forming a first groove regularly arranged on a surface of the buffer layer; forming on the buffer layer on which the first groove is formed An amorphous silicon film; and the amorphous silicon film is subjected to crystallization treatment by an optical annealing process to form a polysilicon film.
  • an amorphous silicon film is formed after forming a regularly arranged first groove on the buffer layer, and then the amorphous silicon film is subjected to crystallization treatment by an optical annealing process.
  • the energy applied thereto is lower relative to the energy applied to the amorphous silicon material at other positions.
  • the amorphous silicon material in the first recess forms an unmelted crystalline seed during the annealing process. Since these first grooves are regularly arranged, the crystal seeds are also regularly arranged, whereby a polycrystalline silicon film having a uniform crystal grain size and regular crystal grain arrangement can be formed.
  • the present embodiment provides a semiconductor device including a substrate, a buffer layer, and a polysilicon film which are sequentially stacked, wherein a surface of the buffer layer which is in contact with the polysilicon film is provided with a regularly arranged first groove, and a polysilicon film is formed on The amorphous silicon film on the buffer layer provided with the regularly arranged first grooves is formed by crystallization treatment by an optical annealing process.
  • Other components in the semiconductor device can be formed in accordance with prior art fabrication methods, and are not described herein.
  • the semiconductor device provided in this embodiment includes the polysilicon film manufactured by the method for preparing the polysilicon film of the present invention, and therefore, the polycrystalline silicon film in the semiconductor device has uniform grain size and regular grain arrangement, thereby making the semiconductor device Performance is improved.
  • the present embodiment provides a display substrate including a substrate, a buffer layer, and a polysilicon film which are sequentially stacked, wherein a surface of the buffer layer that is in contact with the polysilicon film is provided with a regularly arranged first groove.
  • the polycrystalline silicon film is formed by crystallization treatment of an amorphous silicon film formed on the buffer layer provided with the regularly arranged first grooves by an optical annealing process.
  • an amorphous silicon film is formed on the buffer layer. Since the surface of the buffer layer is provided with the first recess, the surface of the amorphous silicon film also forms a second recess corresponding to the first recess. Since the first grooves are regularly arranged, the second grooves are also regularly arranged. Then, the amorphous silicon film is subjected to crystallization treatment using an excimer laser annealing process. Since the amorphous silicon film is provided with a regularly arranged second groove, when the laser light used in the annealing process is focused on the upper surface of the amorphous silicon film, the focus of the laser cannot reach the corresponding corresponding to the second groove. The depth at which the amorphous silicon material is located.
  • the amorphous silicon material corresponding to the second recess receives less energy from the laser than the amorphous silicon material corresponding to the region outside the second recess. Therefore, when the amorphous silicon material in the region other than the second recess is melted, the amorphous silicon material corresponding to the second recess may still be partially melted, thereby forming a crystal seed.
  • the regularly arranged second grooves can form a regularly arranged crystal seed to form a polycrystalline silicon film having a uniform grain size and regular grain arrangement.
  • the buffer layer may include a first buffer sublayer and a second buffer sublayer disposed in a stack.
  • the buffer layer may include a plurality of first buffer sublayers and a plurality of second buffer sublayers, the first buffer sublayer and the second buffer sublayer being alternately arranged.
  • the material of the first buffer sublayer is silicon dioxide
  • the material of the second buffer sublayer is silicon nitride.
  • the thickness of the buffer layer ranges from 100 nm to 600 nm.
  • the buffer layer serves to smooth the substrate and prevent impurities in the substrate from penetrating into the polysilicon film during the formation of the polysilicon film.
  • the distance between the first grooves ranges from 300 nm to 400 nm
  • the shape of the first grooves is circular or square
  • the thickness of the buffer layer ranges from 100 nm to 600 nm.
  • the display substrate provided in this embodiment includes a polycrystalline silicon film produced by the method for preparing a polycrystalline silicon film of the present invention. Therefore, the polycrystalline silicon thin film in the display substrate has a uniform crystal grain size and a regular crystal grain arrangement, thereby improving the performance of the display substrate.
  • the present embodiment further provides a display device, including the display substrate provided by the third embodiment.
  • a display device including the display substrate provided by the third embodiment.
  • the display device provided in this embodiment includes a polysilicon film manufactured by the method for preparing a polysilicon film of the present invention. Therefore, the polycrystalline silicon film in the display device has uniform grain size and regular grain arrangement, thereby improving display quality of the display device. .

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Abstract

一种多晶硅薄膜的制备方法、半导体器件、显示基板及显示装置，所述多晶硅薄膜的制备方法包括：在衬底上形成缓冲层(101)，在所述缓冲层(101)的表面形成规则排列的第一凹槽(102)，在形成了第一凹槽(102)的所述缓冲层(101)上形成非晶硅薄膜(103)，并采用光学退火工艺对所述非晶硅薄膜(103)进行结晶处理从而形成多晶硅薄膜。由于这些第一凹槽(102)是规则排列的，因此能够形成晶粒尺寸均匀而且晶粒排列规则的多晶硅薄膜。

Description

多晶硅薄膜制备方法、半导体器件、显示基板及显示装置 技术领域
本发明涉及半导体技术领域，尤其涉及一种多晶硅薄膜的制备方法、半导体器件、显示基板及显示装置。
背景技术
现有的非晶硅本身存在很多无法避免的缺点，例如，低迁移率、低稳定性等。与非晶硅相比，低温多晶硅具有较高的迁移率和稳定性。因此，低温多晶硅技术迅速发展。然而，多晶硅的晶粒尺寸的不均匀性以及晶粒的不规则排列会引起阈值电压的不均匀性，从而影响利用多晶硅薄膜的显示面板的显示质量。
发明内容
本发明的实施例提供一种多晶硅薄膜的制造方法，用于解决现有技术的多晶硅薄膜的制造方法所制造的多晶硅薄膜中的多晶硅的晶粒尺寸不均匀以及晶粒排列不规则的问题。本发明的实施例还提供了包括该多晶硅薄膜的半导体器件、显示基板和显示装置。
本发明的实施例提供了一种多晶硅薄膜的制备方法，包括：在衬底上形成缓冲层；在所述缓冲层的表面形成规则排列的第一凹槽；在形成了所述第一凹槽的所述缓冲层上形成非晶硅薄膜；以及采用光学退火工艺对所述非晶硅薄膜进行结晶处理，以形成多晶硅薄膜。
可选的，所述光学退火工艺包括准分子激光退火工艺。
可选的，所述缓冲层包括层叠设置的至少一个第一缓冲子层和至少一个第二缓冲子层，所述第一缓冲子层与所述第二缓冲子层交替排列。
可选的，所述第一缓冲子层的材料为二氧化硅，所述第二缓冲子层的材料为氮化硅。
可选的，所述第一凹槽之间的距离的范围为从300nm至400nm。
可选的，所述第一凹槽的形状为圆形或者方形。
可选的，在所述采用光学退火工艺对所述非晶硅薄膜进行结晶处理的步骤之前还包括：对所述非晶硅薄膜进行脱氢处理。
可选的，所述缓冲层的材料为二氧化硅。
可选的，所述缓冲层的厚度的范围为从100nm至600nm。
本发明的实施例还提供了一种半导体器件，包括依次层叠的衬底、缓冲层和多晶硅薄膜，其中，所述缓冲层的与所述多晶硅薄膜接触的表面上设置有规则排列的第一凹槽，所述多晶硅薄膜由形成在设置有规则排列的第一凹槽的所述缓冲层上的非晶硅薄膜经过光学退火工艺进行结晶处理而形成。
本发明的实施例还提供了一种显示基板，包括依次层叠的衬底、缓冲层和多晶硅薄膜，其中，所述缓冲层的与所述多晶硅薄膜接触的表面上设置有规则排列的第一凹槽，所述多晶硅薄膜由形成在设置有规则排列的第一凹槽的所述缓冲层上的非晶硅薄膜经过光学退火工艺进行结晶处理而形成。
可选的，所述缓冲层包括层叠设置的至少一个第一缓冲子层和至少一个第二缓冲子层。
可选的，所述第一缓冲子层与所述第二缓冲子层交替排列，所述第一缓冲子层的材料为二氧化硅，所述第二缓冲子层的材料为氮化硅。
可选的，所述第一凹槽之间的距离的范围为从300nm至400nm。
可选的，所述缓冲层的厚度的范围为从100nm至600nm。
本发明的实施例还提供一种显示装置，包括上述任一显示基板。
本发明具有下述有益效果：
根据本发明的多晶硅薄膜的制备方法包括：在衬底上形成缓冲层；在所述缓冲层的表面形成规则排列的第一凹槽；在形成了第一凹槽的所述缓冲层上形成非晶硅薄膜；以及采用光学退火工艺对所述非晶硅薄膜进行结晶处理从而形成多晶硅薄膜。根据本发明，在缓冲层上形成规则排列的第一凹槽之后形成非晶硅薄膜，然后采用光学退火工艺对非晶硅薄膜进行结晶处理。由于光学退火工艺中的激光束的焦 点不能达到第一凹槽中的非晶硅材料的深度，因此施加到其上的能量相对于施加到其他位置处的非晶硅材料上的能量较低。因此，第一凹槽中的非晶硅材料在退火工艺过程中形成未熔化的结晶种子。由于这些第一凹槽是规则排列的，因此结晶种子也是规则排列的，由此能够形成晶粒尺寸均匀而且晶粒排列规则的多晶硅薄膜。根据本发明的半导体器件、显示基板和显示装置包含根据本发明的上述多晶硅薄膜的制备方法制造的多晶硅薄膜，因此具有改善的性能。
附图说明
图1为本发明第一实施例提供的一种多晶硅薄膜的制备方法的流程图。
图2为根据本发明第一实施例的方法形成的缓冲层的截面图。
图3为图2所示的缓冲层的A-A剖面图。
图4为根据本发明第一实施例的方法形成的非晶硅薄膜的截面图。
图5为对图4所示非晶硅薄膜进行退火处理的示意图。
图6为根据本发明第一实施例的方法形成的多晶硅薄膜的截面图。
图7为图6所示的多晶硅薄膜的B-B剖面图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的多晶硅薄膜的制备方法、半导体器件、显示基板及显示装置进行详细描述。
第一实施例
图1为本发明第一实施例提供的一种多晶硅薄膜的制备方法的流程图。如图1所示，所述多晶硅薄膜的制备方法包括下面的步骤1001至1004。
步骤1001、在衬底上形成缓冲层。
图2为根据本发明第一实施例的方法形成的缓冲层的截面图，图3为图2所示的缓冲层的A-A剖面图。如图2和图3所示，在衬底(未示出)上形成缓冲层101。所述缓冲层101的材料可以为二氧化硅。可选的，所述缓冲层101包括层叠设置的第一缓冲子层和第二缓冲子层(图中未示出)。在实际应用中，所述缓冲层101可以包括层叠设置的多个第一缓冲子层和多个第二缓冲子层，所述第一缓冲子层与所述第二缓冲子层交替地排列。优选的，所述第一缓冲子层的材料为二氧化硅，所述第二缓冲子层的材料为氮化硅。优选的，所述缓冲层的厚度的范围为从100nm至600nm。所述缓冲层用于平滑所述衬底，并且用于防止在形成多晶硅薄膜的过程中衬底内的杂质渗透进入多晶硅薄膜。
步骤1002、在所述缓冲层的表面形成规则排列的第一凹槽。
参见图2和图3，在所述缓冲层101的表面(即，与接触衬底的表面相对的表面)形成规则排列的第一凹槽102。在实际应用中，在所述缓冲层上涂敷光刻胶，采用掩膜板对所述光刻胶进行曝光和显影以形成光刻胶保留区域和光刻胶去除区域，所述光刻胶去除区域对应于形成第一凹槽的图形区域，所述光刻胶保留区域对应于所述图形区域之外的其它区域。对所述缓冲层进行刻蚀以形成第一凹槽。可选的，所述第一凹槽102之间的距离的范围为从300nm至400nm，所述第一凹槽102的形状为圆形或者方形。
步骤1003、在形成了第一凹槽的所述缓冲层上形成非晶硅薄膜。
图4为根据本发明第一实施例的方法形成的非晶硅薄膜的截面图。如图4所示，在所述缓冲层101上形成非晶硅薄膜103。由于所述缓冲层101的表面设置有第一凹槽102，因此所述非晶硅薄膜103的表面也会形成与所述第一凹槽102对应的第二凹槽104。由于所述第一凹槽102是规则排列的，因此所述第二凹槽104也是规则排列的。优选的，对所述非晶硅薄膜进行脱氢处理。
步骤1004、采用光学退火工艺对所述非晶硅薄膜进行结晶处理，以形成多晶硅薄膜。
图5为对图4所示非晶硅薄膜进行退火处理的示意图。如图5 所示，可以采用准分子激光退火工艺对所述非晶硅薄膜103进行结晶处理。由于所述非晶硅薄膜103上设置有规则排列的第二凹槽104，因此，在执行准分子激光退火工艺时，在使得激光108聚焦在非晶硅薄膜103的上表面的情况下，激光108的焦点不能达到所述第二凹槽104对应的非晶硅材料所处的深度。所述第二凹槽104对应的非晶硅材料从激光接收的能量比所述第二凹槽104之外的区域对应的非晶硅材料从激光接收的能量要低。当所述第二凹槽104之外的区域对应的非晶硅材料熔化时，所述第二凹槽104对应的非晶硅材料仍会有一些不能熔化，从而形成结晶种子105(例如，会在与第二凹槽104对应的第一凹槽中的非晶硅材料中形成结晶种子105，如图6所示)。规则排列的第二凹槽104会形成规则排列的结晶种子105，从而形成晶粒尺寸均匀而且晶粒排列规则的多晶硅薄膜。
图6为根据本发明第一实施例的方法形成的多晶硅薄膜的截面图，图7为图6所示的多晶硅薄膜的B-B剖面图。如图6和图7所示，在所述第一凹槽102内形成有结晶种子105，以所述结晶种子105为核心形成晶粒107。由于这些第一凹槽102是规则排列的，因此形成的晶粒107的尺寸均匀，而且晶粒107是规则排布的。
本实施例提供的多晶硅薄膜的制备方法包括：在衬底上形成缓冲层；在所述缓冲层的表面形成规则排列的第一凹槽；在形成了第一凹槽的所述缓冲层上形成非晶硅薄膜；以及采用光学退火工艺对所述非晶硅薄膜进行结晶处理从而形成多晶硅薄膜。根据本实施例，在缓冲层上形成规则排列的第一凹槽之后形成非晶硅薄膜，然后采用光学退火工艺对非晶硅薄膜进行结晶处理。由于光学退火工艺中的激光束的焦点不能达到第一凹槽中的非晶硅材料的深度，因此施加到其上的能量相对于施加到其他位置处的非晶硅材料上的能量较低。因此，第一凹槽中的非晶硅材料在退火工艺过程中形成未熔化的结晶种子。由于这些第一凹槽是规则排列的，因此结晶种子也是规则排列的，由此能够形成晶粒尺寸均匀而且晶粒排列规则的多晶硅薄膜。
第二实施例
本实施例提供一种半导体器件，其包括依次层叠的衬底、缓冲层和多晶硅薄膜，其中，缓冲层的与多晶硅薄膜接触的表面上设置有规则排列的第一凹槽，多晶硅薄膜由形成在设置有规则排列的第一凹槽的缓冲层上的非晶硅薄膜经过光学退火工艺进行结晶处理而形成。该半导体器件中的其他组件可以按照现有技术的制造方法来形成，在此不再赘述。
由此可知，本实施例提供的半导体器件包括通过本发明的多晶硅薄膜的制备方法制造的多晶硅薄膜，因此，该半导体器件中的多晶硅薄膜的晶粒尺寸均匀而且晶粒排列规则，从而半导体器件的性能得到改善。
第三实施例
本实施例提供一种显示基板，其包括依次层叠的衬底、缓冲层和多晶硅薄膜，其中，所述缓冲层的与所述多晶硅薄膜接触的表面上设置有规则排列的第一凹槽，所述多晶硅薄膜由形成在设置有规则排列的第一凹槽的所述缓冲层上的非晶硅薄膜经过光学退火工艺进行结晶处理而形成。
具体来说，在所述缓冲层上形成非晶硅薄膜。由于所述缓冲层的表面设置有第一凹槽，因此所述非晶硅薄膜的表面也会形成与所述第一凹槽对应的第二凹槽。由于所述第一凹槽是规则排列的，因此所述第二凹槽也是规则排列的。然后，采用准分子激光退火工艺对所述非晶硅薄膜进行结晶处理。由于所述非晶硅薄膜上设置有规则排列的第二凹槽，因此，当退火工艺中采用的激光被聚焦在非晶硅薄膜的上表面时，激光的焦点无法达到第二凹槽对应的非晶硅材料所处的深度。所述第二凹槽对应的非晶硅材料从激光接收的能量比所述第二凹槽之外的区域对应的非晶硅材料接收的能量要低。因此，当所述第二凹槽之外的区域的非晶硅材料熔化时，所述第二凹槽对应的非晶硅材料仍会有一些不能熔化，从而形成结晶种子。规则排列的第二凹槽可以形成规则排列的结晶种子，从而形成晶粒尺寸均匀而且晶粒排列规则的多晶硅薄膜。
本实施例中，所述缓冲层可以包括层叠设置的第一缓冲子层和第二缓冲子层。在实际应用中，所述缓冲层可以包括多个第一缓冲子层和多个第二缓冲子层，所述第一缓冲子层与所述第二缓冲子层交替地排列。可选的，所述第一缓冲子层的材料为二氧化硅，所述第二缓冲子层的材料为氮化硅。优选的，所述缓冲层的厚度的范围为从100nm至600nm。所述缓冲层用于平滑所述衬底，并且防止在形成多晶硅薄膜的过程中衬底内的杂质渗透进入多晶硅薄膜。
可选的，所述第一凹槽之间的距离的范围为从300nm至400nm，所述第一凹槽的形状为圆形或者方形，所述缓冲层的厚度的范围为从100nm至600nm。
本实施例提供的显示基板包括通过本发明的多晶硅薄膜的制备方法制造的多晶硅薄膜，因此，该显示基板中的多晶硅薄膜的晶粒尺寸均匀而且晶粒排列规则，从而显示基板的性能得到改善。
第四实施例
本实施例还提供一种显示装置，包括第三实施例提供的显示基板，具体内容可参照上述第三实施例的描述，此处不再赘述。
本实施例提供的显示装置包括通过本发明的多晶硅薄膜的制备方法制造的多晶硅薄膜，因此，该显示装置中的多晶硅薄膜的晶粒尺寸均匀而且晶粒排列规则，从而显示装置的显示质量得到提高。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (16)

  1. 一种多晶硅薄膜的制备方法，包括：
    在衬底上形成缓冲层；
    在所述缓冲层的表面形成规则排列的第一凹槽；
    在形成了所述第一凹槽的所述缓冲层上形成非晶硅薄膜；以及
    采用光学退火工艺对所述非晶硅薄膜进行结晶处理，以形成多晶硅薄膜。
  2. 根据权利要求1所述的多晶硅薄膜的制备方法，其中，所述光学退火工艺包括准分子激光退火工艺。
  3. 根据权利要求1所述的多晶硅薄膜的制备方法，其中，所述缓冲层包括层叠设置的至少一个第一缓冲子层和至少一个第二缓冲子层，所述第一缓冲子层与所述第二缓冲子层交替排列。
  4. 根据权利要求3所述的多晶硅薄膜的制备方法，其中，所述第一缓冲子层的材料为二氧化硅，所述第二缓冲子层的材料为氮化硅。
  5. 根据权利要求1所述的多晶硅薄膜的制备方法，其中，所述第一凹槽之间的距离的范围为从300nm至400nm。
  6. 根据权利要求1所述的多晶硅薄膜的制备方法，其中，所述第一凹槽的形状为圆形或者方形。
  7. 根据权利要求1所述的多晶硅薄膜的制备方法，其中，在所述采用光学退火工艺对所述非晶硅薄膜进行结晶处理的步骤之前还包括：
    对所述非晶硅薄膜进行脱氢处理。
  8. 根据权利要求1所述的多晶硅薄膜的制备方法，其中，所述缓冲层的材料为二氧化硅。
  9. 根据权利要求1所述的多晶硅薄膜的制备方法，其中，所述缓冲层的厚度的范围为从100nm至600nm。
  10. 一种半导体器件，包括依次层叠的衬底、缓冲层和多晶硅薄膜，
    其中，所述缓冲层的与所述多晶硅薄膜接触的表面上设置有规则排列的第一凹槽，所述多晶硅薄膜由形成在设置有规则排列的第一凹槽的所述缓冲层上的非晶硅薄膜经过光学退火工艺进行结晶处理而形成。
  11. 一种显示基板，包括依次层叠的衬底、缓冲层和多晶硅薄膜，
    其中，所述缓冲层的与所述多晶硅薄膜接触的表面上设置有规则排列的第一凹槽，所述多晶硅薄膜由形成在设置有规则排列的第一凹槽的所述缓冲层上的非晶硅薄膜经过光学退火工艺进行结晶处理而形成。
  12. 根据权利要求11所述的显示基板，其中，所述缓冲层包括层叠设置的至少一个第一缓冲子层和至少一个第二缓冲子层，所述第一缓冲子层与所述第二缓冲子层交替排列。
  13. 根据权利要求12所述的显示基板，其中，所述第一缓冲子层的材料为二氧化硅，所述第二缓冲子层的材料为氮化硅。
  14. 根据权利要求11所述的显示基板，其中，所述第一凹槽之间的距离的范围为从300nm至400nm。
  15. 根据权利要求11所述的显示基板，其中，所述缓冲层的厚度的范围为从100nm至600nm。
  16. 一种显示装置，包括权利要求11-15中任一项所述的显示基板。
PCT/CN2015/084215 2015-03-27 2015-07-16 多晶硅薄膜制备方法、半导体器件、显示基板及显示装置 WO2016155149A1 (zh)

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