WO2016150078A1 - 一种阵列基板、显示面板及显示装置 - Google Patents

一种阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2016150078A1
WO2016150078A1 PCT/CN2015/086980 CN2015086980W WO2016150078A1 WO 2016150078 A1 WO2016150078 A1 WO 2016150078A1 CN 2015086980 W CN2015086980 W CN 2015086980W WO 2016150078 A1 WO2016150078 A1 WO 2016150078A1
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Prior art keywords
substrate
passivation layer
layer
pixel structure
organic electroluminescent
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PCT/CN2015/086980
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English (en)
French (fr)
Inventor
邹祥祥
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京东方科技集团股份有限公司
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Priority to US14/892,684 priority Critical patent/US9825112B2/en
Publication of WO2016150078A1 publication Critical patent/WO2016150078A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80516—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device.
  • LED Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • PDP Plasma Display Panel
  • the array substrate of the OLED includes: a display area 101 and a peripheral area 102 surrounding the display area 101; wherein the display area 101 is provided with a plurality of displays for display
  • the pixel structure 103 is provided with a peripheral trace 104 for loading a driving signal to each pixel structure 103.
  • the width of the peripheral region 102 is the width of the border of the OLED (shown as a in FIG. 1).
  • a technique of integrating the gate driving circuit on the OLED array substrate (Gate On Array, GOA) is generally adopted, that is, a gate driving circuit is formed in a peripheral region of the array substrate.
  • GOA Gate On Array
  • embodiments of the present disclosure provide an array substrate, a display panel, and a display device that at least partially alleviate or eliminate the problems in the prior art.
  • a first aspect of the present disclosure provides an array substrate including: a substrate substrate, and peripheral traces and a plurality of pixel structures on the substrate;
  • At least one of the pixel structures has an overlapping area between an orthographic projection of the base substrate and a peripheral region where the peripheral trace is located at an orthographic projection of the base substrate;
  • the film layer of the peripheral trace is located between the film layer where the pixel structure is located and the substrate; or the film layer of the peripheral trace is located at the back of the film layer where the pixel structure is located To one side of the base substrate.
  • the method further includes: a plurality of data lines and a plurality of gate lines disposed on the substrate and intersecting each other and insulated from each other; An orthographic projection of each of the data lines and each of the gate lines on the substrate substrate and an orthogonal projection of the peripheral traces on the substrate substrate do not overlap each other;
  • the adjacent two data lines and the adjacent two gate lines define one pixel structure.
  • the film layer of the peripheral trace may be located between the film layer where the pixel structure is located and the substrate;
  • the substrate may further include: a thin film transistor, a first passivation layer, and a metal corresponding to each of the pixel structures disposed between the substrate and the film layer where the pixel structure is located and sequentially disposed on the substrate a bridge and a second passivation layer; the pixel structure is an organic electroluminescent structure;
  • a drain of the thin film transistor corresponding to the organic electroluminescent structure located in the overlap region is electrically connected to the metal bridge through a first via hole penetrating the first passivation layer, the metal bridge passing through the a second via of the second passivation layer is electrically connected to the anode in the organic electroluminescent structure;
  • a drain of the thin film transistor corresponding to the organic electroluminescent structure located outside the overlap region passes through a third via hole penetrating the first passivation layer and the second passivation layer and the organic electroluminescent structure
  • the anode is electrically connected.
  • an organic resin layer disposed on the second passivation layer may be further included, and the second via hole penetrates the organic resin And a second passivation layer penetrating the organic resin layer, the second passivation layer, and the first passivation layer.
  • the film layer of the peripheral trace may be located on a side of the film layer where the pixel structure is located facing away from the substrate substrate;
  • the array substrate may further include: a second passivation layer, a metal bridge, a first passivation layer, and corresponding to each of the pixel structures disposed on a side of the film layer where the pixel structure is located facing away from the substrate Thin film transistor; the pixel structure is an organic electroluminescent structure;
  • a drain of the thin film transistor corresponding to the organic electroluminescent structure located in the overlap region is electrically connected to the metal bridge through a first via hole penetrating the first passivation layer, a metal bridge electrically connected to the anode in the organic electroluminescent structure through a second via extending through the second passivation layer;
  • a drain of the thin film transistor corresponding to the organic electroluminescent structure located outside the overlap region passes through a third via hole penetrating the first passivation layer and the second passivation layer and the organic electroluminescent structure
  • the anode is electrically connected.
  • the method further includes: a plurality of data lines and a plurality of gate lines disposed on the substrate and intersecting each other and insulated from each other; An orthographic projection of each of the data lines and each of the gate lines on the substrate substrate and an orthogonal projection of the peripheral traces on the substrate substrate do not overlap each other;
  • a width of each of the pixel structures along an extending direction of the gate lines is greater than a distance between adjacent two data lines; and/or a width of each of the pixel structures along an extending direction of the data lines is greater than The distance between two adjacent grid lines.
  • the film layer of the peripheral trace may be located between the film layer where the pixel structure is located and the substrate;
  • the substrate may further include: a thin film transistor and a first passivation layer corresponding to each of the pixel structures disposed between the substrate and the film layer where the pixel structure is located and sequentially disposed on the substrate;
  • the pixel structure is an organic electroluminescent structure;
  • An anode in each of the organic electroluminescent structures is electrically connected to a drain of the corresponding thin film transistor through a first via in the first passivation layer.
  • the method further includes: a metal bridge and a second passivation layer disposed on the first passivation layer; wherein
  • the metal bridge is electrically connected to a drain of the thin film transistor through a first via in the first passivation layer, and the metal bridge passes through a second via in the second passivation layer
  • the anode in the organic electroluminescent structure is electrically connected.
  • the film layer of the peripheral trace may be located on a side of the film layer where the pixel structure is located facing away from the substrate substrate;
  • the array substrate may further include: a first passivation layer disposed in sequence on a side of the film layer facing the pixel structure facing away from the substrate substrate; and a thin film transistor corresponding to each of the pixel structures;
  • An anode in each of the organic electroluminescent structures passes through a first one of the first passivation layers
  • the via is electrically connected to the drain of the corresponding thin film transistor.
  • the method further includes: a metal bridge and a second passivation layer disposed on the first passivation layer; wherein
  • the metal bridge is electrically connected to an anode in the organic electroluminescent structure through a first via in the first passivation layer, and the metal bridge passes through a second one of the second passivation layer
  • the hole is electrically connected to the drain of the thin film transistor.
  • the metal bridge may have a strip shape; each of the metal bridges is located on a different straight line parallel to the grid lines.
  • a peripheral circuit may further be included;
  • the film layer where the peripheral trace is located and the film layer where the peripheral circuit is located are located between the film layer where the pixel structure is located and the substrate substrate; or the film layer where the peripheral trace is located and the film where the peripheral circuit is located The layer is located on a side of the film layer where the pixel structure is located facing away from the substrate.
  • the embodiment of the present disclosure further provides a display panel, including the above array substrate provided by the embodiment of the present disclosure.
  • the display panel is an organic electroluminescence display panel.
  • the embodiment of the present disclosure further provides a display device, including the above display panel provided by the embodiment of the present disclosure.
  • the array substrate comprises: a substrate substrate, and a peripheral trace on the substrate substrate and a plurality of pixel structures. Since the at least one pixel structure has an overlapping area between the orthographic projection of the base substrate and the peripheral area where the peripheral traces are located, that is, the pixel structure extends to a peripheral area where the part or all of the peripheral traces are covered, and because the film layer of the peripheral trace exists Located between the film layer where the pixel structure is located and the substrate substrate or on the side of the film layer where the pixel structure is located facing away from the substrate, so that even if the pixel structure overlaps between the orthographic projection of the substrate substrate and the peripheral region where the peripheral traces are located It does not affect the normal display of the pixel structure, so that the display area is expanded to cover the peripheral area where some or all of the peripheral traces are located, and the border of the display panel can be made compared with the structure in which the existing display area and the peripheral area do not overlap
  • FIG. 1 is a schematic structural view of an array substrate of a conventional organic electroluminescence display panel
  • FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • Figure 3 is a cross-sectional view taken along line AA of Figure 2;
  • FIG. 4 is a schematic structural diagram of an array substrate according to another embodiment of the present disclosure.
  • Figure 5 is a cross-sectional view of Figure 4 along the CC direction
  • Figure 6 is a cross-sectional view taken along line BB of Figure 2;
  • Figure 7 and Figure 8 are cross-sectional views of Figure 4 taken along the DD direction;
  • FIG. 9 is a schematic diagram of a portion of the pixel structure of FIG. 4.
  • FIG. 9 is a schematic diagram of a portion of the pixel structure of FIG. 4.
  • each film layer in the drawings do not reflect the true scale of the array substrate, and are merely intended to illustrate the disclosure.
  • FIG. 3 is a cross-sectional view taken along line AA of FIG. 2
  • FIG. 5 is a cross-sectional view of FIG. 4 along the CC direction, including: a substrate 1 And a peripheral trace 2 and a plurality of pixel structures 3 on the substrate 1;
  • the at least one pixel structure 3 has an overlapping area between the orthographic projection of the base substrate 1 and the peripheral region where the peripheral trace 2 is located (shown by the hatched portion of the grid as shown in FIGS. 2 to 5) on the orthographic projection of the base substrate 1. .
  • the film layer of the peripheral trace 2 is located between the film layer where the pixel structure 3 is located and the substrate 1; or, the film layer of the peripheral trace 2 is located at the back of the film layer where the pixel structure 3 is located.
  • the at least one pixel structure has an overlapping area on the front projection of the substrate substrate in the peripheral region where the front projection and the peripheral trace are located, and the array provided in the embodiment of the present disclosure
  • the film layer of the peripheral trace is located between the film layer where the pixel structure is located and the substrate, even if the pixel structure is orthographically projected on the substrate.
  • the overlapping of the peripheral traces on the substrate substrate does not affect the normal display of the OLED; likewise,
  • the film layer of the peripheral trace is located on the side of the film layer where the pixel structure is located facing away from the substrate, even if The orthographic projection of the pixel structure on the substrate substrate and the orthogonal projection of the peripheral traces on the substrate substrate do not affect the normal display of the OLED; therefore, the display area of the array substrate provided by the embodiment of the present disclosure may be expanded to the cover portion.
  • the peripheral area where all the peripheral traces are located, and the frame of the organic electroluminescent display panel can be made compared with the structure in which the display area 101 and the peripheral area 102 do not overlap each other in the array substrate of the existing OLED as shown in FIG.
  • the width (shown as b shown in Figures 2 and 4) is narrowed.
  • the organic electroluminescence display panel is displayed without a border.
  • peripheral traces in the array substrate provided by the embodiments of the present disclosure are electrically connected to the gate lines and the data lines in the array substrate, and the peripheral traces are disposed and the peripheral traces in the existing array substrate.
  • the peripheral area where the peripheral trace is located is similar to the peripheral area 102 of the array substrate of the existing OLED as shown in FIG. 1 and will not be described herein.
  • the pixel structure has an overlapping area between the orthographic projection of the substrate substrate and the peripheral region where the peripheral trace is located, as shown in FIG. 2 and FIG. 3, in the case where the size of the pixel structure 3 is constant (ie, two adjacent gate lines and two adjacent data lines define one pixel structure), by increasing in the peripheral region where the peripheral trace 2 is located
  • the size of each pixel structure 3 can also be increased (that is, the area occupied by each pixel structure is larger than the adjacent two gate lines and The area occupied by the area defined by two adjacent data lines is implemented, and is not limited herein.
  • the above array substrate provided by the embodiments of the present disclosure is as shown in FIG. 2 and FIG. 3 .
  • the present invention may further include: a plurality of data lines 4 and a plurality of gate lines 5 which are interdigitated and insulated from each other on the base substrate 1; and an orthographic projection of each of the data lines 4 and the respective gate lines 5 on the base substrate 1
  • the orthographic projections of the peripheral traces 2 on the base substrate 1 do not overlap each other, that is, the gate lines 5 and the data lines 4 corresponding to the respective pixel structures 3 are located in the peripheral region where the peripheral traces 2 are located (as shown in FIGS. 2 and 3).
  • the gate line 5 defines a pixel structure 3; the gate lines 5 and the data lines 4 corresponding to the pixel structure 3 located in the overlap region (ie, the pixel structure additionally added with respect to the existing array substrate) are not disposed in the overlapping region, but The area is outside the overlap area, because the peripheral trace 2 is generally disposed in the same layer as the gate line 5 or the data line 4, in order to prevent the gate line 5 and the data line 4 and the peripheral line corresponding to the pixel structure 3 in the overlap area.
  • the problem that the two are electrically connected to each other to cause a short circuit requires that the gate line 5 and the data line 4 corresponding to the pixel structure 3 located in the overlapping area be disposed in an area other than the overlapping area.
  • the pixel structure 3 located in the overlap region may be connected to the corresponding gate line 5 and the data line 4 located outside the overlap region by means of via holes.
  • the above-mentioned array substrate provided by the embodiment of the present disclosure is applied to the top emission type OLED, that is, when the film layer of the peripheral trace is located between the film layer where the pixel structure is located and the substrate substrate, Array substrate, as shown in FIG. 6, wherein FIG. 6 is a cross-sectional view of FIG. 2 along the BB direction, and may further include: a substrate layer 1 and a film layer between the pixel structure 3 and sequentially disposed on the substrate substrate 1. a thin film transistor 6 corresponding to each pixel structure 3, a first passivation layer 7, a metal bridge 8 and a second passivation layer 9; FIG.
  • the 6 is an organic structure comprising a pixel structure 3 including an anode 31, a light-emitting layer 32 and a cathode 33.
  • the light-emitting structure 30 is taken as an example. Since the gate lines 5 and the data lines 4 corresponding to the organic electroluminescent structure 30 located in the overlapping region are located outside the overlapping region, the film corresponding to the organic electroluminescent structure 30 located in the overlapping region is formed.
  • the transistor 6 is also located outside the overlap region.
  • the organic electroluminescent structure 30 can be electrically connected to the corresponding thin film transistor 6 through a via. Specifically, the drain of the thin film transistor 6 passes through the first passivation layer 7 .
  • the via hole is electrically connected to the metal bridge 8 , and the metal bridge 8 is electrically connected to the anode 31 in the organic electroluminescent structure 30 through the second via hole penetrating the second passivation layer 9;
  • the drain of the thin film transistor 6 corresponding to the electroluminescent structure 30 is electrically connected to the anode 31 in the organic electroluminescent structure 30 through a third via penetrating through the first passivation layer 7 and the second passivation layer 9 .
  • the connection between the organic electroluminescent structure 30 outside the overlap region and the thin film transistor 6 corresponding to the organic electroluminescent structure 30 is similar to the existing structure, and will not be described herein. Further, as shown in FIG.
  • an organic resin layer 10 may be further provided on the second passivation layer 9, the second via hole penetrates the organic resin layer 10 and the second passivation layer 9, and the third via hole penetrates the organic resin layer 10.
  • the second passivation layer 9 and the first passivation layer 7 have the same function as the organic resin layer in the existing OLED, and are not described herein.
  • the above array substrate provided by the embodiment of the present disclosure is applied to the base
  • the above-mentioned array substrate provided by the embodiment of the present disclosure may further include: the film layer in the pixel structure facing away from the substrate when the film layer of the pixel structure is located on the side of the film layer facing away from the substrate a second passivation layer, a metal bridge, a first passivation layer, and a thin film transistor corresponding to each pixel structure are disposed on one side of the substrate; taking the pixel structure as an organic electroluminescence structure as an example, because there is an overlap region The gate lines and the data lines corresponding to the electroluminescent structure are located outside the overlapping region.
  • the thin film transistors corresponding to the organic electroluminescent structures located in the overlapping regions are also located outside the overlapping region, and the organic electroluminescent structure can pass through the via holes.
  • the method is electrically connected to the corresponding thin film transistor.
  • the drain of the thin film transistor is electrically connected to the metal bridge through the first via hole penetrating the first passivation layer, and the metal bridge passes through the second passivation layer.
  • the second via is electrically connected to the anode in the organic electroluminescent structure; the thin film transistor corresponding to the organic electroluminescent structure outside the overlapping region
  • the drain is electrically connected to the anode in the organic electroluminescent structure through a third via extending through the first passivation layer and the second passivation layer.
  • the above array substrate provided by the embodiment of the present disclosure is as shown in FIG. 4 and As shown in FIG.
  • a plurality of data lines 4 and a plurality of gate lines 5 which are interdigitated and insulated from each other on the base substrate 1 may be included; each of the data lines 4 and each of the gate lines 5 on the base substrate 1
  • the orthographic projection of the front projection and the outer trace 2 on the base substrate 1 does not overlap each other, so that the problem that each gate line 5 and each data line 4 and the peripheral trace 2 are electrically connected to each other to cause a short circuit can be prevented;
  • the width of the pixel structure 3 in the extending direction of the gate line 5 is larger than the distance between the two data lines 4 adjacent to the pixel structure 3, so that the width of each pixel structure 3 along the extending direction of the gate line 5 can be increased.
  • the pixel structure 3 can be extended in the extending direction of the gate line 5 to cover a peripheral region where some or all of the peripheral traces 2 are located, so that the display region can be extended in the extending direction of the gate line 5 to cover part or all of the periphery.
  • the width of each pixel structure 3 along the extending direction of the data line 4 is larger than between the two gate lines 5 adjacent to the pixel structure 3
  • the distance in this way, can increase the width of each pixel structure 3 along the extending direction of the data line 4, so that the pixel structure 3 can be extended in the extending direction of the data line 4 to a peripheral area where some or all of the peripheral traces 2 can be covered.
  • the display area can be extended in the data line 4
  • the direction extends to cover a peripheral region where some or all of the peripheral traces 2 are located, so that the OLED realizes a narrow bezel design in the extending direction of the data line 4; or, the extension of each pixel structure 3 along the gate line 5 can be simultaneously increased.
  • each pixel structure has an overlapping area with the gate lines and/or the data lines, in order to avoid affecting the normal display of the OLED, it is required according to the OLED.
  • a type ie, a top emission type or a bottom emission type
  • a top emission type is used to set a positional relationship of each pixel structure and a thin film transistor corresponding to the pixel structure.
  • the embodiment of the present disclosure provides The array substrate is as shown in FIG. 7, wherein FIG. 7 is a cross-sectional view along the DD direction of FIG. 4, and may further include: between the substrate layer 1 and the film layer where the pixel structure 3 is located, and sequentially disposed on the substrate substrate 1.
  • the thin film transistor 6 and the first passivation layer 7 corresponding to each pixel structure 3; FIG.
  • the organic electroluminescent structure 30 including the anode 31, the light-emitting layer 32 and the cathode 33 in the pixel structure 3, and each organic electro-electrode
  • the anode 31 in the light emitting structure 30 is electrically connected to the drain in the corresponding thin film transistor 6 through the first via hole in the first passivation layer 7.
  • an organic resin layer 10 may be further disposed on the first passivation layer 7, the first via hole penetrating the organic resin layer 10 and the first passivation layer 7, and the function and appearance of the organic resin layer 10
  • the organic resin layer in some OLEDs has the same function and will not be described here.
  • the thin film transistor is a bottom gate type structure
  • the light-emitting structure and the data lines other than the data lines to which the gray-scale signal is applied to the organic electroluminescent structure overlap each other, and the data lines are disposed in the same layer as the source and drain of the thin film transistor. Therefore, the first passivation layer needs to be disposed.
  • the optical structure is electrically connected to a data line other than the data line to which the gray-scale signal is applied to the organic electroluminescent structure to cause a short circuit; similarly, the direction of extension of each organic electroluminescent structure along the data line is increased. Width, and when the thin film transistor is a top gate type structure, since the organic electroluminescent structure and the gate lines other than the gate lines to which the gate electrode scanning signal is applied to the organic electroluminescent structure overlap each other, and the gate lines and the thin film transistors The gate is disposed in the same layer.
  • the first passivation layer needs to be disposed to prevent the organic electroluminescent structure from being electrically connected to the gate line other than the gate line to which the gate electrode scanning signal is applied to the organic electroluminescent structure, thereby causing a short circuit. problem.
  • the thin film transistors are of a bottom gate type structure; or, increasing the extending direction of each of the organic electroluminescent structures along the gate lines
  • the width of the thin film transistor is a top gate type structure
  • the arrangement of the first passivation layer may be omitted, which is not limited herein.
  • each of the organic electroluminescent structures along the extending direction of the gate lines is significantly larger than the width between the two data lines adjacent to the organic electroluminescent structure, such that each of the organic electroluminescent structures
  • the anode is far from the drain of the corresponding thin film transistor, for example, the distance between the anode in each organic electroluminescent structure and the drain in the corresponding thin film transistor is greater than between the adjacent two data lines
  • the width is different, there may be a problem of short circuit between the two adjacent organic electroluminescent structures.
  • the above array substrate provided by the embodiment of the present disclosure is as shown in FIG. 8 ( FIG. 8 is the direction of the DD in FIG.
  • Another case of the cross-sectional view may further include: a metal bridge 8 and a second passivation layer 9 disposed in sequence on the first passivation layer 7; wherein the metal bridge 8 passes through the first passivation layer 7 A via is electrically connected to the drain of the thin film transistor 6, and the metal bridge 8 is electrically connected to the anode 31 in the organic electroluminescent structure 30 through the second via in the second passivation layer 9, such that Metal bridge 8 will be the anode in organic electroluminescent structure 30
  • the pole 31 is electrically connected to the drain of the corresponding thin film transistor 6, and the adjacent two can be avoided because the anode 31 in each organic electroluminescent structure 30 is far from the drain in the corresponding thin film transistor 6.
  • an organic resin layer 10 may be further disposed on the second passivation layer 9, and the second via hole penetrates through the organic resin layer 10 and the second passivation layer 9, and the function and appearance of the organic resin layer 10
  • the organic resin layer in some OLEDs has the same function and will not be described here.
  • the film layer of the peripheral trace is located on the back of the film layer where the pixel structure is located.
  • the array substrate according to the embodiment of the present disclosure may further include: a first passivation layer and a pixel structure disposed in sequence on a side of the film layer facing away from the substrate substrate Corresponding thin film transistor; taking the pixel structure as an organic electroluminescent structure, the anode in each organic electroluminescent structure is electrically connected to the drain of the corresponding thin film transistor through the first via in the first passivation layer .
  • the width of each of the organic electroluminescent structures along the extending direction of the gate lines is significantly larger than the width between the two data lines adjacent to the organic electroluminescent structure, such that each of the organic electroluminescent structures
  • the anode is far from the drain of the corresponding thin film transistor, for example, the distance between the anode in each organic electroluminescent structure and the drain in the corresponding thin film transistor is greater than between the adjacent two data lines
  • the array substrate provided by the embodiment of the present disclosure may further include: a metal bridge sequentially disposed on the first passivation layer.
  • a second passivation layer wherein the metal bridge is electrically connected to the anode in the organic electroluminescent structure through the first via in the first passivation layer, and the metal bridge passes through the second via in the second passivation layer Electrically connected to the drain in the thin film transistor, such that by electrically connecting the anode in the organic electroluminescent structure with the drain in the corresponding thin film transistor by means of a metal bridge, it is possible to avoid Drain electroluminescent structure corresponding to the anode of the thin film transistor caused by far away from the two adjacent organic electroluminescent problem of a short circuit between the light emitting structure.
  • the specific implementation of the above-described array substrate provided by the embodiment of the present disclosure applied to the bottom emission type OLED is similar to the embodiment applied to the top emission type OLED, and the repeated portions are not described again.
  • FIG. 9 is a schematic diagram of a partial pixel structure in FIG.
  • the shape of the metal bridge 8 can be set to a strip shape, and each metal bridge 8 is disposed at On a different straight line parallel to the grid lines 5, such that by staggering the adjacent metal bridges 8 from each other, it is possible to prevent the electrical connection between the metal bridges 8 and cause a short circuit; and, in the film layer where the outer traces are located Between the film layer of the organic electroluminescent structure and the substrate, that is, when the above array substrate provided by the embodiment of the present disclosure is applied to the top emission type OLED, the metal bridge is located on the film layer and the substrate of the organic electroluminescent structure.
  • the film layer where the peripheral trace is located is located in the film layer of the organic electroluminescent structure facing away from the substrate Side of the plate, i.e. on the embodiment of the present disclosure provides embodiments
  • the metal bridge is located on the side of the film layer where the organic electroluminescence structure is located away from the substrate, even if the metal bridge and the organic electroluminescence structure overlap each other, the OLED is not affected.
  • the normal display since the metal bridge is located on the side of the film layer where the organic electroluminescence structure is located away from the substrate, even if the metal bridge and the organic electroluminescence structure overlap each other, the OLED is not affected. The normal display.
  • the array substrate provided by the embodiment of the present disclosure may further be a GOA structure, that is, the above array substrate provided by the embodiment of the present disclosure may further include a peripheral circuit.
  • the film layer where the peripheral trace is located and the film layer where the peripheral circuit is located are disposed on the film layer and the substrate where the pixel structure is located.
  • the film layer where the peripheral trace is located and the film layer where the peripheral circuit is located are disposed on the film layer where the pixel structure is located facing away from the lining.
  • the above array substrate provided by the embodiments of the present disclosure may be applied to a top emission type OLED, or It is applied to a bottom emission type OLED, which is not limited herein.
  • the manufacturing method specifically includes the following steps:
  • an embodiment of the present disclosure further provides a display panel, including the above array substrate provided by the embodiment of the present disclosure.
  • the implementation of the display panel can be seen above.
  • the embodiments of the array substrate are not repeated here.
  • the above display panel provided by the embodiment of the present disclosure may be an organic electroluminescence display panel.
  • other display panels that can implement the present disclosure are also not limited herein.
  • an embodiment of the present disclosure further provides a display device, which includes the above display panel provided by the embodiment of the present disclosure, and the display device may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, Any product or part that has a display function, such as a navigator.
  • the display device reference may be made to the embodiment of the above display panel, and the repeated description is omitted.
  • An embodiment of the present disclosure provides an array substrate, a display panel, and a display device.
  • the array substrate includes: a substrate substrate, and peripheral traces and a plurality of pixel structures on the substrate. Since the at least one pixel structure has an overlapping area between the orthographic projection of the base substrate and the peripheral area where the peripheral traces are located, that is, the pixel structure extends to a peripheral area where the part or all of the peripheral traces are covered, and because the film layer of the peripheral trace exists Located between the film layer where the pixel structure is located and the substrate substrate or on the side of the film layer where the pixel structure is located facing away from the substrate, so that even if the pixel structure overlaps between the orthographic projection of the substrate substrate and the peripheral region where the peripheral traces are located The normal display of the pixel structure is not affected, so that the display area is expanded to cover a peripheral area where some or all of the peripheral traces are located. Compared with the existing structure in which the display area and the peripheral area do not overlap each other, the width of the frame

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Abstract

一种阵列基板、显示面板及显示装置，该阵列基板包括：衬底基板（1），以及位于衬底基板（1）上的外围走线（2）和多个像素结构（3）。由于至少一个像素结构（3）在衬底基板（1）的正投影与外围走线（2）所在的外围区域具有重叠区域，即像素结构（3）延伸至覆盖部分或全部外围走线（2）所在的外围区域，并且，由于外围走线所在膜层位于像素结构所在膜层与衬底基板（1）之间或位于像素结构所在膜层背向衬底基板（1）的一侧，这样，即使像素结构（3）在衬底基板（1）的正投影与外围走线（2）所在的外围区域相互重叠也不会影响像素结构（3）的正常显示，从而使得显示区域扩大至覆盖部分或全部外围走线（2）所在的外围区域，与现有的显示区域与外围区域互不重叠的结构相比，可以使显示面板的边框的宽度变窄，甚至实现无边框。

Description

一种阵列基板、显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、显示面板及显示装置。
背景技术
随着显示技术的不断发展，发光二极管(Light Emitting Diode，LED)、有机发光二极管(Organic Light Emitting Diode，OLED)及等离子显示器(Plasma Display Panel，PDP)等平板显示器发展迅速。
目前，窄边框甚至无边框是现有显示领域的发展趋势。下面以现有的OLED为例进行说明，OLED的阵列基板，如图1所示，包括：显示区域101和包围该显示区域101的外围区域102；其中，显示区域101内设置有用于显示的多个像素结构103，外围区域102内设置有用于对各像素结构103加载驱动信号的外围走线104，外围区域102的宽度为OLED的边框的宽度(如图1所示的a所示)。为了实现窄边框的设计，一般采用将栅极驱动电路整合于OLED的阵列基板上(Gate On Array，GOA)的技术，即在阵列基板的外围区域内形成栅极驱动电路。然而，整合于OLED的阵列基板上的栅极驱动电路仍然会占据一定的宽度，制约OLED的窄边框的发展。
因此，如何进一步地减小平板显示器的边框的宽度，是本领域技术人员亟需解决的技术问题。
发明内容
有鉴于此，本公开实施例提供了一种阵列基板、显示面板及显示装置，其至少部分地缓解或消除以上现有技术中存在的问题。
因此，本公开的第一方面提供了一种阵列基板，包括：衬底基板，以及位于所述衬底基板上的外围走线和多个像素结构；
至少一个所述像素结构在所述衬底基板的正投影与所述外围走线所在的外围区域在所述衬底基板的正投影具有重叠区域；
所述外围走线所在膜层位于所述像素结构所在膜层与所述衬底基板之间；或者，所述外围走线所在膜层位于所述像素结构所在膜层背 向所述衬底基板的一侧。
在一种可能的实现方式中，在本公开实施例提供的上述阵列基板中，还可以包括：位于所述衬底基板上的交叉而置且相互绝缘的多条数据线和多条栅线；各所述数据线和各所述栅线在所述衬底基板的正投影与所述外围走线在所述衬底基板的正投影互不重叠；
对于位于所述重叠区域以外的像素结构和与该像素结构对应的栅线和数据线，相邻的两条数据线和相邻的两条栅线限定一个像素结构。
在一种可能的实现方式中，在本公开实施例提供的上述阵列基板中，所述外围走线所在膜层可以位于所述像素结构所在膜层与所述衬底基板之间；所述阵列基板还可以包括：位于所述衬底基板与所述像素结构所在膜层之间且在所述衬底基板上依次设置的与各所述像素结构对应的薄膜晶体管、第一钝化层、金属桥和第二钝化层；所述像素结构为有机电致发光结构；
与位于所述重叠区域内的有机电致发光结构对应的薄膜晶体管的漏极通过贯穿所述第一钝化层的第一过孔与所述金属桥电性连接，该金属桥通过贯穿所述第二钝化层的第二过孔与该有机电致发光结构中的阳极电性连接；
与位于所述重叠区域以外的有机电致发光结构对应的薄膜晶体管的漏极通过贯穿所述第一钝化层和所述第二钝化层的第三过孔与该有机电致发光结构中的阳极电性连接。
在一种可能的实现方式中，在本公开实施例提供的上述阵列基板中，还可以包括设置在所述第二钝化层上的有机树脂层，所述第二过孔贯穿所述有机树脂层和所述第二钝化层，所述第三过孔贯穿有机树脂层、第二钝化层和第一钝化层。
在一种可能的实现方式中，在本公开实施例提供的上述阵列基板中，所述外围走线所在膜层可以位于所述像素结构所在膜层背向所述衬底基板的一侧；所述阵列基板还可以包括：在所述像素结构所在膜层背向所述衬底基板的一侧依次设置的第二钝化层、金属桥、第一钝化层和与各所述像素结构对应的薄膜晶体管；所述像素结构为有机电致发光结构；
与位于所述重叠区域内的有机电致发光结构对应的薄膜晶体管的漏极通过贯穿所述第一钝化层的第一过孔与所述金属桥电性连接，该 金属桥通过贯穿所述第二钝化层的第二过孔与该有机电致发光结构中的阳极电性连接；
与位于所述重叠区域以外的有机电致发光结构对应的薄膜晶体管的漏极通过贯穿所述第一钝化层和所述第二钝化层的第三过孔与该有机电致发光结构中的阳极电性连接。
在一种可能的实现方式中，在本公开实施例提供的上述阵列基板中，还可以包括：位于所述衬底基板上的交叉而置且相互绝缘的多条数据线和多条栅线；各所述数据线和各所述栅线在所述衬底基板的正投影与所述外围走线在所述衬底基板的正投影互不重叠；
每个所述像素结构沿所述栅线的延伸方向的宽度大于相邻的两条数据线之间的距离；和/或，每个所述像素结构沿所述数据线的延伸方向的宽度大于相邻的两条栅线之间的距离。
在一种可能的实现方式中，在本公开实施例提供的上述阵列基板中，所述外围走线所在膜层可以位于所述像素结构所在膜层与所述衬底基板之间；所述阵列基板还可以包括：位于所述衬底基板与所述像素结构所在膜层之间且在所述衬底基板上依次设置的与各所述像素结构对应的薄膜晶体管和第一钝化层；所述像素结构为有机电致发光结构；
各所述有机电致发光结构中的阳极通过所述第一钝化层中的第一过孔与对应的所述薄膜晶体管中的漏极电性连接。
在一种可能的实现方式中，在本公开实施例提供的上述阵列基板中，还可以包括：在所述第一钝化层上依次设置的金属桥和第二钝化层；其中，
所述金属桥通过所述第一钝化层中的第一过孔与所述薄膜晶体管中的漏极电性连接，所述金属桥通过所述第二钝化层中的第二过孔与所述有机电致发光结构中的阳极电性连接。
在一种可能的实现方式中，在本公开实施例提供的上述阵列基板中，所述外围走线所在膜层可以位于所述像素结构所在膜层背向所述衬底基板的一侧；所述阵列基板还可以包括：在所述像素结构所在膜层背向所述衬底基板的一侧依次设置的第一钝化层和与各所述像素结构对应的薄膜晶体管；所述像素结构为有机电致发光结构；
各所述有机电致发光结构中的阳极通过所述第一钝化层中的第一 过孔与对应的所述薄膜晶体管中的漏极电性连接。
在一种可能的实现方式中，在本公开实施例提供的上述阵列基板中，还可以包括：在所述第一钝化层上依次设置的金属桥和第二钝化层；其中，
所述金属桥通过所述第一钝化层中的第一过孔与所述有机电致发光结构中的阳极电性连接，所述金属桥通过所述第二钝化层中的第二过孔与所述薄膜晶体管中的漏极电性连接。
在一种可能的实现方式中，在本公开实施例提供的上述阵列基板中，所述金属桥的形状可以为条形；各所述金属桥位于与所述栅线相互平行的不同直线上。
在一种可能的实现方式中，在本公开实施例提供的上述阵列基板中，还可以包括外围电路；
所述外围走线所在膜层与所述外围电路所在膜层位于所述像素结构所在膜层与所述衬底基板之间；或者，所述外围走线所在膜层与所述外围电路所在膜层位于所述像素结构所在膜层背向所述衬底基板的一侧。
本公开实施例还提供了一种显示面板，包括：本公开实施例提供的上述阵列基板。
在一种可能的实现方式中，在本公开实施例提供的上述显示面板中，所述显示面板为有机电致发光显示面板。
本公开实施例还提供了一种显示装置，包括：本公开实施例提供的上述显示面板。
在本公开实施例提供的上述阵列基板、显示面板及显示装置中，该阵列基板包括：衬底基板，以及位于衬底基板上的外围走线和多个像素结构。由于至少一个像素结构在衬底基板的正投影与外围走线所在的外围区域具有重叠区域，即像素结构延伸至覆盖部分或全部外围走线所在的外围区域，并且，由于外围走线所在膜层位于像素结构所在膜层与衬底基板之间或位于像素结构所在膜层背向衬底基板的一侧，这样，即使像素结构在衬底基板的正投影与外围走线所在的外围区域相互重叠也不会影响像素结构的正常显示，从而使得显示区域扩大至覆盖部分或全部外围走线所在的外围区域，与现有的显示区域与外围区域互不重叠的结构相比，可以使显示面板的边框的宽度变窄， 甚至实现无边框。
附图说明
图1为现有的有机电致发光显示面板的阵列基板的结构示意图；
图2为本公开的一个实施例提供的阵列基板的结构示意图；
图3为图2沿AA方向的剖面图；
图4为本公开的另一实施例提供的阵列基板的结构示意图；
图5为图4沿CC方向的剖面图；
图6为图2沿BB方向的剖面图；
图7和图8分别为图4沿DD方向的剖面图；
图9为图4中部分像素结构的示意图。
具体实施方式
下面结合附图，对本公开实施例提供的一种阵列基板、显示面板及显示装置的具体实施方式进行详细地说明。
附图中各膜层的形状和厚度不反映阵列基板的真实比例，目的只是示意说明本公开内容。
本公开实施例提供的一种阵列基板，如图2-图5所示，图3是图2沿AA方向的剖面图，图5是图4沿CC方向的剖面图，包括：衬底基板1，以及位于衬底基板1上的外围走线2和多个像素结构3；
至少一个像素结构3在衬底基板1的正投影与外围走线2所在的外围区域(如图2-图5所示的网格阴影部分所示)在衬底基板1的正投影具有重叠区域。
如图3和图5所示，外围走线2所在膜层位于像素结构3所在膜层与衬底基板1之间；或者，外围走线2所在膜层位于像素结构3所在膜层背向衬底基板1的一侧。
在本公开实施例提供的上述阵列基板，至少一个像素结构在衬底基板的正投影与外围走线所在的外围区域在衬底基板的正投影具有重叠区域，在本公开实施例提供的上述阵列基板应用于顶发射型的OLED(即封装基板一侧为出光侧)时，外围走线所在膜层位于像素结构所在膜层与衬底基板之间，即使像素结构在衬底基板的正投影与外围走线在衬底基板的正投影相互重叠也不会影响OLED的正常显示；同样， 在本公开实施例提供的上述阵列基板应用于底发射的OLED(即阵列基板一侧为出光侧)时，外围走线所在膜层位于像素结构所在膜层背向衬底基板的一侧，即使像素结构在衬底基板的正投影与外围走线在衬底基板的正投影相互重叠也不会影响OLED的正常显示；因此，本公开实施例提供的上述阵列基板的显示区域可以扩大至覆盖部分或全部外围走线所在的外围区域，与如图1所示的现有的OLED的阵列基板中显示区域101与外围区域102互不重叠的结构相比，可以使有机电致发光显示面板的边框的宽度(如图2和图4所示的b所示)变窄。并且，在显示区域延伸至覆盖全部外围走线所在的外围区域时，有机电致发光显示面板为无边框显示。
需要说明的是，本公开实施例提供的上述阵列基板中的外围走线与阵列基板中的栅线和数据线电性连接，该外围走线的设置与现有的阵列基板中的外围走线的设置类似，该外围走线所在的外围区域与如图1所示的现有的OLED的阵列基板的外围区域102类似，在此不做赘述。
在具体实施时，在本公开实施例提供的上述阵列基板中，像素结构在衬底基板的正投影与外围走线所在的外围区域在衬底基板的正投影具有重叠区域，如图2和图3所示，可以在像素结构3的尺寸不变(即相邻的两条栅线和相邻的两条数据线限定一个像素结构)的情况下，通过在外围走线2所在的外围区域增加设置像素结构3的方式来实现；或者，如图4和图5所示，也可以通过增大每个像素结构3的尺寸(即每个像素结构所占面积大于相邻的两条栅线和相邻的两条数据线限定的区域所占面积)的方式来实现，在此不做限定。
在具体实施时，在通过增加像素结构的数量的方式使显示区域延伸至可以覆盖部分或全部外围走线所在的外围区域时，本公开实施例提供的上述阵列基板，如图2和图3所示，还可以包括：位于衬底基板1上的交叉而置且相互绝缘的多条数据线4和多条栅线5；各数据线4和各栅线5在衬底基板1的正投影与外围走线2在衬底基板1的正投影互不重叠，即与各像素结构3对应的栅线5和数据线4均位于外围走线2所在的外围区域(如图2和图3所示的网格阴影部分所示)所包围的区域内；其中，对于位于重叠区域以外的像素结构3和与该像素结构3对应的栅线5和数据线4，相邻的两条数据线4和相邻的两条 栅线5限定一个像素结构3；位于重叠区域内的像素结构3(即相对于现有的阵列基板另外增加的像素结构)所对应的栅线5和数据线4没有设置在重叠区域，而是设置在重叠区域以外的区域，这是由于外围走线2一般与栅线5或数据线4同层设置，为了防止重叠区域内的像素结构3对应的栅线5和数据线4与外围走线2之间电性连接而导致短路的问题，需要将位于重叠区域内的像素结构3对应的栅线5和数据线4设置在重叠区域以外的区域。具体地，位于重叠区域内的像素结构3可以通过过孔的方式与位于重叠区域以外的对应的栅线5和数据线4实现连接。
在具体实施时，在本公开实施例提供的上述阵列基板应用于顶发射型OLED，即外围走线所在膜层位于像素结构所在膜层与衬底基板之间时，本公开实施例提供的上述阵列基板，如图6所示，其中图6是图2沿BB方向的剖面图，还可以包括：位于衬底基板1与像素结构3所在膜层之间且在衬底基板1上依次设置的与各像素结构3对应的薄膜晶体管6、第一钝化层7、金属桥8和第二钝化层9；图6以像素结构3为包括阳极31、发光层32和阴极33的有机电致发光结构30为例，由于位于重叠区域内的有机电致发光结构30所对应的栅线5和数据线4位于重叠区域以外，因此，位于重叠区域内的有机电致发光结构30所对应的薄膜晶体管6也位于重叠区域以外，该有机电致发光结构30可以通过过孔的方式与对应的薄膜晶体管6电性连接，具体地，该薄膜晶体管6的漏极通过贯穿第一钝化层7的第一过孔与金属桥8电性连接，该金属桥8通过贯穿第二钝化层9的第二过孔与该有机电致发光结构30中的阳极31电性连接；与位于重叠区域以外的有机电致发光结构30所对应的薄膜晶体管6的漏极通过贯穿第一钝化层7和第二钝化层9的第三过孔与该有机电致发光结构30中的阳极31电性连接，位于重叠区域以外的有机电致发光结构30和与该有机电致发光结构30对应的薄膜晶体管6的连接与现有的结构类似，在此不做赘述。并且，如图6所示，还可以在第二钝化层9上设置有机树脂层10，第二过孔贯穿有机树脂层10和第二钝化层9，第三过孔贯穿有机树脂层10、第二钝化层9和第一钝化层7，该有机树脂层10的作用与现有的OLED中的有机树脂层的作用相同，在此不做赘述。
在具体实施时，在本公开实施例提供的上述阵列基板应用于底发 射型OLED，即外围走线所在膜层位于像素结构所在膜层背向衬底基板的一侧时，本公开实施例提供的上述阵列基板还可以包括：在像素结构所在膜层背向衬底基板的一侧依次设置的第二钝化层、金属桥、第一钝化层和与各像素结构对应的薄膜晶体管；以像素结构为有机电致发光结构为例，由于位于重叠区域内的有机电致发光结构所对应的栅线和数据线位于重叠区域以外，因此，位于重叠区域内的有机电致发光结构所对应的薄膜晶体管也位于重叠区域以外，该有机电致发光结构可以通过过孔的方式与对应的薄膜晶体管电性连接，具体地，该薄膜晶体管的漏极通过贯穿第一钝化层的第一过孔与金属桥电性连接，该金属桥通过贯穿第二钝化层的第二过孔与该有机电致发光结构中的阳极电性连接；位于重叠区域以外的有机电致发光结构所对应的薄膜晶体管的漏极通过贯穿第一钝化层和第二钝化层的第三过孔与该有机电致发光结构中的阳极电性连接。本公开实施例提供的上述阵列基板应用于底发射型OLED的具体实施与应用于顶发射型OLED的实施例类似，重复之处不再赘述。
在具体实施时，在通过增大每个像素结构的尺寸的方式使显示区域延伸至可以覆盖部分或全部外围走线所在的外围区域时，本公开实施例提供的上述阵列基板，如图4和图5所示，还可以包括：位于衬底基板1上的交叉而置且相互绝缘的多条数据线4和多条栅线5；各数据线4和各栅线5在衬底基板1的正投影与外围走线2在衬底基板1的正投影互不重叠，这样，可以防止各栅线5和各数据线4与外围走线2之间电性连接而导致短路的问题；每个像素结构3沿栅线5的延伸方向的宽度大于与该像素结构3相邻的两条数据线4之间的距离，这样，可以增大每个像素结构3沿栅线5的延伸方向的宽度，从而可以使像素结构3在栅线5的延伸方向延伸至可以覆盖部分或全部外围走线2所在的外围区域，进而可以使显示区域在栅线5的延伸方向延伸至可以覆盖部分或全部外围走线2所在的外围区域，使OLED在栅线5的延伸方向实现窄边框的设计；或者，每个像素结构3沿数据线4的延伸方向的宽度大于与该像素结构3相邻的两条栅线5之间的距离，这样，可以增大每个像素结构3沿数据线4的延伸方向的宽度，从而可以使像素结构3在数据线4的延伸方向延伸至可以覆盖部分或全部外围走线2所在的外围区域，进而可以使显示区域在数据线4的延伸 方向延伸至可以覆盖部分或全部外围走线2所在的外围区域，使OLED在数据线4的延伸方向实现窄边框的设计；或者，还可以同时增大每个像素结构3沿栅线5的延伸方向和沿数据线4的延伸方向两个方向的宽度，使OLED在栅线5的延伸方向和数据线4的延伸方向都实现窄边框的设计，在此不做限定。图4和图5仅以增大每个像素结构3沿栅线5的延伸方向的宽度为例进行说明。
在具体实施时，在采用增大每个像素结构的尺寸的方式时，由于每个像素结构与栅线和/或数据线存在重叠区域，因此，为了避免影响OLED的正常显示，需要根据OLED的类型(即顶发射型或底发射型)来设置每个像素结构和与该像素结构对应的薄膜晶体管的位置关系。具体地，在本公开实施例提供的上述阵列基板应用于顶发射型OLED时，需要将每个像素结构所对应的薄膜晶体管设置在该像素结构与衬底基板之间；在本公开实施例提供的上述阵列基板应用于底发射型OLED时，需要将每个像素结构设置在该像素结构所对应的薄膜晶体管与衬底基板之间。
在具体实施时，在本公开实施例提供的上述阵列基板应用于顶发射型OLED时，即外围走线所在膜层位于像素结构所在膜层与衬底基板之间时；本公开实施例提供的上述阵列基板，如图7所示，其中图7是图4沿DD方向的剖面图，还可以包括：位于衬底基板1与像素结构3所在膜层之间且在衬底基板1上依次设置的与各像素结构3对应的薄膜晶体管6和第一钝化层7；图7以像素结构3为包括阳极31、发光层32和阴极33的有机电致发光结构30为例，各有机电致发光结构30中的阳极31通过第一钝化层7中的第一过孔与对应的薄膜晶体管6中的漏极电性连接。并且，如图7所示，还可以在第一钝化层7上设置有机树脂层10，第一过孔贯穿有机树脂层10和第一钝化层7，该有机树脂层10的作用与现有的OLED中的有机树脂层的作用相同，在此不做赘述。
需要说明的是，在本公开实施例提供的上述阵列基板中，尤其在增大每个有机电致发光结构沿栅线的延伸方向的宽度，且薄膜晶体管为底栅型结构时，由于有机电致发光结构与除对该有机电致发光结构加载灰阶信号的数据线以外的数据线相互重叠，且数据线与薄膜晶体管的源漏极同层设置，因此，需要设置第一钝化层以避免有机电致发 光结构与除对该有机电致发光结构加载灰阶信号的数据线以外的数据线电性连接而导致短路的问题；同理，在增大每个有机电致发光结构沿数据线的延伸方向的宽度，且薄膜晶体管为顶栅型结构时，由于有机电致发光结构与除对该有机电致发光结构加载栅极扫描信号的栅线以外的栅线相互重叠，且栅线与薄膜晶体管的栅极同层设置，因此，需要设置第一钝化层以避免有机电致发光结构与除对该有机电致发光结构加载栅极扫描信号的栅线以外的栅线电性连接而导致短路的问题。
当然，在增大每个有机电致发光结构沿数据线的延伸方向的宽度，且薄膜晶体管为底栅型结构时；或者，在增大每个有机电致发光结构沿栅线的延伸方向的宽度，且薄膜晶体管为顶栅型结构时，也可以省去第一钝化层的设置，在此不做限定。
进一步地，在每个有机电致发光结构沿栅线的延伸方向的宽度明显大于与该有机电致发光结构相邻的两条数据线之间的宽度，使得每个有机电致发光结构中的阳极与对应的薄膜晶体管中的漏极相距较远，例如，每个有机电致发光结构中的阳极与对应的薄膜晶体管中的漏极之间的距离大于相邻的两条数据线之间的宽度时，相邻的两个有机电致发光结构之间可能会存在短路的问题，基于此，本公开实施例提供的上述阵列基板，如图8所示(图8为图4沿DD方向的剖面图的另一种情况)，还可以包括：在第一钝化层7上依次设置的金属桥8和第二钝化层9；其中，金属桥8通过第一钝化层7中的第一过孔与薄膜晶体管6中的漏极电性连接，金属桥8通过第二钝化层9中的第二过孔与有机电致发光结构30中的阳极31电性连接，这样，通过借助金属桥8将有机电致发光结构30中的阳极31与对应的薄膜晶体管6中的漏极电性连接，可以避免由于每个有机电致发光结构30中的阳极31与对应的薄膜晶体管6中的漏极相距较远而导致相邻的两个有机电致发光结构30之间存在短路的问题。此外，如图8所示，还可以在第二钝化层9上设置有机树脂层10，第二过孔贯穿有机树脂层10和第二钝化层9，该有机树脂层10的作用与现有的OLED中的有机树脂层的作用相同，在此不做赘述。
同理，在具体实施时，在本公开实施例提供的上述阵列基板应用于底发射型OLED时，即外围走线所在膜层位于像素结构所在膜层背 向衬底基板的一侧时，本公开实施例提供的上述阵列基板，还可以包括：在像素结构所在膜层背向衬底基板的一侧依次设置的第一钝化层和与各像素结构对应的薄膜晶体管；以像素结构为有机电致发光结构为例，各有机电致发光结构中的阳极通过第一钝化层中的第一过孔与对应的薄膜晶体管中的漏极电性连接。
进一步地，在每个有机电致发光结构沿栅线的延伸方向的宽度明显大于与该有机电致发光结构相邻的两条数据线之间的宽度，使得每个有机电致发光结构中的阳极与对应的薄膜晶体管中的漏极相距较远，例如，每个有机电致发光结构中的阳极与对应的薄膜晶体管中的漏极之间的距离大于相邻的两条数据线之间的宽度时，相邻的两个有机电致发光结构之间可能会存在短路的问题，基于此，本公开实施例提供的上述阵列基板还可以包括：在第一钝化层上依次设置的金属桥和第二钝化层；其中，金属桥通过第一钝化层中的第一过孔与有机电致发光结构中的阳极电性连接，金属桥通过第二钝化层中的第二过孔与薄膜晶体管中的漏极电性连接，这样，通过借助金属桥将有机电致发光结构中的阳极与对应的薄膜晶体管中的漏极电性连接，可以避免由于每个有机电致发光结构中的阳极与对应的薄膜晶体管中的漏极相距较远而导致相邻的两个有机电致发光结构之间存在短路的问题。本公开实施例提供的上述阵列基板应用于底发射型OLED的具体实施与应用于顶发射型OLED的实施例类似，重复之处不再赘述。
在具体实施时，在本公开实施例提供的上述阵列基板中，在每个有机电致发光结构中的阳极与对应的薄膜晶体管中的漏极相距较远，使得相邻两个金属桥之间电性连接而导致短路的问题时，如图9所示(图9为图4中部分像素结构的示意图)，可以将金属桥8的形状设置为条形，并且，将各金属桥8设置在与栅线5相互平行的不同直线上，这样，通过将相邻的金属桥8相互错开，可以防止各金属桥8之间电性连接而导致短路的问题；并且，在外围走线所在膜层位于有机电致发光结构所在膜层与衬底基板之间，即本公开实施例提供的上述阵列基板应用于顶发射型OLED时，由于金属桥位于有机电致发光结构所在膜层与衬底基板之间，因此，即使金属桥与有机电致发光结构相互重叠也不会影响OLED的正常显示；在外围走线所在膜层位于有机电致发光结构所在膜层背向衬底基板的一侧，即本公开实施例提供的上 述阵列基板应用于底发射型OLED时，由于金属桥位于有机电致发光结构所在膜层背向衬底基板的一侧，因此，即使金属桥与有机电致发光结构相互重叠也不会影响OLED的正常显示。
在示例实施例中，本公开实施例提供的阵列基板还可以为GOA结构，即本公开实施例提供的上述阵列基板还可以包括外围电路。为了不影响OLED的正常显示，在本公开实施例提供的上述阵列基板应用于顶发射型OLED时，需要将外围走线所在膜层与外围电路所在膜层设置于像素结构所在膜层与衬底基板之间；或者，在本公开实施例提供的上述阵列基板应用于底发射型OLED时，需要将外围走线所在膜层与外围电路所在膜层设置于像素结构所在膜层背向所述衬底基板的一侧。
需要说明的是，无论是采用增加像素结构的数量的方式，还是采用增大每个像素结构的尺寸的方式，本公开实施例提供的上述阵列基板可以应用于顶发射型OLED，或者，也可以应用于底发射型OLED，在此不做限定。
下面以一个具体的实例对本公开实施例提供的上述阵列基板的制作方法的具体实现方式进行详细说明。以如图8所示的阵列基板为例，其制作方法具体包括以下步骤：
(1)在衬底基板1上形成薄膜晶体管6的图形；
(2)在形成有薄膜晶体管6的图形的衬底基板1上形成第一钝化层7，并在第一钝化层7中刻蚀形成第一过孔；
(3)在形成有第一钝化层7的衬底基板1上形成金属桥8的图形；其中，金属桥8通过第一钝化层7中的第一过孔与薄膜晶体管6中的漏极电性连接；
(4)在形成有金属桥8的衬底基板1上形成第二钝化层9；
(5)在第二钝化层9上形成有机树脂层10，并形成贯穿有机树脂层10和第二钝化层9的第二过孔；
(6)在形成有第二过孔的衬底基板1上形成有机电致发光结构30的图形；其中，有机电致发光结构30中的阳极31通过第二过孔与金属桥8电性连接。
基于同一发明构思，本公开实施例还提供了一种显示面板，包括：本公开实施例提供的上述阵列基板。该显示面板的实施可以参见上述 阵列基板的实施例，重复之处不再赘述。
在示例实施例中，本公开实施例提供的上述显示面板可以为有机电致发光显示面板。当然，也可以为其他的可以实现本公开的显示面板，在此不做限定。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
本公开实施例提供的一种阵列基板、显示面板及显示装置，该阵列基板包括：衬底基板，以及位于衬底基板上的外围走线和多个像素结构。由于至少一个像素结构在衬底基板的正投影与外围走线所在的外围区域具有重叠区域，即像素结构延伸至覆盖部分或全部外围走线所在的外围区域，并且，由于外围走线所在膜层位于像素结构所在膜层与衬底基板之间或位于像素结构所在膜层背向衬底基板的一侧，这样，即使像素结构在衬底基板的正投影与外围走线所在的外围区域相互重叠也不会影响像素结构的正常显示，从而使得显示区域扩大至覆盖部分或全部外围走线所在的外围区域。与现有的显示区域与外围区域互不重叠的结构相比，可以使显示面板的边框的宽度变窄，甚至实现无边框。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (15)

  1. 一种阵列基板，包括：衬底基板，以及位于所述衬底基板上的外围走线和多个像素结构；其中：
    至少一个所述像素结构在所述衬底基板的正投影与所述外围走线所在的外围区域在所述衬底基板的正投影具有重叠区域；
    所述外围走线所在膜层位于所述像素结构所在膜层与所述衬底基板之间；或者，所述外围走线所在膜层位于所述像素结构所在膜层背向所述衬底基板的一侧。
  2. 如权利要求1所述的阵列基板，还包括：位于所述衬底基板上的交叉而置且相互绝缘的多条数据线和多条栅线；各所述数据线和各所述栅线在所述衬底基板的正投影与所述外围走线在所述衬底基板的正投影互不重叠；
    对于位于所述重叠区域以外的像素结构和与该像素结构对应的栅线和数据线，相邻的两条数据线和相邻的两条栅线限定一个像素结构。
  3. 如权利要求2所述的阵列基板，其中，所述外围走线所在膜层位于所述像素结构所在膜层与所述衬底基板之间；所述阵列基板还包括：位于所述衬底基板与所述像素结构所在膜层之间且在所述衬底基板上依次设置的与各所述像素结构对应的薄膜晶体管、第一钝化层、金属桥和第二钝化层；所述像素结构为有机电致发光结构；
    与位于所述重叠区域内的有机电致发光结构对应的薄膜晶体管的漏极通过贯穿所述第一钝化层的第一过孔与所述金属桥电性连接，该金属桥通过贯穿所述第二钝化层的第二过孔与该有机电致发光结构中的阳极电性连接；
    与位于所述重叠区域以外的有机电致发光结构对应的薄膜晶体管的漏极通过贯穿所述第一钝化层和所述第二钝化层的第三过孔与该有机电致发光结构中的阳极电性连接。
  4. 如权利要求3所述的阵列基板，还包括设置在所述第二钝化层上的有机树脂层，所述第二过孔贯穿所述有机树脂层和所述第二钝化层，所述第三过孔贯穿有机树脂层、第二钝化层和第一钝化层。
  5. 如权利要求2所述的阵列基板，其中，所述外围走线所在膜层位于所述像素结构所在膜层背向所述衬底基板的一侧；所述阵列基板 还包括：在所述像素结构所在膜层背向所述衬底基板的一侧依次设置的第二钝化层、金属桥、第一钝化层和与各所述像素结构对应的薄膜晶体管；所述像素结构为有机电致发光结构；
    与位于所述重叠区域内的有机电致发光结构对应的薄膜晶体管的漏极通过贯穿所述第一钝化层的第一过孔与所述金属桥电性连接，该金属桥通过贯穿所述第二钝化层的第二过孔与该有机电致发光结构中的阳极电性连接；
    与位于所述重叠区域以外的有机电致发光结构对应的薄膜晶体管的漏极通过贯穿所述第一钝化层和所述第二钝化层的第三过孔与该有机电致发光结构中的阳极电性连接。
  6. 如权利要求1所述的阵列基板，还包括：位于所述衬底基板上的交叉而置且相互绝缘的多条数据线和多条栅线；各所述数据线和各所述栅线在所述衬底基板的正投影与所述外围走线在所述衬底基板的正投影互不重叠；
    每个所述像素结构沿所述栅线的延伸方向的宽度大于相邻的两条数据线之间的距离；和/或，每个所述像素结构沿所述数据线的延伸方向的宽度大于相邻的两条栅线之间的距离。
  7. 如权利要求6所述的阵列基板，其中，所述外围走线所在膜层位于所述像素结构所在膜层与所述衬底基板之间；所述阵列基板还包括：位于所述衬底基板与所述像素结构所在膜层之间且在所述衬底基板上依次设置的与各所述像素结构对应的薄膜晶体管和第一钝化层；所述像素结构为有机电致发光结构；
    各所述有机电致发光结构中的阳极通过所述第一钝化层中的第一过孔与对应的所述薄膜晶体管中的漏极电性连接。
  8. 如权利要求7所述的阵列基板，还包括：在所述第一钝化层上依次设置的金属桥和第二钝化层；其中，
    所述金属桥通过所述第一钝化层中的第一过孔与所述薄膜晶体管中的漏极电性连接，所述金属桥通过所述第二钝化层中的第二过孔与所述有机电致发光结构中的阳极电性连接。
  9. 如权利要求6所述的阵列基板，其中，所述外围走线所在膜层位于所述像素结构所在膜层背向所述衬底基板的一侧；所述阵列基板还包括：在所述像素结构所在膜层背向所述衬底基板的一侧依次设置 的第一钝化层和与各所述像素结构对应的薄膜晶体管；所述像素结构为有机电致发光结构；
    各所述有机电致发光结构中的阳极通过所述第一钝化层中的第一过孔与对应的所述薄膜晶体管中的漏极电性连接。
  10. 如权利要求9所述的阵列基板，还包括：在所述第一钝化层上依次设置的金属桥和第二钝化层；其中，
    所述金属桥通过所述第一钝化层中的第一过孔与所述有机电致发光结构中的阳极电性连接，所述金属桥通过所述第二钝化层中的第二过孔与所述薄膜晶体管中的漏极电性连接。
  11. 如权利要求3-5、8或10所述的阵列基板，其中，所述金属桥的形状为条形；各所述金属桥位于与所述栅线相互平行的不同直线上。
  12. 如权利要求1-10任一项所述的阵列基板，还包括：外围电路；
    所述外围走线所在膜层与所述外围电路所在膜层位于所述像素结构所在膜层与所述衬底基板之间；或者，所述外围走线所在膜层与所述外围电路所在膜层位于所述像素结构所在膜层背向所述衬底基板的一侧。
  13. 一种显示面板，包括：如权利要求1-12任一项所述的阵列基板。
  14. 如权利要求13所述的显示面板，其中，所述显示面板为有机电致发光显示面板。
  15. 一种显示装置，包括：如权利要求13或14所述的显示面板。
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