WO2016145814A1 - 掩膜版和利用掩膜版制备薄膜晶体管的方法 - Google Patents

掩膜版和利用掩膜版制备薄膜晶体管的方法 Download PDF

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WO2016145814A1
WO2016145814A1 PCT/CN2015/090252 CN2015090252W WO2016145814A1 WO 2016145814 A1 WO2016145814 A1 WO 2016145814A1 CN 2015090252 W CN2015090252 W CN 2015090252W WO 2016145814 A1 WO2016145814 A1 WO 2016145814A1
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Prior art keywords
photoresist
region
retention
thin film
film transistor
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PCT/CN2015/090252
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English (en)
French (fr)
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刘翔
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京东方科技集团股份有限公司
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Priority to US15/126,955 priority Critical patent/US10007175B2/en
Publication of WO2016145814A1 publication Critical patent/WO2016145814A1/zh

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/039—Macromolecular compounds which are photodegradable, e.g. positive electron resists
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Definitions

  • Embodiments of the present invention relate to a mask and a method of fabricating a thin film transistor using a mask.
  • a photoresist portion corresponding to a conventional halftone or gray tone mask and a photoresist partial removal region is different in appearance and design shape after exposure and development. Larger, for example, the actual size differs greatly from the design size, affecting the quality of the thin film transistor of the pixel region of the array substrate.
  • a mask comprising a mask body, the mask body having a pattern region, the pattern region comprising: a portion for removing a photoresist a photoresist partial removal region; a photoresist completely removed region for removing all photoresist; and a photoresist partial removal region and a photoresist completely removed region, a photoresist partial removal region, and photolithography a first photoresist retention region adjacent to the photoresist for retaining the photoresist, and a first photoresist retention region for adjusting a photoresist portion corresponding to the photoresist partial removal region after exposure and development shape.
  • the pattern region further includes: a second photoresist retention region, wherein the photoresist partial removal region is disposed in the first photoresist retention region and the second photoresist retention region between.
  • the number of regions of the photoresist partially removed in the pattern region The amount is two, the number of the first photoresist retention regions is two, and the number of the photoresist completely removed regions is two
  • the pattern region further includes: a second photoresist retention region; Two photoresist completely removed regions, two first photoresist retention regions, two photoresist partial removal regions, and a second photoresist retention region according to one or two of the two photoresist completely removed regions
  • the other of the two remaining areas of the glue retention area is arranged in a row in the order of the other.
  • the pattern region of the mask is used to form a thin film transistor of a pixel region of the array substrate
  • the thin film transistor includes: a metal oxide semiconductor layer; and a source electrode and a drain electrode, the metal oxide
  • the semiconductor layer has a contact portion respectively contacting a portion of the source electrode and a portion of the drain electrode, wherein: the photoresist partial removal region corresponds to the contact portion, and the photoresist completely removed region and the first photolithography
  • the glue retention area corresponds to at least a portion of a region around the thin film transistor of each pixel region of the array substrate; or the photoresist partial removal region and the first photoresist retention region correspond to the contact portion, and the photoresist Completely removing at least a portion of a region around the thin film transistor of each pixel region of the array substrate corresponding to the region; or a portion of the photoresist partial removal region and the adjacent first photoresist retention region corresponding to the contact portion, and The photoresist completely removed region
  • the pattern region of the mask is used to form a thin film transistor of a pixel region of the array substrate, the thin film transistor comprising: a metal oxide semiconductor layer;
  • the metal oxide semiconductor layer having a contact portion respectively contacting a portion of the source electrode and a portion of the drain electrode; and the metal oxide semiconductor in a channel region between the source electrode and the drain electrode
  • An etch barrier layer on the layer wherein the second photoresist retention region corresponds to an etch barrier layer of the thin film transistor of the array substrate, and wherein: the photoresist partial removal region corresponds to the contact portion, and a photoresist completely removed region and a first photoresist retention region corresponding to at least a portion of a region around the thin film transistor of each pixel region of the array substrate; or the photoresist
  • the partial removal region and the first photoresist retention region correspond to the contact portion, and the photoresist completely removed region corresponds to at least a portion of a region around the thin film transistor of each pixel region of the array substrate; or the photoresist a portion of the removed region and a portion of the adjacent first photoresist retention region correspond to the contact portion, and
  • the length of the first photoresist retention region is 0.5-6 ⁇ m.
  • the length of the first photoresist retention region is 1-3 ⁇ m.
  • the light transmittance of the first photoresist remaining region is substantially equal to the light transmittance of the second photoresist remaining region.
  • the length of the photoresist completely removed region is at least 20 times the length of the first photoresist remaining region.
  • the first photoresist remaining region is used to make the difference between the size and the design size of the photoresist portion corresponding to the photoresist partial removal region after exposure and development less than a predetermined value and/or The difference between the position of the photoresist portion corresponding to the photoresist partial removal region after exposure and development and the design position is less than a predetermined value.
  • the first photoresist retention region is for causing a photoresist portion corresponding to the photoresist partial removal region to satisfy a predetermined dimensional tolerance, shape tolerance, and/or position tolerance after exposure and development.
  • a first photoresist remaining region forms an opaque region
  • a photoresist completely removed region forms a completely transparent region
  • a photoresist partially removed region forms a partially transparent region.
  • the first photoresist retention region and the second photoresist retention region form an opaque region
  • the photoresist completely removed region forms a completely transparent region
  • the photoresist The partially removed region forms a partially transparent region.
  • the light transmittance of the first photoresist remaining region is small Or equal to 10%.
  • a method of fabricating a thin film transistor of a pixel region of an array substrate using the above-described mask comprising: forming a photoresist layer on a plurality of layers for forming a thin film transistor, The layer includes: a metal oxide semiconductor layer and an etch barrier layer disposed on the metal oxide semiconductor layer; and exposing the photoresist layer by using the mask, wherein the second photoresist retention area corresponds to the array An etch barrier layer of the thin film transistor of the substrate, and wherein: the photoresist partial removal region corresponds to the contact portion, and the photoresist complete removal region and the first photoresist retention region correspond to each of the array substrates At least a portion of a region around the thin film transistor of the pixel region; or the photoresist partial removal region and the first photoresist retention region correspond to the contact portion, and the photoresist completely removed region corresponds to each of the array substrates At least a portion of a region around the
  • the shape of the photoresist portion corresponding to the photoresist partial removal region after exposure and development is improved.
  • FIG. 1 is a schematic view of a mask according to an embodiment of the present invention, further showing an exposed and developed photoresist layer;
  • FIG. 2 is a schematic plan view of an array substrate after completing a TFT array according to an embodiment of the present invention
  • FIG. 3 is a cross-sectional view of the array substrate along the line AB of FIG. 2 after completion of the first photolithography process, in accordance with an embodiment of the present invention
  • FIG. 4 is a cross-sectional view of the array substrate along the line AB of FIG. 2 after exposure and development of the second photolithography process, in accordance with an embodiment of the present invention
  • FIG. 5 is a second completed sequence of the array substrate along line AB of FIG. 2 according to an embodiment of the present invention. a cross-sectional view after the first etching of the photolithography process;
  • FIG. 6 is a cross-sectional view of the array substrate along the AB line of FIG. 2 after completion of the ashing of the second photolithography process, in accordance with an embodiment of the present invention
  • FIG. 7 is a cross-sectional view of the array substrate along the line AB of FIG. 2 after the second etching of the second photolithography process, in accordance with an embodiment of the present invention
  • FIG. 8 is a cross-sectional view of the array substrate along the line AB of FIG. 2 after completion of the third photolithography process, in accordance with an embodiment of the present invention
  • FIG. 9 is a cross-sectional view of the array substrate along the line AB of FIG. 2 after completion of the fourth photolithography process, according to an embodiment of the present invention.
  • FIG. 10 is a cross-sectional view of the array substrate along the line AB of FIG. 2 after completion of the fifth photolithography process, in accordance with an embodiment of the present invention.
  • FIG. 1 shows a mask 20 in accordance with an embodiment of the present invention.
  • a mask 20 according to an embodiment of the present invention includes a mask body 21 having a pattern region 22, the pattern region 22 including: for removing a portion of the photoresist a photoresist partial removal region 221; a photoresist complete removal region 223 for removing all photoresist; and a photoresist portion between the photoresist partial removal region 221 and the photoresist completely removed region 223
  • the removal region 221 and the photoresist completely removed region 223 are adjacent to the first photoresist retention region 222 for retaining the photoresist, and the first photoresist retention region 222 is used to adjust the corresponding photoresist removal region 221
  • the profile is improved such that the profile is offset from the design profile by less than a predetermined level.
  • the first photoresist retention region 222 is used to make the difference between the size and the design size of the photoresist portion corresponding to the photoresist partial removal region 221 after exposure and development less than a predetermined value and/or to lithography
  • the difference between the position of the photoresist portion corresponding to the adhesive partial removal region 221 and the position after the exposure and development is less than a predetermined value; or, for example, the first photoresist retention region 222 is used to remove the region from the photoresist portion 221
  • the corresponding photoresist portions meet predetermined dimensional tolerances, shape tolerances, and/or positional tolerances after exposure and development. Obviously, other quantities or values can also be used to measure the predetermined degree.
  • the mask 20 can be formed by forming a pattern layer on a substrate such as a quartz material.
  • the mask 20 is a halftone or gray tone mask.
  • the mask 20 can be used for forming the thin film transistor 50 of the pixel region 31 of the array substrate 30 of a display device such as a liquid crystal display device or the array substrate 30 for forming a display device such as a liquid crystal display device.
  • the pattern region 22 may further include: a second photoresist retention region 224, the photoresist portion removal region 221 being disposed in the first photoresist retention region 222 and The second photoresist remains between regions 224.
  • the light transmittance of the first photoresist retention region 222 and the light transmittance of the second photoresist retention region 224 may be substantially equal.
  • the first photoresist retention region 222 and the second photoresist retention region 224 form an opaque region, and the photoresist completely removed region 223 forms a completely transparent region, and the photoresist partially removed region 221 A partially transparent region is formed.
  • the first photoresist retention region 222 may have a light transmittance of less than or equal to 10%.
  • the first photoresist retention region 222 may have a light transmittance of less than or equal to 5%.
  • the first photoresist retention region 222 and the second photoresist retention region 224 form a completely transparent region, and the photoresist completely removed region 223 forms an opaque region, and the photoresist partially removed region 221 A partially transparent region is formed.
  • the first photoresist retention region 222 may have a light transmittance greater than or equal to 90%.
  • the transmittance of the first photoresist retention region 222 can be greater than or equal to 95%.
  • the number of the photoresist partial removal regions 221 is two, and the number of the first photoresist retention regions 222 is two. And the number of the photoresist completely removed regions 223 is two.
  • the pattern region 22 further includes a second photoresist retention region 224.
  • One of the two photoresist completely removed regions 223, one of the two first photoresist retention regions 222, one of the two photoresist partial removal regions 221, the second photoresist retention region 224, and two The other one of the photoresist partial removal regions 221, the other of the two first photoresist retention regions 222, and the other of the two photoresist completely removed regions 223 are in accordance with the two photoresist completely removed regions.
  • One of 223, one of the two first photoresist retention regions 222, one of the two photoresist partial removal regions 221, the second photoresist retention region 224, and the two photoresist partial removal regions 221 The other of the other, the other of the two first photoresist retention regions 222, and the other of the two photoresist completely removed regions 223 are arranged in a row.
  • the pattern region 22 of the reticle 20 is used to form the thin film transistor 50 of the pixel region 31 of the array substrate 30, in accordance with some embodiments of the present invention.
  • the thin film transistor 50 includes: a metal oxide semiconductor layer 4; and a source electrode 6 having a contact portion 41 that is in contact with a portion of the source electrode 6 and a portion of the drain electrode 7, respectively, and a drain electrode 7. .
  • the photoresist partial removal region 221 corresponds to the contact portion 41, and the photoresist completely removed region 223 and the first photoresist retention region 222 correspond to the periphery of the thin film transistor 50 of each of the pixel regions 31 of the array substrate 30.
  • At least a portion of the region; or the photoresist partial removal region 221 and the first photoresist retention region 222 correspond to the contact portion 41, and the photoresist completely removed region 223 corresponds to each pixel of the array substrate 30
  • the completely removed region 223 and the remaining portion of the adjacent first photoresist retention region 222 correspond to at least a portion of the region around the thin film transistor 50 of each of the pixel regions 31 of the array substrate 30.
  • the pattern region 22 of the mask 20 is used to form the thin film transistor 50 of the pixel region 31 of the array substrate 30, in accordance with further embodiments of the present invention.
  • the thin film transistor 50 includes: a metal oxide semiconductor layer 4; a source electrode 6 and a drain electrode 7, the metal oxide semiconductor layer 4 having a contact portion 41 respectively contacting a portion of the source electrode 6 and a portion of the drain electrode 7; And an etch stop layer 5 on the metal oxide semiconductor layer 4 of the channel region between the source electrode 6 and the drain electrode 7.
  • the second photoresist retention region 224 corresponds to the etch stop layer 5 of the thin film transistor 50 of the array substrate 30.
  • the photoresist partial removal region 221 corresponds to the contact portion 41, and the photoresist completely removed region 223 and the first photoresist retention region 222 correspond to the periphery of the thin film transistor 50 of each of the pixel regions 31 of the array substrate 30.
  • At least a portion of the region; or the photoresist partial removal region 221 and the first photoresist retention region 222 correspond to the contact portion 41, and the photoresist completely removed region 223 corresponds to each pixel of the array substrate 30
  • the completely removed region 223 and the remaining portion of the adjacent first photoresist retention region 222 correspond to at least a portion of the region around the thin film transistor 50 of each of the pixel regions 31 of the array substrate 30.
  • the length of the photoresist portion removal region 221 L1 is 1-10 ⁇ m, for example 2-4 ⁇ m
  • the length L2 of the second photoresist retention region 224 is 2-20 ⁇ m, for example 2-8 ⁇ m.
  • the length of the first photoresist retention region 222, or width L3, is 0.5-6 ⁇ m, for example 1-3 ⁇ m.
  • the length L4 of the photoresist completely removed region 223 outside the first photoresist retention region 222 is much larger than L3, for example, L4>20*L3. That is, the length of the photoresist completely removed region 223 is 20 times or more the length of the first photoresist remaining region 222.
  • the method includes forming a photoresist layer 10 on a plurality of layers for forming a thin film transistor 50, the plurality of layers including: a metal oxide semiconductor layer 4 and a metal oxide semiconductor layer An etch stop layer 5 of 4; and exposing the photoresist layer 10 using the mask 100.
  • the second photoresist retention region 224 corresponds to the etch stop layer 5 of the thin film transistor 50 of the array substrate 30.
  • the photoresist partial removal region 221 corresponds to the contact portion 41, and the photoresist completely removed region 223 and the first photoresist retention region 222 correspond to each pixel region 31 of the array substrate 30.
  • At least a portion of a region around the thin film transistor 50; or the photoresist partial removal region 221 and the first photoresist retention region 222 correspond to the contact portion 41, and the photoresist completely removed region 223 corresponds to the array substrate
  • At least a portion of a region around the thin film transistor 50 of each of the pixel regions 31 of 30; or a portion of the photoresist partial removal region 221 and the adjacent first photoresist retention region 222 corresponds to the contact portion 41
  • the photoresist completely removed region 223 and the remaining portion of the adjacent first photoresist retention region 222 correspond to at least a portion of the region around the thin film transistor 50 of each of the pixel regions 31 of the array substrate 30.
  • Step 1 depositing a thickness on the substrate 1 by sputtering or thermal evaporation.
  • Grid metal film may be selected from a metal or an alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., and a gate metal layer composed of a plurality of layers of metal may also satisfy the needs.
  • the gate electrode 2 and the gate line 12 are formed as shown in FIG.
  • Step 2 the thickness is continuously deposited by the PECVD method on the substrate 1 on which the step 1 is completed.
  • the gate insulating layer 3, the insulating layer 3 may be an oxide, a nitride or an oxynitride compound, and the reaction gas for forming a silicon oxide in the PECVD method is SiH 4 , N 2 O; the nitride is formed in the PECVD method.
  • the reaction gas corresponding to the oxynitride compound is SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 ; and then deposited thereon by sputtering or thermal evaporation to a thickness of about
  • the metal oxide semiconductor layer 4 the semiconductor layer may be amorphous IGZO, HIZO, IZO, a-InZnO, a-InZnO, ZnO:F, In 2 O 3 :Sn, In 2 O 3 :Mo, Cd 2 SnO 4 , ZnO: Al, TiO 2 : Nb, Cd-Sn-O or other metal oxides, and then deposited by PECVD method thickness
  • the etch stop layer 5, the etch stop layer 5 may be selected from an oxide, a nitride or an oxynitride compound, and the reaction gas corresponding to the silicon oxide may be SiH 4 , N 2 O; the nitride or the oxyn
  • the development is then exposed using a mask 20 according to an embodiment of the present invention.
  • the first photoresist retention region 222 and the second photoresist retention region 224 form an opaque region
  • the photoresist completely removed region 223 forms a completely transparent region
  • the photoresist partially removed region 221 Forming a partially transparent region (for the negative photoresist, the first photoresist retention region 222 and the second photoresist retention region 224 form a completely transparent region
  • the photoresist completely removed region 223 forms an opaque region
  • the etched portion removing region 221 forms a partially transparent region
  • the opaque region corresponds to the etch barrier layer 5 (semiconductor protective layer portion)
  • the partially transparent region corresponds to the contact of the source electrode 6 and the drain electrode 7 with the semiconductor layer 4.
  • Part 41 is shown in Figure 4.
  • the completely transparent region is distributed only around the thin film transistor 50 and the separation region of each of the pixel regions 31, and a portion of the transparent region is a large-area completely transparent region.
  • the etch barrier layer 5 and the semiconductor layer 4 of the fully exposed region are removed by an etching process.
  • the ashing process of the photoresist 10 is performed once to remove the photoresist of the partially transparent region.
  • an etching process is then performed to remove the etch stop layer 5 of the partially exposed region, and the contact portion 41 of the source electrode 6 and the drain electrode 7 with the semiconductor layer 4 is formed as shown in FIG.
  • Step 3 Depositing the thickness on the substrate 1 on which the step 2 is completed by sputtering or thermal evaporation.
  • the metal film may be a metal or an alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., and a metal layer composed of a plurality of layers of metal can also satisfy the needs.
  • the source electrode 6, the drain electrode 7, and the data line 32 (FIG. 2) are formed by a conventional photolithography process, as shown in FIG.
  • the metal oxide protective layer 8 may be a single layer of silicon oxide or a composite structure of silicon nitride and silicon oxide, or a three-layer structure of silicon nitride/silicon oxynitride/silicon oxide, silicon oxide.
  • the reaction gas corresponding to silicon oxynitride or silicon nitride may be N 2 O, SiH 4 , N 2 O, SiH 4 , NH 3 , N 2 ; SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .
  • the contact area of the transparent pixel electrode and the drain electrode is formed by a common photolithography process, that is, the transparent pixel electrode and the drain electrode contact the via hole 11, as shown in FIG.
  • Step 5 is deposited on the substrate 1 which is completed in step 4 by sputtering or thermal evaporation.
  • the transparent conductive layer and the transparent conductive layer may be ITO or IZO, or other transparent metal oxide; the pixel electrode 9 is formed by one photolithography process, as shown in FIG.
  • a mask for fabricating a metal oxide TFT of a pixel region of an array substrate and a method of fabricating a thin film transistor of a pixel region of the array substrate using a mask.
  • the shape of the photoresist portion corresponding to the photoresist partial removal region after exposure and development is improved.

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Abstract

一种掩膜版以及利用掩膜版制备阵列基板的像素区的薄膜晶体管的方法。所述掩膜版（20）包括掩膜版主体（21），所述掩膜版主体（21）具有图案区域（22），所述图案区域（22）包括：用于去除部分光刻胶的光刻胶部分去除区域（221）；用于去除全部光刻胶的光刻胶完全去除区域（223）；以及在光刻胶部分去除区域（221）和光刻胶完全去除区域（223）之间、与光刻胶部分去除区域（221）和光刻胶完全去除区域（223）邻接的用于保留光刻胶的第一光刻胶保留区域（222），第一光刻胶保留区域（222）用于调整与光刻胶部分去除区域（221）对应的光刻胶部分在曝光并显影后的外形。改善了与光刻胶部分去除区域（221）对应的光刻胶部分在曝光并显影后的外形。

Description

掩膜版和利用掩膜版制备薄膜晶体管的方法 技术领域
本发明的实施例涉及一种掩膜版和利用掩膜版制备薄膜晶体管的方法。
背景技术
在制造显示装置的阵列基板的像素区的薄膜晶体管时，采用传统的半色调或者灰色调掩膜版与光刻胶部分去除区域对应的光刻胶部分在曝光并显影后的外形与设计外形相差较大，例如实际尺寸与设计尺寸相差较大，影响了阵列基板的像素区的薄膜晶体管的质量。
发明内容
本发明的实施例的目的是提供一种掩膜版和利用掩膜版制备薄膜晶体管的方法，由此改善与光刻胶部分去除区域对应的光刻胶部分在曝光并显影后的外形。
根据本发明的实施例，提供了一种掩膜版，所述掩膜版包括掩膜版主体，所述掩膜版主体具有图案区域，所述图案区域包括：用于去除部分光刻胶的光刻胶部分去除区域；用于去除全部光刻胶的光刻胶完全去除区域；以及在光刻胶部分去除区域和光刻胶完全去除区域之间、与光刻胶部分去除区域和光刻胶完全去除区域邻接的用于保留光刻胶的第一光刻胶保留区域，第一光刻胶保留区域用于调整与光刻胶部分去除区域对应的光刻胶部分在曝光并显影后的外形。
根据本发明的实施例，所述图案区域还包括：第二光刻胶保留区域，所述光刻胶部分去除区域设置在第一光刻胶保留区域和所述第二光刻胶保留区域之间。
根据本发明的实施例，在所述图案区域中，所述光刻胶部分去除区域的数 量是两个，所述第一光刻胶保留区域的数量是两个，并且所述光刻胶完全去除区域的数量是两个，所述图案区域还包括：第二光刻胶保留区域；两个光刻胶完全去除区域、两个第一光刻胶保留区域、两个光刻胶部分去除区域、第二光刻胶保留区域按照两个光刻胶完全去除区域中的一个、两个第一光刻胶保留区域中的一个、两个光刻胶部分去除区域中的一个、第二光刻胶保留区域、两个光刻胶部分去除区域中的另一个、两个第一光刻胶保留区域中的另一个、两个光刻胶完全去除区域中的另一个的顺序排列成一排。
根据本发明的实施例，掩膜版的所述图案区域用于形成阵列基板的像素区的薄膜晶体管，所述薄膜晶体管包括：金属氧化物半导体层；以及源电极和漏电极，所述金属氧化物半导体层具有分别与源电极的一部分和漏电极的一部分接触的接触部分，其中：所述光刻胶部分去除区域对应所述接触部分，并且所述光刻胶完全去除区域和第一光刻胶保留区域对应阵列基板的每一个像素区的薄膜晶体管周围的区域的至少一部分；或者所述光刻胶部分去除区域和第一光刻胶保留区域对应所述接触部分，并且所述光刻胶完全去除区域对应阵列基板的每一个像素区的薄膜晶体管周围的区域的至少一部分；或者所述光刻胶部分去除区域和相邻的第一光刻胶保留区域的一部分对应所述接触部分，并且所述光刻胶完全去除区域和相邻的第一光刻胶保留区域的其余部分对应阵列基板的每一个像素区的薄膜晶体管周围的区域的至少一部分。
根据本发明的实施例，掩膜版的所述图案区域用于形成阵列基板的像素区的薄膜晶体管，所述薄膜晶体管包括：金属氧化物半导体层；
源电极和漏电极，所述金属氧化物半导体层具有分别与源电极的一部分和漏电极的一部分接触的接触部分；以及在源电极和漏电极之间的沟道区域的所述金属氧化物半导体层上的刻蚀阻挡层，其中所述第二光刻胶保留区域对应阵列基板的薄膜晶体管的刻蚀阻挡层，并且其中：所述光刻胶部分去除区域对应所述接触部分，并且所述光刻胶完全去除区域和第一光刻胶保留区域对应阵列基板的每一个像素区的薄膜晶体管周围的区域的至少一部分；或者所述光刻胶 部分去除区域和第一光刻胶保留区域对应所述接触部分，并且所述光刻胶完全去除区域对应阵列基板的每一个像素区的薄膜晶体管周围的区域的至少一部分；或者所述光刻胶部分去除区域和相邻的第一光刻胶保留区域的一部分对应所述接触部分，并且所述光刻胶完全去除区域和相邻的第一光刻胶保留区域的其余部分对应阵列基板的每一个像素区的薄膜晶体管周围的区域的至少一部分。
根据本发明的实施例，第一光刻胶保留区域的长度是0.5-6μm。
根据本发明的实施例，第一光刻胶保留区域的长度是1-3μm。
根据本发明的实施例，第一光刻胶保留区域的透光率与第二光刻胶保留区域的透光率大致相等。
根据本发明的实施例，所述光刻胶完全去除区域的长度是第一光刻胶保留区域的长度的至少20倍上。
根据本发明的实施例，第一光刻胶保留区域用于使与光刻胶部分去除区域对应的光刻胶部分在曝光并显影后的尺寸与设计尺寸的差值小于预定值和/或使与光刻胶部分去除区域对应的光刻胶部分在曝光并显影后的位置与设计位置的差值小于预定值。
根据本发明的实施例，第一光刻胶保留区域用于使与光刻胶部分去除区域对应的光刻胶部分在曝光并显影后满足预定的尺寸公差，形状公差和/或位置公差。
根据本发明的实施例，对于正性光刻胶，第一光刻胶保留区域形成不透光区域，光刻胶完全去除区域形成完全透光区域，光刻胶部分去除区域形成部分透光区域。
根据本发明的实施例，对于正性光刻胶，第一光刻胶保留区域和第二光刻胶保留区域形成不透光区域，光刻胶完全去除区域形成完全透光区域，光刻胶部分去除区域形成部分透光区域。
根据本发明的实施例，对于正性光刻胶，第一光刻胶保留区域的透光率小 于或等于10％。
根据本发明的实施例，提供一种利用上述的掩膜版制备阵列基板的像素区的薄膜晶体管的方法，包括：在用于形成薄膜晶体管的多个层上形成光刻胶层，所述多个层包括：金属氧化物半导体层以及设置在金属氧化物半导体层的刻蚀阻挡层；以及利用所述掩膜版对光刻胶层进行曝光，其中所述第二光刻胶保留区域对应阵列基板的薄膜晶体管的刻蚀阻挡层，并且其中：所述光刻胶部分去除区域对应所述接触部分，并且所述光刻胶完全去除区域和第一光刻胶保留区域对应阵列基板的每一个像素区的薄膜晶体管周围的区域的至少一部分；或者所述光刻胶部分去除区域和第一光刻胶保留区域对应所述接触部分，并且所述光刻胶完全去除区域对应阵列基板的每一个像素区的薄膜晶体管周围的区域的至少一部分；或者所述光刻胶部分去除区域和相邻的第一光刻胶保留区域的一部分对应所述接触部分，并且所述光刻胶完全去除区域和相邻的第一光刻胶保留区域的其余部分对应阵列基板的每一个像素区的薄膜晶体管周围的区域的至少一部分。
采用本发明的实施例的上述技术方案，例如，改善了与光刻胶部分去除区域对应的光刻胶部分在曝光并显影后的外形。
附图说明
图1为根据本发明的实施例的掩膜版的示意图，其中还示出了曝光并显影后的光刻胶层；
图2为根据本发明的实施例的阵列基板在完成TFT阵列之后的平面示意图；
图3为根据本发明的实施例的阵列基板沿图2中的AB线的、完成第一次光刻工艺之后的截面图；
图4为根据本发明的实施例的阵列基板沿图2中的AB线的、完成第二次光刻工艺的曝光显影之后的截面图；
图5为根据本发明的实施例的阵列基板沿图2中的AB线的、完成第二次 光刻工艺的第一次刻蚀之后的截面图；
图6为根据本发明的实施例的阵列基板沿图2中的AB线的、完成第二次光刻工艺的灰化之后的截面图；
图7为根据本发明的实施例的阵列基板沿图2中的AB线的、完成第二次光刻工艺的第二次刻蚀之后的截面图；
图8为根据本发明的实施例的阵列基板沿图2中的AB线的、完成第三次光刻工艺之后的截面图；
图9为根据本发明的实施例的阵列基板沿图2中的AB线的、完成第四次光刻工艺之后的截面图；以及
图10为根据本发明的实施例的阵列基板沿图2中的AB线的、完成第五次光刻工艺之后的截面图。
具体实施方式
下面结合附图，对本发明实施例的具体实施方式进行详细地说明。另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其他情况下，公知的结构和装置以图示的方式体现以简化附图。
图1示出了根据本发明的实施例的掩膜版20。如图1所示，根据本发明的实施例的掩膜版20包括掩膜版主体21，所述掩膜版主体21具有图案区域22，所述图案区域22包括：用于去除部分光刻胶的光刻胶部分去除区域221；用于去除全部光刻胶的光刻胶完全去除区域223；以及在光刻胶部分去除区域221和光刻胶完全去除区域223之间、与光刻胶部分去除区域221和光刻胶完全去除区域223邻接的用于保留光刻胶的第一光刻胶保留区域222，第一光刻胶保留区域222用于调整与光刻胶部分去除区域221对应的光刻胶部分在曝光并显影后的外形。例如，改善该外形，使该外形与设计外形的偏差小于预定程度。 例如，第一光刻胶保留区域222用于使与光刻胶部分去除区域221对应的光刻胶部分在曝光并显影后的尺寸与设计尺寸的差值小于预定值和/或使与光刻胶部分去除区域221对应的光刻胶部分在曝光并显影后的位置与设计位置的差值小于预定值；或例如，第一光刻胶保留区域222用于使与光刻胶部分去除区域221对应的光刻胶部分在曝光并显影后满足预定的尺寸公差，形状公差和/或位置公差。显然，也可以利用其它的量或数值来衡量该预定程度。
如图1、2所示，例如，掩膜版20可以通过在诸如石英材料的基板上形成图案层而形成。掩膜版20是半色调或者灰色调掩膜板。掩膜版20可以用于形成诸如液晶显示装置的显示装置的阵列基板30的像素区31的薄膜晶体管50或用于形成诸如液晶显示装置的显示装置的阵列基板30。
参见图1，根据本发明的一些实施例，所述图案区域22还可以包括：第二光刻胶保留区域224，所述光刻胶部分去除区域221设置在第一光刻胶保留区域222和所述第二光刻胶保留区域224之间。例如，第一光刻胶保留区域222的透光率与第二光刻胶保留区域224的透光率可以大致相等。
对于正性光刻胶，第一光刻胶保留区域222和第二光刻胶保留区域224形成不透光区域，光刻胶完全去除区域223形成完全透光区域，光刻胶部分去除区域221形成部分透光区域。根据本发明的实施例，对于正性光刻胶，例如，第一光刻胶保留区域222的透光率可以小于或等于10％。例如，对于正性光刻胶，第一光刻胶保留区域222的透光率可小于或等于5％。
对于负性光刻胶，第一光刻胶保留区域222和第二光刻胶保留区域224形成完全透光区域，光刻胶完全去除区域223形成不透光区域，光刻胶部分去除区域221形成部分透光区域。对于负性光刻胶，例如，第一光刻胶保留区域222的透光率可以大于或等于90％。例如，对于负性光刻胶，第一光刻胶保留区域222的透光率可大于或等于95％。
参见图1，根据本发明的另一些实施例，在所述图案区域22中，所述光刻胶部分去除区域221的数量是两个，所述第一光刻胶保留区域222的数量是两 个，并且所述光刻胶完全去除区域223的数量是两个。所述图案区域22还包括：第二光刻胶保留区域224。两个光刻胶完全去除区域223中的一个、两个第一光刻胶保留区域222中的一个、两个光刻胶部分去除区域221中的一个、第二光刻胶保留区域224、两个光刻胶部分去除区域221中的另一个、两个第一光刻胶保留区域222中的另一个、两个光刻胶完全去除区域223中的另一个按照两个光刻胶完全去除区域223中的一个、两个第一光刻胶保留区域222中的一个、两个光刻胶部分去除区域221中的一个、第二光刻胶保留区域224、两个光刻胶部分去除区域221中的另一个、两个第一光刻胶保留区域222中的另一个、两个光刻胶完全去除区域223中的另一个的顺序排列成一排。
参见图1、2和图10，根据本发明的一些实施例，掩膜版20的所述图案区域22用于形成阵列基板30的像素区31的薄膜晶体管50。所述薄膜晶体管50包括：金属氧化物半导体层4；以及源电极6和漏电极7，所述金属氧化物半导体层4具有分别与源电极6的一部分和漏电极7的一部分接触的接触部分41。所述光刻胶部分去除区域221对应所述接触部分41，并且所述光刻胶完全去除区域223和第一光刻胶保留区域222对应阵列基板30的每一个像素区31的薄膜晶体管50周围的区域的至少一部分；或者所述光刻胶部分去除区域221和第一光刻胶保留区域222对应所述接触部分41，并且所述光刻胶完全去除区域223对应阵列基板30的每一个像素区31的薄膜晶体管50周围的区域的至少一部分；或者所述光刻胶部分去除区域221和相邻的第一光刻胶保留区域222的一部分对应所述接触部分41，并且所述光刻胶完全去除区域223和相邻的第一光刻胶保留区域222的其余部分对应阵列基板30的每一个像素区31的薄膜晶体管50周围的区域的至少一部分。
参见图1、2和图10，根据本发明的另一些实施例，掩膜版20的所述图案区域22用于形成阵列基板30的像素区31的薄膜晶体管50。所述薄膜晶体管50包括：金属氧化物半导体层4；源电极6和漏电极7，所述金属氧化物半导体层4具有分别与源电极6的一部分和漏电极7的一部分接触的接触部分41； 以及在源电极6和漏电极7之间的沟道区域的所述金属氧化物半导体层4上的刻蚀阻挡层5。所述第二光刻胶保留区域224对应阵列基板30的薄膜晶体管50的刻蚀阻挡层5。所述光刻胶部分去除区域221对应所述接触部分41，并且所述光刻胶完全去除区域223和第一光刻胶保留区域222对应阵列基板30的每一个像素区31的薄膜晶体管50周围的区域的至少一部分；或者所述光刻胶部分去除区域221和第一光刻胶保留区域222对应所述接触部分41，并且所述光刻胶完全去除区域223对应阵列基板30的每一个像素区31的薄膜晶体管50周围的区域的至少一部分；或者所述光刻胶部分去除区域221和相邻的第一光刻胶保留区域222的一部分对应所述接触部分41，并且所述光刻胶完全去除区域223和相邻的第一光刻胶保留区域222的其余部分对应阵列基板30的每一个像素区31的薄膜晶体管50周围的区域的至少一部分。
如图1所示，根据本发明的一些实施例，为了调整与光刻胶部分去除区域221对应的光刻胶部分在曝光并显影后的外形或形貌，光刻胶部分去除区域221的长度L1为1-10μm，例如2-4μm，第二光刻胶保留区域224的长度L2为2-20μm，例如2-8μm。第一光刻胶保留区域222的长度或称为宽度L3为0.5-6μm，例如1-3μm。第一光刻胶保留区域222外侧的光刻胶完全去除区域223的长度L4远大于L3，例如，L4>20*L3。即所述光刻胶完全去除区域223的长度是第一光刻胶保留区域222的长度的20倍以上。
下面描述根据本发明的实施例的利用上述掩膜版100制备阵列基板30的像素区31的薄膜晶体管50的方法。
参见图1至10，该方法包括：在用于形成薄膜晶体管50的多个层上形成光刻胶层10，所述多个层包括：金属氧化物半导体层4以及设置在金属氧化物半导体层4的刻蚀阻挡层5；以及利用所述掩膜版100对光刻胶层10进行曝光。所述第二光刻胶保留区域224对应阵列基板30的薄膜晶体管50的刻蚀阻挡层5。所述光刻胶部分去除区域221对应所述接触部分41，并且所述光刻胶完全去除区域223和第一光刻胶保留区域222对应阵列基板30的每一个像素区31 的薄膜晶体管50周围的区域的至少一部分；或者所述光刻胶部分去除区域221和第一光刻胶保留区域222对应所述接触部分41，并且所述光刻胶完全去除区域223对应阵列基板30的每一个像素区31的薄膜晶体管50周围的区域的至少一部分；或者所述光刻胶部分去除区域221和相邻的第一光刻胶保留区域222的一部分对应所述接触部分41，并且所述光刻胶完全去除区域223和相邻的第一光刻胶保留区域222的其余部分对应阵列基板30的每一个像素区31的薄膜晶体管50周围的区域的至少一部分。
下面描述根据本发明的实施例的利用上述掩膜版100制备阵列基板30的像素区31的薄膜晶体管50的方法的一个示例。
步骤1，如图3所示，在基板1上采用溅射或热蒸发的方法沉积厚度约
Figure PCTCN2015090252-appb-000001
的栅金属膜。栅金属膜可以选用Cr、W、Cu、Ti、Ta、Mo、等金属或合金，由多层金属组成的栅金属层也能满足需要。通过一次光刻工艺后，形成栅电极2和栅极线12(图2)，如图3所示。
步骤2，如图4所示，在完成步骤1的基板1上通过PECVD方法连续沉积厚度为
Figure PCTCN2015090252-appb-000002
的栅极绝缘层3，绝缘层3可以选用氧化物、氮化物或者氧氮化合物，所述PECVD方法中形成氧化硅对应的反应气体采用SiH4，N2O；所述PECVD方法中形成氮化物或氧氮化合物对应的反应气体是SiH4、NH3、N2或SiH2Cl2、NH3、N2；然后在其上通过溅射或热蒸发的方法沉积上厚度约为
Figure PCTCN2015090252-appb-000003
的金属氧化物半导体层4，半导体层可以是采用非晶IGZO、HIZO、IZO、a-InZnO、a-InZnO、ZnO:F、In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2:Nb、Cd-Sn-O或其他金属氧化物制成，接着再通过PECVD方法沉积厚度为
Figure PCTCN2015090252-appb-000004
的刻蚀阻挡层5，刻蚀阻挡层5可以选用氧化物、氮化物或者氧氮化合物，硅的氧化物对应的反应气体可以为SiH4，N2O；氮化物或者氧氮化合物对应气体是SiH4，NH3，N2或SiH2Cl2，NH3，N2；阻挡层也可以使用Al2O3，或者双层的阻挡结构，最后形成光刻胶层10。然后使用根据本发明的实施例的掩膜板20曝光显影。对于正性光刻胶，第一光刻胶保留区域222和第二光刻胶保留区域224形成不透光区域，光刻胶完全去除区域223形成完全透光区域，光刻胶部分去除区域221形成部分透光区域(对于负性光刻胶，第 一光刻胶保留区域222和第二光刻胶保留区域224形成完全透光区域，光刻胶完全去除区域223形成不透光区域，光刻胶部分去除区域221形成部分透光区域)，不透光区域对应于刻蚀阻挡层5(半导体保护层部分)，部分透光区域对应于源电极6和漏电极7与半导体层4的接触部分41，如图4所示。完全透光区区域只分布在薄膜晶体管50周围及每个像素区31的分离区，靠近部分透光区域的是大面积的完全透光区域。如图5所示，通过刻蚀工艺去除掉完全曝光区域的刻蚀阻挡层5和半导体层4。如图6所示，接着进行一次光刻胶10的灰化工艺，去除部分透光区域的光刻胶。如图7所示，接着进行一次刻蚀工艺，去除掉部分曝光区域的刻蚀阻挡层5，形成源电极6和漏电极7与半导体层4的接触部分41，如图7所示。
步骤3、在完成步骤2的基板1上采用溅射或热蒸发的方法沉积厚度为
Figure PCTCN2015090252-appb-000005
的源电极6和漏电极7的金属膜。金属膜可以选用Cr、W、Cu、Ti、Ta、Mo等金属或合金，由多层金属组成的金属层也能满足需要。通过一次普通的光刻工艺形成源电极6、漏电极7、及数据线32(图2)，如图8所示。
步骤4，如图9所示，在完成步骤3的基板1上通过PECVD方法沉积厚度为
Figure PCTCN2015090252-appb-000006
的金属氧化物保护层8，金属氧化物保护层8可以选用单层的氧化硅或氮化硅与氧化硅的复合结构，或者氮化硅/氮氧化硅/氧化硅的三层结构，氧化硅、氮氧化硅、氮化硅对应的反应气体可以为N2O，SiH4；N2O,SiH4,NH3，N2；SiH4,NH3,N2或SiH2Cl2，NH3，N2。通过一次普通的光刻工艺形成透明像素电极与漏电极的接触区域，即透明像素电极与漏电极接触过孔11，如图9所示。
步骤5，如图10所示，在完成步骤4的基板1上通过溅射或热蒸发的方法沉积上厚度约为
Figure PCTCN2015090252-appb-000007
的透明导电层和透明导电层可以是ITO或者IZO，或者其他的透明金属氧化物；通过一次光刻工艺形成像素电极9，如图8所示。
如上所述，根据本发明的实施例，提供了一种制作阵列基板的像素区的金属氧化物TFT的掩膜版以及利用掩膜版制备阵列基板的像素区的薄膜晶体管的方法。改善了与光刻胶部分去除区域对应的光刻胶部分在曝光并显影后的外形。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护 范围应由权利要求限定。

Claims (15)

  1. 一种掩膜版，包括掩膜版主体，所述掩膜版主体具有图案区域，所述图案区域包括：
    用于去除部分光刻胶的光刻胶部分去除区域；
    用于去除全部光刻胶的光刻胶完全去除区域；以及
    在光刻胶部分去除区域和光刻胶完全去除区域之间、与光刻胶部分去除区域和光刻胶完全去除区域邻接的用于保留光刻胶的第一光刻胶保留区域，第一光刻胶保留区域用于调整与光刻胶部分去除区域对应的光刻胶部分在曝光并显影后的外形。
  2. 根据权利要求1所述的掩膜版，其中：
    所述图案区域还包括：第二光刻胶保留区域，所述光刻胶部分去除区域设置在第一光刻胶保留区域和所述第二光刻胶保留区域之间。
  3. 根据权利要求1所述的掩膜版，其中：
    在所述图案区域中，所述光刻胶部分去除区域的数量是两个，所述第一光刻胶保留区域的数量是两个，并且所述光刻胶完全去除区域的数量是两个，
    所述图案区域还包括：第二光刻胶保留区域，
    所述两个光刻胶完全去除区域、两个第一光刻胶保留区域、两个光刻胶部分去除区域、第二光刻胶保留区域按照两个光刻胶完全去除区域中的一个、两个第一光刻胶保留区域中的一个、两个光刻胶部分去除区域中的一个、第二光刻胶保留区域、两个光刻胶部分去除区域中的另一个、两个第一光刻胶保留区域中的另一个、两个光刻胶完全去除区域中的另一个的顺序排列成一排。
  4. 根据权利要求1所述的掩膜版，其中：
    掩膜版的所述图案区域用于形成阵列基板的像素区的薄膜晶体管，
    所述薄膜晶体管包括：金属氧化物半导体层以及源电极和漏电极，
    所述金属氧化物半导体层具有分别与源电极的一部分和漏电极的一部分接触的接触部分，
    其中：
    所述光刻胶部分去除区域对应所述接触部分，并且所述光刻胶完全去除区域和第一光刻胶保留区域对应阵列基板的每一个像素区的薄膜晶体管周围的区域的至少一部分；或者
    所述光刻胶部分去除区域和第一光刻胶保留区域对应所述接触部分，并且所述光刻胶完全去除区域对应阵列基板的每一个像素区的薄膜晶体管周围的区域的至少一部分；或者
    所述光刻胶部分去除区域和相邻的第一光刻胶保留区域的一部分对应所述接触部分，并且所述光刻胶完全去除区域和相邻的第一光刻胶保留区域的其余部分对应阵列基板的每一个像素区的薄膜晶体管周围的区域的至少一部分。
  5. 根据权利要求3所述的掩膜版，其中：
    掩膜版的所述图案区域用于形成阵列基板的像素区的薄膜晶体管，
    所述薄膜晶体管包括：
    源电极和漏电极；
    金属氧化物半导体层，所述金属氧化物半导体层具有分别与源电极的一部分和漏电极的一部分接触的接触部分；以及
    在源电极和漏电极之间的沟道区域的所述金属氧化物半导体层上的刻蚀阻挡层，
    其中所述第二光刻胶保留区域对应阵列基板的薄膜晶体管的刻蚀阻挡层，
    并且其中：
    所述光刻胶部分去除区域对应所述接触部分，并且所述光刻胶完全去除区域和第一光刻胶保留区域对应阵列基板的每一个像素区的薄膜晶体管周围的 区域的至少一部分；或者
    所述光刻胶部分去除区域和第一光刻胶保留区域对应所述接触部分，并且所述光刻胶完全去除区域对应阵列基板的每一个像素区的薄膜晶体管周围的区域的至少一部分；或者
    所述光刻胶部分去除区域和相邻的第一光刻胶保留区域的一部分对应所述接触部分，并且所述光刻胶完全去除区域和相邻的第一光刻胶保留区域的其余部分对应阵列基板的每一个像素区的薄膜晶体管周围的区域的至少一部分。
  6. 根据权利要求1至5中任一项所述的掩膜版，其中：
    第一光刻胶保留区域的长度是0.5-6μm。
  7. 根据权利要求1至5中任一项所述的掩膜版，其中：
    第一光刻胶保留区域的长度是1-3μm。
  8. 根据权利要求1至5中任一项所述的掩膜版，其中：
    第一光刻胶保留区域的透光率与第二光刻胶保留区域的透光率大致相等。
  9. 根据权利要求1至5中任一项所述的掩膜版，其中：
    所述光刻胶完全去除区域的长度是第一光刻胶保留区域的长度的至少20倍。
  10. 根据权利要求1至5中任一项所述的掩膜版，其中：
    所述第一光刻胶保留区域用于使与光刻胶部分去除区域对应的光刻胶部分在曝光并显影后的尺寸与设计尺寸的差值小于预定值和/或使与光刻胶部分去除区域对应的光刻胶部分在曝光并显影后的位置与设计位置的差值小于预定值。
  11. 根据权利要求1至5中任一项所述的掩膜版，其中：
    第一光刻胶保留区域用于使与光刻胶部分去除区域对应的光刻胶部分在曝光并显影后满足预定的尺寸公差，形状公差和/或位置公差。
  12. 根据权利要求1至5中任一项所述的掩膜版，其中：
    对于正性光刻胶，第一光刻胶保留区域形成不透光区域，光刻胶完全去除区域形成完全透光区域，光刻胶部分去除区域形成部分透光区域。
  13. 根据权利要求2、3或5所述的掩膜版，其中：
    对于正性光刻胶，第一光刻胶保留区域和第二光刻胶保留区域形成不透光区域，光刻胶完全去除区域形成完全透光区域，光刻胶部分去除区域形成部分透光区域。
  14. 根据权利要求1至5中任一项所述的掩膜版，其中：
    对于正性光刻胶，第一光刻胶保留区域的透光率小于或等于10％。
  15. 一种利用权利要求1至14中的任一项所述的掩膜版制备阵列基板的像素区的薄膜晶体管的方法，包括：
    在用于形成薄膜晶体管的多个层上形成光刻胶层，所述多个层包括：金属氧化物半导体层以及设置在金属氧化物半导体层的刻蚀阻挡层；以及
    利用所述掩膜版对光刻胶层进行曝光，其中所述第二光刻胶保留区域对应阵列基板的薄膜晶体管的刻蚀阻挡层，
    并且其中：
    所述光刻胶部分去除区域对应所述接触部分，并且所述光刻胶完全去除区域和第一光刻胶保留区域对应阵列基板的每一个像素区的薄膜晶体管周围的区域的至少一部分；或者
    所述光刻胶部分去除区域和第一光刻胶保留区域对应所述接触部分，并且 所述光刻胶完全去除区域对应阵列基板的每一个像素区的薄膜晶体管周围的区域的至少一部分；或者
    所述光刻胶部分去除区域和相邻的第一光刻胶保留区域的一部分对应所述接触部分，并且所述光刻胶完全去除区域和相邻的第一光刻胶保留区域的其余部分对应阵列基板的每一个像素区的薄膜晶体管周围的区域的至少一部分。
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CN104716026B (zh) 2017-09-01
US20170110490A1 (en) 2017-04-20

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