WO2016123964A1 - 阵列基板、内嵌式触摸面板和显示装置 - Google Patents

阵列基板、内嵌式触摸面板和显示装置 Download PDF

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Publication number
WO2016123964A1
WO2016123964A1 PCT/CN2015/087799 CN2015087799W WO2016123964A1 WO 2016123964 A1 WO2016123964 A1 WO 2016123964A1 CN 2015087799 W CN2015087799 W CN 2015087799W WO 2016123964 A1 WO2016123964 A1 WO 2016123964A1
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layer
signal trace
signal
insulating layer
array substrate
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PCT/CN2015/087799
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English (en)
French (fr)
Inventor
曲连杰
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US14/906,191 priority Critical patent/US10198119B2/en
Publication of WO2016123964A1 publication Critical patent/WO2016123964A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04111—Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, an in-cell touch panel, and a display device.
  • FIG. 1 is a schematic structural diagram of an array substrate of an in-cell touch panel in the prior art.
  • the array substrate includes: a display area 10 and a non-display area 20 located at a periphery of the display area 10, and is disposed in the non-display area.
  • the GOA unit 30 is connected to a gate line (not shown) located in the display area through a lateral gate drive signal line 104.
  • the touch driving signal line 102 is connected to a touch driving electrode (not shown) located in the display area.
  • the overlapping area is shown in the area surrounded by the dotted circle in FIG. 1, wherein the dotted circle is surrounded by the overlapping area of the touch driving signal line 102 and the gate driving signal line 104, and the dotted line 202 is surrounded by the horizontal direction.
  • the overlapping area of the touch driving signal line 102 and the vertical touch driving signal line 102 is shown in the area surrounded by the dotted circle in FIG. 1, wherein the dotted circle is surrounded by the overlapping area of the touch driving signal line 102 and the gate driving signal line 104, and the dotted line 202 is surrounded by the horizontal direction.
  • the overlapping area of the touch driving signal line 102 and the vertical touch driving signal line 102 is shown in the area surrounded by the dotted circle in FIG. 1, wherein the dotted circle is surrounded by the overlapping area of the touch driving signal line 102 and the gate driving signal line 104, and the dotted line 202 is surrounded by the horizontal direction.
  • FIG. 2 is a cross-sectional view showing the overlapping area of the touch driving signal line and the gate driving signal line in FIG. 1.
  • 101 is a substrate
  • 102 is a touch driving signal line
  • 103 is The gate insulating layer (GI)
  • 104 is a gate driving signal line
  • 105 is a passivation layer, wherein the thickness of the gate insulating layer 103 is generally only several thousand angstroms, so that the overlapping touch driving signal lines 102 and the gate driving signals are The capacitance generated between the lines 104 is large, and the signal coupling effect is also very strong.
  • the gate driving signal line 104 transmits the gate driving signal
  • the gate driving signals in the gate driving signal line 104 of the overlapping region are partially coupled.
  • the touch drive signal line 102 causes the noise of the touch drive signal to be very large, which affects the improvement of the signal to noise ratio. There is also a phenomenon of flicker (picture jitter).
  • the present disclosure provides an array substrate, an in-cell touch panel, and a display device to solve the problem of strong signal coupling between the overlapping signal lines of the existing non-display area of the array substrate, resulting in a signal line.
  • the signal transmitted is noisy.
  • the present disclosure provides an array substrate including a display area and a non-display area, wherein the display area is provided with a gate line, a data line, a thin film transistor, and a pixel electrode, and the thin film transistor includes: a gate, a gate insulating layer, an active layer and a source drain, wherein the non-display area is provided with a first signal trace and a second signal trace, and the first signal trace and the second signal trace are different Intersecting, the first signal trace is disposed in the same material as the gate line, and the gate insulating layer and the at least one elevated layer are between the first signal trace and the second signal trace in the overlap region .
  • the display area is further provided with a touch driving electrode, wherein the first signal trace is a touch driving signal line, and is connected to the touch driving electrode for transmitting to the touch driving electrode.
  • Touch drive signal is a touch driving signal line
  • the second signal trace includes: a gate driving signal line connected to the gate line for transmitting a gate driving signal to the gate line.
  • the second signal trace includes: a touch driving signal line connected to the touch driving electrode.
  • a common electrode is disposed in the display area, an intermediate insulating layer is disposed between the layer where the common electrode is located and the layer where the data line is located, and the second signal trace includes: a disconnected source and drain a metal segment and a common electrode wire for connecting the disconnected source/drain metal segments, wherein the source/drain metal segment is disposed in the same material as the data line, and the common electrode wire is in the same layer as the common electrode a material arrangement, the common electrode wire is located at an overlap region of the first signal trace and the second signal trace, and the common electrode trace is connected to a first signal trace located in the overlap region
  • the gate insulating layer and the intermediate insulating layer are interposed, and the intermediate insulating layer serves as the elevated layer.
  • a common electrode is disposed in the display area, and an intermediate insulating layer is disposed between the layer where the common electrode is located and the layer where the data line is located, and the second signal trace is the same layer as the common electrode a material arrangement having the gate between the first signal trace and the second signal trace in the overlap region a rim layer and the intermediate insulating layer, the intermediate insulating layer serving as the elevated layer.
  • the intermediate insulating layer may be made of a resin material and has a thickness of 1 to 2 um.
  • the second signal trace is disposed in the same material as the data line, and at least a gate insulating layer and a semiconductor lift are disposed between the first signal trace and the second signal trace in the overlap region.
  • the semiconductor elevated layer and the active layer of the thin film transistor are disposed in the same layer, and the peninsular layer is raised as a high layer.
  • the second signal trace includes: a disconnected source/drain metal segment and a pixel electrode lead for connecting the disconnected source/drain metal segment, the source/drain metal segment being in the same layer as the data line
  • the pixel electrode wire is disposed in the same material as the pixel electrode, and the pixel electrode wire is located at an overlapping region of the first signal trace and the second signal trace.
  • the pixel electrode wire has at least the gate insulating layer and the passivation layer between the first signal traces located in the overlap region, and the passivation layer serves as the elevated layer.
  • the second signal trace is disposed in the same material as the pixel electrode, and at least the gate insulating layer and the blunt layer are between the first signal trace and the second signal trace in the overlap region.
  • the passivation layer serves as the elevated layer.
  • the present disclosure also provides an in-cell touch panel including the above array substrate.
  • the present disclosure also provides a display device including the above-described in-cell touch panel.
  • FIG. 1 is a schematic structural view of an array substrate of an in-cell touch panel in the prior art
  • FIG. 2 is a cross-sectional view showing a region where the touch driving signal line and the gate driving signal line overlap in FIG. 1;
  • FIG. 3 is a front elevational view of an array substrate of an embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view of an array substrate including a raised upper layer according to Embodiment 1 of the present disclosure
  • FIG. 5 is a cross-sectional view of an array substrate including a raised upper layer according to Embodiment 2 of the present disclosure
  • FIG. 6 is a cross-sectional view of an array substrate including a raised upper layer according to Embodiment 3 of the present disclosure
  • FIG. 7 is a cross-sectional view of an array substrate including a raised upper layer according to Embodiment 4 of the present disclosure
  • FIG. 8 is a cross-sectional view of an array substrate including a raised upper layer according to a fifth embodiment of the present disclosure.
  • the magnitude of the capacitance between the two wires is determined by the overlapping area s between the two and the spacing d between the two.
  • the capacitance between the two can be changed by changing the spacing d between the two.
  • At least one elevated layer is added in the overlapping area of the two signal traces to change the overlap.
  • the spacing between the two signal traces in the region reduces the capacitance between the two, reduces the signal coupling, improves the signal-to-noise ratio, and eliminates the phenomenon of picture jitter of the display device having the array substrate.
  • An embodiment of the present disclosure provides an array substrate including a display area and a non-display area, wherein the display area is provided with a gate line, a data line, a thin film transistor, and a pixel electrode, and the thin film transistor includes: a gate and a gate insulating layer An active layer and a source drain, wherein the non-display area is provided with a first signal trace and a second signal trace, and the first signal trace intersects with the second signal trace, the The first signal trace is disposed in the same material as the gate line, wherein the gate insulating layer and the at least one elevated layer are between the first signal trace and the second signal trace in the overlap region.
  • At least one elevated layer is added between the first signal trace and the second signal trace, thereby increasing the first signal trace and the second signal trace located in the overlap region.
  • the distance between the two reduces the capacitance between the two, reduces the signal coupling, improves the signal-to-noise ratio, and eliminates the phenomenon of picture jitter of the display device having the array substrate.
  • the first signal trace and the second signal trace are signal traces for transmitting signals to the display area, for example, to signal lines (gate lines or data) located in the display area. Signals such as lines, etc. or electrodes (touch drive electrodes or common electrodes, etc.).
  • the first signal trace is a touch drive signal line, and is connected to a touch drive electrode located in the display area for transmitting a touch drive signal to the touch drive electrode.
  • the second signal trace is a gate drive signal line connected to a gate line located in the display area for transmitting a gate drive signal to the gate line.
  • FIG. 3 is a front view of an array substrate according to an embodiment of the present disclosure.
  • the array substrate includes: a display area 10 and a non-display area 20 located at a periphery of the display area 10.
  • the non-display area 20 is provided with a GOA unit 30 and The touch driving signal line 102, the GOA unit 30 is connected to the gate line (not shown) located in the display area 10 through the lateral gate driving signal line 104, and the touch driving signal line 102 and the touch located in the display area 10.
  • Drive electrodes (not shown) are connected.
  • the overlapping area please refer to the area surrounded by the dotted circle 201 in FIG. If the distance between the touch driving signal line 102 and the gate driving signal line 104 in the overlapping region is small, a large capacitance is generated between the two, and the signal coupling effect is strong.
  • the gate driving signal line 104 When the gate driving signal is transmitted, the gate driving signal in the gate driving signal line 104 in the overlapping region is partially coupled into the touch driving signal line 102, resulting in a very large noise of the touch driving signal, which affects the signal. The increase in noise ratio also causes picture jitter.
  • At least one elevated layer 301 is added between the touch driving signal line 102 and the gate driving signal line 104 located in the overlapping region, thereby increasing the touch driving layer located in the overlapping region.
  • the distance between the moving signal line 102 and the gate driving signal line 104 reduces the capacitance between the two, reduces the signal coupling, improves the signal-to-noise ratio, and eliminates the phenomenon of picture jitter of the display device having the array substrate.
  • the first signal trace and the second signal trace are touch drive signal lines.
  • One of them is a horizontal touch driving signal line, and the other is a vertical touch driving signal line.
  • the distance between the two touch driving signal lines 102 located in the overlapping area is increased.
  • the capacitance between the two is reduced, the signal coupling is reduced, the signal-to-noise ratio is improved, and the picture jitter phenomenon of the display device having the array substrate is eliminated.
  • FIG. 4 is a cross-sectional view of an array substrate including a raised upper layer according to Embodiment 1 of the present disclosure.
  • the array substrate includes a base substrate 401, a first signal trace 402, a gate insulating layer 403, a second signal trace 404, an intermediate insulating layer 405, and a passivation layer 406.
  • the first signal trace 402 is disposed in the same material as the gate line of the array substrate.
  • the first signal trace 402 can be a touch drive signal line.
  • the intermediate insulating layer 405 is an insulating layer between a layer where the common electrode of the array substrate is located and a layer where the data line is located.
  • the second signal trace 404 can be a gate drive signal line or a touch drive signal line.
  • the second signal trace 404 includes: a broken source/drain metal segment 4041 and a common electrode trace 4042 for connecting the disconnected source/drain metal segments 4041, the source/drain metal segment 4041 and the array substrate
  • the data line is disposed in the same layer as the material.
  • the common electrode wire 4042 is disposed in the same material as the common electrode of the array substrate, and the common electrode wire 4042 is connected to the source/drain metal segment 4041 through the via.
  • the common electrode wire 4042 is located at an overlapping area of the first signal trace 402 and the second signal trace 404.
  • the common electrode wire 4042 has a gate insulating layer 403 and the intermediate insulating layer 405 between the first signal traces 402 located in the overlap region, and the intermediate insulating layer 405 serves as a raised upper layer.
  • FIG. 5 is a cross-sectional view of an array substrate including a raised upper layer according to Embodiment 2 of the present disclosure.
  • the array substrate includes a base substrate 401, a first signal trace 402, a gate insulating layer 403, a second signal trace 404, an intermediate insulating layer 405, and a passivation layer 406.
  • the first signal trace 402 is disposed in the same layer as the gate line of the array substrate.
  • the first signal trace 402 can be a touch drive signal line.
  • the intermediate insulating layer 405 is an insulating layer between a layer where the common electrode of the array substrate is located and a layer where the data line is located.
  • the second signal trace 404 can be a gate drive signal line or a touch drive signal line.
  • the second signal trace 404 is disposed in the same material as the common electrode, that is, the second signal trace 404 is completely made of a material used for the common electrode, such as ITO.
  • the gate insulating layer 403 and the intermediate insulating layer 405 are provided between the first signal trace 402 and the second signal trace 404 in the overlap region, and the intermediate insulating layer 405 is used as the upper layer.
  • the intermediate insulating layer 405 may be made of a resin or the like and has a thickness of about 1 to 2 um (micrometers).
  • the first signal trace 402 and the second signal trace 404 are used.
  • the capacitance between the first signal trace 402 and the second signal trace 404 located in the overlapping region can be reduced by 70% to 90. %.
  • the intermediate insulating layer 405 located in the overlapping region of the first signal trace 402 and the second signal trace 404 is used as the upper layer to raise the first signal trace 402 and the second signal in the overlapping region.
  • FIG. 6 is a cross-sectional view of an array substrate including a raised upper layer according to Embodiment 3 of the present disclosure.
  • the array substrate includes a base substrate 401, a first signal trace 402, a gate insulating layer 403, a semiconductor lift layer 407, a second signal trace 404, and a passivation layer 406.
  • the first signal trace 402 is disposed in the same layer as the gate line of the array substrate.
  • the first signal trace 402 can be a touch drive signal line.
  • the semiconductor elevated layer 407 is the same layer as the active layer of the thin film transistor on the array substrate Material settings.
  • the second signal trace 404 can be a gate drive signal line or a touch drive signal line.
  • the second signal trace 404 is disposed in the same material as the data line of the array substrate. That is, the second signal trace 404 is made of source/drain metal.
  • a gate insulating layer 403 and a semiconductor lift layer 407 which is raised as a high layer.
  • the second signal traces 404 are all made of the same material as the data lines, that is, the source and drain metal materials. Therefore, the second signal traces 404 can be increased without reducing the resistance of the second signal traces 404.
  • FIG. 7 is a cross-sectional view of an array substrate including a raised upper layer according to Embodiment 4 of the present disclosure.
  • the array substrate includes a base substrate 401, a first signal trace 402, a gate insulating layer 403, a second signal trace 404, an intermediate insulating layer 405, and a passivation layer 406.
  • the first signal trace 402 is disposed in the same layer as the gate line of the array substrate.
  • the first signal trace 402 can be a touch drive signal line.
  • the intermediate insulating layer 405 is an insulating layer between the layer where the common electrode is located and the layer where the data line is located.
  • the second signal trace 404 can be a gate drive signal line or a touch drive signal line.
  • the second signal trace 404 includes: a broken source/drain metal segment 4041 and a pixel electrode wire 4043 for connecting the disconnected source/drain metal segment, and the source/drain metal segment 4041 is in the same layer as the data line.
  • the pixel electrode wire 4043 is disposed in the same material as the pixel electrode, and the pixel electrode wire 4043 is located in the first signal trace 402 and the first An overlapping region of the two signal traces 404, the pixel electrode traces 4043 and the first signal trace 402 located in the overlap region, having the gate insulating layer 403, the intermediate insulating layer 405, and passivation Layer 406, the intermediate insulating layer 405 and the passivation layer 406 serve as the elevated layers.
  • FIG. 8 is a cross-sectional view of an array substrate including a raised upper layer according to Embodiment 5 of the present disclosure.
  • the array substrate includes: a substrate substrate 401, a first signal trace 402, a gate insulating layer 403, a second signal trace 404, an intermediate insulating layer 405, and a passivation layer 406.
  • the first signal trace 402 is disposed in the same layer as the gate line of the array substrate.
  • the first signal trace 402 can be a touch drive signal line.
  • the intermediate insulating layer 405 is an insulating layer between the layer where the common electrode is located and the layer where the data line is located.
  • the second signal trace 404 is disposed in the same material as the pixel electrode of the array substrate, that is, the second signal trace 404 is completely made of a material used for the pixel electrode, such as ITO.
  • the gate insulating layer 403, the intermediate insulating layer 405, and the passivation layer 406 are interposed between the first signal trace 402 and the second signal trace 404 in the overlap region, the intermediate insulating layer 405 and blunt Layer 406 acts as the elevated layer.
  • the elevated layer includes the intermediate insulating layer 405 and the passivation layer 406, the distance between the first signal trace 402 and the second signal trace 404 located in the overlap region is larger. The capacitance will get smaller.
  • the touch driving electrodes are generally multiplexed with the common electrodes, that is, the common electrode layer is divided into a plurality of touch driving electrodes and a plurality of common electrodes, and the touch driving electrodes and The common electrode is spaced apart, and the touch driving electrode is loaded with the touch driving signal during the touch time period, and the common electrode signal is loaded during the display time period and multiplexed into the common electrode.
  • An embodiment of the present disclosure further provides an in-cell touch panel, including the array substrate in any of the above embodiments.
  • Embodiments of the present disclosure also provide a display device including the above-described in-cell touch panel.

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Abstract

本公开提供一种阵列基板、内嵌式触摸面板和显示装置。该阵列基板包括：显示区域和非显示区域，所述显示区域内设置有栅线、数据线、薄膜晶体管和像素电极，所述薄膜晶体管包括：栅极、栅极绝缘层、有源层和源漏极，所述非显示区域中设置有第一信号走线和第二信号走线，所述第一信号走线与所述第二信号走线异层相交，所述第一信号走线与所述栅线同层同材料设置，处于交叠区域的第一信号走线和第二信号走线之间具有所述栅极绝缘层和至少一抬高层。

Description

阵列基板、内嵌式触摸面板和显示装置
相关申请的交叉引用
本申请主张在2015年2月6日在中国提交的中国专利申请号No.201510065014.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、内嵌式触摸面板和显示装置。
背景技术
请参考图1，图1为现有技术中的内嵌式触摸面板的阵列基板的结构示意图，该阵列基板包括：显示区域10和位于显示区域10外围的非显示区域20，非显示区域内设置有GOA(Gate driver on array)单元30和触控驱动电极(TX)走线102，GOA单元30通过横向的栅极驱动信号线104与位于显示区域中的栅线(图未示出)连接，触控驱动信号线102与位于显示区域中的触摸驱动电极(图未示出)连接。由于同处非显示区域，触控驱动信号线102与栅极驱动信号线104之间，以及横向的触控驱动信号线102与竖向的触控驱动信号线102之间，不可避免的会存在交叠区域，交叠区域请参见图1中虚线圈所包围区域，其中虚线圈201包围的是触控驱动信号线102和栅极驱动信号线104的交叠区域，虚线圈202包围的是横向的触控驱动信号线102与竖向的触控驱动信号线102的交叠区域。
请参考图2，图2为图1中的触控驱动信号线与栅极驱动信号线交叠区域的剖面示意图，图2中，101为衬底基板，102为触控驱动信号线，103为栅绝缘层(GI)，104为栅极驱动信号线，105为钝化层，其中，栅绝缘层103的厚度一般只有几千埃，使得交叠的触控驱动信号线102与栅极驱动信号线104之间产生的电容较大，信号耦合作用也非常强，当栅极驱动信号线104传输栅极驱动信号时，交叠区域的栅极驱动信号线104中的栅极驱动信号会部分耦合到触控驱动信号线102当中，导致触控驱动信号的噪声非常大，既影响了信噪比的提升， 也产生了flicker(画面抖动)的现象。
发明内容
有鉴于此，本公开提供一种阵列基板、内嵌式触摸面板和显示装置，以解决现有的位于阵列基板非显示区域的交叠的信号线之间的信号耦合作用强，导致信号线中传输的信号噪声大的问题。
为解决上述技术问题，本公开提供一种阵列基板，包括显示区域和非显示区域，所述显示区域内设置有栅线、数据线、薄膜晶体管和像素电极，所述薄膜晶体管包括：栅极、栅极绝缘层、有源层和源漏极，所述非显示区域中设置有第一信号走线和第二信号走线，所述第一信号走线与所述第二信号走线异层相交，所述第一信号走线与所述栅线同层同材料设置，处于交叠区域的第一信号走线和第二信号走线之间具有所述栅极绝缘层和至少一抬高层。
可选地，所述显示区域内还设置有触控驱动电极，所述第一信号走线为触控驱动信号线，与所述触控驱动电极连接，用于向所述触控驱动电极传输触控驱动信号。
可选地，所述第二信号走线包括：与所述栅线连接的，用于向所述栅线传输栅极驱动信号的栅极驱动信号线。
可选地，所述第二信号走线包括：与所述触控驱动电极连接的触控驱动信号线。
可选地，所述显示区域内还设置有公共电极，所述公共电极所在层与所述数据线所在层之间具有一中间绝缘层，所述第二信号走线包括：断开的源漏金属段以及用于连接断开的源漏金属段的公共电极搭线，所述源漏金属段与所述数据线同层同材料设置，所述公共电极搭线与所述公共电极同层同材料设置，所述公共电极搭线位于所述第一信号走线和所述第二信号走线的交叠区域，所述公共电极搭线与位于所述交叠区域的第一信号走线之间具有所述栅极绝缘层和所述中间绝缘层，所述中间绝缘层作为所述抬高层。
可选地，所述显示区域内还设置有公共电极，述公共电极所在层与所述数据线所在层之间具有一中间绝缘层，所述第二信号走线与所述公共电极同层同材料设置，处于交叠区域的第一信号走线和第二信号走线之间具有所述栅极绝 缘层和所述中间绝缘层，所述中间绝缘层作为所述抬高层。
可选地，所述中间绝缘层可采用树脂材料制成，厚度可达1～2um。
可选地，所述第二信号走线与所述数据线同层同材料设置，处于交叠区域的第一信号走线和第二信号走线之间至少具有栅极绝缘层和一半导体抬高层，所述半导体抬高层与所述薄膜晶体管的有源层同层同材料设置，所述半岛层抬高层作为所述抬高层。
可选地，所述第二信号走线包括：断开的源漏金属段以及用于连接断开的源漏金属段的像素电极搭线，所述源漏金属段与所述数据线同层同材料设置，所述像素电极搭线与所述像素电极同层同材料设置，所述像素电极搭线位于所述第一信号走线和所述第二信号走线的交叠区域，所述像素电极搭线与位于所述交叠区域的第一信号走线之间至少具有所述栅极绝缘层和钝化层，所述钝化层作为所述抬高层。
可选地，所述第二信号走线与所述像素电极同层同材料设置，处于交叠区域的第一信号走线和第二信号走线之间至少具有所述栅极绝缘层和钝化层，所述钝化层作为所述抬高层。
本公开还提供一种内嵌式触摸面板，包括上述阵列基板。
本公开还提供一种显示装置，包括上述内嵌式触摸面板。
本公开的上述技术方案的有益效果如下：
通过在位于阵列基板的非显示区域的两信号走线的交叠区域增加至少一抬高层，以改变处于交叠区域的两信号走线之间的间距，减小两者之间的电容，降低信号耦合作用，提升了信噪比，消除了具有该阵列基板的显示装置的画面抖动现象。
附图说明
图1为现有技术中的内嵌式触摸面板的阵列基板的结构示意图；
图2为图1中的触控驱动信号线与栅极驱动信号线交叠区域的剖面示意图；
图3为本公开实施例的阵列基板的正视图；
图4为本公开实施例一的包含抬高层的阵列基板的剖视图；
图5为本公开实施例二的包含抬高层的阵列基板的剖视图；
图6为本公开实施例三的包含抬高层的阵列基板的剖视图；
图7为本公开实施例四的包含抬高层的阵列基板的剖视图；
图8为本公开实施例五的包含抬高层的阵列基板的剖视图。
具体实施方式
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
根据电容的计算公式C＝εs/d可知，两导线之间的电容的大小，由两者之间的交叠面积s以及两者之间的间距d决定。当交叠面积s固定时，可通过改变两者之间的间距d来改变两者之间的电容。
因此，本公开实施例中，为减小位于阵列基板的非显示区域的两信号走线的交叠区域的电容，在两信号走线的交叠区域增加至少一抬高层，以改变处于交叠区域的两信号走线之间的间距，减小两者之间的电容，降低信号耦合作用，提升了信噪比，消除了具有该阵列基板的显示装置的画面抖动现象。
下面将结合附图和实施例，对本公开的具体实施方式作进一步详细描述。以下实施例用于说明本公开，但不用来限制本公开的范围。
本公开实施例提供一种阵列基板，包括显示区域和非显示区域，所述显示区域内设置有栅线、数据线、薄膜晶体管和像素电极，所述薄膜晶体管包括：栅极、栅极绝缘层、有源层和源漏极，所述非显示区域中设置有第一信号走线和第二信号走线，所述第一信号走线与所述第二信号走线异层相交，所述第一信号走线与所述栅线同层同材料设置，其中，处于交叠区域的第一信号走线和第二信号走线之间具有所述栅极绝缘层和至少一抬高层。
由于同处非显示区域，第一信号走线与第二信号走线之间，不可避免的会 存在交叠区域，如果位于交叠区域的一信号走线与第二信号走线之间的距离较小，会使得两者之间产生较大的电容，信号耦合作用强，导致第一信号走线与第二信号走线中传输的信号噪声大。
为解决该问题，本公开实施例中，在第一信号走线和第二信号走线之间增加至少一抬高层，从而增加位于交叠区域的第一信号走线和第二信号走线之间的距离，减小两者之间的电容，降低信号耦合作用，提升了信噪比，消除了具有该阵列基板的显示装置的画面抖动现象。
本公开实施例中，所述第一信号走线和所述第二信号走线是用于向显示区域传输信号的信号走线，例如向位于所述显示区域内的信号线(栅线或数据线等)或电极(触控驱动电极或公共电极等)等传输信号。
在本公开的一具体实施例中，所述第一信号走线为触控驱动信号线，与位于显示区域内的触控驱动电极连接，用于向所述触控驱动电极传输触控驱动信号。第二信号走线为栅极驱动信号线，与位于显示区域内的栅线连接，用于向所述栅线传输栅极驱动信号。
请参考图3，图3为本公开实施例的阵列基板的正视图，该阵列基板包括：显示区域10和位于显示区域10外围的非显示区域20，非显示区域20内设置有GOA单元30和触控驱动信号线102，GOA单元30通过横向的栅极驱动信号线104与位于显示区域10中的栅线(图未示出)连接，触控驱动信号线102与位于显示区域10中的触摸驱动电极(图未示出)连接。
由于同处非显示区域，触控驱动信号线102与栅极驱动信号线104之间，不可避免的会存在交叠区域，交叠区域请参见图3中虚线圈201包围的区域。如果位于交叠区域的触控驱动信号线102与栅极驱动信号线104之间的距离较小，会使得两者之间产生较大的电容，信号耦合作用强，当栅极驱动信号线104传输栅极驱动信号时，位于交叠区域的栅极驱动信号线104中的栅极驱动信号会部分耦合到触控驱动信号线102当中，导致触控驱动信号的噪声非常大，既影响了信噪比的提升，也产生了画面抖动现象。
因此，本公开实施例中，通过在位于交叠区域的触控驱动信号线102与栅极驱动信号线104之间增加至少一抬高层301，从而增加位于交叠区域的触控驱 动信号线102与栅极驱动信号线104之间的距离，减小两者之间的电容，降低信号耦合作用，提升了信噪比，消除了具有该阵列基板的显示装置的画面抖动现象。
在本公开的另一具体实施例中，所述第一信号走线和第二信号走线均为触控驱动信号线。其中，一个为横向的触控驱动信号线，另一个为竖向的触控驱动信号线。
请再次参考图3，由于同处非显示区域，横向的触控驱动信号线102与竖向的触控驱动信号线102之间，不可避免的会存在交叠区域，交叠区域请参见图3中虚线圈202包围的区域。如果位于交叠区域的两条触控驱动信号线102之间的距离较小，也会使得两者之间产生较大的电容，信号耦合作用强。
因此，本公开实施例中，通过在位于交叠区域的两触控驱动信号线102之间增加至少一抬高层301，从而增加位于交叠区域的两触控驱动信号线102之间的距离，减小两者之间的电容，降低信号耦合作用，提升了信噪比，消除了具有该阵列基板的显示装置的画面抖动现象。
下面举例对本公开实施例中的抬高层的具体设置方式进行说明。
请参考图4，图4为本公开实施例一的包含抬高层的阵列基板的剖视图。该阵列基板包括：衬底基板401，第一信号走线402，栅绝缘层403，第二信号走线404、中间绝缘层405以及钝化层406。
其中，第一信号走线402与所述阵列基板的栅线同层同材料设置。本实施例中第一信号走线402可以为触控驱动信号线。
所述中间绝缘层405为所述阵列基板的公共电极所在层和数据线所在层之间的绝缘层。
所述第二信号走线404可以为栅极驱动信号线，也可以为触控驱动信号线。所述第二信号走线404包括：断开的源漏金属段4041以及用于连接断开的源漏金属段4041的公共电极搭线4042，所述源漏金属段4041与所述阵列基板的数据线同层同材料设置，所述公共电极搭线4042与所述阵列基板的公共电极同层同材料设置，所述公共电极搭线4042通过过孔与源漏金属段4041连接。所述公共电极搭线4042位于所述第一信号走线402和所述第二信号走线404的交叠区域， 所述公共电极搭线4042与位于所述交叠区域的第一信号走线402之间具有栅极绝缘层403和所述中间绝缘层405，所述中间绝缘层405作为抬高层。
请参考图5，图5为本公开实施例二的包含抬高层的阵列基板的剖视图。该阵列基板包括：衬底基板401，第一信号走线402，栅绝缘层403，第二信号走线404、中间绝缘层405以及钝化层406。
其中，第一信号走线402与所述阵列基板的栅线同层同材料设置，本实施例中，第一信号走线402可以为触控驱动信号线。
所述中间绝缘层405为所述阵列基板的公共电极所在层和数据线所在层之间的绝缘层。
所述第二信号走线404可以为栅极驱动信号线，也可以为触控驱动信号线。所述第二信号走线404与所述公共电极同层同材料设置，即第二信号走线404完全采用公共电极所用材料制成，例如ITO等。此时，处于交叠区域的第一信号走线402和第二信号走线404之间具有所述栅极绝缘层403和所述中间绝缘层405，所述中间绝缘层405作为抬高层。
上述两实施例中，所述中间绝缘层405可采用树脂等材料制成，厚度可达1～2um(微米)左右，与现有技术中，第一信号走线402和第二信号走线404的交叠区域仅具有栅极绝缘层的结构相比，本公开实施例中，可使得位于交叠区域的第一信号走线402和第二信号走线404之间的电容降低70％～90％。
上述两实施例中，利用位于第一信号走线402和第二信号走线404交叠区域的中间绝缘层405作为抬高层，抬高位于交叠区域的第一信号走线402和第二信号走线404之间的距离，从而减小两者之间的电容，降低信号耦合作用，提升了信噪比，消除了具有该阵列基板的显示装置的画面抖动现象。
请参考图6，图6为本公开实施例三的包含抬高层的阵列基板的剖视图。该阵列基板包括：衬底基板401，第一信号走线402，栅绝缘层403，半导体抬高层407，第二信号走线404以及钝化层406。
其中，第一信号走线402与所述阵列基板的栅线同层同材料设置，本公开实施例中，第一信号走线402可以为触控驱动信号线。
所述半导体抬高层407与所述阵列基板上的薄膜晶体管的有源层同层同材 料设置。
所述第二信号走线404可以为栅极驱动信号线，也可以为触控驱动信号线。所述第二信号走线404与所述阵列基板的数据线同层同材料设置。即所述第二信号走线404采用源漏金属制成。
处于交叠区域的第一信号走线402和第二信号走线404之间至少具有栅极绝缘层403和半导体抬高层407，所述半导体抬高层407作为抬高层。
本公开实施例中，第二信号走线404全部采用与数据线相同的材料制成，即源漏金属材料，因而，可在不减小第二信号走线404电阻的情况下，增加处于交叠区域的第一信号走线402和第二信号走线404之间的距离。
请参考图7，图7为本公开实施例四的包含抬高层的阵列基板的剖视图。该阵列基板包括：衬底基板401，第一信号走线402，栅绝缘层403，第二信号走线404、中间绝缘层405和钝化层406。
其中，第一信号走线402与所述阵列基板的栅线同层同材料设置，本实施例中，第一信号走线402可以为触控驱动信号线。
中间绝缘层405为位于公共电极所在的层与数据线所在的层之间的绝缘层。
所述第二信号走线404可以为栅极驱动信号线，也可以为触控驱动信号线。所述第二信号走线404包括：断开的源漏金属段4041以及用于连接断开的源漏金属段的像素电极搭线4043，所述源漏金属段4041与所述数据线同层同材料设置，即采用源漏金属制成，所述像素电极搭线4043与所述像素电极同层同材料设置，所述像素电极搭线4043位于所述第一信号走线402和所述第二信号走线404的交叠区域，所述像素电极搭线4043与位于所述交叠区域的第一信号走线402之间、具有所述栅极绝缘层403、中间绝缘层405和钝化层406，所述中间绝缘层405和钝化层406作为所述抬高层。
请参考图8，图8为本公开实施例五的包含抬高层的阵列基板的剖视图。该阵列基板包括：衬底基板401，第一信号走线402，栅绝缘层403，第二信号走线404、中间绝缘层405和钝化层406，
其中，第一信号走线402与所述阵列基板的栅线同层同材料设置，本实施例中，第一信号走线402可以为触控驱动信号线。
中间绝缘层405为位于公共电极所在的层与数据线所在的层之间的绝缘层。
所述第二信号走线404与所述阵列基板的像素电极同层同材料设置，即第二信号走线404完全采用像素电极所用材料制成，例如ITO等。此时，处于交叠区域的第一信号走线402和第二信号走线404之间具有所述栅极绝缘层403、中间绝缘层405和钝化层406，所述中间绝缘层405和钝化层406作为所述抬高层。
上述两实施例中，由于抬高层包括中间绝缘层405和钝化层406，因而位于交叠区域的第一信号走线402和第二信号走线404之间距离更大，两者之间的电容会变得更小。
上述实施例中的包括触控驱动电极的阵列基板中，触控驱动电极通常是与公共电极复用，即将公共电极层分割成多个触控驱动电极和多个公共电极，触控驱动电极和公共电极间隔设置，触控驱动电极在触控时间段被加载触控驱动信号，在显示时间段被加载公共电极信号，复用为公共电极。
本公开实施例还提供一种内嵌式触摸面板，包括上述任一实施例中的阵列基板。
本公开实施例还提供一种显示装置，包括上述内嵌式触摸面板。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (14)

  1. 一种阵列基板，包括显示区域和非显示区域，所述显示区域内设置有栅线、数据线、薄膜晶体管和像素电极，所述薄膜晶体管包括：栅极、栅极绝缘层、有源层和源漏极，所述非显示区域中设置有第一信号走线和第二信号走线，所述第一信号走线与所述第二信号走线异层相交，所述第一信号走线与所述栅线同层同材料设置，其中，处于交叠区域的第一信号走线和第二信号走线之间具有所述栅极绝缘层和至少一抬高层。
  2. 根据权利要求1所述的阵列基板，其中，所述显示区域内还设置有触控驱动电极，所述第一信号走线为触控驱动信号线，与所述触控驱动电极连接，用于向所述触控驱动电极传输触控驱动信号。
  3. 根据权利要求2所述的阵列基板，其中，所述第二信号走线包括：与所述栅线连接的，用于向所述栅线传输栅极驱动信号的栅极驱动信号线。
  4. 根据权利要求2所述的阵列基板，其中，所述第二信号走线包括：与所述触控驱动电极连接的触控驱动信号线。
  5. 根据权利要求3或4所述的阵列基板，其中，所述显示区域内还设置有公共电极，所述公共电极所在层与所述数据线所在层之间具有一中间绝缘层，所述第二信号走线包括：断开的源漏金属段以及用于连接断开的源漏金属段的公共电极搭线，所述源漏金属段与所述数据线同层同材料设置，所述公共电极搭线与所述公共电极同层同材料设置，所述公共电极搭线位于所述第一信号走线和所述第二信号走线的交叠区域，所述公共电极搭线与位于所述交叠区域的第一信号走线之间具有所述栅极绝缘层和所述中间绝缘层，所述中间绝缘层作为所述抬高层。
  6. 根据权利要求3或4所述的阵列基板，其中，所述显示区域内还设置有公共电极，述公共电极所在层与所述数据线所在层之间具有一中间绝缘层，所述第二信号走线与所述公共电极同层同材料设置，处于交叠区域的第一信号走线和第二信号走线之间具有所述栅极绝缘层和所述中间绝缘层，所述中间绝缘层作为所述抬高层。
  7. 根据权利要求5或6所述的阵列基板，其中，所述中间绝缘层可采用树脂材料制成，厚度可达1～2um。
  8. 根据权利要求3或4所述的阵列基板，其中，所述第二信号走线与所述数据线同层同材料设置，处于交叠区域的第一信号走线和第二信号走线之间至少具有栅极绝缘层和一半导体抬高层，所述半导体抬高层与所述薄膜晶体管的有源层同层同材料设置，所述半岛层抬高层作为所述抬高层。
  9. 根据权利要求3或4所述的阵列基板，其中，所述第二信号走线包括：断开的源漏金属段以及用于连接断开的源漏金属段的像素电极搭线，所述源漏金属段与所述数据线同层同材料设置，所述像素电极搭线与所述像素电极同层同材料设置，所述像素电极搭线位于所述第一信号走线和所述第二信号走线的交叠区域，所述像素电极搭线与位于所述交叠区域的第一信号走线之间至少具有所述栅极绝缘层和钝化层，所述钝化层作为所述抬高层。
  10. 根据权利要求9所述的阵列基板，其中，所述像素电极搭线与位于所述交叠区域的第一信号走线之间具有所述栅极绝缘层、中间绝缘层和钝化层，所述中间绝缘层和所述钝化层作为所述抬高层。
  11. 根据权利要求3或4所述的阵列基板，其中，所述第二信号走线与所述像素电极同层同材料设置，处于交叠区域的第一信号走线和第二信号走线之间至少具有所述栅极绝缘层和钝化层，所述钝化层作为所述抬高层。
  12. 根据权利要求11所述的阵列基板，其中，处于交叠区域的第一信号走线和第二信号走线之间具有所述栅极绝缘层、中间绝缘层和钝化层，所述中间绝缘层和所述钝化层作为所述抬高层。
  13. 一种内嵌式触摸面板，包括如权利要求1-2任一项所述的阵列基板。
  14. 一种显示装置，包括如权利要求13所述的内嵌式触摸面板。
PCT/CN2015/087799 2015-02-06 2015-08-21 阵列基板、内嵌式触摸面板和显示装置 WO2016123964A1 (zh)

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