WO2016115826A1 - 非破坏性读出铁电存储器及其制备方法和操作方法 - Google Patents
非破坏性读出铁电存储器及其制备方法和操作方法 Download PDFInfo
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2273—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
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- G11C11/2275—Writing or programming circuits or methods
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
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Definitions
- the present invention relates to the field of ferroelectric memory technology, and in particular to a non-destructive readout ferroelectric memory, and more particularly to a ferroelectric memory based on a non-destructive readout operation of an electrode having a gap and a method and operation for preparing the ferroelectric memory method.
- Ferroelectric Random Access Memory is a method of storing data by using two different polarization orientations ("0" or “1") in a electric field using ferroelectric domains (or “domains”).
- Non-volatile memory which may also be referred to as “ferroelectric memory.”
- the storage medium layer of the ferroelectric memory is a ferroelectric thin film layer having a ferroelectric domain that can be reversed (or referred to as "flip").
- the fastest phase of the domain inversion that can be measured in the laboratory can be achieved. 0.2ns, in fact it can be faster.
- the inversion speed of the domain determines the read and write time of the memory.
- the coercive voltage of the domain inversion determines the read/write voltage of the device, which decreases almost proportionally as the thickness of the film decreases. Therefore, the ferroelectric memory has the advantages of fast data reading speed, low driving voltage and high storage density, and has received extensive attention and rapid development in recent years.
- ferroelectric memories can be mainly divided into two categories: destructive readout (DRO) FRAM and non-destructive readout (NDRO) FeFET.
- DRO destructive readout
- NDRO non-destructive readout
- DRO ferroelectric memory replaces the conventional storage charge capacitance with a ferroelectric capacitor (a capacitor formed by using a ferroelectric thin film layer as a dielectric layer), and uses its polarization inversion to realize data writing and Read. So far, all ferroelectric memories used in the market have adopted this mode of operation, in which a memory cell is constructed with one transistor T and one ferroelectric capacitor C (ie, 1T1C), and the 1T1C memory cell is used as a circuit design. During the read operation, by using the charge integration method, the voltage reading of the reference capacitor in series with the 1T1C memory cell is used to determine whether the ferroelectric thin film layer is inverted, thereby identifying the logic information in the memory cell.
- a ferroelectric capacitor a capacitor formed by using a ferroelectric thin film layer as a dielectric layer
- the voltage reading causes the domain reversal of the ferroelectric thin film layer. Therefore, its disadvantage is that the information reading is destructive, the reliability is poor, and it is necessary to re-read after the reading operation. Write back the original logical information state.
- the area of the ferroelectric capacitor C of the memory cell continues to shrink, and The read charge is proportional to the area of the ferroelectric capacitor C, so the readable charge is also less and less; when the device memory cell size is less than 260 nm, the current readout circuit basically cannot recognize the logic information stored in the memory cell. , seriously hindered the development of ferroelectric memory in the direction of high density.
- the non-destructive readout (NDRO) ferroelectric memory is a ferroelectric field effect transistor (FeFET) that forms a MFS structure by replacing the gate dielectric layer of a conventional MOSFET with a ferroelectric thin film layer.
- the source-drain current I ds can be changed by the control of the polarization direction, the difference can be several orders of magnitude, and the stored information can achieve non-destructive reading at a small voltage. It has high-density integration, high read/write speed, non-destructive read and low power consumption.
- due to the poor performance of the logic information of the device it can only reach several days or several months, while the memory market generally requires not less than 10 years. Therefore, this structure is still in the laboratory research stage and has not been practically applied to memory products.
- the destructive readout (DRO) ferroelectric memory of current commercial applications is mainly read by charge integration of ferroelectric capacitors.
- DRO destructive readout
- ferroelectric memory of current commercial applications is mainly read by charge integration of ferroelectric capacitors.
- it has the disadvantage of destructive reading, and needs to be read after reading.
- Rewriting data accompanied by a large number of erase and rewrite operations, resulting in reduced reliability of the device, affecting the data read speed; and, this read principle limits the ferroelectric capacitor C to scale down, storage
- the density is low, for example, the current commercial application of ferroelectric memory is only 8MB.
- the present invention provides the following technical solutions.
- a non-destructive readout ferroelectric memory comprising a ferroelectric thin film layer and a first electrode layer at least partially disposed on the ferroelectric thin film layer, the first electrode layer being disposed a gap corresponding to the ferroelectric thin film layer and dividing the first electrode layer into at least two portions, wherein polarization directions of the domains in the ferroelectric thin film layer are substantially non-parallel to the iron The normal direction of the electrical film layer;
- ferroelectric thin film layer is configured to partially reverse a domain of the ferroelectric thin film layer corresponding to the gap when the read signal is biased between the two portions of the first electrode layer In turn, a domain wall conductive via that conducts the two portions of the first electrode layer is formed.
- a first electrode layer with the gap is formed on the ferroelectric thin film layer.
- a method of operating a non-destructive readout ferroelectric memory wherein, in a read operation, between the two portions of the first electrode layer
- the read signal in a certain direction is read by reading the magnitude of the current between the two portions to determine whether the domain wall conductive path is successfully established, thereby reading the stored logic information.
- Figure 1 is a cross-sectional view showing the structure of a non-destructive readout ferroelectric memory in accordance with a first embodiment of the present invention.
- FIG. 2 is a top plan view of the upper electrode of the non-destructive readout ferroelectric memory of FIG. 1.
- FIG. 3 is still another top plan view of the upper electrode of the non-destructive readout ferroelectric memory of FIG. 1.
- FIG. 4 is a schematic diagram showing the operation process and operation principle of the write "1" and read “1" of the ferroelectric memory of the embodiment shown in FIG. 1.
- FIG. 5 is a schematic diagram showing the operation process and operation principle of the write "0" and the read “0" of the ferroelectric memory of the embodiment shown in FIG. 1.
- Fig. 6 is a I-V graph when a voltage scanning operation is performed on a read electrode pair of a ferroelectric memory storing logic information "1" according to the first embodiment of the present invention.
- Fig. 7 is a I-V graph when voltage scanning is performed on a pair of read electrodes of a ferroelectric memory storing logic information "0" according to the first embodiment of the present invention.
- Fig. 8 is a view showing an I-V curve of a read current of a fixed read voltage of a read electrode pair of a ferroelectric memory according to a first embodiment of the present invention as a function of a write voltage.
- Figure 9 is a diagram showing the electric field distribution when the read signal is biased on the read electrode pair of the ferroelectric memory of the embodiment of the present invention.
- Figure 10 is a diagram showing the relationship between the on-state read current I and the gap distance d of the ferroelectric memory of the first embodiment of the present invention at a read signal of 4V.
- Figure 11 is a graph showing the relationship between the on-state current and the off-state current with the number of read/write times N of the ferroelectric memory of the first embodiment of the present invention under the read pulse voltages of +/- 4V and 1 kHz.
- Figure 12 is a cross-sectional view showing the structure of a non-destructive readout ferroelectric memory in accordance with a second embodiment of the present invention.
- FIG. 13 is a schematic diagram showing the principle of write operation of the ferroelectric memory of the embodiment shown in FIG.
- Fig. 14 is a schematic view showing the process of the method of manufacturing the ferroelectric memory according to the first embodiment of the present invention.
- Figure 15 is a cross-sectional view showing the structure of a non-destructive readout ferroelectric memory in accordance with a third embodiment of the present invention.
- Figure 16 is a plan view showing the planar structure of the upper electrode of the non-destructive readout ferroelectric memory shown in Figure 15.
- Figure 17 is still another top plan view of the upper electrode of the non-destructive readout ferroelectric memory of Figure 15.
- Fig. 18 is a view showing the principle of operation of writing "1" and writing "0" of the ferroelectric memory of the embodiment shown in Fig. 15.
- Fig. 19 is a view showing the operation procedure and operation principle of the read "1" and read “0" of the ferroelectric memory of the embodiment shown in Fig. 15.
- Fig. 20 is a I-V graph when a voltage scanning operation is performed on a pair of read/write electrodes of a ferroelectric memory in which logic information "0"/"1" stored in the +/- 4 V write voltage of the third embodiment of the present invention is performed.
- Figure 21 is a diagram showing the relationship between the on-state read current I and the gap distance d of the ferroelectric memory of the third embodiment of the present invention at a read signal of 3V.
- Figure 22 is a graph showing the relationship of the read current with the data retention time after the write "1" / "0" operation of the +/- 4 V ferroelectric memory of the third embodiment of the present invention.
- Figure 23 is a schematic view showing the process of preparing a ferroelectric memory according to a third embodiment of the present invention.
- Figure 24 is a cross-sectional view showing the structure of a non-destructive readout ferroelectric memory in accordance with a fourth embodiment of the present invention.
- Fig. 25 is a view showing the principle of operation of writing "1" and writing "0" of the ferroelectric memory of the embodiment shown in Fig. 24.
- Fig. 26 is a view showing the operation procedure and operation principle of the read "1" and read “0" of the ferroelectric memory of the embodiment shown in Fig. 24.
- Figure 27 is a schematic view showing the process of preparing a ferroelectric memory according to a fourth embodiment of the present invention.
- the domain direction or the polarization direction is exemplarily given for clarity of description, but it should be understood that the domain direction or polarization direction of the ferroelectric memory is not limited to the embodiment as shown in the figure. The direction of the out.
- FIG. 1 is a cross-sectional structural view showing a non-destructive readout ferroelectric memory according to a first embodiment of the present invention
- FIG. 2 is a plan view showing a top view of an upper electrode of the nondestructive readout ferroelectric memory shown in FIG. 1.
- a partial cross-sectional structure of a ferroelectric memory 10 is shown, which mainly includes a substrate 101, a lower electrode layer 103, a ferroelectric thin film layer 105, and an upper electrode layer 107, wherein the upper electrode layer 107 is disposed at The ferroelectric thin film layer 105 is in contact with and is in contact therewith, and the upper electrode layer 107 is provided with a gap 109 which is divided into a plurality of portions.
- the gap 109 divides the upper electrode layer 107 into two portions, that is, the read electrode portion 1071 And the read electrode portion 1073, the read electrode portion 1071 and the read electrode portion 1073 constitute a pair of read electrodes, which in this embodiment constitutes the upper electrode layer 107 of this embodiment, which can also be used in the embodiment The write operation of the ferroelectric memory 10.
- the substrate 101 may be various substrate materials commonly used in ferroelectric memories, for example, it may be Si, SrTiO 3 or LiNbO 3 .
- the material selection of the substrate 100 is primarily determined by the lower electrode layer 103 and the ferroelectric thin film layer 105.
- the substrate 101 may be a Si substrate that is easily compatible with a semiconductor CMOS process and contributes to mass production.
- a base material such as SrTiO 3 or LiNbO 3 is selected in accordance with the lattice constant requirements of the lower electrode 101 and the ferroelectric thin film layer 105 to obtain an epitaxial thin film layer excellent in performance.
- the lower electrode layer 103 is grown on the substrate 101, which may be a low resistivity conductive material, for example, it may be selected from a combination of one or more of Pt, SrRuO 3 , LaNiO 3 .
- the thickness of the lower electrode layer 103 may be 50 to 100 nm, for example, 80 nm.
- the lower electrode layer 103 can be formed, but not limited to, by a thin film deposition method such as sputtering, chemical vapor deposition (CVD), pulsed laser deposition (PLD), or the like.
- the ferroelectric thin film layer 105 is formed on the lower electrode layer 103, and may be any ferroelectric material having a suitable domain structure, and may be specifically selected from the following materials: barium ferrite BiFeO 3 , La-doped barium ferrite salt (Bi , La) FeO 3 , lead zirconate titanate (Pb, Zr) TiO 3 or lithium niobate LiNbO 3 ; however, it should be understood that the ferroelectric thin film layer 105 specific ferroelectric material type is not limited, those skilled in the art Any type of ferroelectric material can be used.
- the method of preparing the ferroelectric thin film layer 105 is also not limited, and for example, it can be formed by a thin film deposition method such as sputtering, CVD, or PLD.
- the thickness of the ferroelectric thin film layer 105 may range from greater than or equal to 5 nanometers and less than or equal to 500 nanometers, for example, it may be 20 nm, 30 nm, or 50 nm.
- the read electrode portion 1071 and the read electrode portion 1073 may be formed in this embodiment by patterning the etch gaps 109 through successive metal film layers, although in other embodiments they may be separately patterned.
- the read electrode portion 1071 and the read electrode portion 1073 constitute a pair of read electrodes, where "read” reflects that they have at least a function of a read operation, but the functions of the read electrode portion 1071 and the read electrode portion 1073 are not limited.
- the read electrode portion 1071 and the read electrode portion 1073 constitute the upper electrode 107 of the ferroelectric memory of the embodiment of the present invention.
- the upper electrode layer 107 is located above the ferroelectric thin film layer 105 and is in contact with the ferroelectric thin film layer 105, and the lower electrode layer 102 on the other side of the ferroelectric thin film layer 105 constitutes an electrode pair for writing the memory.
- the read electrode portion 1071 and/or the read electrode portion 1073 may be a low resistivity conductive material, for example, it may be selected from a combination of one or more of Pt, SrRuO 3 , and LaNiO 3 .
- the thickness of the read electrode portion 1071 and/or the read electrode portion 1073 may be 5 to 100 nm, for example, 20 nm.
- the read electrode portion 1071 and/or the read electrode portion 1073 can be formed, but not limited to, by a thin film deposition method such as sputtering, CVD, PLD, or the like.
- the gap 109 is used to achieve relative electrical isolation between the read electrode portion 1071 and the read electrode portion 1073 (the electrical isolation does not include the following case of the domain wall conductive path established during the read operation), and the gap 109 may pass through the metal flat layer electron beam. Processing, nanoimprinting, or other photolithographic methods are obtained, but the method of forming the gap 109 is not limited to the embodiment of the present invention.
- the pitch d of the gap 109 may range from greater than or equal to 2 nanometers and less than or equal to 500 nanometers, more preferably greater than or equal to 5 nanometers and less than or equal to 100 nanometers, for example, may be 10 nanometers, 135 nanometers, 125 nanometers, etc., pitch d
- the shape of the gap 109 is not limited In the shape shown in FIG. 2, in other embodiments, the gap 109 may even be zigzag or the like.
- the width w dimension (i.e., the width dimension of the gap) of the read electrode portion 1071 and the read electrode portion 1073 in the vertical gap direction may be greater than or equal to 5 nanometers and less than or equal to 500 nanometers, for example, 50 nanometers.
- the gap 109 divides the upper electrode layer 107 into four portions, that is, the read electrode portion 1071, the read electrode portion 1073, the read electrode portion 1075, and the read electrode portion 1077, and any two adjacent readings on both sides of the gap 109 are read.
- the electrode portions may each constitute a set of read electrode pairs, for example, the read electrode portion 1073 and the read electrode portion 1077, the read electrode portion 1075 and the read electrode portion 1077; of course, four read electrode portions as shown in FIG. 3 may also be formed. Read the electrode pair.
- the ferroelectric thin film layer 105 is required to satisfy the conditions in which both ferroelectric domains have components in-plane and out-of-plane, that is, have in-plane components (spontaneous polarization of ferroelectric domains is The projection on the film surface) and the out-of-plane component (the projection of the spontaneous polarization of the ferroelectric domain on the surface of the vertical film surface), the ferroelectric thin film layer 105 can form the domains 1051 and 1053 in two directions as shown in FIG. The polarization direction of the domain 1051 is completely opposite to the polarization direction of the domain 1053.
- the domain After the bias is greater than the coercive voltage, the domain is oriented in the direction of the electric field, and therefore, the direction of the bias electric field is opposite to the direction of the original domain.
- the domain 1051 or 1053 When the voltage is greater than the coercive voltage, the domain 1051 or 1053 is inverted.
- the polarization direction of the domains of the ferroelectric thin film layer 105 is substantially non-perpendicular and substantially non-parallel to the normal of the ferroelectric thin film layer 105 (as indicated by the dashed line perpendicular to the ferroelectric thin film layer 105). Specifically, as shown in FIG.
- the in-plane component and the out-of-plane component are placed to implement their write and read operations.
- it can be realized by controlling the crystal orientation of the ferroelectric thin film layer 105.
- a 100 nm thick BiFeO 3 ferroelectric thin film layer 105 can be epitaxially grown on the (001) SrTiO 3 lower electrode layer 103.
- the polarization direction of the domains of the BiFeO 3 ferroelectric thin film layer 105 is along the ⁇ 111> direction.
- the gap 109 may be correspondingly placed in the lower electrode layer 103 based on the manner in which the upper electrode layer 107 is disposed above, and the "on the iron” of claim 1 in the present application "On the electrically thin film layer” is not limited to being understood as being located “above the ferroelectric thin film layer”. Since a gap is provided in the "first electrode layer", the present application can realize a non-destructive readout operation only by the "first electrode layer".
- FIG. 4 is a schematic diagram showing the operation procedure and operation principle of the write "1" and the read “1" of the ferroelectric memory of the embodiment shown in FIG. 1.
- FIG. 5 is a diagram showing the write of the ferroelectric memory of the embodiment shown in FIG. 0" and read “0" operation process and schematic diagram of the operation principle.
- a voltage V write at least larger than the coercive electric field of the ferroelectric thin film layer 105 is applied between the upper electrode layer 107 and the lower electrode layer 103, so that the domain is inverted, thereby realizing The logical information "1" or "0" of the ferroelectric memory 10 is written.
- the information "1" is stored in the polarization direction of the domain 1051 shown in the drawing, and the upper electrode layer 107 and the lower electrode layer 103 are in the operation of writing "1".
- a write signal V write1 larger than the coercive field of the ferroelectric thin film layer 105 is applied between the upper electrode layer 107 and the lower electrode layer 103 biased with a negative voltage to form a negative voltage in the ferroelectric thin film layer 105.
- the electric field E1 in the direction shown in the figure (defined as "+” write voltage at this time), the domains are uniformly flipped to form the domain 1051 of the polarization direction as shown, thereby realizing the writing of the memory logic information "1".
- the storage information "0" is represented by the polarization direction of the electric domain 1053 shown in the drawing, and the upper electrode layer 107 and the lower electrode layer are formed during the operation of writing "0".
- a write signal V write2 larger than the coercive field of the ferroelectric thin film layer 105 is applied between the 103, the upper electrode layer 107 is biased by a negative voltage, and the lower electrode layer 103 is biased with a positive voltage to form a ferroelectric thin film layer 105.
- the electric field E2 in the direction shown (in this case, defined as "-" write voltage), the domains are uniformly flipped to form the domains 1053 of the polarization direction as shown, thereby enabling the writing of the memory logic information "0".
- the specific signal forms of the write signals V write1 and V write2 are not limitative, for example, they may be voltage pulse signals of a certain frequency or the like.
- the read operation principle is completely different from the conventional read operation principle of the ferroelectric memory, in which the lower electrode layer 103 does not need a bias signal during the read operation, it can be left floating, and the read signal Vread is biased at the read. Between the pair of electrodes. Taking the bias electrode portion 1071 and the read electrode portion 1073 as an example, as shown in FIG. 4(b), during the read "1" operation, the read voltage Vread1 is biased between the read electrode portion 1071 and the read electrode portion 1073.
- the read electrode portion 1073 is biased in the forward direction, and the read electrode portion 1071 is biased in the negative direction, thereby forming an electric field E3 (in this case, a "+" read voltage) between the read electrode portion 1073 and the read electrode portion 1071 in the direction shown. Due to the presence of the gap 109, the electric field E3 may locally affect the electrical domain of a portion of the ferroelectric thin film layer corresponding to the gap 109. As the electric field E3 increases, as shown, the corresponding portion below the gap 109 is shown.
- the domains therein are reversed, that is, the domain 1051 corresponding to the gap 109 is partially inverted to form as shown in FIG. 4(b).
- the domain 1051b, the other domains of the ferroelectric thin film layer 105 are substantially unaffected by the electric field E3 (or the electric field E3 is insufficiently affected to cause the domain to reverse), and the domains are not inverted, corresponding to the formation
- the polarization domain of the domain 1051a and the domain 1051b is substantially the same. 1051a opposite to the direction of polarization of the.
- the domain 1051b is inverted by the electric field component in the direction opposite to the polarization direction of the domain 1051a by the electric field E3. Therefore, in the case where the coercive voltage of the ferroelectric thin film layer is known, it can be calculated.
- the minimum voltage at which the domain 1051b is formed that is, the minimum read voltage Vread1 .
- a portion of the ferroelectric thin film layer portion having the electric domain 1051a and the ferroelectric thin film layer portion having the electric domain 1051b that is, a boundary wall or interface between the electric domain 1051a and the electric domain 1051b, thereby generating electrification
- the domain wall or domain boundary 1051c and thus, based on the domain wall conduction mechanism, a conductive path is formed between the read electrode portion 1073 and the read electrode portion 1071, that is, a "domain wall conductive path", correspondingly generating a read current signal I read1 , which is indicated
- the logic signal "1" is read. Therefore, the read operation process is completely different from the charge readout method of the conventional capacitor structure ferroelectric memory, and the manner in which the current reads the logic signal is realized in the embodiment of the present application.
- the read voltage signal V read1 between the read electrode portion 1073 and the read electrode portion 1071 is removed, as shown in FIG. 4(b), the electric field E3 disappears, and at this time, the pole is removed.
- the domain 1051b is reversed to the original polarization direction by the influence of the domain 1051a, that is, the domain 1051b instantaneously disappears, and the domain 101 is substantially restored to the initial state (the state before the read operation).
- the domain wall 1051c also disappears substantially, and the previously formed conductive path also disappears (if the conductive path does not disappear, it does not substantially affect the stored data state).
- the logical information "1" stored by the ferroelectric memory 10 before the read operation does not change after the read operation, realizing non-destructive reading.
- the smaller the volume of the portion of the ferroelectric thin film layer having the electric domain 1051b relative to the portion of the ferroelectric thin film layer having the electric domain 1051a the better, that is, the ferroelectric of the domain which partially inverts during reading.
- the pitch d of the gap 109 is less than or equal to one-half of the thickness of the ferroelectric thin film layer 105, or the pitch d is one quarter of the thickness of the ferroelectric thin film layer 105.
- the read voltage portion V11 is biased between the read electrode portion 1071 and the read electrode portion 1073, and the read electrode portion 1073 is biased in the negative direction and the read electrode portion.
- 1071 is biased forward so that an electric field E4 (in this case, a "-" read voltage) is formed between the read electrode portion 1071 and the read electrode portion 1073 (in this case, a "-" read voltage), and due to the presence of the gap 109, the electric field E4 can be locally The electrical domain of the partial ferroelectric thin film layer corresponding to the gap 109 is affected.
- the domain 1053 corresponding to the gap 109 is partially inverted to form the domain 1053b as shown in FIG. 5(b), and the other portions of the ferroelectric thin film layer 105. Since the domain is substantially unaffected by the electric field E4 (or the electric field E4 has insufficient influence on it to invert the domain), the domain is not inverted, corresponding to the formation of the domain 1053a as shown, and the polarization of the domain 1053b. It is substantially opposite to the polarization direction of the domain 1053a.
- the domain 1053b is inverted by the electric field component in the direction opposite to the polarization direction of the domain 1053a by the electric field E4. Therefore, in the case where the coercive voltage of the ferroelectric thin film layer is known, the formation can be calculated.
- the minimum read voltage V read2 of the domain 1053b is the minimum read voltage V read2 of the domain 1053b .
- the boundary between the ferroelectric thin film layer portion having the electric domain 1053a and the ferroelectric thin film layer portion having the electric domain 1053b that is, the boundary wall or interface between the electric domain 1053a and the electric domain 1053b, generates a charged domain.
- the wall or domain boundary 1053c and thus, based on the domain wall conduction mechanism, generates a conductive path, that is, a "domain wall conductive path" between the read electrode portion 1071 and the read electrode portion 1073, correspondingly generating a read current signal I read2 , which indicates reading The logic signal "0".
- the read voltage signal V read2 between the read electrode portion 1071 and the read electrode portion 1073 is removed , as shown in FIG. 5(b), the electric field E4 disappears, and at this time, in the depolarization field
- the domain 1053b is reversed to the original polarization direction by the influence of the domain 1053a, that is, the domain 1053b disappears instantaneously, and the domain 103 is restored to the initial state (the state before the read operation).
- the 1053c also disappeared, and the conductive channels that were created before disappeared. Therefore, the logical information "0" stored by the ferroelectric memory 10 before the read operation does not change after the read operation, realizing non-destructive reading.
- the principle of reading "1" shown in Fig. 4(b) above is basically the same as the principle of reading "0" shown in Fig. 5(b). It should be understood that in the read “1” operation, the read voltage signal Vread2 as shown in FIG. 5(b) may also be biased between the read electrode portion 1071 and the read electrode portion 1073, thereby reading the electrode portion 1071 and the read electrode portion. A domain wall conductive path is not generated between 1073, and the read current is substantially 0, which indicates that the logic information "1" is read; similarly, in the read "0” operation, between the read electrode portion 1071 and the read electrode portion 1073 It is also possible to bias the read voltage signal V read1 as shown in FIG.
- Fig. 6 is a view showing an I-V chart when a voltage scanning operation is performed on a pair of read electrodes of a ferroelectric memory storing logic information "1" according to the first embodiment of the present invention.
- a “+” scan is performed to form a pair between the read electrode pairs. Similar to the electric field E3 shown in Fig. 4(b), as the electric field increases, the local domains exposed to the surface portion of the gap 109 are reversed, gradually forming 71° or 109° or 180° with the original domain.
- the angle of the electric domain is as shown in Fig. 4(a), such as the 1051b domain, and the charged domain wall or domain boundary is gradually enlarged.
- the voltage is increased to about +2.4V, the current between the pair of read electrodes is sharply increased.
- the ferroelectric thin film layer forms a domain wall conductive path connecting the pair of read electrodes, the read current is "on”; when the read electric field is gradually reduced or disappears, the inverted domain is instantaneously restored to the initial state.
- the domain wall conductive channel is closed.
- an electric field E4 similar to that shown in FIG.
- Fig. 7 is a view showing an I-V curve when voltage scanning is performed on a pair of read electrodes of a ferroelectric memory storing logic information "0" according to the first embodiment of the present invention.
- the electric field E4 shown in Fig. 5(b) Similar to the electric field E4 shown in Fig. 5(b), when the voltage is increased to about -1.8V, the current between the pair of read electrodes is sharply increased, and the surface of the ferroelectric thin film layer is formed to be electrically connected to the domain of the read electrode pair.
- the read current is "on”; when the read electric field is gradually reduced or disappears, the inverted domain will instantaneously return to the initial state, and the domain wall conductive path is closed. Then, the "+” is scanned, and an electric field E4 similar to that shown in FIG. 4(b) is formed between the pair of read electrodes, and the current between the pair of read electrodes is very small, indicating that no domain wall conductive path is formed in the ferroelectric thin film layer. In the "off" state.
- Fig. 8 is a view showing the I-V curve of the read electrode pair of the ferroelectric memory according to the first embodiment of the present invention showing different read/write pulses in its illustration, wherein the read voltage is fixed at -1.5V.
- the on-state voltage that is, the voltage forming the domain wall conduction path
- the off-state voltage that is, the voltage at which the domain wall conduction path is turned off
- It is -1V; when a "+" voltage is applied, a conductive domain wall or domain boundary cannot be formed, and the read current is always off.
- the IV curves of the embodiments shown in FIG. 6 to FIG. 8 above can prove that the ferroelectric memory 10 of the embodiment of the present invention can realize a non-destructive read operation, that is, the domain wall is conductive under the action of the depolarization field. The channel will disappear and you can return to the "off state" from "on”.
- FIG. 9 is a schematic diagram showing electric field distribution when a read signal is biased on a read electrode pair of a ferroelectric memory according to an embodiment of the present invention; wherein, the electric field depth distribution of the ferroelectric thin film layer corresponding to the gap is shown with the voltage of the read signal. Variety.
- the read electrode pair is two Au read electrode portions
- the read signal is applied to the read electrode pair
- the ferroelectric thin film layer is BiFeO 3
- the coercive electric field is 13.45 MV/m
- the read electrode pair, the gap, and the iron The size parameter of the electro-film layer is as shown in FIG. 9; as shown in FIG.
- the electric field depth distribution in the ferroelectric thin film layer at the gap varies with the applied read voltage, and when a read signal of a certain voltage is biased on the pair of read electrodes, The closer to the gap surface (ie, the smaller the depth), the greater the electric field strength, and vice versa, the electric field depth distribution at the gap changes with the applied voltage.
- the electric field at a certain depth from the surface of the gap reaches the coercive field E c required for the inversion of the domain, the domain of the local ferroelectric thin film layer above the depth will be similar to that shown in Fig. 4(b) or Fig. 5 (b) The reversal shown.
- the ferroelectric memory of the embodiment of the present invention can perform a read operation at a relatively small voltage, and the power consumption of the read operation is small.
- FIG. 10 is a schematic diagram showing the relationship between the on-state read current I and the gap distance d of the ferroelectric memory of the first embodiment of the present invention under the read signal of 4 V; wherein the dots represent experimental result values, and the solid line shows theoretical simulation. result.
- V read 4V
- the on-state read current I is proportional to d -2.5 , that is, the smaller the gap d, the on-state read current I can be sharply increased, so that even if the ferroelectric memory is in equal proportion
- the gap of the ferroelectric memory can be correspondingly reduced, and the on-state read current does not decrease, and the logic information read recognition is high. Therefore, it is very advantageous for small size, high density applications.
- the ferroelectric memory of the embodiment of the present invention utilizes a gap provided in the first electrode layer, and an electric field between the gaps during a read operation may partially invert a domain of the ferroelectric thin film layer to establish a domain wall conductive path. Therefore, non-destructive readout of the current mode can be realized; and the on-state current read out when the domain wall conductive path is established can be increased as the pitch of the gap is decreased, and therefore, the ferroelectric memory of the embodiment of the present invention is very Conducive to small size, high density applications.
- Figure 11 shows a ferroelectric memory of the first embodiment of the present invention at frequencies of +/- 4V and 1 kHz.
- FIG. 12 is a cross-sectional view showing the structure of a non-destructive readout ferroelectric memory in accordance with a second embodiment of the present invention.
- the read electrode portion 1071 and the read electrode portion 1073 do not constitute the upper electrode layer of the ferroelectric memory 20, and therefore, in this embodiment, the ferroelectric memory 20 is included in the read electrode portion 1071 and the read electrode portion 1073.
- the ferroelectric memory 20 similarly includes the substrate 101, the lower electrode layer 103, the ferroelectric thin film layer 105, the gap 109, and the like of the ferroelectric memory as shown in FIG. 1, and will not be further described herein. Therefore, the read operation operation and principle of the ferroelectric memory 20 with respect to the ferroelectric memory 10 shown in FIG. 1 are substantially the same.
- FIG. 13 is a schematic diagram showing the principle of write operation of the ferroelectric memory of the embodiment shown in FIG.
- a voltage V write at least greater than the coercive electric field of the ferroelectric thin film layer 105 is applied between the upper electrode layer 230 and the lower electrode layer 103 to cause the domain 1051 or 1053 to be inverted, thereby achieving the The writing of the logical information "1" or "0" of the ferroelectric memory 20.
- the gap 109 may be filled or partially filled with the insulating dielectric layer, or may not be filled with the insulating dielectric layer.
- Fig. 14 is a schematic view showing the process of the method for preparing a ferroelectric memory according to the first embodiment of the present invention.
- a substrate 100 as shown in FIG. 1 or as shown in FIG. 12 is provided.
- the material selection of the substrate 100 is mainly determined by the lower electrode layer 103 and the ferroelectric thin film layer 105.
- the substrate 101 may be a Si substrate that is easily compatible with semiconductor CMOS processes.
- the lower electrode layer 103 is formed on the substrate 100.
- the lower electrode layer 10 may be selected from Pt, SrRuO, 3 LaNbO one kind of combination of three or more; thickness of the lower electrode layer 103 may be 5 ⁇ 100nm, for example, 80nm; lower electrode layer 103 can be formed, but not limited to, by a thin film deposition method such as sputtering, chemical vapor deposition (CVD), pulsed laser deposition (PLD), or the like.
- a ferroelectric thin film layer 105 is formed.
- the ferroelectric thin film layer 105 may be, but not limited to, selected from the group consisting of barium ferrite BiFeO 3 , La-doped barium ferrite salt (Bi, La) FeO 3 , and lead zirconate titanate salt (Pb, Zr)TiO 3 or lithium niobate LiNbO 3 ; the ferroelectric thin film layer 105 can be formed by a thin film deposition method such as sputtering, CVD, PLD or the like.
- a pair of read electrodes are formed on the ferroelectric thin film layer 105.
- the pair of read electrodes is composed of the read electrode portion 1071 and the read electrode portion 1073, and a gap 109 of a nanometer size is formed between the read electrode portion 1071 and the read electrode portion 1073;
- the pair of read electrodes may be selected from Pt, SrRuO 3 , a combination of one or more of LaNiO 3 ;
- the thickness of the read electrode portion 1071 and/or the read electrode portion 1073 may be 5 to 100 nm, for example, 20 nm; the read electrode portion 1071 and/or the read electrode portion 1073 may be It is not limited to being formed by a thin film deposition method such as sputtering, CVD, or PLD.
- Gap 109 can be, but is not limited to, obtained by electron beam processing, nanoimprinting, or other photolithographic methods.
- the ferroelectric memory of the embodiment shown in Fig. 1 is basically formed, and in this embodiment, the read electrode portion 1071 and the read electrode portion 1073 are simultaneously used to form the upper electrode layer of the memory.
- step S950 the insulating dielectric layer 210 as shown in FIG. 12 is covered on the pair of read electrodes.
- step S960 deposition is performed to form an upper electrode layer 230 as shown in FIG. 12, and the upper electrode layer 230 may be a continuous metal layer for forming an upper electrode layer of the ferroelectric memory 20 of the embodiment shown in FIG. Used for the write operation process.
- ferroelectric memory 20 of the embodiment shown in Fig. 12 is basically formed.
- the ferroelectric memory of the embodiment of the present invention has fewer added process steps than the conventional ferroelectric capacitor structure FRAM, and the preparation process is not complicated.
- Figure 15 is a cross-sectional structural view showing a non-destructive readout ferroelectric memory according to a third embodiment of the present invention
- Figure 16 is a plan view showing the top surface of the upper electrode of the non-destructive readout ferroelectric memory shown in Figure 15;
- a partial cross-sectional structure of the ferroelectric memory 30 is shown, which mainly includes a substrate 301, a ferroelectric thin film layer 305, and a first electrode layer 307, which is defined as a read/write electrode layer 307.
- the read/write electrode layer 307 is disposed on and in contact with the ferroelectric thin film layer 305, so that the electric field signal can be biased onto the ferroelectric thin film layer 405.
- the ferroelectric memory 30 of the embodiment of the present invention is different from the conventional ferroelectric memory in that it does not need to be disposed on the opposite electrode layer on the opposite side of the read/write electrode layer 307, and the read/write electrode layer 307 can be used in the ferroelectric memory 30.
- the read operation can also be used to implement a write operation, and the first electrode layer 307 is therefore also referred to as the read/write electrode layer 307.
- the read/write electrode layer 307 is provided with a gap 309 which is divided into a plurality of portions.
- the gap 309 divides the read/write electrode layer 307 into at least two portions, that is, read.
- Write electrode portion 3071 and read/write electrode portion 3073, read/write electrode The portion 3071 and the read/write electrode portion 3073 constitute a pair of read/write electrodes.
- the pair of read/write electrodes mainly constitute the read/write electrode layer 307 of this embodiment.
- the substrate 301 can be various substrate materials commonly used in ferroelectric memories, for example, it can be Si, SrTiO 3 or LiNbO 3 .
- the material selection of the substrate 100 is primarily determined by the combination of the substrate 301 and the ferroelectric thin film layer 305.
- the substrate 301 can be a Si substrate that is easily compatible with semiconductor CMOS processes and contributes to mass production.
- a base material such as SrTiO 3 or LiNbO 3 is selected in accordance with the lattice constant requirement of the ferroelectric thin film layer 305 to obtain an epitaxial thin film layer excellent in performance.
- the ferroelectric thin film layer 305 is formed on the substrate 301, and may be any ferroelectric material having a suitable domain structure, and may be specifically selected from the following materials: barium ferrite BiFeO 3 , La-doped barium ferrite salt (Bi, La) FeO 3 , lead zirconate titanate (Pb, Zr)TiO 3 or lithium niobate LiNbO 3 ; however, it should be understood that the ferroelectric thin film layer 305 is not limited in specific ferroelectric material type, and those skilled in the art can Use any type of ferroelectric material.
- the method of preparing the ferroelectric thin film layer 305 is also not limited, and for example, it can be formed by a thin film deposition method such as sol-gel, sputtering, CVD, or PLD.
- the thickness of the ferroelectric thin film layer 305 may range from greater than or equal to 5 nanometers and less than or equal to 500 nanometers, for example, it may be 20 nm, 30 nm, 50 nm, or 100 nm.
- the read/write electrode portion 3071 and the read/write electrode portion 3073 may be formed by patterning the etch gap 309 through a continuous metal thin film layer in this embodiment. Of course, in other embodiments, they may be separately patterned. In this context, the read and write electrode portion 3071 and the read and write electrode portion 3073 form a pair of read and write electrodes, where "read” reflects that they have at least the function of a read operation, where "write” reflects that they have at least a write operation.
- the read/write electrode portion 3071 and/or the read/write electrode portion 3073 may be a low resistivity conductive material, for example, it may be selected from a combination of one or more of Pt, SrRuO 3 , and LaNiO 3 .
- the thickness of the read/write electrode portion 3071 and/or the read/write electrode portion 3073 may be 5 to 100 nm, for example, 20 nm.
- the read/write electrode portion 3071 and/or the read/write electrode portion 3073 can be formed, but not limited to, by a thin film deposition method such as sputtering, evaporation, CVD, PLD, or the like.
- the gap 309 is used to achieve relative electrical isolation between the read/write electrode portion 3071 and the read/write electrode portion 3073 (the electrical isolation does not include the following case of the domain wall conductive path established during the read operation), and the gap 309 can pass through the metal leveling layer. Electron beam processing, nanoimprinting, or other photolithographic methods are obtained, but the method of forming the gap 309 is not limited to the embodiment of the present invention.
- the pitch d of the gap 309 may range from greater than or equal to 2 nanometers and less than or equal to 500 nanometers.
- the gap 309 can be various nano-sized gaps 305.
- the shape of the gap 309 is not limited to the shape as shown in FIG. 16, and in other embodiments, the gap 309 may even be zigzag or the like.
- the width w dimension (i.e., the width dimension of the gap) of the read/write electrode portion 3071 and the read/write electrode portion 3073 in the vertical gap direction may be greater than or equal to 5 nanometers and less than or equal to 500 nanometers, for example, 50 nanometers.
- Figure 17 is a diagram showing still another top plan view of the upper electrode of the non-destructive readout ferroelectric memory of Figure 15.
- the gap 309 divides the read/write electrode layer 307 into four parts, that is, the read/write electrode portion 3071, the read/write electrode portion 3073, the read/write electrode portion 3075, and the read/write electrode portion 3077, and the gap 309 is adjacent to both sides.
- Any two read/write electrode portions may form a pair of read/write electrode pairs, for example, read/write electrode portion 3073 and read/write electrode portion 3077, read/write electrode portion 3075 and read/write electrode portion 3077; of course, four
- the read/write electrode portions shown in Fig. 17 constitute a pair of read/write electrodes.
- the ferroelectric thin film layer 305 is required to satisfy the condition that the ferroelectric domain has a component in the plane, that is, has an in-plane component (spontaneous polarization of the ferroelectric domain on the film surface) Projection), the ferroelectric thin film layer 305 can form the domains 3051 or 3053 in two directions as shown in FIG. 15, the polarization direction of the domain 3051 is completely opposite to the polarization direction of the domain 3053, and the bias is greater than the coercive voltage. Thereafter, the domains are oriented in the direction of the electric field.
- the domains 3051 or 3053 are inverted.
- the polarization direction of the domains of the ferroelectric thin film layer 305 is substantially non-parallel to the normal to the ferroelectric thin film layer 305 (as indicated by the dashed line perpendicular to the ferroelectric thin film layer 305), or substantially not vertical.
- the read/write electrode layer 307 as shown in FIG.
- it can be realized by controlling the crystal orientation of the ferroelectric thin film layer 305.
- a 100 nm thick BiFeO 3 ferroelectric thin film layer 305 can be epitaxially grown on the (001) SrTiO 3 substrate 301, wherein BiFeO the polarization direction of the electric domain ferroelectric thin film layer 305 is along the ⁇ 111> direction.
- Fig. 18 is a view showing the principle of operation of writing "1" and writing "0" of the ferroelectric memory of the embodiment shown in Fig. 15.
- the logical information "0" is stored in the polarization direction in which the domain 3051 of the ferroelectric thin film layer 305 is located for illustration.
- the write signal Vwrite1 is biased between the read/write electrode portion 3073 of the read/write electrode layer 307 and the read/write electrode portion 3071, that is, read and write.
- the electrode portion 3073 and the read/write electrode portion 3071 constitute an offset write signal Vwrite1 on the pair of read/write electrodes.
- the direction of the write signal is the forward bias of the read/write electrode portion 3073, and the negative direction of the read/write electrode portion 3071, so that they are formed.
- the electric field E1 is substantially in the direction shown in Fig. 18(a).
- the electric field E1 may affect the domain of a portion of the ferroelectric thin film layer corresponding to the gap 309, and the electric field component of the electric field E1 in a direction opposite to the polarization direction of the domain 3051a is greater than that of the domain.
- the domain 3051 is inverted to form the domain 3053a (the domain 3053a is substantially the same as the polarization of the domain 3053 shown in FIG. 15).
- the write signal Vwrite1 Based on the electric field intensity distribution of the ferroelectric thin film layer 305 under the action of the write signal Vwrite1, it can be seen that the larger the write voltage of V write1 is, the deeper the depth of the inverted domain 3053a is.
- the longitudinal direction of the reversed domain 3053a (the direction of the vertical ferroelectric thin film layer 305) can be penetrated through the ferroelectric thin film layer 305 by controlling the magnitude of the voltage of the write signal and/or by the thickness of the ferroelectric thin film layer 305; For example, as shown in FIG. 18(a), under the action of the write signal Vwrite1 having a write voltage of a certain magnitude (for example, +4 V), the domain of the portion of the ferroelectric thin film layer 305 corresponding to the gap 309 (i.e., substantially below the gap 309) The domains in the ferroelectric thin film layer 305 are substantially completely inverted to form the domains 3053a.
- the domains of other portions of the ferroelectric thin film layer 305 are substantially unaffected by the electric field E1 (or the electric field E1 is insufficiently affected to cause the domain to reverse), and the domains are not inverted, correspondingly formed as shown in Fig. 18(a).
- the illustrated domain 3051a that is, a partial domain other than the inversion of the domain 3051, constitutes the domain 3051a.
- the polarization direction of the domain 3053a is substantially opposite to the polarization direction of the domain 3051a, and thus, the boundary wall or interface between the domain 3051a and the domain 3053a, thereby generating a charged domain wall or domain boundary 3054, but domains
- the corresponding conductive channel of wall 3054 will be turned off near the substrate without affecting the read current during the readout process. Therefore, preferably, the substrate 301 may be an insulating substrate formed of various insulating materials.
- the domain wall 3054 is formed through the ferroelectric thin film layer 305 after the "1" operation, that is, the upper surface and the lower surface of the ferroelectric thin film layer 305 can be penetrated, so that the domain 3053a is not
- the domain 3051a is surrounded on all four sides, and the domain 3053a does not automatically return to the state before the write "1" under the depolarization, and the written logic information is saved; the specific shape of the domain wall 3054 is also not affected by the present invention.
- the illustrated shape limitations of the embodiments are limited, for example, the two domain walls 3054 can form a generally cylindrical shape.
- the domain 3053a is inverted by the electric field component in the direction opposite to the polarization direction of the domain 3051a by the electric field E1, the coercive voltage of the ferroelectric thin film layer and the thickness of the ferroelectric thin film layer have been In the known case, the minimum write voltage V write1 forming the domain 3053a can be calculated.
- the read/write electrode portion 3073 and the read/write electrode portion 3071 constitute a read/write electrode pair bias write signal Vwrite2 , write signal Vwrite2 and write signal.
- the direction of V write1 is reversed, in which the read/write electrode portion 3073 is biased in the negative direction, and the read/write electrode portion 3071 is biased in the forward direction so that they form an electric field E2 substantially in the direction shown in Fig. 18(b).
- the electric field E2 may affect the domain of the portion of the ferroelectric thin film layer corresponding to the gap 309, that is, it may affect the domain 3053a as shown in FIG. 18(a), and the electric field E2 is in the domain.
- the domain 3053a When the electric field component in the direction opposite to the polarization direction of 3053a is larger than the coercive voltage at which the domain is inverted, the domain 3053a is inverted, returns to the original or initial polarization direction, and the domain 3051 is uniformly formed. At this time, the logical information is written as "0".
- the domain 3053a can be all inverted and inverted into the domain 3051 by controlling the magnitude of the voltage of the write signal; for example, as shown in FIG.
- the write signal V having a write voltage of a certain magnitude (for example, -4 V)
- the domain 3053a of the portion of the ferroelectric thin film layer 305 corresponding to the gap 309 i.e., the domain 3053a in the ferroelectric thin film layer 305 substantially below the gap 309 is completely rotated to form the domain 3051, and the domain wall 3054 disappears.
- the specific signal form of the write signals V write1 and V write2 is not limited, for example, it may be a voltage pulse signal of a certain frequency or the like.
- Fig. 19 is a view showing the operation process and operation principle of the read “1" and read “0" of the ferroelectric memory of the embodiment shown in Fig. 15.
- the read operation principle is completely different from the conventional read operation principle of the ferroelectric memory, in which the substrate 301 does not need a bias signal during the read operation, it can be left floating, and the read signal Vread is biased at the read and write.
- the following is an example in which the pair of electrodes is biased between the read/write electrode portion 3071 and the read/write electrode portion 3073.
- the read/write electrode portion 3071 and the read/write electrode portion 3073 are biased between the read signals Vread , and the read/write electrode portion 3073 is biased to the forward and read/write electrodes.
- the portion 3071 is biased in the negative direction so that an electric field E3 (defined as "+” read voltage) in the direction shown in the figure is formed between the read/write electrode portion 3073 and the read/write electrode portion 3071, and the electric field is present due to the existence of the gap 309.
- E3 can influence the gap 309 corresponding to the portion of the electrical domain ferroelectric thin film layer is partially due to the absence of an electric field E3 component of the electric field of the ferroelectric domain inversion 3053a, and therefore, regardless of how to read the read voltage V read signal is increased,
- the domain 3053a remains completely unchanged, and a conductive path cannot be formed between the read/write electrode portion 3073 and the read/write electrode portion 3071.
- the read current I read 0, and the read current I read is in the off state (ie, the off state), indicating The logical information "1" is read.
- the read voltage V read signal read is preferably less than the write voltage V write1 write signal, so that, to avoid “over” in the read write operation.
- the read signal V read is removed, since the domains in the ferroelectric thin film layer are substantially unchanged during the above read operation, the read signal V read is removed and the electricity in the ferroelectric thin film layer is removed. The domain does not change.
- the electric field E3 can locally affect the electrical domain of the portion of the ferroelectric thin film layer corresponding to the gap 309. As the electric field E3 increases, as shown in FIG. 19(b), the corresponding partial ferroelectric portion below the gap 309 In the film layer 305, that is, a portion of the surface layer portion exposed to the gap 309, the domains therein are reversed, that is, the domain 3051 is partially inverted to form the domain 3053b as shown in FIG.
- the other domains of the layer 305 are substantially unaffected by the electric field E3 (or the electric field E3 is insufficiently affected to cause their domains to reverse), the domains are not inverted, corresponding to the formation of the domain 3051b as shown,
- the polarization direction of the domain 3053b is substantially opposite to the polarization direction of the domain 3051b.
- the domain 3053b is inverted by the electric field component in the direction opposite to the polarization direction of the domain 3051 by the electric field E3. Therefore, when the coercive voltage of the ferroelectric thin film layer is known, it can be calculated.
- 3053b formed of domains of the minimum read voltage V read.
- the read current I read is in the On state (ie, the ON state), indicating that the logic signal “0” is read.
- the read voltage signal V read between the read/write electrode portion 3073 and the read/write electrode portion 3071 is removed, as shown in FIG. 19(b), the electric field E3 disappears.
- the domain 3053b is reversed to the original polarization direction by the influence of the domain 3051b, that is, the domain 3053b disappears instantaneously, and the domain 301 is substantially restored to the state before the read operation.
- the wall 3058 also substantially disappears, and the previously formed conductive passages also disappear. Therefore, the logical information "0" stored by the ferroelectric memory 30 before the read operation does not change after the read operation, realizing non-destructive reading.
- the read operation performance of the ferroelectric memory can be optimized.
- the pitch d of the gap 309 is smaller or larger than the thickness of the ferroelectric thin film layer 305.
- Figure 20 is a diagram showing the IV of the read/write electrode pair of the ferroelectric memory in which the logic information "0"/"1" is stored at the +/-4V write voltage of the third embodiment of the present invention.
- An electric field E3 similar to that shown in FIG. 19(b) is formed between the pair of electrodes, and as the electric field increases, the local domain of the surface portion exposed to the gap 309 is reversed, and gradually forms, for example, [1, 1, 1].
- the charged domain wall or domain boundary gradually expands Large, when the voltage is increased to about +2.1V, the current between the pair of read and write electrodes is sharply increased, and the surface conduction path of the pair of read/write electrodes is formed in the ferroelectric thin film layer at this time, and the read current is "on" ( On)"; when the electric field between the pair of read and write electrodes continues to increase, when the voltage V increases to about +3.1V, the current I sharply decreases; when the electric field between the pair of read and write electrodes continues to increase, at the voltage V When increased to about +4V, the portions of the ferroelectric thin film layer between the gap 309 and the substrate 301 are all reversed, that is, enlarged by the domain 3053b as shown in FIG.
- the domain 3053a implements reverse writing of the logical information "1", at which time the domain wall 3054 is discontinuous at the substrate 101, so that the current I is substantially reduced to zero, which is in the "off state".
- the domains of the portion of the ferroelectric thin film layer 305 corresponding to the gap 309 penetrate the ferroelectric thin film layer 305 longitudinally, that is, the portion of the ferroelectric thin film layer between the gap 309 and the substrate 301.
- the domains 3053a are all inverted. As shown in FIG. 18(a), the domain 3051a is difficult to generate a depolarization field for the domain 3053a, the polarization direction of the domain 3053a remains unchanged, and the conductive path does not exist. Therefore, the current I is substantially reduced to zero.
- the electric field depth distribution in the ferroelectric thin film layer at the gap changes with the applied read voltage, and a certain voltage is biased on the pair of read/write electrodes.
- the closer to the gap surface ie, the smaller the depth
- the depth distribution of the electric field at the gap changes with the applied voltage.
- the electric field at a certain depth from the surface of the gap reaches the coercive field E c required for the inversion of the domain
- the domain of the local ferroelectric thin film layer above the depth will be similar to that shown in Fig. 18(a) or Fig. 19 (b) The reversal shown. Therefore, the larger the voltage of the read signal, the deeper the domain wall conductive path, the larger the voltage of the write signal, and the more the domain wall 3054 is perpendicular to the surface of the substrate 301.
- the read voltage of the read signal Vread should be such that the depth of the formed domain wall conductive path is smaller than the thickness of the ferroelectric thin film layer, for example, should be smaller than 3.1 similar to that shown in FIG. The voltage point of V. Therefore, the read voltage of the read signal Vread is less than the write voltage of the write signal.
- the ferroelectric memory according to the third embodiment of the present invention utilizes a gap provided in the read/write electrode layer, and an electric field between the gaps during a read operation can partially invert a domain of the ferroelectric thin film layer to establish domain wall conduction.
- the channel therefore, enables non-destructive readout of the current mode; and the on-state current read out when the domain wall conductive path is established can be increased as the pitch of the gap decreases; meanwhile, during the write operation, the gap
- the smaller the pitch the smaller the thickness of the ferroelectric thin film layer, and the lower the write voltage of the write signal. Therefore, the ferroelectric memory of the embodiment of the present invention is very advantageous for small-sized, high-density applications, and it is easy to use the requirement that the device size is continuously scaled down.
- Figure 22 is a diagram showing the relationship of the read current with the data retention time of the ferroelectric memory of the third embodiment of the present invention after the write "1" / "0" operation of +/- 4V.
- the read voltage is +3V
- the read current magnitude is related to the direction of the write signal, that is, related to the domain write direction
- the read current can be substantially constant with time, whether in the "1" state or the "0" state. It remains stable, indicating that the domains written based on the principle as shown in Fig. 18 have good retention characteristics, and the ferroelectric memory 30 has good logic information retention characteristics.
- the gap 309 may be filled or partially filled with the insulating dielectric layer, or may not be filled with the insulating dielectric layer.
- Fig. 23 is a view showing the process of the method for preparing a ferroelectric memory according to a third embodiment of the present invention.
- a substrate 100 as shown in FIG. 15 is provided.
- the material selection of the substrate 100 is mainly determined by the ferroelectric thin film layer 305.
- the substrate 301 may be Si.
- a ferroelectric thin film layer 305 is formed.
- the ferroelectric thin film layer 305 may be, but not limited to, selected from the group consisting of barium ferrite BiFeO 3 , La-doped barium ferrite salt (Bi, La) FeO 3 , and lead zirconate titanate (Pb, Zr)TiO 3 or lithium niobate LiNbO 3 ; the ferroelectric thin film layer 305 can be formed by a thin film deposition method such as sputtering, CVD, PLD or the like.
- a dielectric layer may be formed on the substrate prior to forming the ferroelectric thin film layer 305 on the substrate.
- a pair of read/write electrodes is formed on the ferroelectric thin film layer 305.
- the pair of read/write electrodes is composed of the read/write electrode portion 3071 and the read/write electrode portion 3073, and a nanometer-sized gap 309 is formed between the read/write electrode portion 3071 and the read/write electrode portion 3073;
- the read/write electrode pair can be a combination of one or more selected from the group consisting of Pt, SrRuO 3 , and LaNiO 3 ;
- the thickness of the read/write electrode portion 3071 and/or the read/write electrode portion 3073 may be 5 to 100 nm, for example, 20 nm;
- the read/write electrode portion 3071 And/or the read/write electrode portion 3073 can be formed, but not limited to, by a thin film deposition method such as sputtering, CVD, PLD, or the like.
- Gap 309 can be, but is not limited to, obtained by electron beam processing, nanoimprinting, or other photolith
- an insulating dielectric layer may also be filled in the gap 309.
- the ferroelectric memory of the embodiment shown in Fig. 15 is basically formed, and in this embodiment, the read/write electrode portion 3071 and the read/write electrode portion 3073 are simultaneously used to form the upper electrode layer 307 of the memory.
- the ferroelectric memory of the third embodiment of the present invention does not require the formation of the lower electrode layer in comparison with the conventional FRAM process of the ferroelectric capacitor structure, the structure is very simple, and the preparation process is very simple and low in cost.
- FIG. 24 is a cross-sectional view showing the structure of a non-destructive readout ferroelectric memory in accordance with a fourth embodiment of the present invention.
- a partial cross-sectional structure of the ferroelectric memory 40 is shown, which mainly includes a substrate 401, a ferroelectric thin film layer 405, and a first electrode layer 407, which is defined as a read/write electrode layer 407.
- the read/write electrode layer 307 is disposed on and in contact with the ferroelectric thin film layer 405, so that the electric field signal can be biased onto the ferroelectric thin film layer 405.
- the ferroelectric memory 40 of the embodiment of the present invention is different from the conventional ferroelectric memory in that it does not need to be disposed on the opposite electrode layer on the opposite side of the read/write electrode layer 407, and the read/write electrode layer 407 can be used in the ferroelectric memory 40.
- the read operation can also be used to implement a write operation, and the first electrode layer 407 is therefore also referred to as the read/write electrode layer 407.
- the read/write electrode layer 407 of the ferroelectric memory 40 is also provided with a gap 409 which divides the read/write electrode layer 407 into at least two portions, that is, the read/write electrode portion 4071 and the read/write electrode portion 4073, and the read/write electrode portion 4071.
- the read/write electrode portion 4073 constitutes a pair of read/write electrodes.
- the read/write electrode pair mainly constitutes the read/write electrode layer 407 of this embodiment.
- the read/write electrode layer 407 of the ferroelectric memory 40 is substantially the same as the read/write electrode layer of the ferroelectric memory 30, and the main difference is that the read/write electrode layer 407
- the ferroelectric thin film layer 405 is formed substantially in a cladding manner, wherein at least a portion of the read/write electrode layer 407 is formed on the ferroelectric thin film layer 405, although a portion of the read/write electrode layer 407 is formed directly on the substrate 301.
- the substrate 401 of the ferroelectric memory 40 and the substrate 301 of the ferroelectric memory 30 can be disposed substantially the same.
- a ferroelectric thin film layer 405 is formed over the substrate 401, which can be patterned to form a small area ferroelectric thin film layer 405.
- the ferroelectric thin film layer 405 may be any ferroelectric material having a suitable domain structure, and may be specifically selected from the following materials: barium ferrite BiFeO 3 , La-doped barium ferrite salt (Bi, La) FeO 3 , zirconium and titanium Lead acid salt (Pb, Zr) TiO 3 or lithium niobate LiNbO 3 ; however, it should be understood that the ferroelectric thin film layer 305 is not limited in specific ferroelectric material type, and those skilled in the art can select any kind of ferroelectric material type.
- the method of preparing the ferroelectric thin film layer 305 is also not limited, and for example, it can be formed by a thin film deposition method such as sol-gel, sputtering, CVD, or PLD.
- the thickness of the ferroelectric thin film layer 305 may range from greater than or equal to 5 nanometers and less than or equal to 500 nanometers, for example, it may be 20 nm, 30 nm, 50 nm, or 100 nm.
- the gap 409 is used to achieve relative electrical isolation between the read/write electrode portion 4071 and the read/write electrode portion 4073 (the electrical isolation does not include the following case of the domain wall conductive path established during the read operation), and the gap 409 may pass through the metal leveling layer. Electron beam processing, nanoimprinting, or other photolithographic methods are obtained, but the method of forming the gap 409 is not limited to the embodiment of the present invention.
- the pitch d of the gap 409 may range from greater than or equal to 2 nanometers and less than or equal to 500 nanometers, more preferably greater than or equal to 5 nanometers and less than or equal to 100 nanometers, for example, may be 10 nanometers, 135 nanometers, 125 nanometers, etc., pitch d
- the shape of the gap 409 is not limited to the shape shown in FIG. 24, and in other embodiments, the gap 409 may even be zigzag or the like.
- the width w dimension (i.e., the width dimension of the gap) of the read/write electrode portion 4071 and the read/write electrode portion 4073 in the vertical gap direction may be greater than or equal to 5 nanometers and less than or equal to 500 nanometers, for example, 50 nanometers.
- the ferroelectric thin film layer 405 is required to satisfy the condition that its ferroelectric domain has a component in the plane, that is, has an in-plane component (spontaneous polarization of the ferroelectric domain on the film surface) Projection), the ferroelectric thin film layer 405 can form the domains 4051 or 4053 in two directions as shown in FIG. 24, and the polarization direction of the domain 4051 is completely opposite to the polarization direction of the domain 4053, and the bias is greater than the coercive voltage. Thereafter, the domains are oriented in the direction of the electric field.
- the domains 4051 or 4053 are inverted.
- the polarization direction of the domains of the ferroelectric thin film layer 405 is substantially non-parallel to the normal to the ferroelectric thin film layer 405 (as indicated by the dashed line perpendicular to the ferroelectric thin film layer 405), or substantially not vertical.
- the angle ⁇ between the normal line of the ferroelectric thin film layer 405 and the polarization direction of the domain is not equal to 0 and 180°, for example, 30° ⁇ ⁇ ⁇ 60°.
- ⁇ 45°, such that the domains have in-plane components.
- it can be realized by controlling the crystal orientation of the ferroelectric thin film layer 405.
- a 100 nm thick BiFeO 3 ferroelectric thin film layer 405 can be epitaxially grown on the (001) SrTiO 3 substrate 301, wherein BiFeO the polarization direction of the electric domain ferroelectric thin film layer 305 is along the ⁇ 111> direction.
- Fig. 25 is a view showing the principle of operation of writing "1" and writing "0" of the ferroelectric memory of the embodiment shown in Fig. 24.
- the logical information "1" is stored in the polarization direction in which the domain 3051 of the ferroelectric thin film layer 405 is located for illustration.
- the write signal Vwrite1 is biased between the read/write electrode portion 4073 and the read/write electrode portion 4071 of the read/write electrode layer 407, that is, read and write.
- the electrode portion 4073 and the read/write electrode portion 4071 constitute an offset write signal Vwrite1 on the pair of read/write electrodes, the direction of the write signal is the forward bias of the read/write electrode portion 4073, and the negative direction of the read/write electrode portion 4071, so that they An electric field E1 substantially in the direction shown in Fig. 28(a) is formed.
- E1 can be made sufficiently large to flip the domains 4053 (if any) opposite to the domain 4051 to form a uniform as shown in Fig. 28(a).
- the illustrated domain 4051 completes the write "1" operation.
- the logic information "0" is stored in the polarization direction in which the domain 3053 of the ferroelectric thin film layer 405 is located for illustration.
- FIG. 25 (b) the electrode portion 4073 and the read write signals V write2 bias direction between the portions 4071, a write signal and a write signal V write2 V write1 read and write the opposite electrode, thereby the thin film ferroelectric layer 405 to An electric field E2 of opposite directions is applied.
- E2 can be made sufficiently large to flip the domains 4051 (if any) opposite to the domain 4053 to form a uniform image as shown in FIG. b)
- the domain 4053 is shown to complete the write "0" operation.
- Fig. 26 is a view showing the operation process and operation principle of the read “1" and read “0" of the ferroelectric memory of the embodiment shown in Fig. 24.
- the read operation principle is completely different from the conventional read operation principle of the ferroelectric memory, in which the substrate 401 does not need a bias signal during the read operation, it can be left floating, and the read signal V read is biased in the read and write operation.
- the following is an example in which the pair of electrodes is biased between the read/write electrode portion 4071 and the read/write electrode portion 4073.
- the read/write electrode portion 4071 and the read/write electrode portion 4073 are biased between the read signals Vread , and the read/write electrode portion 4073 is biased to the forward and read/write electrodes.
- the portion 4071 is biased negatively, thereby forming an electric field E3 (in this case, a "+” read voltage) in the direction shown in the figure between the read/write electrode portion 4073 and the read/write electrode portion 4071, and the electric field is not present due to the absence of the electric field E3.
- E3 in this case, a "+” read voltage
- the domain 4051 remains completely unchanged, and the conductive channel cannot be formed between the read/write electrode portion 4073 between the read/write electrode portion 4071.
- the read current I read 0, and the read current I read is in the Off state (ie, the OFF state), indicating that the logic information "1" is read.
- the read signal V read is removed, since the domain in the ferroelectric thin film layer does not substantially change during the above read operation, the read signal V read is removed and the electricity in the ferroelectric thin film layer is removed. The domain does not change.
- the electric field E3 can locally affect the electrical domain of the portion of the ferroelectric thin film layer corresponding to the gap 309. As the electric field E3 increases, as shown in FIG. 26(b), the corresponding partial ferroelectric portion below the gap 409 In the film layer 405, that is, a portion of the surface layer portion exposed to the gap 409, the domains therein are reversed, that is, the domain 4053 is partially inverted to form the domain 4051b as shown in FIG.
- the other domains of the layer 405 are substantially unaffected by the electric field E3 (or the electric field E3 is insufficiently affected to cause their domains to reverse), the domains are not inverted, corresponding to the formation of the domain 4053b as shown,
- the polarization direction of the domain 4051b is substantially opposite to the polarization direction of the domain 4053b.
- the domain 4051b is inverted by the electric field component in the direction opposite to the polarization direction of the domain 4053 by the electric field E3. Therefore, in the case where the coercive voltage of the ferroelectric thin film layer is known, it can be calculated. 4051b formed of domains of the minimum read voltage V read.
- the portion of the ferroelectric thin film layer portion having the electric domain 4053b and the ferroelectric thin film layer portion having the electric domain 4051b that is, the boundary wall or interface between the electric domain 4051b and the electric domain 4053b, thereby generating electrification
- the domain wall or domain boundary 4058 and thus, based on the domain wall conduction mechanism, a conductive path 4058 is formed between the read/write electrode portion 4073 and the read/write electrode portion 4071, that is, a "domain wall conductive path", corresponding to a read current signal I read
- the read current I read is in the On state (ie, the ON state), indicating that the logic signal “0” is read.
- the read voltage signal V read between the read/write electrode portion 4073 and the read/write electrode portion 4071 is removed, and as shown in FIG. 26(b), the electric field E3 disappears.
- the domain 4051b is reversed to the original polarization direction by the influence of the domain 4053b, that is, the domain 4051b disappears instantaneously, and the domain 403 is substantially restored to the state before the read operation.
- the wall 4058 also substantially disappears, and the previously produced conductive passages also disappear. Therefore, the logical information "0" stored by the ferroelectric memory 40 before the read operation does not change significantly after the read operation, achieving non-destructive reading.
- Fig. 27 is a view showing the process of the method for preparing a ferroelectric memory according to a fourth embodiment of the present invention.
- a substrate 400 as shown in FIG. 24 is provided.
- the material selection of the substrate 400 is mainly determined by the ferroelectric thin film layer 405.
- the substrate 401 may be Si.
- a ferroelectric thin film layer is deposited on the substrate 401 and the ferroelectric thin film layer is etched to form a ferroelectric thin film layer 405 as shown in FIG.
- the size of the ferroelectric thin film layer 405 can range from nanometer size.
- a pair of read/write electrodes is formed on the ferroelectric thin film layer 405.
- a metal layer is first deposited to cover the ferroelectric thin film layer 405, and then a gap 409 is formed on the electro thin film layer 405 to form a read/write electrode portion 4071 and a read/write electrode portion 4073 constituting the pair of read/write electrodes.
- the gap 309 can be, but is not limited to, obtained by electron beam processing, nanoimprinting, or other photolithographic methods.
- the ferroelectric memory of the embodiment shown in Fig. 24 is basically formed, and the preparation process is very simple and low in cost.
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Abstract
Description
Claims (31)
- 一种非破坏性读出铁电存储器,包括铁电薄膜层和至少部分设置在所述铁电薄膜层上的第一电极层,其特征在于,所述第一电极层中设置有间隙,所述间隙对应位于所述铁电薄膜层上并将所述第一电极层分为至少两个部分,所述铁电薄膜层中的电畴的极化方向基本不平行所述铁电薄膜层的法线方向;其中,所述铁电薄膜层被配置为在所述第一电极层的所述两个部分之间偏置读信号时、对应所述间隙的部分所述铁电薄膜层的电畴局部被反转而建立有使所述第一电极层的所述两个部分导电的畴壁导电通道。
- 如权利要求1所述的非破坏性读出铁电存储器,其特征在于,还包括与所述第一电极层相对设置的第二电极层,所述铁电薄膜层设置在所述第一电极层和第二电极层之间;其中所述铁电薄膜层中的电畴的极化方向还基本不垂直所述铁电薄膜层的法线方向。
- 如权利要求2所述的非破坏性读出铁电存储器,其特征在于,所述第一电极层中的至少两个部分包括第一读电极部分和第二读电极部分,所述第一读电极部分和第二读电极部分组成读电极对,所述读信号被偏置在所述读电极对上。
- 如权利要求2所述的非破坏性读出铁电存储器,其特征在于,在所述第一电极层和第二电极层之间可操作地偏置写信号以使所述铁电薄膜层中的电畴的极化方向发生统一地翻转。
- 如权利要求2所述的非破坏性读出铁电存储器,其特征在于,还包括第三电极层,所述第三电极层与所述第二电极层相对地设置;其中,在所述第三电极层与所述第二电极层之间可操作地偏置写信号以使所述铁电薄膜层中的电畴的极化方向发生统一地翻转;在所述第三电极层与所述第一电极层之间设置有至少填充所述间隙的绝缘介质层。
- 如权利要求1所述的非破坏性读出铁电存储器,其特征在于,所述第一电极层为读写电极层;其中,所述铁电薄膜层还被配置为在所述读写电极层中的所述两 个部分之间偏置第一方向的写信号时、对应所述间隙的部分所述铁电薄膜层的电畴以纵向地贯穿所述铁电薄膜层的方式被反转。
- 如权利要求6所述的非破坏性读出铁电存储器,其特征在于,在所述读写电极层中的邻接所述间隙的两个部分之间偏置与所述第一方向相反的第二方向的写信号时,使以纵向地贯穿所述铁电薄膜层的方式被反转的所述电畴反转回到初始极化方向。
- 如权利要求6所述的非破坏性读出铁电存储器,其特征在于,配置所述铁电薄膜层的厚度和/或所述间隙的间距以使在偏置预定大小的写电压作用下对应所述间隙的部分所述铁电薄膜层的电畴能够以纵向地贯穿所述铁电薄膜层的方式被反转。
- 如权利要求8所述的非破坏性读出铁电存储器,其特征在于,配置所述铁电薄膜层的厚度和/或所述间隙的间距以使在偏置预定大小的读电压作用下对应所述间隙的部分所述铁电薄膜层的电畴局部能够被反转而建立所述畴壁导电通道。
- 如权利要求1所述的非破坏性读出铁电存储器,其特征在于,所述第一电极层为读写电极层,所述读写电极层中的至少两个部分包括第一读写电极部分和第二读写电极部分,所述第一读写电极部分和第二读写电极部分组成读写电极对,所述写信号或读信号被偏置在所述读写电极对上。
- 如权利要求1或10所述的非破坏性读出铁电存储器,其特征在于,其中,所述铁电薄膜层的电畴统一地翻转为第一极化方向的电畴时,表示存储第一逻辑信息;所述铁电薄膜层的电畴统一地翻转为第二极化方向的电畴时,表示存储第二逻辑信息;所述第一极化方向与所述第二极化方向相反。
- 如权利要求1所述的非破坏性读出铁电存储器,其特征在于,所述铁电薄膜层还被配置为在撤去所述偏置在第一电极层的所述两个部分之间的所述读信号后、被反转的部分所述铁电薄膜层的电畴恢复至初始的极化方向并且所述畴壁导电通道消失。
- 如权利要求1所述的非破坏性读出铁电存储器,其特征在于,在所述读信号的读电压固定的情况下,建立所述畴壁导电通道时的开态电流随所述间隙的间距的减小而增大;和/或所述读信号的读电压越大,对应所述间隙的部分所述铁电薄膜层 的电畴中被反转部分的占比越大;和/或所述读信号的读电压越大,形成的所述畴壁导电通道相对间隙的表面的深度越深。
- 如权利要求1所述的非破坏性读出铁电存储器,其特征在于,所述间隙的间距大于或等于2纳米且小于或等于500纳米,或者大于或等于5纳米且小于或等于100纳米;所述间隙的宽度大于或等于5纳米且小于或等于500纳米。
- 如权利要求1所述的非破坏性读出铁电存储器,其特征在于,所述间隙的间距小于所述铁电薄膜层的厚度或者所述铁电薄膜层的厚度的二分之一。
- 如权利要求1所述的非破坏性读出铁电存储器,其特征在于,所述铁电薄膜层为铁酸铋BiFeO3、掺La的铁酸铋盐(Bi,La)FeO3、锆钛酸铅盐(Pb,Zr)TiO3或者铌酸锂盐LiNbO3。
- 如权利要求1所述的非破坏性读出铁电存储器,其特征在于,所述铁电薄膜层的厚度大于或等于5纳米且小于或等于500纳米。
- 如权利要求1所述的非破坏性读出铁电存储器,其特征在于,所述第一电极层的厚度大于或等于5纳米且小于或等于100纳米。
- 如权利要求1所述的非破坏性读出铁电存储器,其特征在于,通过控制所述铁电薄膜层生长的晶向,以至于所述铁电薄膜层的电畴的极化方向基本不平行所述铁电薄膜层的法线方向。
- 如权利要求1所述的非破坏性读出铁电存储器,其特征在于,所述间隙中被填入或部分填入绝缘介质材料。
- 一种如权利要求1所述的非破坏性读出铁电存储器的制备方法,其特征在于,包括步骤:提供基底;形成铁电薄膜;以及在所述铁电薄膜层上形成带有所述间隙的第一电极层。
- 如权利要求21所述的制备方法,其特征在于,还包括步骤:在形成所述铁电薄膜之前在所述基底上形成第二电极层。
- 如权利要求22所述的制备方法,其特征在于,还包括步骤:在所述第一电极层上沉积绝缘介质层;以及在所述绝缘介质层上形成第三电极层。
- 一种如权利要求1所述的非破坏性读出铁电存储器的操作方法,其特征在于,在读操作时,在所述第一电极层中的所述两个部分之间偏置某一方向的读信号,通过读取该两个部分之间的电流大小以判断是否成功建立所述畴壁导电通道,从而读出存储的逻辑信息。
- 如权利要求24所述的操作方法,其特征在于,所述铁电存储器还包括与所述第一电极层相对设置的第二电极层,所述铁电薄膜层设置在所述第一电极层和第二电极层之间;所述操作方法中,在写操作时,在所述第一电极层和第二电极层之间偏置写信号以使所述铁电薄膜层中的电畴的极化方向发生统一地翻转。
- 如权利要求25所述的操作方法,其特征在于,所述非破坏性读出铁电存储器还包括第三电极层,所述第三电极层与所述第二电极层相对地设置;其中,所述操作方法中,在写操作时,在所述第三电极层与所述第二电极层之间偏置写信号以使所述铁电薄膜层中的电畴的极化方向发生统一地翻转。
- 如权利要求24所述的操作方法,其特征在于,所述第一电极层为读写电极层;所述操作方法中,在写操作时:在读写电极层中的所述两个部分之间偏置第一方向的写信号,对应所述间隙的部分所述铁电薄膜层的电畴以纵向地贯穿所述铁电薄膜层的方式被反转,从而写入第一逻辑信息;在读写电极层中的邻接所述间隙的两个部分之间偏置与所述第一方向相反的第二方向的写信号,使以纵向地贯穿所述铁电薄膜层的方式被反转的所述电畴反转回到初始极化方向,从而写入第二逻辑信息。
- 如权利要求27所述的写操作方法,其特征在于,在铁电薄膜层中,以纵向地贯穿所述铁电薄膜层的方式被反转的所述电畴与未被反转的所述电畴之间形成畴壁,该畴壁贯通所述铁电薄膜层的上表面和下表面。
- 如权利要求24所述的操作方法,其特征在于,撤去所述读信号后,读操作过程中局部被反转的电畴基本回复至读操作前的极化方向,从而所述畴壁导电通道消失。
- 如权利要求24所述的操作方法,其特征在于,所述第一电极层为读写电极层;所述操作方法中,在写操作时:在读写电极层中的所述两个部分之间偏置第一方向的写信号,使所述铁电薄膜层的电畴统一地翻转为第一极化方向,完成对第一逻辑信息的写操作;在读写电极层中的所述两个部分之间偏置与第一方向相反的第二方向的写信号,所述铁电薄膜层的电畴统一地翻转为第二极化方向的电畴,完成对第二逻辑信息的写操作;其中所述第一极化方向与所述第二极化方向相反。
- 如权利要求24所述的操作方法,其特征在于,在所述读信号的读电压固定的情况下,建立所述畴壁导电通道时的开态电流随所述间隙的间距的减小而增大;和/或所述读信号的读电压越大,对应所述间隙的部分所述铁电薄膜层的电畴中被反转部分的占比越大;和/或所述读信号的读电压越大,形成的所述畴壁导电通道相对间隙的表面的深度越深。
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US14/916,889 US9685216B2 (en) | 2015-01-24 | 2015-06-26 | Non-destructive readout ferroelectric memory as well as method of preparing the same and method of operating the same |
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CN108475523B (zh) * | 2016-04-12 | 2021-10-19 | 复旦大学 | 大电流读出铁电单晶薄膜存储器及其制备方法和操作方法 |
CN109378313B (zh) | 2018-09-23 | 2020-10-30 | 复旦大学 | 一种低功耗三维非易失性存储器及其制备方法 |
KR101992953B1 (ko) | 2018-10-12 | 2019-06-27 | 브이메모리 주식회사 | 전기장을 이용한 전류 경로 제어 방법 및 전자 소자 |
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CN112928116B (zh) * | 2019-12-06 | 2024-03-22 | 财团法人工业技术研究院 | 铁电记忆体 |
CN113113536A (zh) * | 2021-04-07 | 2021-07-13 | 中国石油大学(华东) | 一种透明多值非易失阻变存储单元及其制备方法 |
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