WO2016112684A1 - 显示面板及其制备方法、显示装置 - Google Patents

显示面板及其制备方法、显示装置 Download PDF

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Publication number
WO2016112684A1
WO2016112684A1 PCT/CN2015/087334 CN2015087334W WO2016112684A1 WO 2016112684 A1 WO2016112684 A1 WO 2016112684A1 CN 2015087334 W CN2015087334 W CN 2015087334W WO 2016112684 A1 WO2016112684 A1 WO 2016112684A1
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Prior art keywords
insulating layer
sccm
ranges
signal line
layer
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PCT/CN2015/087334
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English (en)
French (fr)
Inventor
李婧
崔玉琳
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US14/905,380 priority Critical patent/US9825063B2/en
Priority to EP15832873.2A priority patent/EP3249687B1/en
Publication of WO2016112684A1 publication Critical patent/WO2016112684A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to a display panel, a preparation method thereof, and a display device.
  • Flat panel displays are currently the most popular displays, which are widely used in electronic products such as computer screens and mobile phones because of their slim profile, power saving and no radiation.
  • the display panel is a main component of the flat panel display. As shown in FIG. 1, the display panel includes a pixel area 1, a fan-out area 2, and a driving circuit area 3.
  • the pixel region 1 includes a plurality of gate lines 11 and data lines 12 arranged to intersect each other, and a first insulating layer 13 (typically a gate insulating layer) is disposed between the gate lines 11 and the data lines 12, and is disposed above the data lines 12.
  • a second insulating layer 14 typically a passivation layer
  • the gate lines 11 and the data lines 12 extend to the fan-out region 2, respectively.
  • the driving circuit region 3 includes a plurality of gate driving chips for supplying gate scanning signals for the respective gate lines 11 and a plurality of source driving chips for supplying data voltage signals to the respective data lines 12.
  • a first via 15 penetrating through the first insulating layer 13 and the second insulating layer 14 is formed over the gate line 11 in the fan-out region 2, and the data line 12 in the fan-out region 2 is formed.
  • a second via 16 penetrating through the second insulating layer 14 is formed above, so that the gate driving chip is electrically connected to the gate line 11 through the first via 15 and the source driving chip is electrically connected to the data line 12 through the second via 16 .
  • the first via 15 and the second via 16 are formed by one patterning process, thereby reducing process steps and cost.
  • the inventors have found that at least the following problems exist in the prior art. Since the first via 15 and the second via 16 are formed by one patterning process, the time taken to form the two vias by etching is the same, but the first via 15 needs to be simultaneously etched first. The insulating layer 13 and the second insulating layer 14 are only formed when the second via 16 is formed The second insulating layer 14 needs to be etched. Therefore, under the same etching time, the opening of the second via hole 16 formed by etching is inevitably caused to be larger than the opening of the first via hole 15 formed by etching.
  • the pin of the gate driving chip is just completely inserted into the first via 15, that is, the pin of the gate driving chip is completely wrapped by the hole wall of the first via 15, in this case, due to the second via
  • the opening of the 16 is large, and when the pin of the source driving chip is inserted into the second via 16, there is no guarantee that the pin of the source driving chip is completely wrapped by the hole wall of the second via 16, resulting in the second via.
  • the data line 12 below the 16 is exposed and will be contaminated by the external environment (water vapor, oxygen, etc.), resulting in poor contact and affecting the display effect.
  • the embodiment of the invention provides a display panel, a preparation method thereof and a display device, which can effectively improve the failure of the driver chip due to the large via hole.
  • the problem of the tube being completely wrapped, thereby preventing the defect caused by the bare signal line under the pin.
  • An embodiment of the present invention provides a display panel including a pixel area and a fan-out area, in which a plurality of first signal lines and a second signal line disposed to cross each other are disposed, the first signal line And the second signal line respectively extending to each fan-out area, a first insulating layer is disposed between the first signal line and the second signal line, and a second is disposed above the second signal line An insulating layer, the second insulating layer includes at least four layers, and a density of each layer structure of the second insulating layer gradually decreases in a direction away from the first insulating layer.
  • each layer structure of the second insulating layer may be the same.
  • the display panel may further include a driving circuit region, each of the fan-out regions being disposed between the pixel region and the driving circuit region, the driving circuit region including a plurality of first driving chips and a plurality of a second driving chip electrically connected to the first signal line through a first via hole penetrating through the first insulating layer and the second insulating layer in the fan-out region, and the second driving chip
  • the second signal line is electrically connected to the second signal line through a second via hole penetrating the second insulating layer in the fan-out region.
  • the inner wall of the second through hole may be stepped, and the position of each step is The boundary position of any two adjacent layer structures of the second insulating layer.
  • the diameter of the circle surrounded by each step may be sequentially increased in a direction away from the first insulating layer.
  • the second insulating layer may include a four-layer structure.
  • each of the four layers of the second insulating layer may range from 10 nm to 50 nm, 50 nm to 500 nm, 50 nm to 500 nm, and 10 nm to 50 nm in a direction away from the first insulating layer.
  • the etching rate range of each of the four-layer structure of the second insulating layer may be 300 nm/min to 600 nm/min, 300 nm/min to 800 nm/min, respectively, in a direction away from the first insulating layer. 300 nm/min to 1000 nm/min, and 300 nm/min to 1500 nm/min.
  • the etching rate of the second layer structure in a direction away from the first insulating layer may be smaller than the etching rate of the third layer structure by 100 nm/min to 700 nm. /min.
  • the first signal line is a gate line
  • the second signal line is a data line
  • the first driving chip is a gate driving chip
  • the second driving chip is a source driving chip.
  • the first signal line is a data line
  • the second signal line is a gate line
  • the first driving chip is a source driving chip
  • the second driving chip is a gate driving chip
  • Another embodiment of the present invention provides a method of preparing a display panel, the display panel including a pixel area and a fan-out area, the method comprising: sequentially forming a first signal line, a first insulating layer, and a second signal on the substrate. a step of the line and the second insulating layer, the first signal line and the second signal line being arranged to intersect each other in the pixel region, and extending from the pixel region to each fan-out region, respectively; forming the The step of forming the second insulating layer includes sequentially forming at least four layers of insulating films having a gradually decreasing density over the substrate on which the second signal lines are formed to form respective layer structures of the second insulating layer.
  • each layer structure of the second insulating layer may be the same.
  • the second insulating layer may include a four-layer structure, and the step of sequentially forming the four-layer structure of the second insulating layer over the substrate on which the second signal line is formed includes: using NH 3 , N 2 , and SiH 4
  • the reaction gas forms the second insulating layer by a chemical vapor deposition process in a temperature range of 250 ° C to 400 ° C.
  • the SiH 4 flow rate ranges from 500 sccm to 1500 sccm
  • the NH 3 flow rate ranges from 2000 sccm to 4000 sccm
  • the N 2 flow rate ranges from 10000 sccm to 30,000 sccm
  • the reaction power ranges from 3000 W to 6000 W.
  • the reaction pressure ranges from 500 mtorr to 1000 mtorr and the reaction pitch ranges from 500 mils to 1500 mils.
  • the SiH 4 flow rate ranges from 1000 sccm to 2000 sccm
  • the NH 3 flow rate ranges from 3000 sccm to 5000 sccm
  • the N 2 flow rate ranges from 10000 sccm to 30,000 sccm
  • the reaction power ranges from 3000 W to 7000 W.
  • the reaction pressure ranges from 800 mtorr to 1500 mtorr and the reaction pitch ranges from 800 mils to 1500 mils.
  • the SiH 4 flow rate ranges from 1000 sccm to 2000 sccm
  • the NH 3 flow rate ranges from 3000 sccm to 7000 sccm
  • the N 2 flow rate ranges from 10000 sccm to 30,000 sccm
  • the reaction power ranges from 3000 W to 7000 W.
  • the reaction pressure ranges from 1000 mtorr to 2500 mtorr and the reaction pitch ranges from 800 mils to 1500 mils.
  • the SiH 4 flow rate ranges from 1000 sccm to 2000 sccm
  • the NH 3 flow rate ranges from 4000 sccm to 8000 sccm
  • the N 2 flow rate ranges from 10,000 sccm to 30,000 sccm
  • the reaction power ranges from 5000 W to 7000 W.
  • the reaction pressure ranges from 2000 mtorr to 3000 mtorr and the reaction pitch ranges from 800 mils to 1500 mils.
  • the display panel may further include a driving circuit region, each of the fan-out regions being disposed between the pixel region and the driving circuit region, the driving circuit region including a plurality of first driving chips and a plurality of a second driving chip, after forming the second insulating layer, the method may further include: forming a first through the first insulating layer and the second insulating layer in the fan-out region by a patterning process a via hole, and a second via hole penetrating the second insulating layer is formed in the fan-out region, such that the first driving chip is electrically connected to the first signal line through the first via hole, The second driving chip is electrically connected to the second signal line through the second via.
  • the inner wall of the second via hole may be stepped, and each step is located at a boundary position of any two adjacent layer structures of the second insulating layer.
  • a diameter of a circle surrounded by each step may be along a distance away from the first insulating layer The direction increases in turn.
  • each of the four layers of the second insulating layer may range from 10 nm to 50 nm, 50 nm to 500 nm, 50 nm to 500 nm, and 10 nm to 50 nm in a direction away from the first insulating layer.
  • the etching rate of each of the four-layer structure of the second insulating layer may be 300 nm/min to 600 nm/min, 300 nm/min to 800 nm/min, 300 nm in the direction away from the first insulating layer. /min to 1000 nm/min, and 300 nm/min to 1500 nm/min.
  • the etching rate of the second layer structure in the four-layer structure of the second insulating layer is smaller than the etching rate of the third layer structure by 100 nm/min to 700 nm/min.
  • Yet another embodiment of the present invention provides a display device including the above display panel.
  • the species is The second insulating layer of the structure will form a via having a stepped inner wall during the etching process, correspondingly reducing the aperture of the via hole to avoid the occurrence of signal line exposure.
  • the above display panel can be prepared, and the process of the method is simple, and thus can be easily realized.
  • the display device includes the above display panel, so that the display device has a high yield and a good display quality.
  • FIG. 1 is a schematic view of a conventional display panel.
  • Figure 2 is a cross-sectional view taken along line A-A' of Figure 1.
  • Figure 3 is a cross-sectional view taken along line B-B' of Figure 1.
  • FIG. 4 is a schematic view of a second insulating layer (passivation layer) of a display panel in accordance with an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a first via forming a display panel in accordance with an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a second via forming a display panel in accordance with an embodiment of the present invention.
  • Embodiments of the present invention provide a display panel including a pixel area and a fan-out area, the pixel area including a plurality of first signal lines and a second signal line disposed to intersect each other, the first signal line and the The second signal lines respectively extend to the fan-out area, a first insulating layer is disposed between the first signal line and the second signal line, and a second insulating layer is disposed above the second signal line, the second insulating layer includes At least a four-layer structure in which the density of each layer structure gradually decreases in a direction away from the first insulating layer.
  • the signal lines on the display panel are electrically connected to the driving chip to provide signals to the pixel units connected to the signal lines through the driving chip, and the signal lines extend from the pixel area to the fan-out area.
  • the corresponding via hole is etched at a position corresponding to the signal line in the fan-out region, and the pin of the driving chip is inserted into the via hole to electrically connect the driving chip to the signal line.
  • these signal lines are not arranged in the same layer, so the depth of the vias is also different.
  • these via holes are usually formed by one patterning process, thereby causing a large aperture of a via hole having a small depth to be large, so that the pin of the driver chip cannot be completely inserted after being inserted into the via hole.
  • the hole wall of the via hole is wrapped, causing a part of the signal line under the via hole to be exposed, which causes the signal line to be defective and affects the display quality.
  • the structure of the insulating layer (second insulating layer) formed with the shallow via holes is changed, that is, the second insulating layer of at least four layers is employed, and each of the second insulating layers is structured
  • the density is gradually reduced in a direction away from the first insulating layer (gate insulating layer).
  • a via hole having a stepped inner wall is formed, and the aperture of the via hole is correspondingly reduced to avoid occurrence of signal line exposure, and can be flexibly changed. Production monitoring size.
  • a display panel includes a pixel area, a fan-out area, and a driving circuit area, and each fan-out area is disposed in a pixel area and a driving circuit. Between the roads. A first signal line and a second signal line intersecting each other are disposed in the pixel region, and the first signal line and the second signal line respectively extend to the respective fan-out areas. A first driving chip and a second driving chip are disposed in the driving circuit region. A first insulating layer is disposed between the layer where the first signal line is located and the layer where the second signal line is located, and a second insulating layer is further disposed above the second signal line.
  • the first driving chip is electrically connected to the first signal line through a first via hole penetrating the first insulating layer and the second insulating layer above the first signal line in the fan-out region, and the second driving chip passes through the fan-out
  • the second via of the second insulating layer above the second signal line in the region is electrically connected to the second signal line.
  • the second insulating layer in the present embodiment includes at least four layers, and the density of each layer structure of the second insulating layer gradually decreases in a direction away from the first insulating layer.
  • the first signal line may be the gate line 11
  • the second signal line may be the data line 12
  • the first driving chip may be a gate driving chip
  • the second The driver chip can be a source driver chip.
  • the first signal line may be the data line 12
  • the second signal line may be the gate line 11
  • the first driving chip may be a source driving chip
  • the second driving chip may be a gate driving chip.
  • the plurality of gate lines 11 and the plurality of data lines 12 disposed to cross each other define a plurality of pixel units, and a gate insulating layer 13 is disposed between the gate lines 11 and the data lines 12 (first insulating layer)
  • a passivation layer 14 (second insulating layer) is further disposed above the data line 12.
  • a first via 15 is etched in the gate insulating layer 13 and the passivation layer 14 formed above the gate line 11 in the fan-out region near the driving circuit region to penetrate the gate insulating layer 13 and the passivation layer 14 in the data.
  • a second via 16 is etched into the passivation layer 14 formed over the line 12 to penetrate the passivation layer 14.
  • the pin of the gate driving chip of the driving circuit region is electrically connected to the gate line 11 through the first via 15 to provide the gate scanning line number for the gate line 11, and the pin of the source driving chip passes the second.
  • Via 16 is electrically coupled to data line 12 to provide a data voltage signal to data line 12.
  • the passivation layer 14 employs at least four layers of structures, that is, the structures 14-1, 14-2, 14-3, and 14-4 shown in FIG. 4, and the density of each layer structure The direction away from the gate insulating layer 13 is decreased, so that the inner wall of the second via hole 16 formed by etching the passivation layer 14 has a circular step shape.
  • the density of two adjacent layer structures is different, so these two
  • the degree of etching of the layer structure is also different, that is, the layer structure having a large density is smaller in aperture formed by etching the layer structure having a smaller density, so that it is easy to form a step at the interface of the boundary of the adjacent layer structure, thereby making
  • the aperture of the inner wall of the second via hole 16 sequentially increases in a direction away from the gate insulating layer 13.
  • the aperture of the pin that the second via hole 16 can actually accommodate should be the smallest aperture in the inner wall of the second via hole 16, that is, the aperture formed by etching the layer having the largest density.
  • the aperture of the second via hole 16 of the present embodiment is smaller than that of the via hole etched by the passivation layer 14 of the prior art structure, so that the source of the second aperture 16 cannot be avoided because the second aperture 16 is too large.
  • the data lines of the driver chip are completely wrapped and the data lines are exposed, thereby avoiding display defects.
  • the passivation layer 14 and the gate insulating layer 13 need to be etched when the first via 15 is formed, and the first via 15 and the second via 16 are formed in the same patterning process. Therefore, the structural change of the passivation layer 14 also has a certain influence on the aperture of the first via hole 15, but it should be understood that the density of the gate insulating layer 13 is the highest density in the passivation layer 14.
  • the one-layer structure that is, the first layer structure 14-1 of the passivation layer 14
  • the aperture of the first via hole 15 depends on the gate insulating layer 13.
  • the increase in the difficulty of etching may result in a decrease in the aperture of the first via 15 formed, but does not affect the gate driving chip.
  • the pin is inserted into the first via 15, and the gate driver chip is pressed down with a slight force, and the pin can be inserted into the first via 15 to be in contact with the gate line.
  • the material of each layer structure of the passivation layer 14 is the same. In this case, when the layer structure of the passivation layer 14 is formed, the process is simple and the production efficiency can be improved. It can be understood that the material of each layer structure of the passivation layer 14 may also be different, as long as the density of each layer structure of the passivation layer is sequentially decreased in the direction away from the gate insulating layer 13, and is blunt
  • the inner wall of the second via hole 16 formed when the layer 14 is etched may be stepped.
  • the material of the passivation layer 14 in this embodiment may be silicon nitride, which may not be limited to such a material, or may be other insulating materials such as silicon oxide.
  • the passivation layer 14 in this embodiment can be passivated by a four-layer structure.
  • Floor It has been experimentally verified that when the passivation layer 14 is formed in a two-layer or three-layer structure in which the density is gradually reduced, after the passivation layer 14 is etched, a via having a stepped inner wall cannot be formed, but the inner wall is formed.
  • the convex curved vias are understood to be such that the vias still do not completely enclose the pins of the driver chip.
  • the passivation layer 14 is formed in a five-layer or more-layer structure, after the passivation layer 14 is etched, although a via having a stepped inner wall is also formed, the structure of the passivation layer 14 is obtained.
  • the passivation layer 14 of the four-layer structure has a simple structure, and at the same time, after etching, a via hole having a stepped inner wall can be formed, and the pin of the driving chip can be completely wrapped, so that the bare data existing in the prior art can be solved. Bad line problem.
  • the preparation of the four-layer passivation layer 14 is easy to implement, saving preparation time and improving production efficiency.
  • the thickness of the four-layer structure ranges from 10 nm to 50 nm, 50 nm to 500 nm, and 50 nm, respectively. 500 nm, and 10 nm to 50 nm.
  • the thickness range does not constitute a limitation on the embodiment, and the thickness range may be specifically set according to specific conditions.
  • the second layer structure 14-2 and the The thickness of the three-layer structure 14-3 is not much different, and the thicknesses of the first layer structure 14-1 and the fourth layer structure 14-4 are both smaller than the thicknesses of the second layer structure 14-2 and the third layer structure 14-3.
  • the second via hole 16 is formed by etching, it is easier to form a step in the inner wall of the second via hole 16, as shown in FIG.
  • the etching rate range for the four-layer structure is 300 nm/min to 600 nm/min, respectively. 300 nm/min to 800 nm/min, 300 nm/min to 1000 nm/min, and 300 nm/min to 1500 nm/min. It can be understood that the density of each layer structure can be characterized by the etch rate for each layer structure of the passivation layer 14, and the etch rate of the layer having a higher density is lower, otherwise the reverse.
  • the inner wall of the second via hole 16 formed by etching the passivation layer 14 can be more easily formed into an annular step.
  • the etching rate of the second layer structure 14-2 of the passivation layer 14 is smaller than the etching rate of the third layer structure 14-3 by 100 nm/min to 700 nm/min, that is, the second layer structure 14-2
  • a perfect annular step can be formed on the inner wall of the second via hole 16 formed by etching the passivation layer 14.
  • the diameter of the annular (circular) step formed at the position of the interface of the second layer structure 14-2 and the third layer structure 14-3 of the passivation layer 14 can be regarded as the monitored The aperture of the two vias 16.
  • a method of fabricating a display panel wherein the display panel can be the display panel described in the above embodiments.
  • the display panel includes a pixel area, a fan-out area, and a driving circuit area. Each of the fan-out regions is disposed between the pixel region and the driving circuit region.
  • the pixel area includes a plurality of first signal lines and a second signal line disposed to intersect each other, and the first signal line and the second signal line respectively extend to a fan-out area.
  • a first insulating layer is disposed between the first signal line and the second signal line, and a second insulating layer is disposed over the second signal line, the second insulating layer includes at least four layers of structures, each of which is structured The density gradually decreases in a direction away from the first insulating layer.
  • the driving circuit region includes a plurality of first driving chips and a plurality of second driving chips, and the first driving chip passes through a first via hole penetrating through the first insulating layer and the second insulating layer in the fan-out region
  • the first signal line is electrically connected
  • the second driving chip is electrically connected to the second signal line through a second via hole penetrating through the second insulating layer in the fan-out region.
  • the second insulating layer includes a four-layer structure, and the materials of the four-layer structure are the same, and the material may be silicon nitride.
  • the method for preparing the display panel of this embodiment includes the following steps 1 to 3.
  • the first signal line pattern and the first insulating layer are formed on the substrate.
  • the substrate is made of a transparent material such as glass and is pre-cleaned.
  • a sputtering method for example, a thermal evaporation method, a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, a Low Pressure Chemical Vapor Deposition (LPCVD) method, and an atmospheric pressure chemistry are used on a substrate.
  • Atmospheric Pressure Chemical Vapor Deposition A first metal thin film is formed by an APCVD) method or an Electron Cyclotron Resonance Chemical Vapor Deposition (ECR-CVD) method, and a patterning process of exposing, developing, etching, and stripping the first metal thin film is performed. The pattern including the first signal line is formed, and then the first insulating layer is formed by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition or sputtering.
  • the pattern of the second signal line and the second insulating layer are formed by a patterning process.
  • the method of forming the second signal line is the same as the method of forming the first signal line, and will not be described in detail herein.
  • the second insulating layer is formed in a different manner from the first insulating layer. Taking the case where the material of the second insulating layer is silicon nitride, the step of forming the second insulating layer specifically includes: passing the reaction gas of NH 3 , N 2 and SiH 4 through the chemistry at a temperature ranging from 250 ° C to 400 ° C. The vapor deposition process sequentially forms the first layer to the fourth layer of the second insulating layer, and the specific process conditions are as follows.
  • the SiH 4 flow rate ranges from 500 sccm to 1500 sccm
  • the NH 3 flow rate ranges from 2000 sccm to 4000 sccm
  • the N 2 flow rate ranges from 10000 sccm to 30,000 sccm
  • the reaction power ranges from 3000 W to 6000 W.
  • the reaction pressure ranges from 500 mtorr to 1000 mtorr and the reaction pitch ranges from 500 mils to 1500 mils.
  • the SiH 4 flow rate ranges from 1000 sccm to 2000 sccm
  • the NH 3 flow rate ranges from 3000 sccm to 5000 sccm
  • the N 2 flow rate ranges from 10000 sccm to 30,000 sccm
  • the reaction power ranges from 3000 W to 7000 W.
  • the reaction pressure ranges from 800 mtorr to 1500 mtorr and the reaction pitch ranges from 800 mils to 1500 mils.
  • the SiH 4 flow rate ranges from 1000 sccm to 2000 sccm
  • the NH 3 flow rate ranges from 3000 sccm to 7000 sccm
  • the N 2 flow rate ranges from 10000 sccm to 30,000 sccm
  • the reaction power ranges from 3000 W to 7000 W.
  • the reaction pressure ranges from 1000 mtorr to 2500 mtorr and the reaction pitch ranges from 800 mils to 1500 mils.
  • the SiH 4 flow rate ranges from 1000 sccm to 2000 sccm
  • the NH 3 flow rate ranges from 4000 sccm to 8000 sccm
  • the N 2 flow rate ranges from 10,000 sccm to 30,000 sccm
  • the reaction power ranges from 5000 W to 7000 W.
  • the reaction pressure ranges from 2000 mtorr to 3000 mtorr and the reaction pitch ranges from 800 mils to 1500 mils.
  • the four-layer structure of the second insulating layer can be formed by adjusting the flow rate of each gas, controlling the reaction power, the pressure, and the spacing.
  • the SiH 4 flow rate ranges from 1000 sccm to 2000 sccm
  • the NH 3 flow rate ranges from 2000 sccm to 8000 sccm
  • the N 2 flow rate ranges from 10,000 sccm to 30,000 sccm
  • the reaction power ranges from 3000 W to 7000 W
  • the reaction pressure ranges from 500 mtorr to 3000 mtorr
  • the reaction pitch ranges. It is from 500 mils to 1500 mils.
  • each layer structure forming the second insulating layer is different, and only the four-layer structure with different densities can be formed.
  • Methods of controlling the gas flow rate, reaction power, reaction pressure, and reaction pitch to form a film layer having the same material and different densities are known to those skilled in the art, and thus will not be described in detail herein.
  • the thickness of each layer structure ranges from 10 nm to 50 nm, 50 nm to 500 nm, 50 nm to 500 nm, and 10 nm to 50 nm, respectively, but the thickness range does not constitute a limitation on the embodiment. , can also be set according to the specific circumstances. It should be noted that after a plurality of tests, when the thickness of the first layer structure and the fourth layer structure of the second insulating layer are not much different, the thicknesses of the second layer structure and the third layer structure are not much different.
  • the thicknesses of the first layer structure and the fourth layer structure are both smaller than the thicknesses of the second layer structure and the third layer structure, in the step of subsequently forming the second via hole by etching, it is easier to be in the inner wall of the second via hole Form a step in the middle.
  • the etching rate for each layer structure ranges from 300 nm/min to 600 nm/min, 300 nm/min to 800 nm/min, 300 nm/min to 1000 nm/min, and 300 nm, respectively. /min to 1500nm/min.
  • the density of each layer structure can be characterized by the etch rate of each layer structure of the second insulating layer, and the etch rate of the layer having a higher density is lower, otherwise the reverse.
  • the etching rate of the second layer structure of the second insulating layer is smaller than the etching rate of the third layer structure by 100 nm/min to 700 nm/min, that is, the density of the second layer structure is
  • the diameter of the annular step formed at the position of the second layer structure and the third layer structure interface of the second insulating layer in the subsequent step can be regarded as the aperture of the second via hole to be monitored.
  • a pattern including the first via hole and the second via hole is formed by a patterning process.
  • an organic film is formed over the fourth layer structure of the second insulating layer by a coating (including spin coating) method.
  • the organic film is formed using an organic resin including an acrylic film-forming resin, a phenol resin film-forming resin, a vinyl polymer film-forming resin, or a polyimide film-forming resin.
  • a first via hole penetrating the first insulating layer and the second insulating layer and connecting the first signal line and the first driving chip, and penetrating the second insulating layer and for using the second signal line by a patterning process a second via connected to the second driver chip.
  • the position of each step is the boundary position of any two adjacent layer structures in the second insulating layer, and the diameter of the circle surrounded by each step increases in a direction away from the first insulating layer.
  • the second insulating layer having a four-layer structure is taken as an example, and the second insulating layer having four or more layers can be prepared in the same manner, as long as the gas flow rate is controlled accordingly. , reaction power, reaction pressure and reaction spacing can be achieved.
  • the formed second insulating layer structure includes at least four layers, so that an annular step must be formed on the inner wall of the second via hole formed by etching the second insulating layer. .
  • the monitoring aperture of the second via hole in the second insulating layer of the embodiment will change, that is, the monitoring aperture of the second via hole will be reduced, so that the second insulating layer can be
  • the pin of the second driving chip inserted into the second via hole is completely wrapped to prevent the external environment from polluting the pin of the second driving chip and the second signal line below the second via hole, thereby avoiding the occurrence of defects.
  • a display device including the display panel described in the above embodiments is provided.
  • the display device of this embodiment has better performance and higher yield.
  • the display device provided in this embodiment may be any mode liquid crystal display device such as TN, ADS, IPS, LTPS.
  • the display device may be any product or component having a display function such as a liquid crystal panel, a liquid crystal television, a display, a mobile phone, a navigator or the like.

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Abstract

一种显示面板及其制备方法、显示装置。所述显示面板包括像素区（1）和扇出区（2），在所述像素区（1）中设置有多条相互交叉设置的第一信号线（11）和第二信号线（12），所述第一信号线（11）和所述第二信号线（12）分别延伸至扇出区（2），在第一信号线（11）和第二信号线（12）之间设置有第一绝缘层（13），在第二信号线（12）上方设置有第二绝缘层（14），所述第二绝缘层（14）包括至少四层结构，并且所述第二绝缘层（14）的每层结构的致密度沿远离所述第一绝缘层（13）的方向逐渐降低。在所述第二绝缘层（14）中通过刻蚀形成的过孔的尺寸较现有技术中形成的过孔而言有所减小。

Description

显示面板及其制备方法、显示装置 技术领域
本发明属于显示技术领域，具体涉及显示面板及其制备方法、显示装置。
背景技术
平板显示器为目前主要流行的显示器，其具有外形轻薄、省电以及无辐射等特点而被广泛地应用于电脑屏幕、移动电话等电子产品上。
显示面板是平板显示器的主要组成部分，如图1所示，显示面板包括像素区1、扇出区2以及驱动电路区3。像素区1包括多条相互交叉设置的栅线11和数据线12，在栅线11和数据线12之间设置有第一绝缘层13(通常为栅极绝缘层)，在数据线12上方设置有第二绝缘层14(通常为钝化层)，并且栅线11和数据线12分别延伸至扇出区2。驱动电路区3包括用于为各栅线11提供栅极扫描信号的多个栅极驱动芯片以及用于为各数据线12提供数据电压信号的多个源极驱动芯片。如图2和3所示，在扇出区2中的栅线11上方形成有贯穿第一绝缘层13和第二绝缘层14的第一过孔15，在扇出区2中的数据线12上方形成有贯穿第二绝缘层14的第二过孔16，使得栅极驱动芯片通过第一过孔15与栅线11电连接，源极驱动芯片通过第二过孔16与数据线12电连接。通常第一过孔15和第二过孔16是采用一次构图工艺形成的，因此可以减少工艺步骤，并且节约成本。
发明人发现现有技术中至少存在如下问题。由于第一过孔15和第二过孔16是采用一次构图工艺形成的，因此通过刻蚀形成两个过孔所消耗的时间相同，但是在形成第一过孔15时需要同时刻蚀第一绝缘层13和第二绝缘层14，而在形成第二过孔16时则只 需刻蚀第二绝缘层14。因此，在相同的刻蚀时间的条件下，必然导致刻蚀形成的第二过孔16的开口大于刻蚀形成的第一过孔15的开口。若栅极驱动芯片的管脚刚好完全插入到第一过孔15中，即，栅极驱动芯片的管脚被第一过孔15的孔壁完全包裹，在此情况下，由于第二过孔16的开口较大，在将源极驱动芯片的管脚插入第二过孔16时，则无法保证源极驱动芯片的管脚被第二过孔16的孔壁完全包裹，导致第二过孔16下方的数据线12裸露而将被外界环境(水汽、氧气等)污染，从而造成接触不良，影响显示效果。
发明内容
为了解决现有的显示面板的扇出区的过孔中存在的问题，本发明实施例提供了显示面板及其制备方法和显示装置，其能够有效改善由于过孔较大造成无法将驱动芯片的管脚完全包裹的问题，进而防止管脚下方的信号线裸露造成的不良。
本发明一个实施例提供一种显示面板，其包括像素区和扇出区，在所述像素区中设置有多条相互交叉设置的第一信号线和第二信号线，所述第一信号线和所述第二信号线分别延伸至各个扇出区，在所述第一信号线和所述第二信号线之间设置有第一绝缘层，在所述第二信号线上方设置有第二绝缘层，所述第二绝缘层包括至少四层结构，并且所述第二绝缘层的每层结构的致密度沿远离所述第一绝缘层的方向逐渐降低。
所述第二绝缘层的每层结构的材料可以相同。
所述显示面板还可以包括驱动电路区，所述扇出区的每一个设置在所述像素区和所述驱动电路区之间，所述驱动电路区包括多个第一驱动芯片和多个第二驱动芯片，所述第一驱动芯片通过贯穿所述扇出区中的第一绝缘层和第二绝缘层的第一过孔与所述第一信号线电连接，并且所述第二驱动芯片通过贯穿所述扇出区中的第二绝缘层的第二过孔与所述第二信号线电连接。
所述第二过孔的内壁可以呈台阶状，每节台阶所在位置为所 述第二绝缘层的任意两相邻层结构的交界位置。
每节台阶所围成的圆形的直径可以沿远离所述第一绝缘层的方向依次增大。
所述第二绝缘层可以包括四层结构。
所述第二绝缘层的四层结构中的每层结构的厚度范围在远离所述第一绝缘层方向上可以依次为10nm至50nm、50nm至500nm、50nm至500nm、和10nm至50nm。
对所述第二绝缘层的四层结构中的每层结构的刻蚀速率范围在远离所述第一绝缘层方向上可以依次为300nm/min至600nm/min、300nm/min至800nm/min、300nm/min至1000nm/min、和300nm/min至1500nm/min。
在所述第二绝缘层的四层结构中，对沿远离所述第一绝缘层的方向上的第二层结构的刻蚀速率可以比第三层结构的刻蚀速率小100nm/min至700nm/min。
所述第一信号线为栅线，所述第二信号线为数据线，所述第一驱动芯片为栅极驱动芯片，所述第二驱动芯片为源极驱动芯片。
可替代地，所述第一信号线为数据线，所述第二信号线为栅线，所述第一驱动芯片为源极驱动芯片，所述第二驱动芯片为栅极驱动芯片。
本发明另一个实施例提供一种制备显示面板的方法，所述显示面板包括像素区和扇出区，所述方法包括：依次在基底上形成第一信号线、第一绝缘层、第二信号线和第二绝缘层的步骤，所述第一信号线和所述第二信号线在所述像素区中布置为相互交叉，并且分别从所述像素区延伸至各个扇出区；形成所述第二绝缘层的步骤包括：在形成有所述第二信号线的基底上方，依次形成至少四层致密度逐渐降低的绝缘薄膜，以形成第二绝缘层的各层结构。
所述第二绝缘层的每层结构的材料可以相同。
所述第二绝缘层可以包括四层结构，在形成有所述第二信号线的基底上方依次形成所述第二绝缘层的四层结构的步骤包括： 利用NH3、N2和SiH4的反应气体在250℃至400℃的温度范围内通过化学气相沉积工艺形成所述第二绝缘层。当形成所述第二绝缘层的第一层结构时，SiH4流量范围为500sccm至1500sccm，NH3流量范围为2000sccm至4000sccm，N2流量范围为10000sccm至30000sccm，反应功率范围为3000W至6000W，反应压强范围为500mtorr至1000mtorr，反应间距范围为500mils至1500mils。当形成所述第二绝缘层的第二层结构时，SiH4流量范围为1000sccm至2000sccm，NH3流量范围为3000sccm至5000sccm，N2流量范围为10000sccm至30000sccm，反应功率范围为3000W至7000W，反应压强范围为800mtorr至1500mtorr，反应间距范围为800mils至1500mils。当形成所述第二绝缘层的第三层结构时，SiH4流量范围为1000sccm至2000sccm，NH3流量范围为3000sccm至7000sccm，N2流量范围为10000sccm至30000sccm，反应功率范围为3000W至7000W，反应压强范围为1000mtorr至2500mtorr，反应间距范围为800mils至1500mils。当形成所述第二绝缘层的第四层结构时，SiH4流量范围为1000sccm至2000sccm，NH3流量范围为4000sccm至8000sccm，N2流量范围为10000sccm至30000sccm，反应功率范围为5000W至7000W，反应压强范围为2000mtorr至3000mtorr，反应间距范围为800mils至1500mils。
所述显示面板还可以包括驱动电路区，所述扇出区的每一个设置在所述像素区和所述驱动电路区之间，所述驱动电路区包括多个第一驱动芯片和多个第二驱动芯片，在形成所述第二绝缘层之后，所述方法还可以包括：通过构图工艺，在所述扇出区中形成贯穿所述第一绝缘层和所述第二绝缘层的第一过孔，并且在所述扇出区中形成贯穿所述第二绝缘层的第二过孔，使得所述第一驱动芯片通过所述第一过孔与所述第一信号线电连接，所述第二驱动芯片通过所述第二过孔与所述第二信号线电连接。
所述第二过孔的内壁可以呈台阶状，每节台阶所在位置为所述第二绝缘层的任意两相邻层结构的交界位置。
每节台阶所围成的圆形的直径可以沿远离所述第一绝缘层的 方向依次增大。
所述第二绝缘层的四层结构中的每层结构的厚度范围在远离所述第一绝缘层方向上可以依次为10nm至50nm、50nm至500nm、50nm至500nm、和10nm至50nm。
所述第二绝缘层的四层结构中的每层结构的刻蚀速率范围在远离所述第一绝缘层方向上可以依次为300nm/min至600nm/min、300nm/min至800nm/min、300nm/min至1000nm/min、和300nm/min至1500nm/min。
对所述第二绝缘层的四层结构中的第二层结构的刻蚀速率比第三层结构的刻蚀速率小100nm/min至700nm/min。
本发明又一实施例提供一种显示装置，其包括上述的显示面板。
在本发明实施例的显示面板中，由于采用至少四层结构的第二绝缘层，并且第二绝缘层的每层结构的致密度沿远离所述第一绝缘层的方向逐渐降低，因此该种结构的第二绝缘层在刻蚀过程中将形成内壁为台阶状的过孔，相应地减小了过孔的孔径，以避免出现信号线暴露的情况产生。
在本发明实施例的制备显示面板的方法，可以制备出上述的显示面板，同时该方法的工艺简单，从而容易被实现。
本发明实施例的显示装置包括上述的显示面板，因此该显示装置的良率较高，显示品质较好。
附图说明
图1为现有的显示面板的示意图。
图2为沿图1的A-A′线截取的剖视图。
图3为沿图1的B-B′线截取的剖视图。
图4为根据本发明的实施例的显示面板的第二绝缘层(钝化层)的示意图。
图5为根据本发明的实施例的形成显示面板的第一过孔的示意图。
图6为根据本发明的实施例的形成显示面板的第二过孔的示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
本发明实施例提供了一种显示面板，其包括像素区和扇出区，所述像素区包括多条相互交叉设置的第一信号线和第二信号线，所述第一信号线和所述第二信号线分别延伸至扇出区，在第一信号线和第二信号线之间设置有第一绝缘层，在第二信号线上方设置有第二绝缘层，所述第二绝缘层包括至少四层结构，其每层结构的致密度沿远离所述第一绝缘层的方向逐渐降低。
本领域技术人员可以理解的是，显示面板上的信号线与驱动芯片电连接，以通过驱动芯片为与信号线连接的像素单元提供信号，这些信号线从像素区延伸至扇出区。通过在扇出区与该信号线对应的位置处刻蚀相应的过孔，并且将驱动芯片的管脚插入到过孔中，以使驱动芯片与信号线电连接。然而，这些信号线并非同层设置，因此过孔的深度也是不同的。在现有技术中为了提高生产效率以及节约成本，通常采用一次构图工艺形成这些过孔，因此导致深度较小的过孔的孔径较大，使得驱动芯片的管脚插入该过孔后无法完全被过孔的孔壁包裹，导致该过孔下方的信号线的一部分裸露，进而导致该信号线产生不良，影响显示品质。
在本实施例中，对形成有较浅过孔的绝缘层(第二绝缘层)的结构进行改变，即，采用至少四层结构的第二绝缘层，并且第二绝缘层中的每层结构的致密度沿远离第一绝缘层(栅极绝缘层)的方向逐渐降低。在针对具有该结构的第二绝缘层的刻蚀过程中，将形成内壁为台阶状的过孔，相应减小了过孔的孔径，以避免出现信号线暴露的情况产生，并且可灵活地改变生产的监控尺寸。
具体地，在本发明的一个实施例中，一种显示面板包括像素区、扇出区以及驱动电路区，每个扇出区设置在像素区与驱动电 路区之间。在像素区中设置有相互异面交叉的第一信号线和第二信号线，第一信号线和第二信号线分别延伸至各个扇出区。在驱动电路区中设置有第一驱动芯片和第二驱动芯片。在第一信号线所在层和第二信号线所在层之间设置有第一绝缘层，在第二信号线上方还设置有第二绝缘层。所述第一驱动芯片通过贯穿扇出区中第一信号线上方的第一绝缘层和第二绝缘层的第一过孔与第一信号线电连接，所述第二驱动芯片通过贯穿扇出区中第二信号线上方的第二绝缘层的第二过孔与第二信号线电连接。此外，本实施例中的第二绝缘层包括至少四层结构，并且第二绝缘层的每层结构的致密度沿远离所述第一绝缘层的方向逐渐降低。
如图4至6所示，在本实施例中，例如，第一信号线可以为栅线11，第二信号线可以为数据线12，第一驱动芯片可以为栅极驱动芯片，并且第二驱动芯片可以为源极驱动芯片。应当理解的是，可替代地，第一信号线可以为数据线12，第二信号线可以为栅线11，第一驱动芯片可以为源极驱动芯片，并且第二驱动芯片可以为栅极驱动芯片。
在本实施例中，彼此交叉设置的多条栅线11和多条数据线12限定出多个像素单元，在栅线11和数据线12之间设置有栅极绝缘层13(第一绝缘层)，在数据线12上方还设置有钝化层14(第二绝缘层)。在扇出区中靠近驱动电路区的栅线11上方形成的栅极绝缘层13和钝化层14中刻蚀出第一过孔15以贯穿栅极绝缘层13和钝化层14，在数据线12上方形成的钝化层14中刻蚀出第二过孔16以贯穿钝化层14。此时，驱动电路区的栅极驱动芯片的管脚通过第一过孔15与栅线11电连接，以便为栅线11提供栅极扫描线号，源极驱动芯片的管脚则通过第二过孔16与数据线12电连接，以便为数据线12提供数据电压信号。在本实施例中，钝化层14采用至少四层的结构，即，图4中所示的结构14-1、14-2、14-3和14-4，并且每层结构的致密度沿远离栅极绝缘层13的方向递减，从而通过刻蚀钝化层14所形成的第二过孔16的内壁为圆形台阶状。可以理解的是，两相邻层结构的致密度不同，故这两 层结构的被刻蚀的程度也是不同，即，致密度大的层结构较致密度小的层结构刻蚀形成的孔径小，从而很容易在相邻层结构交界的界面处形成台阶，进而使得第二过孔16内壁的孔径沿远离所述栅极绝缘层13的方向依次增大。此时，第二过孔16实际上所能容纳的管脚的孔径应当是第二过孔16内壁中的最小孔径，也就是致密度最大的一层结构被刻蚀形成的孔径。因此相对于现有一层结构的钝化层14所刻蚀出的过孔而言，本实施例的第二过孔16的孔径较小，从而可以避免由于第二孔径16过大无法将源极驱动芯片的管脚完全包裹而导致的数据线裸露，从而避免显示不良的现象。
需要说明的是，在形成第一过孔15时需要刻蚀钝化层14和栅极绝缘层13，并且在同一次构图工艺中形成第一过孔15和第二过孔16。因此，钝化层14的结构改变同样会对第一过孔15的孔径造成一定的影响，但是，应当理解的是，栅极绝缘层13的致密度相对于钝化层14中致密度最大的一层结构(也就是钝化层14的第一层结构14-1)而言还要大，因此，第一过孔15的孔径取决于栅极绝缘层13。而且，即使采用与现有技术中同样长的刻蚀时间，由于刻蚀难易程度增加，会导致所形成的第一过孔15的孔径有所减小，但并不会影响栅极驱动芯片的管脚插入到第一过孔15中，只要稍微用力将栅极驱动芯片下压，其管脚即可插入第一过孔15中以与栅线接触。
例如，钝化层14的每层结构的材料相同。在此情况下，在形成钝化层14各层结构时，工艺简单，可以提高生产效率。可以理解的是，钝化层14的每层结构的材料也可以是不相同的，只要在远离栅极绝缘层13的方向上钝化层的各层结构的致密度依次降低，并且在对钝化层14进行刻蚀时所形成的第二过孔16的内壁能够呈台阶状即可。例如，本实施例中的钝化层14的材料可以为氮化硅，其也可以不局限于这种材料，也可以是氧化硅等其他的绝缘材料。
如上所述，本实施例中的钝化层14可以采用四层结构的钝化 层。经过实验验证，当钝化层14采用致密度逐渐降低的两层或者三层结构时，在对该钝化层14进行刻蚀之后，不能形成内壁为台阶状的过孔，而是形成内壁为外凸的弧形的过孔，可以理解的是，这种过孔仍然不能将驱动芯片的管脚完全包裹。此外，当钝化层14采用五层或者更多层结构时，在对该钝化层14进行刻蚀之后，虽然同样可以形成内壁呈台阶状的过孔，但是随着钝化层14结构的层数的增多，势必会造成工艺的复杂，同时也会增加生产成本，并且效率降低。然而，四层结构的钝化层14结构简单，同时经刻蚀后可以形成内壁为台阶状的过孔，可以将驱动芯片的管脚完全包裹，故可以解决现有技术中存在的裸露的数据线不良的问题。此外，四层结构的钝化层14的制备容易实现，节约制备时间，提高生产效率。
具体的，在钝化层14所包括的四层结构14-1、14-2、14-3、14-4中，该四层结构的厚度范围分别为10nm至50nm、50nm至500nm、50nm至500nm、以及10nm至50nm。但是，此厚度范围并不构成对本实施例的限制，也可以根据具体情况具体设定厚度范围。需要说明的是，在经过多次试验之后得出，当钝化层14的第一层结构14-1和第四层结构14-4的厚度相差不大，第二层结构14-2和第三层结构14-3的厚度相差不大，并且第一层结构14-1和第四层结构14-4的厚度均小于第二层结构14-2和第三层结构14-3的厚度时，通过刻蚀形成第二过孔16时，更容易地在第二过孔16内壁中形成台阶，如图6所示。
具体的，在钝化层所包括的四层结构14-1、14-2、14-3、14-4中，针对该四层结构的刻蚀速率范围分别为300nm/min至600nm/min、300nm/min至800nm/min、300nm/min至1000nm/min、以及300nm/min至1500nm/min。可以理解的是，可以通过针对钝化层14的每层结构的刻蚀速率来表征每层结构的致密度，致密度较大的层的刻蚀速率较低，否则反之。同时，通过合理设置钝化层14的每层结构的致密度，可以使得在刻蚀钝化层14所形成的第二过孔16的内壁更容易被形成为环形台阶。通过实验验证得知， 对钝化层14的第二层结构14-2的刻蚀速率比对第三层结构14-3的刻蚀速率小100nm/min至700nm/min时，也就是说第二层结构14-2的致密度与14-3的致密度之间的差距较大时，可以在刻蚀钝化层14所形成的第二过孔16的内壁形成较完美的环形台阶。在该情况下，在钝化层14的第二层结构14-2和第三层结构14-3的交界面的位置处所形成的环形(圆形)台阶的直径则可以看作为所监控的第二过孔16的孔径。
在本发明的另一个实施例中，提供一种显示面板的制备方法，其中该显示面板可以为上述实施例中所述的显示面板。该显示面板包括像素区、扇出区和驱动电路区。所述扇出区的每一个设置在所述像素区和所述驱动电路区之间。所述像素区包括多条相互交叉设置的第一信号线和第二信号线，所述第一信号线和所述第二信号线分别延伸至扇出区。在第一信号线和第二信号线之间设置有第一绝缘层，在第二信号线上方设置有第二绝缘层，所述第二绝缘层包括至少四层结构，其每层结构的致密度沿远离所述第一绝缘层的方向逐渐降低。所述驱动电路区包括多个第一驱动芯片和多个第二驱动芯片，所述第一驱动芯片通过贯穿所述扇出区中的第一绝缘层和第二绝缘层的第一过孔与所述第一信号线电连接，所述第二驱动芯片通过贯穿所述扇出区中的第二绝缘层的第二过孔与所述第二信号线电连接。
在本实施例中，例如，第二绝缘层包括四层结构，且四层结构的材料相同，该材料可以为氮化硅。
本实施例的显示面板的制备方法包括以下步骤一至步骤三。
步骤一中，在基底上形成第一信号线图案和第一绝缘层。
具体的，在该步骤中基板采用玻璃等透明材料制成并且经过预先清洗。例如，在基板上采用溅射方式、热蒸发方式、等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition：简称PECVD)方式、低压化学气相沉积(Low Pressure Chemical Vapor Deposition：简称LPCVD)方式、大气压化学气相沉积(Atmospheric Pressure Chemical Vapor Deposition： 简称APCVD)方式或电子回旋谐振化学气相沉积(Electron Cyclotron Resonance Chemical Vapor Deposition：简称ECR-CVD)方式形成第一金属薄膜，通过对该第一金属薄膜进行曝光、显影、刻蚀、剥离的构图工艺来形成包括第一信号线的图案，然后采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式形成第一绝缘层。
步骤二中，在完成上述步骤的基底上，通过构图工艺形成第二信号线的图案和第二绝缘层。
在该步骤中，第二信号线的形成方法与第一信号线的形成方法相同，在此不再详细描述。特别是，在该步骤中，第二绝缘层的形成方法是与第一绝缘层的形成方法不同。以第二绝缘层的材料为氮化硅的情况为例，形成第二绝缘层的步骤具体包括：利用NH3、N2和SiH4的反应气体在250℃至400℃的温度范围内通过化学气相沉积工艺依次形成所述第二绝缘层的第一层至第四层，具体工艺条件分别如下所述。
当形成所述第二绝缘层的第一层结构时，SiH4流量范围为500sccm至1500sccm，NH3流量范围为2000sccm至4000sccm，N2流量范围为10000sccm至30000sccm，反应功率范围为3000W至6000W，反应压强范围为500mtorr至1000mtorr，反应间距范围为500mils至1500mils。
当形成所述第二绝缘层的第二层结构时，SiH4流量范围为1000sccm至2000sccm，NH3流量范围为3000sccm至5000sccm，N2流量范围为10000sccm至30000sccm，反应功率范围为3000W至7000W，反应压强范围为800mtorr至1500mtorr，反应间距范围为800mils至1500mils。
当形成所述第二绝缘层的第三层结构时，SiH4流量范围为1000sccm至2000sccm，NH3流量范围为3000sccm至7000sccm，N2流量范围为10000sccm至30000sccm，反应功率范围为3000W至7000W，反应压强范围为1000mtorr至2500mtorr，反应间距范 围为800mils至1500mils。
当形成所述第二绝缘层的第四层结构时，SiH4流量范围为1000sccm至2000sccm，NH3流量范围为4000sccm至8000sccm，N2流量范围为10000sccm至30000sccm，反应功率范围为5000W至7000W，反应压强范围为2000mtorr至3000mtorr，反应间距范围为800mils至1500mils。
需要说明的是，上述步骤中只是给出一个具体的实现方式，而在实际中，通过调节各气体的流量，控制反应功率、压强以及间距，可形成所述第二绝缘层的四层结构。上述步骤中，SiH4流量范围为1000sccm至2000sccm，NH3流量范围为2000sccm至8000sccm，N2流量范围为10000sccm至30000sccm，反应功率范围为3000W至7000W，反应压强范围为500mtorr至3000mtorr，反应间距范围为500mils至1500mils。同时，需要说明的是，形成第二绝缘层的每层结构的气体流量、反应功率、压强以及间距均不同，只有这样才能形成致密度不同的四层结构。如何控制气体流量、反应功率、反应压强以及反应间距，以形成材料相同且致密度不同的膜层的方法是本领域技术人员已知的，故在此不详细描述。
在第二绝缘层所包括的四层结构中，每层结构的厚度范围分别为10nm至50nm、50nm至500nm、50nm至500nm、以及10nm至50nm，但是此厚度范围并不构成对本实施例的限制，也可以根据具体情况具体设定。需要说明的是，在经过多次试验之后得出，当第二绝缘层的第一层结构和第四层结构的厚度的相差不大，第二层结构和第三层结构的厚度相差不大，并且第一层结构和第四层结构的厚度均小于第二层结构和第三层结构的厚度时，在随后通过刻蚀形成第二过孔的步骤中，更容易在第二过孔内壁中形成台阶。
在第二绝缘层所包括的四层结构中，针对每层结构的刻蚀速率范围分别为300nm/min至600nm/min、300nm/min至800nm/min、300nm/min至1000nm/min、以及300nm/min至1500nm/min。可以 理解的是，可以通过第二绝缘层的每层结构的刻蚀速率来表征每层结构的致密度，致密度较大的层的刻蚀速率较低，否则反之。同时，可以理解的是，通过合理地设置第二绝缘层的每层结构的致密度，可以使得在随后刻蚀第二绝缘层的步骤中更容易在第二过孔的内壁中形成环形台阶。通过实验验证得知，对第二绝缘层的第二层结构的刻蚀速率比第三层结构的刻蚀速率小100nm/min至700nm/min时，也就是说第二层结构的致密度与第三层结构的致密度差距较大时，可以在随后刻蚀第二绝缘层的步骤中在第二过孔的内壁中形成较完美的环形台阶。在此情况下，随后步骤中在第二绝缘层的第二层结构和第三层结构交界面的位置处所形成的环形台阶的直径则可以被看作为所监控的第二过孔的孔径。
步骤三中，在完成上述步骤的基底上，通过构图工艺形成包括第一过孔和第二过孔的图案。
在该步骤中，采用涂覆(包括旋涂)方法，在第二绝缘层的第四层结构上方形成有机膜。有机膜采用有机树脂形成，有机树脂包括丙烯酸类成膜树脂、酚醛树脂类成膜树脂、乙烯基聚合物成膜树脂或聚酰亚胺成膜树脂。然后通过构图工艺，形成贯穿第一绝缘层和第二绝缘层并且用于将第一信号线和第一驱动芯片连接的第一过孔、以及贯穿第二绝缘层并且用于将第二信号线与第二驱动芯片连接的第二过孔。每节台阶所在位置为所述第二绝缘层中的任意两相邻层结构的交界位置，并且每节台阶所围成的圆形的直径沿远离所述第一绝缘层的方向依次增大。
至此完成显示面板上扇形区中的过孔的制备。
需要说明的是，上述实施例中仅仅是以制备四层结构的第二绝缘层为例进行说明的，以同样的方法还可以制备四层以上结构的第二绝缘层，只要相应地控制气体流量、反应功率、反应压强以及反应间距即可实现。
可以理解的是，在本实施例的制备方法中，所形成的第二绝缘层结构至少包括四层，因此在通过刻蚀第二绝缘层形成的第二过孔的内壁上一定会形成环形台阶。在此情况下，与单层结构的 第二绝缘层相比，本实施例的第二绝缘层中的第二过孔的监控孔径将会发生改变，也就是第二过孔的监控孔径将会减小，从而第二绝缘层可以将插入到第二过孔中的第二驱动芯片的管脚完全包裹，避免外界环境对第二驱动芯片的管脚以及第二过孔下方的第二信号线造成污染，从而避免产生不良。
在本发明的另一个实施例中，提供一种显示装置，其包括上述实施例中所述的显示面板。本实施例的显示装置的性能更好并且良率较高。
本实施例所提供的显示装置可以为TN、ADS、IPS、LTPS等任何模式的液晶显示装置。该显示装置可以为液晶面板、液晶电视、显示器、手机、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (20)

  1. 一种显示面板，包括像素区和扇出区，在所述像素区中设置有多条相互交叉设置的第一信号线和第二信号线，所述第一信号线和所述第二信号线分别延伸至各个扇出区，其中，
    在所述第一信号线和所述第二信号线之间设置有第一绝缘层，在所述第二信号线上方设置有第二绝缘层，所述第二绝缘层包括至少四层结构，并且所述第二绝缘层的每层结构的致密度沿远离所述第一绝缘层的方向逐渐降低。
  2. 根据权利要求1所述的显示面板，其中，所述第二绝缘层的每层结构的材料相同。
  3. 根据权利要求1所述的显示面板，还包括驱动电路区，其中，
    所述扇出区的每一个设置在所述像素区和所述驱动电路区之间，
    所述驱动电路区包括多个第一驱动芯片和多个第二驱动芯片，所述第一驱动芯片通过贯穿所述扇出区中的第一绝缘层和第二绝缘层的第一过孔与所述第一信号线电连接，并且所述第二驱动芯片通过贯穿所述扇出区中的第二绝缘层的第二过孔与所述第二信号线电连接。
  4. 根据权利要求3所述的显示面板，其中，所述第二过孔的内壁呈台阶状，每节台阶所在位置为所述第二绝缘层的任意两相邻层结构的交界位置。
  5. 根据权利要求4所述的显示面板，其中，每节台阶所围成的圆形的直径沿远离所述第一绝缘层的方向依次增大。
  6. 根据权利要求1至5中任意一项所述的显示面板，其中，所述第二绝缘层包括四层结构。
  7. 根据权利要求6所述的显示面板，其中，所述第二绝缘层的四层结构中的每层结构的厚度范围在远离所述第一绝缘层方向上依次为10nm至50nm、50nm至500nm、50nm至500nm、和10nm至50nm。
  8. 根据权利要求6所述的显示面板，其中，对所述第二绝缘层的四层结构中的每层结构的刻蚀速率范围在远离所述第一绝缘层方向上依次为300nm/min至600nm/min、300nm/min至800nm/min、300nm/min至1000nm/min、和300nm/min至1500nm/min。
  9. 根据权利要求8所述的显示面板，其中，对所述第二绝缘层的四层结构中的第二层结构的刻蚀速率比第三层结构的刻蚀速率小100nm/min至700nm/min。
  10. 根据权利要求1-5中任意一项所述的显示面板，其中，所述第一信号线为栅线，所述第二信号线为数据线，所述第一驱动芯片为栅极驱动芯片，所述第二驱动芯片为源极驱动芯片。
  11. 根据权利要求1-5中任意一项所述的显示面板，其中，所述第一信号线为数据线，所述第二信号线为栅线，所述第一驱动芯片为源极驱动芯片，所述第二驱动芯片为栅极驱动芯片。
  12. 一种制备显示面板的方法，所述显示面板包括像素区和扇出区，所述方法包括：依次在基底上形成第一信号线、第一绝缘层、第二信号线和第二绝缘层的步骤，所述第一信号线和所述第二信号线在所述像素区中布置为相互交叉，并且分别从所述像 素区延伸至各个扇出区，其中，
    形成所述第二绝缘层的步骤包括：在形成有所述第二信号线的基底上方，依次形成至少四层致密度逐渐降低的绝缘薄膜，以形成第二绝缘层的各层结构。
  13. 根据权利要求12所述的方法，其中，所述第二绝缘层的每层结构的材料相同。
  14. 根据权利要求13所述的方法，其中，所述第二绝缘层包括四层结构，在形成有所述第二信号线的基底上方依次形成所述第二绝缘层的四层结构的步骤包括：利用NH3、N2和SiH4的反应气体在250℃至400℃的温度范围内通过化学气相沉积工艺形成所述第二绝缘层，其中，
    当形成所述第二绝缘层的第一层结构时，SiH4流量范围为500sccm至1500sccm，NH3流量范围为2000sccm至4000sccm，N2流量范围为10000sccm至30000sccm，反应功率范围为3000W至6000W，反应压强范围为500mtorr至1000mtorr，反应间距范围为500mils至1500mils；
    当形成所述第二绝缘层的第二层结构时，SiH4流量范围为1000sccm至2000sccm，NH3流量范围为3000sccm至5000sccm，N2流量范围为10000sccm至30000sccm，反应功率范围为3000W至7000W，反应压强范围为800mtorr至1500mtorr，反应间距范围为800mils至1500mils；
    当形成所述第二绝缘层的第三层结构时，SiH4流量范围为1000sccm至2000sccm，NH3流量范围为3000sccm至7000sccm，N2流量范围为10000sccm至30000sccm，反应功率范围为3000W至7000W，反应压强范围为1000mtorr至2500mtorr，反应间距范围为800mils至1500mils；以及
    当形成所述第二绝缘层的第四层结构时，SiH4流量范围为1000sccm至2000sccm，NH3流量范围为4000sccm至8000sccm， N2流量范围为10000sccm至30000sccm，反应功率范围为5000W至7000W，反应压强范围为2000mtorr至3000mtorr，反应间距范围为800mils至1500mils。
  15. 根据权利要求12-14中任意一项所述的方法，其中，所述显示面板还包括驱动电路区，所述扇出区的每一个设置在所述像素区和所述驱动电路区之间，所述驱动电路区包括多个第一驱动芯片和多个第二驱动芯片，在形成所述第二绝缘层之后，所述方法还包括：
    通过构图工艺，在所述扇出区中形成贯穿所述第一绝缘层和所述第二绝缘层的第一过孔，并且在所述扇出区中形成贯穿所述第二绝缘层的第二过孔，使得所述第一驱动芯片通过所述第一过孔与所述第一信号线电连接，所述第二驱动芯片通过所述第二过孔与所述第二信号线电连接，
    所述第二过孔的内壁呈台阶状，每节台阶所在位置为所述第二绝缘层的任意两相邻层结构的交界位置。
  16. 根据权利要求15所述的方法，其中，所述每节台阶所围成的圆形的直径沿远离所述第一绝缘层的方向依次增大。
  17. 根据权利要求14所述的方法，其中，所述第二绝缘层的四层结构中的每层结构的厚度范围在远离所述第一绝缘层方向上依次为10nm至50nm、50nm至500nm、50nm至500nm、和10nm至50nm。
  18. 根据权利要求14所述的方法，其中，对所述第二绝缘层的四层结构中的每层结构的刻蚀速率范围在远离所述第一绝缘层方向上依次为300nm/min至600nm/min、300nm/min至800nm/min、300nm/min至1000nm/min、和300nm/min至1500nm/min。
  19. 根据权利要求18所述的方法，其中，在所述第二绝缘层的四层结构中，对沿远离所述第一绝缘层方向上的第二层结构的刻蚀速率比第三层结构的刻蚀速率小100nm/min至700nm/min。
  20. 一种显示装置，包括权利要求1至11中任意一项所述的显示面板。
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