WO2021092936A1 - 显示面板、拼接显示面板、其制备方法 - Google Patents

显示面板、拼接显示面板、其制备方法 Download PDF

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Publication number
WO2021092936A1
WO2021092936A1 PCT/CN2019/118919 CN2019118919W WO2021092936A1 WO 2021092936 A1 WO2021092936 A1 WO 2021092936A1 CN 2019118919 W CN2019118919 W CN 2019118919W WO 2021092936 A1 WO2021092936 A1 WO 2021092936A1
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WIPO (PCT)
Prior art keywords
signal driving
base substrate
signal
vias
display
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PCT/CN2019/118919
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English (en)
French (fr)
Inventor
曲连杰
杨虹
赵合彬
邱云
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/118919 priority Critical patent/WO2021092936A1/zh
Priority to CN201980002449.2A priority patent/CN113272881B/zh
Priority to US16/978,810 priority patent/US20230095298A1/en
Publication of WO2021092936A1 publication Critical patent/WO2021092936A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • G09F9/3026—Video wall, i.e. stackable semiconductor matrix display modules
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a spliced display panel, and a preparation method thereof.
  • a large-size display panel usually needs to be formed by splicing multiple small-size display panels.
  • the splicing seams between small-sized display panels are relatively large, resulting in poor display effects.
  • a base substrate is provided with a plurality of display regions; each of the display regions includes a plurality of pixel units; the pixel unit includes a plurality of sub-pixels; the sub-pixels include a light-emitting chip;
  • the gaps between two adjacent rows of pixel units have a first distance along the row direction, and the gaps between two adjacent rows of pixel units have a second distance along the column direction;
  • the gap between the display areas closest to the row direction has a third distance along the row direction, and the third distance is substantially the same as the first distance; and/or,
  • the gap between the display areas closest to the column direction has a fourth pitch in the column direction, and the fourth pitch is substantially the same as the second pitch.
  • the sub-pixel array in the display area is arranged, and the sub-pixel further includes a driving circuit configured to drive the light-emitting chip.
  • each display area includes: a plurality of first signal driving lines and a plurality of second signal driving lines located between the base substrate and the light-emitting chip; wherein , The first signal driving line and the second signal driving line are crossed and insulated;
  • the driving circuits in one row of sub-pixels are electrically connected to one of the first signal driving lines, and the driving circuits in one column of sub-pixels are electrically connected to one of the second signal driving lines.
  • each display area includes: a plurality of first signal transmission lines, a plurality of second signal transmission lines, and a plurality of A driving chip electrically connected to the first signal transmission line and the second signal transmission line;
  • One of the first signal driving lines is electrically connected to one of the first signal transmission lines through a first via hole corresponding to penetrate the base substrate; and one of the second signal driving lines is electrically connected to one of the first signal transmission lines through corresponding first vias penetrating the base substrate The second via is electrically connected to one of the second signal transmission lines.
  • one first signal driving line corresponds to one first via; each of the first vias is located at the same end of the first signal driving line.
  • one first signal driving line corresponds to one first via; some of the first vias are located at one end of the first signal driving line, and the rest are The first via is located at the other end of the first signal driving line.
  • the first via hole corresponding to the first signal driving line in odd-numbered rows is located at one end of the first signal driving line, and the first via hole corresponding to the first signal driving line in even-numbered rows is located at the end of the first signal driving line.
  • the first signal drives the other end of the line.
  • one of the first signal driving lines corresponds to two of the first vias; one of the first vias is located at one end of the first signal driving line, and the other is located at one end of the first signal driving line.
  • the first via is located at the other end of the first signal driving line.
  • one second signal driving line corresponds to one second via; each second via is located at the same end of the second signal driving line.
  • one second signal driving line corresponds to one second via; some of the second vias are located at one end of the second signal driving line, and the rest are The second via is located at the other end of the second signal driving line.
  • the second via hole corresponding to the second signal driving line in the odd-numbered column is located at one end of the second signal driving line, and the second via hole corresponding to the second signal driving line in the even-numbered column is located at the end of the second signal driving line.
  • the second signal drives the other end of the line.
  • one second signal drive line corresponds to two second vias; one second via is located at one end of the second signal drive line, and the other is located at one end of the second signal drive line.
  • the second via is located at the other end of the second signal driving line.
  • each of the display areas includes a plurality of pixel units; the pixel units include a plurality of sub-pixels; the sub-pixels include a light-emitting chip;
  • the gaps between two adjacent rows of pixel units have a first distance along the row direction, and the gaps between two adjacent rows of pixel units have a second distance along the column direction;
  • the gap between the display areas closest to the row direction has a third distance along the row direction, and the third distance is substantially the same as the first distance; and/or,
  • the gap between the display areas closest to the column direction has a fourth pitch in the column direction, and the fourth pitch is substantially the same as the second pitch.
  • the forming a plurality of the display areas includes:
  • each of the display areas on the same base substrate a plurality of first signal driving lines and a plurality of second signal driving lines are formed; wherein, the first signal driving lines and the second signal driving lines Lines are crossed and insulated;
  • a conductive material is formed in each of the first via holes and each of the second via holes, so that one of the first signal driving lines is electrically connected to one of the first signal transmission lines through the corresponding first via holes, and one of the first signal transmission lines is electrically connected to the first signal transmission line through the corresponding first via hole.
  • the second signal driving line is electrically connected to a second signal transmission line through a corresponding second via hole.
  • the forming a conductive material in each of the first via holes and each of the second via holes includes:
  • a first photoresist layer is formed on the side of the base substrate facing the first signal drive line, and a second photoresist layer is formed on the side of the base substrate away from the first signal drive line
  • the first photoresist layer has a plurality of third vias and a plurality of fourth vias
  • the second photoresist layer has a plurality of fifth vias and a plurality of sixth vias
  • one The orthographic projection of the third via on the base substrate covers an orthographic projection of the first via on the base substrate
  • the orthographic projection of the fourth via on the base substrate covers An orthographic projection of the second via on the base substrate
  • an orthographic projection of the fifth via on the base substrate covers an orthographic projection of the first via on the base substrate
  • An orthographic projection of the sixth via on the base substrate covers an orthographic projection of the second via on the base substrate;
  • each of the first via holes, each of the second via holes, and each of the first vias Three vias, each of the fourth vias, each of the fifth vias, and each of the sixth vias are filled with conductive material.
  • the method further includes:
  • the first photoresist layer and the second photoresist layer are removed.
  • the spliced display panel provided by the embodiment of the present disclosure includes: a plurality of the above-mentioned display panels;
  • the gaps between the display areas of the display panels nearest to each other in the row direction have a fifth distance in the row direction, and the fifth distance is substantially the same as the first distance; and/or,
  • the gaps between the display areas of the display panels that are closest in the column direction have a sixth pitch in the column direction, and the sixth pitch is substantially the same as the second pitch.
  • FIG. 1 is a schematic diagram of a top view structure of some display panels provided by embodiments of the present disclosure
  • FIG. 2 is a schematic cross-sectional view of the display panel shown in FIG. 1 along the AA' direction;
  • FIG. 3a is a schematic structural diagram of a driving circuit provided by an embodiment of the disclosure.
  • 3b is a schematic diagram of a cross-sectional structure of a sub-pixel in a display panel provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a top view of the light-emitting side of other display panels provided by the embodiments of the present disclosure.
  • FIG. 5 is a schematic top view of the structure of some display panels facing away from the light-emitting chip according to the embodiments of the present disclosure
  • FIG. 6a is a schematic cross-sectional view of the display panel shown in FIG. 4 along the AA' direction;
  • FIG. 6b is a schematic cross-sectional view of the display panel shown in FIG. 4 along the BB' direction;
  • FIG. 7a is a schematic top view of some other display panels provided by the embodiments of the present disclosure.
  • FIG. 7b is a schematic top view of some other display panels provided by the embodiments of the present disclosure.
  • FIG. 8 is a schematic top view of the structure of still other display panels provided by the embodiments of the present disclosure.
  • FIG. 9 is a schematic diagram of a top view structure of still other display panels provided by the embodiments of the present disclosure.
  • FIG. 10 is a schematic diagram of a top view structure of still other display panels provided by the embodiments of the present disclosure.
  • FIG. 11 is a flow chart of the preparation method provided by the embodiment of the disclosure.
  • the display panel provided by the embodiment of the present disclosure, as shown in FIG. 1 and FIG. 2, includes:
  • the base substrate 100 is provided with a plurality of display areas AA; each display area AA includes: a plurality of pixel units PX; the pixel unit PX includes a plurality of sub-pixels spx; the sub-pixels spx includes a light-emitting chip 210;
  • the gap between two adjacent columns of pixel units PX has a first pitch W1 along the row direction F1
  • the gap between two adjacent rows of pixel units PX has a first distance along the column direction F2.
  • the gap between the display areas AA closest to the row direction F1 has a third pitch W3 in the row direction F1, and the third pitch W3 can be substantially the same as the first pitch W1.
  • the gap between the display areas AA nearest to each other along the column direction F2 has a fourth distance W4 along the column direction F2, and the fourth distance W4 and the second distance W2 can be substantially the same.
  • the third pitch may be approximately the same as the first pitch and/or the fourth pitch may be approximately the same as the second pitch, so as to make a uniform transition between the display area and the display area, thereby reducing the splicing caused by the splicing accuracy of the splicing process.
  • the problem of larger seams can improve the display effect.
  • one base substrate can be used to form multiple display areas for splicing, there is no need to prepare multiple independent display areas first, and then splice these independent display areas into display panels, so that splicing is not required.
  • the process can form a large-size display panel and improve production efficiency.
  • all the display areas AA can share a base substrate 100.
  • the two adjacent display areas AA share a boundary with sub-micron precision, so that it is not necessary to use The splicing process can form a large-size display panel. Therefore, as the resolution increases, the problem of visible splices will not occur, and the influence of splices on the display effect will be further reduced.
  • the size of the base substrate 100 can be utilized to the greatest extent, and a display panel without a frame or an ultra-narrow frame can be realized.
  • the number of display areas provided on the base substrate may be 2, 3, 4, 6 or more. In actual applications, it can be designed and determined according to the actual application environment, which is not limited here.
  • the base substrate 100 in the preparation process, usually adopts a glass substrate.
  • the size of the glass substrate can reach about 110 inches, and the size of the display area AA is usually 11 inches. Therefore, a base substrate 100 can be used for all display panels within 110 inches. In this way, a large-size display panel product can be realized without physical splicing.
  • the gap between two adjacent columns of pixel units PX has a first pitch W1 along the row direction F1.
  • the first distance W1 in each display area AA may be approximately the same. It should be noted that in the actual process, due to the limitation of process conditions or other factors, the first distance W1 in each display area AA may not be exactly the same, and there may be some deviations, so the first distance in each display area AA As long as the same relationship between a distance W1 substantially satisfies the same conditions, they all belong to the protection scope of the present disclosure. For example, the first distance W1 in each display area AA may be the same as allowed within the allowable error range.
  • the gap between the display areas AA nearest to each other in the row direction F1 has a third distance W3 in the row direction F1, which can make the third distance W3 and the first A spacing W1 is approximately the same.
  • the gap between the display area AA closest in the row direction F1 and the gap between two adjacent columns of pixel units PX in the display area AA can be aligned along the row.
  • the gaps in the direction F1 are prepared approximately the same, that is, the gap between the display images of the two adjacent display areas AA of the same base substrate 100 can be approximately the same as the gap between the pixel units PX, which can further reduce Problems with the visibility of splicing seams.
  • the above-mentioned third pitch W3 and the first pitch W1 may not be completely the same, and there may be some deviations.
  • the ratio between the third distance W3 and the first distance W1 can be Satisfy It can be stated that the third distance W3 is the same as the first distance W1.
  • W3 selects a value between 300 ⁇ m and 700 ⁇ m, which means that the third distance W3 is the same as the first distance W1.
  • the distance between the third distance W3 and the first distance W1 ratio It can also be set according to the critical value that human eyes can recognize that there is an obvious gap size between the display areas.
  • the ratio between the third distance W3 and the first distance W1 can also be set together according to the above two methods.
  • the third pitch W3 is substantially the same as the first pitch W1.
  • the gap between two adjacent rows of pixel units PX has a second pitch W2 along the column direction F2.
  • the second spacing W2 in each display area AA may be approximately the same. It should be noted that in the actual process, due to the limitation of process conditions or other factors, the second spacing W2 in each display area AA may not be exactly the same, and there may be some deviations. Therefore, the first interval in each display area AA The same relationship between the two distances W2 as long as it substantially satisfies the same conditions, and they all belong to the protection scope of the present disclosure. For example, the second spacing W2 in each display area AA may be the same as allowed within the allowable error range.
  • the gap between the display areas AA closest to the column direction F2 has a fourth distance W4 along the column direction F2, and the fourth distance W4 can be set to The two pitches W2 are approximately the same. In this way, by making the fourth pitch W4 and the second pitch W2 approximately the same, the gap between the display area AA closest in the column direction F2 and the gap between two adjacent rows of pixel units PX in the display area AA can be aligned along the column.
  • the gaps in the direction F2 are prepared approximately the same, that is, the gaps between the display screens of the two adjacent display areas AA of the same base substrate 100 can be approximately the same as the gaps between the pixel units PX, which can further reduce Problems with the visibility of splicing seams.
  • the fourth pitch W4 and the second pitch W2 may not be completely the same, and there may be some deviations.
  • the distance between the fourth distance W4 and the second distance W2 ratio It can also be set according to the critical value that human eyes can recognize that there is a clear gap between the display areas.
  • the ratio between the fourth distance W4 and the second distance W2 can also be set together according to the above two methods.
  • the fourth pitch W4 and the second pitch W2 are substantially the same.
  • the display panel may include: a plurality of pixel units PX arranged in an array in each display area AA.
  • Each pixel unit PX may include a plurality of sub-pixels spx. Further, the sub-pixels spx in the display area AA may be arranged in an array.
  • the pixel unit PX may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. In this way, red, green and blue can be mixed to achieve color display.
  • the pixel unit PX may also include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels.
  • the light-emitting color and specific number of the sub-pixels spx in the pixel unit PX can be designed and determined according to the actual application environment, which is not limited here.
  • the sub-pixel spx may further include a driving circuit configured to drive the light-emitting chip 210 to emit light.
  • the light emitting chip 210 may be at least one of a light emitting diode (Light Emitting Diode, LED), a micro light emitting diode (Micro Light Emitting Diode, Micro LED), and a mini light emitting diode (Mini Light Emitting Diode, Mini LED).
  • the anode of the Micro LED is used as the first end of the light-emitting chip 210
  • the cathode of the Micro LED is used as the second end of the light-emitting chip 210.
  • the driving circuit may include: a switching transistor M01, a driving transistor M0, and a storage capacitor C0.
  • the gate of the first switching transistor M01 is electrically connected to the scan signal terminal SCAN, the first electrode of the first switching transistor M01 is electrically connected to the data signal terminal DATA, and the second electrode of the first switching transistor M01 is electrically connected to the gate of the driving transistor M0. connection.
  • the first terminal of the driving transistor M0 is electrically connected to the first power terminal VDD
  • the second terminal of the driving transistor M0 is electrically connected to the first terminal of the light emitting chip 210
  • the second terminal of the light emitting chip 210 is electrically connected to the second power terminal VSS .
  • the first end of the storage capacitor C0 is electrically connected to the first power supply terminal VDD, and the second end of the storage capacitor C0 is electrically connected to the gate of the driving transistor M0.
  • the working process of the above-mentioned driving circuit may be basically the same as the working process in the related art, and will not be repeated here.
  • the driving circuit can also adopt other structures, which are not limited here.
  • the display panel may further include: a transistor array layer 220 for forming various film layers of the above-mentioned transistors and various film layers of the above-mentioned capacitors.
  • the transistor array layer 220 is located between the light-emitting chip 210 and the base substrate 100.
  • the transistor array layer 220 may include: an active layer 221 located on a side of the base substrate 100, a gate layer 222 located on a side of the active layer 221 away from the base substrate 100, and a gate layer 222 located away from the substrate.
  • the capacitor electrode layer 223 on the side of the substrate 100 is located on the source and drain electrode layer 224 (having a source electrode 2241 and a drain electrode 2242) on the side of the capacitor electrode layer 223 away from the base substrate 100.
  • the active layer 221, the gate layer 222, and the capacitor electrode layer 223 are insulated from each other
  • the source and drain electrode layers 224, the gate layer 222, and the capacitor electrode layer 223 are insulated from each other.
  • the source electrode 2241 and the drain electrode 2242 are respectively insulated from each other.
  • the layer 221 is electrically connected.
  • the transistor array layer 220 further includes a buffer layer 225 located between the base substrate 100 and the active layer 221, and a gate insulating layer 226 located between the active layer 221 and the gate layer 222 so that the active layer 221 and The gate layer 222 is insulated, and the interlayer dielectric layer 227 located between the gate layer 222 and the capacitor electrode layer 223 is arranged so that the gate layer 222 is insulated from the capacitor electrode layer 223, and is located between the capacitor electrode layer 223 and the source/drain electrode layer 224
  • the interlayer insulating layer 228 between the capacitor electrode layer 223 and the source and drain electrode layers 224 are arranged to insulate, and the planarization layer 229 is located between the source and drain electrode layer 224 and the light-emitting chip 210.
  • the first end of the light-emitting chip 210 passes through The planarization layer 229 is electrically connected to the drain 2242 through the via hole, and the second end of the light-emitting chip 210 is electrically connected to the cathode power supply line, so as to provide a driving signal to the light-emitting chip 210 through the drain 2242 and to the second terminal through the cathode power line.
  • the power terminal VSS provides a low voltage signal to provide a low voltage signal to the second terminal of the light emitting chip 210 to drive the light emitting chip 210 to emit light.
  • the capacitor electrode layer 223 and the gate layer 222 form a capacitor structure. It should be noted that FIG. 3b only uses one transistor in one sub-pixel spx as an example for illustration.
  • each display area AA may include: a plurality of first signal driving lines 111 and a plurality of second signal driving lines 112; Wherein, the first signal driving line 111 and the second signal driving line 112 are crossed and insulated. Exemplarily, the first signal driving line 111 and the second signal driving line 112 are located between the base substrate 100 and the light emitting chip 210. It should be noted that FIG. 4 only takes two display areas AA as an example for illustration, one of the display areas is AA-1, and the other display area is AA-2.
  • the first signal driving line 111 may extend along the row direction F1 of the sub-pixel spx
  • the second signal driving line 112 may extend along the column direction F2 of the sub-pixel spx.
  • the driving circuits in a row of sub-pixels spx are electrically connected to a first signal driving line 111
  • the driving circuits in a column of sub-pixels spx are electrically connected to a second signal driving line 112.
  • signals can be transmitted to the driving circuit through the first signal driving line 111 and the second signal driving line 112, so that the driving circuit drives the light-emitting chip 210 to emit light.
  • the scan signal terminal SCAN of the driving circuit in a row of sub-pixels spx is electrically connected to a first signal driving line 111
  • the data signal terminal DATA of the driving circuit in a column of sub-pixels spx is electrically connected to a second signal driving line 112.
  • the present invention includes but is not limited to this.
  • the first signal driving line 111 may be provided in the same layer as the gate layer 222. In this way, when the display panel is prepared, the gate layer 222 and the first signal driving line 111 can be simultaneously formed through a patterning process, without adding a separate process for preparing the first signal driving line 111, which can simplify the manufacturing process and save production costs. ,Increase productivity.
  • the second signal driving line 112 may be provided in the same layer as the source and drain electrode layer 224. In this way, when preparing the display panel, it is only necessary to change the original patterning pattern when forming the pattern of the source-drain electrode layer 224, and simultaneously form the pattern of the source-drain electrode layer 224 and the pattern of the second signal driving line 112 through one patterning process. Adding the process of separately preparing the second signal driving line 112 can simplify the preparation process, save production costs, and improve production efficiency.
  • each display area AA may include: located on the side of the base substrate 100 away from the light-emitting chip 210 A plurality of first signal transmission lines 121, a plurality of second signal transmission lines 122, and a driving chip 130 electrically connected to the first signal transmission line 121 and the second signal transmission line 122 respectively; wherein, one first signal driving line 111 passes through the substrate correspondingly
  • the first via 141 of the base substrate 100 is electrically connected to a first signal transmission line 121; and a second signal driving line 112 is electrically connected to a second signal transmission line 122 through a second via 142 corresponding to the base substrate 100.
  • the driving chip 130 when driving the display panel to display, the driving chip 130 can generate a driving signal for driving the light-emitting chip 210 to emit light, and then the first signal transmission line 121 and the second signal transmission line 122 are used to transmit the driving signal to the first signal driving line 111 and the first signal driving line 111 and the second signal transmission line, respectively.
  • the two signal driving lines 112 are used to drive the light-emitting chip 210 to emit light.
  • the first via 141 may penetrate the base substrate 100, the buffer layer 225, and the gate insulating layer 226. That is, one first signal driving line 111 is electrically connected to one first signal transmission line 121 through the conductive material in the first via 141 penetrating the base substrate 100, the buffer layer 225, and the gate insulating layer 226.
  • the present disclosure includes but is not limited to this.
  • the second via 142 may penetrate the base substrate 100, the buffer layer 225, the gate insulating layer 226, the interlayer dielectric layer 227 and the interlayer insulating layer 228. That is, one second signal driving line 112 passes through the conductive material in the second via 142 passing through the base substrate 100, the buffer layer 225, the gate insulating layer 226, the interlayer dielectric layer 227, and the interlayer insulating layer 228 and one The second signal transmission line 122 is electrically connected.
  • the present disclosure includes but is not limited to this.
  • the shape of the first via 141 may be a rectangle, a circle, an ellipse, or the like.
  • the size of the first via 141 may be 5-50 ⁇ m.
  • the size of the first via hole 141 may be 5 ⁇ m, 10 ⁇ m, 15 ⁇ m, 20 ⁇ m, 30 ⁇ m, 40 ⁇ m, or 50 ⁇ m, which is not limited herein.
  • the shape of the second via hole 142 may be a rectangle, a circle, an ellipse, or the like.
  • the size of the second via 142 may be 5-50 ⁇ m.
  • the size of the second via 142 may be 5 ⁇ m, 10 ⁇ m, 15 ⁇ m, 20 ⁇ m, 30 ⁇ m, 40 ⁇ m, or 50 ⁇ m, which is not limited herein.
  • the materials of the first signal driving line 111, the first signal transmission line 121, the second signal driving line 112, and the second signal transmission line 122 may all be set as metal materials.
  • the metal material may include: gold, silver, copper, aluminum, and the like.
  • the materials of the first signal driving line 111, the first signal transmission line 121, the second signal driving line 112, and the second signal transmission line 122 may be the same.
  • the conductive material in the first via hole and the second via hole may be the same as the material of the first signal driving line 111.
  • the present disclosure includes but is not limited to this.
  • the first signal transmission line 121 is electrically connected to the pins of the driving chip 130 through bonding terminals
  • the second signal transmission line 122 is also corresponding to the pins of the driving chip 130 through bonding terminals. Electric connection.
  • the first signal transmission line 121 and the second signal transmission line 122 may be provided in the same layer, the same material, and insulated. In this way, when the display panel is prepared, the patterns of the first signal transmission line 121 and the second signal transmission line 122 can be simultaneously formed through a patterning process, which can simplify the manufacturing process, save production costs, and improve production efficiency.
  • one first signal driving line 111 may correspond to one first via 141.
  • there are fewer first vias 141 on the base substrate 100 which not only simplifies the design difficulty of the first vias 141, but also improves the reliability of the base substrate 100.
  • the first via 141 in the same display area AA may be located in the first The same end of the signal driving line 111.
  • the first via holes 141 in the display areas AA-1 and AA-2 are located at the same end of the first signal driving line 111.
  • the first via 141 in the display areas AA-1 and AA-2 is located at the same position of the first signal driving line 111.
  • each display area AA that is, the first via 141 in the display areas AA-1 and AA-2 are located at the left end of the first signal driving line 111.
  • the first via 141 in the display areas AA-1 and AA-2 is located at the right end of the first signal driving line 111. This can further simplify the design difficulty of the first via 141.
  • one second signal driving line 112 may correspond to one second via 142.
  • the number of second vias 142 on the base substrate 100 can be reduced, which not only simplifies the design difficulty of the second vias 142, but also improves the reliability of the base substrate 100.
  • the second via holes 142 in the same display area AA can be located in the second The same end of the signal driving line 112.
  • each display area AA that is, all the second via holes 142 in the display areas AA-1 and AA-2 are located at the same end of the second signal driving line 112.
  • the second via 142 in the display areas AA-1 and AA-2 is located at the same position of the second signal driving line 112.
  • each display area AA that is, the second via 142 in the display areas AA-1 and AA-2 are located at the left end of the second signal driving line 112, or the second via 142 is located at the second signal driving line. 112 at the right end. This can further simplify the design difficulty of the second via 142.
  • FIG. 7a and FIG. 7b are modified for some implementations in the above-mentioned embodiments.
  • the following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities are not repeated here.
  • the display panel may have two display areas: AA-1 and AA-2. As shown in Fig. 7b, the display panel may also have 6 display areas: AA-1, AA-2, AA-3, AA-4, AA-5, AA-6.
  • part of the first via 141 is located at one end of the first signal driving line 111, and the remaining part of the first via 141 is located at the other end of the first signal driving line 111.
  • the first vias 141 corresponding to the first signal driving lines 111 in odd rows are located at one end of the first signal driving lines 111
  • the first vias 141 corresponding to the first signal driving lines 111 in even rows are located at one end of the first signal driving line 111.
  • 141 is located at the other end of the first signal driving line 111.
  • the first via 141 corresponding to the first signal driving line 111 in odd rows is located at the left end of the first signal driving line 111
  • the first via 141 corresponding to the first signal driving line 111 in even rows is located at the left end of the first signal driving line 111.
  • a signal drives the right end of the line 111.
  • the present disclosure includes but is not limited to this.
  • part of the second via 142 is located at one end of the second signal driving line 112, and the remaining part of the second via 142 is located at the other end of the second signal driving line 112.
  • the second via 142 corresponding to the second signal driving line 112 in odd columns is located at one end of the second signal driving line 112
  • the second via corresponding to the second signal driving line 112 in even columns is located at one end of the second signal driving line 112 in the same display area.
  • 142 is located at the other end of the second signal driving line 112.
  • the second via 142 corresponding to the second signal drive line 112 in odd columns is located at the lower end of the second signal drive line 112, and the second via 142 corresponding to the second signal drive line 112 in even columns is located at the bottom of the second signal drive line 112.
  • Two signals drive the upper end of the line 112.
  • the present disclosure includes but is not limited to this.
  • the positions of the first via holes 141 are the same, and the positions of the second via holes 142 are all the same.
  • the first via 141 corresponding to the first signal driving line 111 in odd rows is located at the left end of the first signal driving line 111
  • the first via 141 corresponding to the first signal driving line 111 in even rows is located at the first signal driving line 111. Drive the right end of the line 111.
  • the second via 142 corresponding to the second signal drive line 112 in the odd-numbered column is located at the lower end of the second signal drive line 112, and the second via 142 corresponding to the second signal drive line 112 in the even-numbered column is located at the second signal drive line 112 in the display area.
  • the embodiments of the present disclosure provide further structural schematic diagrams of display panels, as shown in FIG. 8, which are modified with respect to some implementations in the above-mentioned embodiments.
  • FIG. 8 Only the differences between this embodiment and the above-mentioned embodiment will be described, and the similarities will not be repeated here.
  • one first signal driving line 111 may also correspond to two first via holes 141.
  • the first signal driving line 111 can be electrically connected to the first signal transmission line 121 through the two first vias 141, so that the resistance of the first signal driving line 111 can be reduced, the signal attenuation can be reduced, and the display effect can be further improved.
  • two first vias 141 corresponding to the same first signal driving line 111 can be made, and one first via 141 is located on the first signal driving line.
  • One end of 111 and the other first via 141 is located at the other end of the first signal driving line 111.
  • a first via 141 is provided at the left end of each first signal driving line 111, and a first via 141 is also provided at the right end.
  • one second signal driving line 112 may also correspond to two second via holes 142.
  • the second signal driving line 112 and the second signal transmission line 122 can be electrically connected through the two second vias 142, so that the resistance of the second signal driving line 112 can be reduced, the signal attenuation can be reduced, and the display effect can be further improved.
  • two second vias 142 corresponding to the same second signal driving line 112 can be made, and one second via 142 is located on the second signal driving line.
  • One end of 112 and the other second via 142 are located at the other end of the second signal driving line 112.
  • a second via 142 is provided at the left end of each second signal driving line 112, and a second via 142 is also provided at the right end.
  • embodiments of the present disclosure also provide a method for manufacturing the above-mentioned display panel, which may include the following steps: forming multiple display areas on the same base substrate; wherein each display area includes multiple pixel units; and the pixel units include Multiple sub-pixels; sub-pixels include light-emitting chips.
  • the gap between two adjacent columns of pixel units has a first distance along the row direction, and the gap between two adjacent rows of pixel units has a second distance along the column direction.
  • the gap between the display areas closest to the row direction has a third distance along the row direction, and the third distance is substantially the same as the first distance; and/or,
  • the gap between the display areas closest to the column direction has a fourth pitch in the column direction, and the fourth pitch is substantially the same as the second pitch.
  • forming a plurality of display areas AA may include the following steps:
  • each display area AA on the same base substrate 100 a plurality of first signal driving lines 111 and a plurality of second signal driving lines 112 are formed; among them, the first signal driving line 111 and the second signal driving line 112 cross and insulated installation;
  • a conductive material is formed in each first via hole 141 and each second via hole 142, so that a first signal driving line 111 is electrically connected to a first signal transmission line 121 through a corresponding first via hole 141, and a second signal transmission line 121 is electrically connected.
  • the signal driving line 112 is electrically connected to a second signal transmission line 122 through a corresponding second via 142.
  • the conductive material may be a metal material.
  • the conductive material can be the same as the material of the first signal driving line 111, which can reduce the resistance and reduce the interference of signal transmission.
  • step S11 forming a plurality of first signal driving lines 111 and a plurality of second signal driving lines 112 in each display area AA on the same base substrate 100 may specifically include the following steps:
  • a buffer layer, an active layer, and a gate insulating layer are sequentially formed;
  • a capacitor electrode layer and an interlayer insulating layer are sequentially formed on the side of the interlayer dielectric layer away from the base substrate 100;
  • a second signal driving line 112 and a source/drain layer are formed on the side of the interlayer insulating layer away from the base substrate 100.
  • step S12 forming a plurality of first signal transmission lines 121 and a plurality of second signal transmission lines 122 on the side of the base substrate 100 away from the first signal driving line 111, may specifically include the following steps: adopting the same pattern In the process, a plurality of first signal transmission lines 121 and a plurality of second signal transmission lines 122 are formed on the side of the base substrate 100 away from the first signal driving line 111.
  • step S13 forming a plurality of channels penetrating through the base substrate 100
  • the first via 141 and the plurality of second vias 142 may specifically include the following steps: etching one end of the first signal transmission line 121 and one end of the second signal transmission line 122 to form a through-gate insulating layer and interlayer insulation Layer and the first via 141 and the second via 142 of the base substrate 100.
  • the structure of the formed display panel is as shown in FIG. 4, which will not be repeated here.
  • step S13 forming a penetrating through the base substrate 100
  • the plurality of first via holes 141 and the plurality of second via holes 142 may specifically include the following steps: etching both ends of the first signal transmission line 121 and both ends of the second signal transmission line 122 to form a through-gate insulating layer , The interlayer insulating layer and the first via 141 and the second via 142 of the base substrate 100.
  • the structure of the formed display panel is as shown in FIG. 8, and will not be repeated here.
  • forming a conductive material in each first via hole 141 and each second via hole 142 may specifically include the following steps:
  • a first photoresist layer is formed on the side of the base substrate 100 facing the first signal driving line 111, and a second photoresist layer is formed on the side of the base substrate 100 away from the first signal driving line 111;
  • a photoresist layer has a plurality of third via holes 143 and a plurality of fourth via holes 144, and the second photoresist layer has a plurality of fifth via holes and a plurality of sixth via holes;
  • the orthographic projection of the base substrate 100 covers the orthographic projection of a first via 141 on the base substrate 100, and the orthographic projection of a fourth via 144 on the base substrate 100 covers the orthographic projection of a second via 142 on the base substrate 100.
  • Orthographic projection the orthographic projection of a fifth via on the base substrate 100 covers the orthographic projection of a first via 141 on the base substrate 100, and the orthographic projection of a sixth via on the base substrate 100 covers a second via Orthographic projection of the hole 142 on the base substrate 100;
  • each first via 141, each second via 142, and each third via 143 Using one of sputtering process, atomic layer deposition process, evaporation process, electron beam evaporation process, and electrochemical deposition process, in each first via 141, each second via 142, and each third via 143 , Each fourth via hole 144, each fifth via hole, and each sixth via hole are filled with conductive material.
  • each first via 141, each second via 142, each third via 143, each fourth via 144, each fifth via, and each sixth via is filled with a conductive material
  • it may further include: removing the first photoresist layer and the second photoresist layer. This can reduce the thickness of the display panel.
  • the first photoresist layer and the second photoresist layer may not be removed, so that the first photoresist layer and the second photoresist layer can be used to permanently protect the display panel.
  • the edge of the third via 143 on the orthographic projection of the base substrate 100 and the edge of the corresponding first via 141 on the orthographic projection of the base substrate 100 have a first preset distance.
  • the fourth via 144 has a second predetermined distance between the edge of the orthographic projection of the base substrate 100 and the edge of the corresponding second via 142 of the orthographic projection of the base substrate 100.
  • first preset distance second preset distance
  • third preset distance fourth preset distance between the edge of the sixth via hole in the orthographic projection of the base substrate 100 and the edge of the corresponding second via hole 142 in the orthographic projection of the base substrate 100. It should be noted that the above-mentioned first preset distance, second preset distance, third preset distance, and fourth preset distance may be determined according to the accuracy required in the preparation process, which is not limited herein.
  • the above preparation method will be described below by taking the preparation of the display panel shown in FIG. 7a as an example.
  • the preparation method provided by the embodiment of the present disclosure may include the following steps:
  • each display area AA ie AA-1, AA-2) in one base substrate 100, a buffer layer, an active layer, and a gate insulating layer are sequentially formed.
  • the first signal driving line 111 and the gate layer are formed on the side of the gate insulating layer away from the base substrate 100.
  • An interlayer dielectric layer, a capacitor electrode layer and an interlayer insulating layer are sequentially formed on the side of the first signal driving line 111 and the gate layer away from the base substrate 100.
  • a second signal driving line 112 and a source/drain layer are formed on the side of the interlayer insulating layer away from the base substrate 100.
  • a plurality of first signal transmission lines 121 and a plurality of second signal transmission lines 122 are formed on the side of the base substrate 100 away from the first signal driving line 111.
  • Etching is performed on one end of the first signal transmission line 121 and one end of the second signal transmission line 122 to form a first via 141 and a second via that penetrate the gate insulating layer, the interlayer insulating layer, and the base substrate 100 142.
  • a first photoresist layer is formed on the side of the base substrate 100 facing the first signal driving line 111, and a second photoresist layer is formed on the side of the base substrate 100 away from the first signal driving line 111;
  • the first photoresist layer has a plurality of third vias 143 and a plurality of fourth vias 144
  • the second photoresist layer has a plurality of fifth vias and a plurality of sixth vias
  • a third via The orthographic projection of the hole 143 on the base substrate 100 covers the orthographic projection of a first via 141 on the base substrate 100, and the orthographic projection of a fourth via 144 on the base substrate 100 covers a second via 142 on the substrate.
  • the orthographic projection of the substrate 100, the orthographic projection of a fifth via on the base substrate 100 covers the orthographic projection of a first via 141 on the base substrate 100, and the orthographic projection of a sixth via on the base substrate 100 covers one The orthographic projection of the second via 142 on the base substrate 100.
  • the gap between the display areas AA of the display panel closest in the row direction F1 has a fifth distance W5 in the row direction F1, and the fifth distance W5 is approximately the same as the first distance W1; and/or, is closest in the column direction F2
  • the gap between the display areas AA of adjacent display panels has a sixth pitch W6 along the column direction F2, and the sixth pitch W6 is substantially the same as the second pitch W2. It should be noted that, for the first distance W1 and the second distance W2, reference may be made to the above description of the first distance W1 and the second distance W2, which will not be repeated here.
  • the spliced display panel provided by the embodiment of the present invention can splice the above-mentioned multiple display panels provided with multiple display areas, and can realize a larger size spliced display panel product. In this way, compared to using independent display areas for multiple splicing, the number of splicing seams can be greatly reduced, thereby reducing the problems of visibility and reliability of splicing seams caused by splicing seams.
  • the above-mentioned one display panel with multiple display areas can be used as a splicing unit, so as to realize a larger-sized display panel by splicing these display panels.
  • the product In this way, compared to using independent display areas AA for multiple splicing, the number of splicing seams can be greatly reduced, thereby reducing the problems of visibility and reliability of splicing seams caused by splicing seams.
  • two of the above-mentioned display panels may be used for splicing to form a spliced display panel.
  • the display panels 300-1 and 300-2 are used for splicing to form a spliced display panel, and each display panel 300-1 and 300-2 includes two adjacent display areas AA. That is, the display panel 300-1 includes two display areas AA, and the display panel 300-2 includes two display areas AA.
  • the display panels 300-1 to 300-4 are used to form a spliced display panel.
  • Each display panel 300-1 to 300-4 may include six adjacent display areas AA.
  • the display area AA in the display panel 300-1 shares a base substrate 100
  • the display area AA in the display panel 300-2 shares a base substrate 100
  • the display area AA in the display panel 300-3 shares a base substrate 100.
  • the substrate 100 and the display area AA in the display panel 300-4 share a base substrate 100.
  • more display panels can also be used to form a spliced display panel by splicing, which is not limited here.
  • the gap has a fifth pitch W5 in the row direction F1, and the fifth pitch W5 can be substantially the same as the first pitch W1. In this way, by making the fifth pitch W5 approximately the same as the first pitch W1, the gap between the nearest adjacent display area AA in the panel group adjacent in the row direction F1 and the two adjacent columns of pixel units PX in the display area AA can be adjusted.
  • the gap between the two is approximately the same as the gap along the row direction F1, that is, the gap between two adjacent display areas AA of the same base substrate 100 can be approximately the same as the gap between the pixel units PX, so that It can further reduce the problem of the visibility of the splicing seam.
  • the above-mentioned fifth pitch W5 and the first pitch W1 may not be completely the same, and there may be some deviations.
  • the ratio between the fifth pitch W5 and the first pitch W1 can be Satisfy It can be stated that the fifth pitch W5 is the same as the first pitch W1.
  • the distance between the fifth interval W5 and the first interval W1 ratio It can also be set according to the critical value that human eyes can recognize that there is a clear gap between the display areas.
  • the ratio between the fifth distance W5 and the first distance W1 can also be set together according to the above two methods.
  • the fifth pitch W5 is substantially the same as the first pitch W1.
  • the gap between the display areas AA of the nearest neighboring display areas AA in the panel groups adjacent to each other in the column direction F2 There is a sixth pitch W6 along the column direction F2, and the sixth pitch W6 is substantially the same as the second pitch W2.
  • the gap between the display area AA of the nearest display area AA in the panel group adjacent in the column direction F2 can be adjusted to the two adjacent rows in the display area AA.
  • the gap between the pixel units PX is approximately the same as the gap along the column direction F2. That is to say, the gap between the two adjacent display areas AA of the same base substrate 100 can be changed from the gap between the pixel units PX. Roughly the same, which can further reduce the problem of the visibility of the seam.
  • the above-mentioned sixth pitch W6 and the second pitch W2 may not be completely the same, and there may be some deviations.
  • the ratio between the sixth pitch W6 and the second pitch W2 can be Satisfy It can be stated that the sixth pitch W6 is the same as the second pitch W2.
  • the distance between the sixth interval W6 and the second interval W2 ratio It can also be set according to the critical value that human eyes can recognize that there is a clear gap between the display areas.
  • the ratio between the sixth interval W6 and the second interval W2 can also be set together according to the above two methods.
  • the sixth pitch W6 is substantially the same as the second pitch W2.
  • At least one of the above-mentioned display panel and the spliced display panel provided by the embodiments of the present disclosure may be applied to a large-size display device.
  • the display device may be any product or component with a display function such as a display.
  • Other indispensable components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, and should not be used as a limitation to the present disclosure.
  • the display panel, the spliced display panel, and the manufacturing method thereof provided by the embodiments of the present disclosure are provided by arranging a plurality of display areas on a base substrate, and each display area is provided with a plurality of light-emitting chips, so that when the display panel is prepared, After the light-emitting chip is prepared on one base substrate, multiple display areas can be formed.
  • the third pitch may be approximately the same as the first pitch and/or the fourth pitch may be approximately the same as the second pitch, so as to make a uniform transition between the display area and the display area, thereby reducing the splicing caused by the splicing accuracy of the splicing process.
  • the problem of larger seams can improve the display effect.
  • one base substrate can be used to form multiple display areas for splicing, there is no need to prepare multiple independent display areas first, and then splice these independent display areas into display panels, so that splicing is not required.
  • the process can form a large-size display panel and improve production efficiency.

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Abstract

一种显示面板、拼接显示面板、其制备方法，其中，显示面板包括：衬底基板（100），衬底基板（100）上设置有多个显示区（AA）；各显示区（AA）包括多个像素单元（PX）；像素单元（PX）包括多个子像素（spx）；子像素（spx）包括发光芯片（210）；其中，同一显示区（AA）中，相邻两列像素单元（PX）之间的间隙在沿行方向（F1）上具有第一间距（W1），并且，相邻两行像素单元（PX）之间的间隙在沿列方向（F2）上具有第二间距（W2）；沿行方向（F1）最近邻的显示区（AA）之间的间隙在沿行方向（F1）上具有第三间距（W3），第三间距（W3）与第一间距（W1）大致相同；和/或，沿列方向（F2）最近邻的显示区（AA）之间的间隙在沿列方向（F2）上具有第四间距（W4），第四间距（W4）与第二间距（W2）大致相同。

Description

显示面板、拼接显示面板、其制备方法 技术领域
本公开涉及显示技术领域，特别涉及显示面板、拼接显示面板、其制备方法。
背景技术
一般，由于工艺制程等因素，大尺寸的显示面板通常需要采用多个小尺寸的显示面板进行拼接形成。然而，由于拼接工艺的限定，导致小尺寸的显示面板之间的拼接缝较大，从而导致显示效果不佳。
发明内容
本公开实施例提供的显示面板，包括：
衬底基板，所述衬底基板上设置有多个显示区；各所述显示区包括多个像素单元；所述像素单元包括多个子像素；所述子像素包括发光芯片；
其中，同一所述显示区中，相邻两列像素单元之间的间隙在沿行方向上具有第一间距，并且，相邻两行像素单元之间的间隙在沿列方向上具有第二间距；
沿所述行方向最近邻的显示区之间的间隙在沿所述行方向上具有第三间距，所述第三间距与所述第一间距大致相同；和/或，
沿所述列方向最近邻的显示区之间的间隙在沿所述列方向上具有第四间距，所述第四间距与所述第二间距大致相同。
可选地，在本公开实施例中，所述显示区中的子像素阵列排布，并且所述子像素还包括被配置为驱动所述发光芯片的驱动电路。
可选地，在本公开实施例中，每一所述显示区包括：位于所述衬底基板与所述发光芯片之间的多条第一信号驱动线和多条第二信号驱动线；其中，所述第一信号驱动线和所述第二信号驱动线交叉且绝缘设置；
一行子像素中的驱动电路电连接一条所述第一信号驱动线，一列子像素中的驱动电路电连接一条所述第二信号驱动线。
可选地，在本公开实施例中，每一所述显示区包括：位于所述衬底基板背离所述发光芯片一侧的多条第一信号传输线、多条第二信号传输线以及分别与所述第一信号传输线和所述第二信号传输线电连接的驱动芯片；
一条所述第一信号驱动线通过对应贯穿所述衬底基板的第一过孔与一条所述第一信号传输线电连接；且一条所述第二信号驱动线通过对应贯穿所述衬底基板的第二过孔与一条所述第二信号传输线电连接。
可选地，在本公开实施例中，一条所述第一信号驱动线对应一个所述第一过孔；各所述第一过孔位于所述第一信号驱动线的同一端。
可选地，在本公开实施例中，一条所述第一信号驱动线对应一个所述第一过孔；部分所述第一过孔位于所述第一信号驱动线的一端，其余部分所述第一过孔位于所述第一信号驱动线的另一端。
可选地，在本公开实施例中，奇数行第一信号驱动线对应的第一过孔位于所述第一信号驱动线的一端，偶数行第一信号驱动线对应的第一过孔位于所述第一信号驱动线的另一端。
可选地，在本公开实施例中，一条所述第一信号驱动线对应两个所述第一过孔；一个所述第一过孔位于所述第一信号驱动线的一端，另一个所述第一过孔位于所述第一信号驱动线的另一端。
可选地，在本公开实施例中，一条所述第二信号驱动线对应一个所述第二过孔；各所述第二过孔位于所述第二信号驱动线的同一端。
可选地，在本公开实施例中，一条所述第二信号驱动线对应一个所述第二过孔；部分所述第二过孔位于所述第二信号驱动线的一端，其余部分所述第二过孔位于所述第二信号驱动线的另一端。
可选地，在本公开实施例中，奇数列第二信号驱动线对应的第二过孔位于所述第二信号驱动线的一端，偶数列第二信号驱动线对应的第二过孔位于所述第二信号驱动线的另一端。
可选地，在本公开实施例中，一条所述第二信号驱动线对应两个所述第二过孔；一个所述第二过孔位于所述第二信号驱动线的一端，另一个所述第二过孔位于所述第二信号驱动线的另一端。
本公开实施例提供的上述显示面板的制备方法，包括：
在同一所述衬底基板上形成多个所述显示区；其中，各所述显示区包括多个像素单元；所述像素单元包括多个子像素；所述子像素包括发光芯片；
其中，同一所述显示区中，相邻两列像素单元之间的间隙在沿行方向上具有第一间距，并且，相邻两行像素单元之间的间隙在沿列方向上具有第二间距；
沿所述行方向最近邻的显示区之间的间隙在沿所述行方向上具有第三间距，所述第三间距与所述第一间距大致相同；和/或，
沿所述列方向最近邻的显示区之间的间隙在沿所述列方向上具有第四间距，所述第四间距与所述第二间距大致相同。
可选地，在本公开实施例中，所述形成多个所述显示区，包括：
在同一所述衬底基板中的每个所述显示区内，形成多条第一信号驱动线和多条第二信号驱动线；其中，所述第一信号驱动线和所述第二信号驱动线交叉且绝缘设置；
在所述衬底基板背离所述第一信号驱动线的一侧形成多条第一信号传输线和多条第二信号传输线；
形成多个第一过孔和多个第二过孔；
在各所述第一过孔和各所述第二过孔中形成导电材料，使一条所述第一信号驱动线通过对应的第一过孔与一条所述第一信号传输线电连接，一条所述第二信号驱动线通过对应的第二过孔与一条所述第二信号传输线电连接。
可选地，在本公开实施例中，所述在各所述第一过孔和各所述第二过孔中形成导电材料，包括：
在所述衬底基板面向所述第一信号驱动线的一侧形成第一光刻胶层，以及在所述衬底基板背离所述第一信号驱动线的一侧形成第二光刻胶层；其中， 所述第一光刻胶层具有多个第三过孔和多个第四过孔，所述第二光刻胶层具有多个第五过孔和多个第六过孔；一个所述第三过孔在所述衬底基板的正投影覆盖一个所述第一过孔在所述衬底基板的正投影，一个所述第四过孔在所述衬底基板的正投影覆盖一个所述第二过孔在所述衬底基板的正投影，一个所述第五过孔在所述衬底基板的正投影覆盖一个所述第一过孔在所述衬底基板的正投影，一个所述第六过孔在所述衬底基板的正投影覆盖一个所述第二过孔在所述衬底基板的正投影；
采用溅射工艺、原子层淀积工艺、蒸镀工艺、电子束蒸发工艺以及电化学沉积工艺中的一种，在各所述第一过孔、各所述第二过孔、各所述第三过孔、各所述第四过孔、各所述第五过孔以及各所述第六过孔中填充导电材料。
可选地，在本公开实施例中，在所述在各所述第一过孔、各所述第二过孔、各所述第三过孔、各所述第四过孔、各所述第五过孔以及各所述第六过孔中填充导电材料之后，还包括：
去除所述第一光刻胶层和所述第二光刻胶层。
本公开实施例提供的拼接显示面板，包括：多个上述显示面板；
沿所述行方向最近邻的显示面板的显示区之间的间隙在所述沿行方向上具有第五间距，所述第五间距与所述第一间距大致相同；和/或，
沿所述列方向最近邻的显示面板的显示区之间的间隙在沿列方向上具有第六间距，所述第六间距与所述第二间距大致相同。
附图说明
图1为本公开实施例提供的一些显示面板的俯视结构示意图；
图2为图1所示的显示面板中沿AA’方向上的剖视结构示意图；
图3a为本公开实施例提供的驱动电路的结构示意图；
图3b为本公开实施例提供的显示面板中一个子像素的剖视结构示意图；
图4为本公开实施例提供的又一些显示面板的出光侧的俯视结构示意图；
图5为本公开实施例提供的一些显示面板背离发光芯片一侧的俯视结构 示意图；
图6a为图4所示的显示面板中沿AA’方向上的剖视结构示意图；
图6b为图4所示的显示面板中沿BB’方向上的剖视结构示意图；
图7a为本公开实施例提供的又一些显示面板的俯视结构示意图；
图7b为本公开实施例提供的又一些显示面板的俯视结构示意图；
图8为本公开实施例提供的又一些显示面板的俯视结构示意图；
图9为本公开实施例提供的又一些显示面板的俯视结构示意图；
图10为本公开实施例提供的又一些显示面板的俯视结构示意图；
图11为本公开实施例提供的制备方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本公开实施例提供的显示面板，如图1与图2所示，包括：
衬底基板100，该衬底基板100上设置有多个显示区AA；各显示区AA包括：多个像素单元PX；像素单元PX包括多个子像素spx；子像素spx包括发光芯片210；
其中，同一显示区AA中，相邻两列像素单元PX之间的间隙在沿行方向F1上具有第一间距W1，并且相邻两行像素单元PX之间的间隙在沿列方向F2上具有第二间距W2。
并且，沿行方向F1最近邻的显示区AA之间的间隙在沿行方向F1上具有第三间距W3，可以使第三间距W3与第一间距W1大致相同。和/或，沿列方向F2最近邻的显示区AA之间的间隙在沿列方向F2上具有第四间距W4，可以使第四间距W4与第二间距W2大致相同。
本公开实施例提供的上述显示面板中，通过在一个衬底基板上设置多个显示区，并且，每个显示区设置有多个发光芯片，这样在制备显示面板时，可以在一个衬底基板上制备发光芯片后，形成多个显示区。这样可以使第三间距与第一间距大致相同和/或第四间距与第二间距大致相同，以使显示区与显示区之间均匀过渡，从而可以降低由于拼接工艺的拼接精度导致的拼接缝较大的问题，提高显示效果。并且，由于采用一个衬底基板即可以形成多个用于拼接的显示区，可以不用再先制备多个独立的显示区，再将这些独立的显示区进行拼接成显示面板，从而可以不采用拼接工艺即可以形成大尺寸显示面板，提高生产效率。
在具体实施时，在本公开实施例中，如图1与图2所示，可以使所有显示区AA共用一个衬底基板100。例如可以具有6个显示区，并使这6个显示区AA共用同一个衬底基板100。这样可以仅仅需要一个衬底基板100，即可形成大尺寸显示面板。并且，由于直接在该衬底基板100上形成多个显示区AA，相当于在衬底基板100上进行分区，因此相邻的两个显示区AA共用一条亚微米精度的边界，从而可以不采用拼接工艺即可以形成大尺寸显示面板。因此，随着分辨率的增加，不会产生拼接缝可见的问题，进一步降低拼接缝 对显示效果的影响。并且，这样还可以最大程度的利用衬底基板100的尺寸，进而可以实现无边框或超窄边框的显示面板。
需要说明的是，衬底基板上设置的显示区的数量可以为2个、3个、4个、6个或更多个。在实际应用中，可以根据实际应用环境来设计确定，在此不作限定。
示例性地，在制备过程中，衬底基板100通常采用玻璃基板。一般玻璃基板的尺寸可以达到110英寸左右，而显示区AA的尺寸通常为11英寸，因此，110英寸以内的显示面板均可以采用一块衬底基板100进行制备。这样可以不需要通过物理拼接即可实现大尺寸显示面板的产品。
在具体实施时，在本公开实施例中，如图1与图2所示，同一显示区AA中，相邻两列像素单元PX之间的间隙在沿行方向F1上具有第一间距W1。进一步地，每一个显示区AA中的第一间距W1可以大致相同。需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素，每一个显示区AA中的第一间距W1并不能完全相同，可能会有一些偏差，因此每一个显示区AA中的第一间距W1之间的相同关系只要大致满足相同条件即可，均属于本公开的保护范围。例如，每一个显示区AA中的第一间距W1可以是在误差允许范围之内所允许的相同。
示例性地，针对共用同一衬底基板100的显示区AA，沿行方向F1最近邻的显示区AA之间的间隙在沿行方向F1上具有第三间距W3，可以使第三间距W3与第一间距W1大致相同。这样通过使第三间距W3与第一间距W1大致相同，可以将沿行方向F1最近邻的显示区AA之间的间隙与显示区AA中相邻两列像素单元PX之间的间隙在沿行方向F1的间隙制备的大致相同，也就是说，可以将同一衬底基板100的相邻两个显示区AA的显示画面之间的间隙与像素单元PX之间的间隙大致相同，从而可以进一步降低拼接缝可视性的问题。
需要说明的是，实际工艺中，由于工艺条件的限制或其他因素，上述第三间距W3与第一间距W1并不能完全相同，可能会有一些偏差。在具体实施 时，可以使第三间距W3与第一间距W1之间的比值
Figure PCTCN2019118919-appb-000001
满足
Figure PCTCN2019118919-appb-000002
时可以说明第三间距W3与第一间距W1是相同的。例如，在实际应用中，例如在W1＝500μm时，那么W3选取300μm～700μm之间的数值，即可以说明第三间距W3与第一间距W1是相同的。
由于人眼的识别能力，若显示区之间的间隙在一定范围内时，人眼可能不会识别出显示区之间存在明显的间隙，因此，第三间距W3与第一间距W1之间的比值
Figure PCTCN2019118919-appb-000003
还可以根据人眼能识别出显示区之间存在明显的间隙大小的临界值进行设定。
当然，还可以根据上述两个方式共同设定第三间距W3与第一间距W1之间的比值
Figure PCTCN2019118919-appb-000004
以满足第三间距W3与第一间距W1大致相同的条件。这些均属于本公开的保护范围。
在具体实施时，在本公开实施例中，如图1所示，同一显示区AA中，相邻两行像素单元PX之间的间隙在沿列方向F2上具有第二间距W2。进一步地，每一个显示区AA中的第二间距W2可以大致相同。需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素，每一个显示区AA中的第二间距W2并不能完全相同，可能会有一些偏差，因此每一个显示区AA中的第二间距W2之间的相同关系只要大致满足相同条件即可，均属于本公开的保护范围。例如，每一个显示区AA中的第二间距W2可以是在误差允许范围之内所允许的相同。
示例性地，针对共用同一衬底基板100的显示区AA，沿列方向F2最近邻的显示区AA之间的间隙在沿列方向F2上具有第四间距W4，可以使第四间距W4与第二间距W2大致相同。这样通过使第四间距W4与第二间距W2大致相同，可以将沿列方向F2最近邻的显示区AA之间的间隙与显示区AA中相邻两行像素单元PX之间的间隙在沿列方向F2的间隙制备的大致相同，也就是说，可以将同一衬底基板100的相邻两个显示区AA的显示画面之间 的间隙与像素单元PX之间的间隙大致相同，从而可以进一步降低拼接缝可视性的问题。
需要说明的是，实际工艺中，由于工艺条件的限制或其他因素，上述第四间距W4与第二间距W2并不能完全相同，可能会有一些偏差。在具体实施时，可以使第四间距W4与第二间距W2之间的比值
Figure PCTCN2019118919-appb-000005
满足
Figure PCTCN2019118919-appb-000006
时可以说明第四间距W4与第二间距W2是相同的。例如，在实际应用中，例如在W2＝500μm时，那么W4选取300μm～700μm之间的数值，即可以说明第四间距W4与第二间距W2是相同的。
由于人眼的识别能力，若显示区之间的间隙在一定范围内时，人眼可能不会识别出显示区之间存在明显的间隙，因此，第四间距W4与第二间距W2之间的比值
Figure PCTCN2019118919-appb-000007
还可以根据人眼能识别出显示区之间存在明显的间隙大小的临界值进行设定。
当然，还可以根据上述两个方式共同设定第四间距W4与第二间距W2之间的比值
Figure PCTCN2019118919-appb-000008
以满足第四间距W4与第二间距W2大致相同的条件。这些均属于本公开的保护范围。
在具体实施时，在本公开实施例中，如图1所示，显示面板可以包括：位于各显示区AA中阵列排布的多个像素单元PX。每个像素单元PX可以包括多个子像素spx。进一步地，显示区AA中的子像素spx可以阵列排布。示例性地，像素单元PX可以包括红色子像素，绿色子像素以及蓝色子像素，这样可以通过红绿蓝进行混色，以实现彩色显示。或者，像素单元PX也可以包括红色子像素，绿色子像素、蓝色子像素以及白色子像素，这样可以通过红绿蓝白进行混色，以实现彩色显示。当然，在实际应用中，像素单元PX中的子像素spx的发光颜色和具体数量可以根据实际应用环境来设计确定，在此不作限定。
在具体实施时，在本公开实施例中，子像素spx还可以包括被配置为驱动 发光芯片210发光的驱动电路。其中，发光芯片210可以为发光二极管(Light Emitting Diode，LED)、微型发光二极管(Micro Light Emitting Diode，Micro LED)以及迷你发光二极管(Mini Light Emitting Diode，Mini LED)中的至少一种。例如，Micro LED的正极作为发光芯片210的第一端，Micro LED的负极作为发光芯片210的第二端。
在具体实施时，在本公开实施例中，如图3a所示，驱动电路可以包括：开关晶体管M01、驱动晶体管M0以及存储电容C0。
第一开关晶体管M01的栅极与扫描信号端SCAN电连接，第一开关晶体管M01的第一极与数据信号端DATA电连接，第一开关晶体管M01的第二极与驱动晶体管M0的栅极电连接。
驱动晶体管M0的第一端与第一电源端VDD电连接，驱动晶体管M0的第二端与发光芯片210的第一端电连接，且发光芯片210的第二端与第二电源端VSS电连接。
存储电容C0的第一端与第一电源端VDD电连接，存储电容C0的第二端与驱动晶体管M0的栅极电连接。
上述驱动电路的工作过程可以与相关技术中的工作过程基本相同，在此不作赘述。当然，在实际应用中，驱动电路还可以采用其他结构，在此不作限定。
示例性地，如图2至图3b所示，显示面板还可以包括：晶体管阵列层220，用于形成上述晶体管的各个膜层以及形式上述电容的各个膜层。其中，晶体管阵列层220位于发光芯片210与衬底基板100之间。示例性地，晶体管阵列层220可以包括：位于衬底基板100一侧的有源层221，位于有源层221背离衬底基板100一侧的栅极层222，位于栅极层222背离衬底基板100一侧的电容电极层223，位于电容电极层223背离衬底基板100一侧的源漏电极层224(具有源极2241与漏极2242)。其中，有源层221、栅极层222以及电容电极层223相互绝缘设置，源漏电极层224、栅极层222以及电容电极层223相互绝缘设置，源极2241与漏极2242分别与有源层221电连接。并且，晶 体管阵列层220还包括：位于衬底基板100与有源层221之间的缓冲层225，位于有源层221与栅极层222之间的栅绝缘层226以使有源层221与栅极层222绝缘设置，位于栅极层222与电容电极层223之间的层间介质层227以使栅极层222与电容电极层223绝缘设置，位于电容电极层223与源漏电极层224之间的层间绝缘层228以使电容电极层223与源漏电极层224绝缘设置，位于源漏电极层224与发光芯片210之间的平坦化层229，发光芯片210的第一端通过贯穿平坦化层229过孔与漏极2242电连接，并且，发光芯片210的第二端与阴极电源线电连接，从而通过漏极2242向发光芯片210提供驱动信号，并且通过阴极电源线向第二电源端VSS提供给低电压信号，以向发光芯片210的第二端提供低电压信号，以驱动发光芯片210发光。并且，电容电极层223与栅极层222形成了电容结构。需要说明的是，图3b仅是以一个子像素spx中的一个晶体管为例进行说明的。
在具体实施时，在本公开实施例中，如图4、图6a以及图6b所示，每一显示区AA可以包括：多条第一信号驱动线111和多条第二信号驱动线112；其中，第一信号驱动线111和第二信号驱动线112交叉且绝缘设置。示例性地，第一信号驱动线111和第二信号驱动线112位于衬底基板100与发光芯片210之间。需要说明的是，图4仅是以两个显示区AA为例进行说明的，其中一个显示区为AA-1，另一个显示区为AA-2。
示例性地，如图4所示，第一信号驱动线111可以沿子像素spx的行方向F1延伸，第二信号驱动线112可以沿子像素spx的列方向F2延伸。一行子像素spx中的驱动电路电连接一条第一信号驱动线111，一列子像素spx中的驱动电路电连接一条第二信号驱动线112。这样可以通过第一信号驱动线111和第二信号驱动线112向驱动电路传输信号，以使驱动电路驱动发光芯片210发光。例如，一行子像素spx中的驱动电路的扫描信号端SCAN电连接一条第一信号驱动线111，一列子像素spx中的驱动电路的数据信号端DATA电连接一条第二信号驱动线112。当然，本发明包括但不限于此。
示例性地，第一信号驱动线111可以与栅极层222同层设置。这样在制 备显示面板时，可以通过一次构图工艺同时形成栅极层222和第一信号驱动线111的图形，不用增加单独制备第一信号驱动线111的工艺，可以简化制备工艺流程，节省生产成本，提高生产效率。
示例性地，第二信号驱动线112可以与源漏电极层224同层设置。这样在制备显示面板时，只需在形成源漏电极层224的图形时改变原有的构图图形，通过一次构图工艺同时形成源漏电极层224的图形和第二信号驱动线112的图形，不用增加单独制备第二信号驱动线112的工艺，可以简化制备工艺流程，节省生产成本，提高生产效率。
在具体实施时，在本公开实施例中，如图4至图6b所示，每一显示区AA(例如AA-1，AA-2)可以包括：位于衬底基板100背离发光芯片210一侧的多条第一信号传输线121、多条第二信号传输线122以及分别与第一信号传输线121和第二信号传输线122电连接的驱动芯片130；其中，一条第一信号驱动线111通过对应贯穿衬底基板100的第一过孔141与一条第一信号传输线121电连接；且一条第二信号驱动线112通过对应贯穿衬底基板100的第二过孔142与一条第二信号传输线122电连接。这样在驱动显示面板显示时，可以通过驱动芯片130产生驱动发光芯片210发光的驱动信号，然后采用第一信号传输线121和第二信号传输线122分别将驱动信号传输到第一信号驱动线111和第二信号驱动线112，以驱动发光芯片210发光。
示例性地，如图6a所示，第一过孔141可以贯穿衬底基板100、缓冲层225、栅绝缘层226。也就是说，一条第一信号驱动线111通过贯穿衬底基板100、缓冲层225以及栅绝缘层226的第一过孔141中的导电材料与一条第一信号传输线121电连接。当然，本公开包括但不限于此。
示例性地，如图6b所示，第二过孔142可以贯穿衬底基板100、缓冲层225、栅绝缘层226、层间介质层227以及层间绝缘层228。也就是说，一条第二信号驱动线112通过贯穿衬底基板100、缓冲层225、栅绝缘层226、层间介质层227以及层间绝缘层228的第二过孔142中的导电材料与一条第二信号传输线122电连接。当然，本公开包括但不限于此。
在具体实施时，在本公开实施例中，在俯视显示面板时，第一过孔141的形状可以为矩形、圆形、椭圆形等形状。示例性地，第一过孔141的尺寸可以为5～50μm。例如，第一过孔141的尺寸可以为5μm、10μm、15μm、20μm、30μm、40μm或50μm，在此不作限定。
在具体实施时，在本公开实施例中，在俯视显示面板时，第二过孔142的形状可以为矩形、圆形、椭圆形等形状。示例性地，第二过孔142的尺寸可以为5～50μm。例如，第二过孔142的尺寸可以为5μm、10μm、15μm、20μm、30μm、40μm或50μm，在此不作限定。
在具体实施时，在本公开实施例中，第一信号驱动线111、第一信号传输线121、第二信号驱动线112、第二信号传输线122的材料可以均设置为金属材料。示例性地，金属材料可以包括：金、银、铜、铝等。
示例性地，第一信号驱动线111、第一信号传输线121、第二信号驱动线112、第二信号传输线122的材料可以相同。进一步地，第一过孔和第二过孔中的导电材料可以与第一信号驱动线111的材料相同。当然，本公开包括但不限于此。
在具体实施时，在本公开实施例中，第一信号传输线121通过邦定端子与驱动芯片130的引脚对应电连接，第二信号传输线122也通过邦定端子与驱动芯片130的引脚对应电连接。
在具体实施时，在本公开实施例中，第一信号传输线121和第二信号传输线122可以同层同材质且绝缘设置。这样在制备显示面板时，可以通过一次构图工艺同时形成第一信号传输线121和第二信号传输线122的图形，可以简化制备工艺流程，节省生产成本，提高生产效率。
在具体实施时，在本公开实施例中，如图4与图5所示，可以使一条第一信号驱动线111对应一个第一过孔141。这样可以使衬底基板100上的第一过孔141较少，不仅可以简化第一过孔141的设计难度，还可以提高衬底基板100的信赖性。
在具体实施时，在本公开实施例中，如图4与图5所示，可以使同一显 示区AA中，即显示区AA-1和AA-2中的各第一过孔141位于第一信号驱动线111的同一端。示例性地，每一个显示区AA中，即显示区AA-1和AA-2中的所有第一过孔141位于第一信号驱动线111的同一端。进一步地，每一个显示区AA中，即显示区AA-1和AA-2中的第一过孔141所位于第一信号驱动线111的位置均相同。例如，每一个显示区AA中，即显示区AA-1和AA-2中的第一过孔141均位于第一信号驱动线111的左端。或者，显示区AA-1和AA-2中的第一过孔141位于第一信号驱动线111的右端。这样可以进一步简化第一过孔141的设计难度。
在具体实施时，在本公开实施例中，如图4与图5所示，可以使一条第二信号驱动线112对应一个第二过孔142。这样可以使衬底基板100上的第二过孔142较少，不仅可以简化第二过孔142的设计难度，还可以提高衬底基板100的信赖性。
在具体实施时，在本公开实施例中，如图4与图5所示，可以使同一显示区AA中，即显示区AA-1和AA-2中的各第二过孔142位于第二信号驱动线112的同一端。示例性地，每一个显示区AA中，即显示区AA-1和AA-2中的所有第二过孔142位于第二信号驱动线112的同一端。进一步地，每一个显示区AA中，即显示区AA-1和AA-2中的第二过孔142所位于第二信号驱动线112的位置均相同。例如，每一个显示区AA中，即显示区AA-1和AA-2中的第二过孔142均位于第二信号驱动线112的左端，或者，第二过孔142位于第二信号驱动线112的右端。这样可以进一步简化第二过孔142的设计难度。
本公开实施例提供了又一些显示面板的结构示意图，如图7a与图7b所示，其针对上述实施例中的部分实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图7a所示，显示面板可以具有2个显示区：AA-1、AA-2。如图7b所示，显示面板也可以具有6个显示区：AA-1、AA-2、AA-3、AA-4、AA-5、AA-6。
在具体实施时，在本公开实施例中，如图7a与图7b所示，可以使同一显示区中，部分第一过孔141位于第一信号驱动线111的一端，其余部分第一过孔141位于第一信号驱动线111的另一端。示例性地，可以使同一显示区中，奇数行第一信号驱动线111对应的第一过孔141位于第一信号驱动线111的一端，偶数行第一信号驱动线111对应的第一过孔141位于第一信号驱动线111的另一端。例如，每一个显示区中，奇数行第一信号驱动线111对应的第一过孔141位于第一信号驱动线111的左端，偶数行第一信号驱动线111对应的第一过孔141位于第一信号驱动线111的右端。这样可以进一步提高衬底基板100的信赖性。当然，本公开包括但不限于此。
在具体实施时，在本公开实施例中，如图7a与图7b所示，可以使同一显示区中，部分第二过孔142位于第二信号驱动线112的一端，其余部分第二过孔142位于第二信号驱动线112的另一端。示例性地，可以使同一显示区中，奇数列第二信号驱动线112对应的第二过孔142位于第二信号驱动线112的一端，偶数列第二信号驱动线112对应的第二过孔142位于第二信号驱动线112的另一端。例如，每一个显示区中，奇数列第二信号驱动线112对应的第二过孔142位于第二信号驱动线112的下端，偶数列第二信号驱动线112对应的第二过孔142位于第二信号驱动线112的上端。这样可以进一步提高衬底基板100的信赖性。当然，本公开包括但不限于此。
在具体实施时，在本公开实施例中，如图7a与图7b所示，第一过孔141的位置均相同，且第二过孔142的位置均相同。例如，显示区中的奇数行第一信号驱动线111对应的第一过孔141位于第一信号驱动线111的左端，偶数行第一信号驱动线111对应的第一过孔141位于第一信号驱动线111的右端。并且，显示区中的奇数列第二信号驱动线112对应的第二过孔142位于第二信号驱动线112的下端，偶数列第二信号驱动线112对应的第二过孔142位于第二信号驱动线112的上端。
本公开实施例提供了又一些显示面板的结构示意图，如图8所示，其针对上述实施例中的部分实施方式进行了变形。下面仅说明本实施例与上述实 施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图8所示，也可以使一条第一信号驱动线111对应两个第一过孔141。这样可以通过两个第一过孔141使第一信号驱动线111与第一信号传输线121电连接，从而可以降低第一信号驱动线111的电阻，降低信号的衰减，进一步提高显示效果。
在具体实施时，在本公开实施例中，如图8所示，可以使针对同一第一信号驱动线111对应的两个第一过孔141，一个第一过孔141位于第一信号驱动线111的一端，另一个第一过孔141位于第一信号驱动线111的另一端。例如，每一条第一信号驱动线111的左端设置一个第一过孔141，右端也设置一个第一过孔141。
在具体实施时，在本公开实施例中，如图8所示，也可以使一条第二信号驱动线112对应两个第二过孔142。这样可以通过两个第二过孔142使第二信号驱动线112与第二信号传输线122电连接，从而可以降低第二信号驱动线112的电阻，降低信号的衰减，进一步提高显示效果。
在具体实施时，在本公开实施例中，如图8所示，可以使针对同一第二信号驱动线112对应的两个第二过孔142，一个第二过孔142位于第二信号驱动线112的一端，另一个第二过孔142位于第二信号驱动线112的另一端。例如，每一条第二信号驱动线112的左端设置一个第二过孔142，右端也设置一个第二过孔142。
需要说明的是，在不冲突的情况下，上述实施方式与实施方式中的特征可以相互组合，在此不做赘述。
基于同一发明构思，本公开实施例还提供了上述显示面板的制备方法，可以包括如下步骤：在同一衬底基板上形成多个显示区；其中，各显示区包括多个像素单元；像素单元包括多个子像素；子像素包括发光芯片。
在具体实施时，同一显示区中，相邻两列像素单元之间的间隙在沿行方向上具有第一间距，并且，相邻两行像素单元之间的间隙在沿列方向上具有第二间距；
沿行方向最近邻的显示区之间的间隙在沿行方向上具有第三间距，第三间距与第一间距大致相同；和/或，
沿列方向最近邻的显示区之间的间隙在沿列方向上具有第四间距，第四间距与第二间距大致相同。具体参见前述描述，在此不作赘述。
在具体实施时，在本公开实施例中，形成多个显示区AA，如图11所示，可以包括如下步骤：
S11、在同一衬底基板100中的每个显示区AA内，形成多条第一信号驱动线111和多条第二信号驱动线112；其中，第一信号驱动线111和第二信号驱动线112交叉且绝缘设置；
S12、在衬底基板100背离第一信号驱动线111的一侧形成多条第一信号传输线121和多条第二信号传输线122；
S13、形成多个第一过孔141和多个第二过孔142；
S14、在各第一过孔141和各第二过孔142中形成导电材料，使一条第一信号驱动线111通过对应的第一过孔141与一条第一信号传输线121电连接，一条第二信号驱动线112通过对应的第二过孔142与一条第二信号传输线122电连接。示例性地，导电材料可以为金属材料。例如，导电材料可以与第一信号驱动线111的材料相同，这样可以降低电阻，降低信号传输的干扰。
其中，示例性地，步骤S11、在同一衬底基板100中的每个显示区AA内，形成多条第一信号驱动线111和多条第二信号驱动线112，具体可以包括如下步骤：
在同一衬底基板100中的每个显示区AA内，依次形成缓冲层、有源层和栅绝缘层；
在栅绝缘层背离衬底基板100一侧形成第一信号驱动线111和栅极层；
在第一信号驱动线111和栅极层背离衬底基板100一侧形成层间介质层；
在层间介质层背离衬底基板100一侧依次形成电容电极层和层间绝缘层；
在层间绝缘层背离衬底基板100一侧形成第二信号驱动线112和源漏极层。
其中，示例性地，步骤S12、在衬底基板100背离第一信号驱动线111的一侧形成多条第一信号传输线121和多条第二信号传输线122，具体可以包括如下步骤：采用同一构图工艺，在衬底基板100背离第一信号驱动线111的一侧形成多条第一信号传输线121和多条第二信号传输线122。
其中，示例性地，在一条第一信号驱动线111对应一个第一过孔141，一条第二信号驱动线112对应一个第二过孔142时，步骤S13、形成贯穿衬底基板100的多个第一过孔141和多个第二过孔142，具体可以包括如下步骤：在第一信号传输线121的一端和第二信号传输线122的一端进行刻蚀，以形成贯穿栅绝缘层、层间绝缘层以及衬底基板100的第一过孔141和第二过孔142。例如，形成的显示面板的结构如图4所示，在此不作赘述。
其中，示例性地，在一条第一信号驱动线111对应两个第一过孔141，一条第二信号驱动线112对应两个第二过孔142时，步骤S13、形成贯穿衬底基板100的多个第一过孔141和多个第二过孔142，具体可以包括如下步骤：在第一信号传输线121的两端和第二信号传输线122的两端进行刻蚀，以形成贯穿栅绝缘层、层间绝缘层以及衬底基板100的第一过孔141和第二过孔142。例如，形成的显示面板的结构如图8所示，在此不作赘述。
其中，示例性地，在各第一过孔141和各第二过孔142中形成导电材料，具体可以包括如下步骤：
在衬底基板100面向第一信号驱动线111的一侧形成第一光刻胶层，以及在衬底基板100背离第一信号驱动线111的一侧形成第二光刻胶层；其中，第一光刻胶层具有多个第三过孔143和多个第四过孔144，第二光刻胶层具有多个第五过孔和多个第六过孔；一个第三过孔143在衬底基板100的正投影覆盖一个第一过孔141在衬底基板100的正投影，一个第四过孔144在衬底基板100的正投影覆盖一个第二过孔142在衬底基板100的正投影，一个第五过孔在衬底基板100的正投影覆盖一个第一过孔141在衬底基板100的正投影，一个第六过孔在衬底基板100的正投影覆盖一个第二过孔142在衬底基板100的正投影；
采用溅射工艺、原子层淀积工艺、蒸镀工艺、电子束蒸发工艺以及电化学沉积工艺中的一种，在各第一过孔141、各第二过孔142、各第三过孔143、各第四过孔144、各第五过孔以及各第六过孔中填充导电材料。
其中，示例性地，在各第一过孔141、各第二过孔142、各第三过孔143、各第四过孔144、各第五过孔以及各第六过孔中填充导电材料之后，还可以包括：去除第一光刻胶层和第二光刻胶层。这样可以降低显示面板厚度。当然，也可以不去除第一光刻胶层和第二光刻胶层，这样可以采用第一光刻胶层和第二光刻胶层对显示面板进行永久保护。
其中，第三过孔143在衬底基板100的正投影的边缘与对应的第一过孔141在衬底基板100的正投影的边缘具有第一预设间距。第四过孔144在衬底基板100的正投影的边缘与对应的第二过孔142在衬底基板100的正投影的边缘具有第二预设间距。第五过孔在衬底基板100的正投影的边缘与对应的第一过孔141在衬底基板100的正投影的边缘具有第三预设间距。第六过孔在衬底基板100的正投影的边缘与对应的第二过孔142在衬底基板100的正投影的边缘具有第四预设间距。需要说明的是，上述第一预设间距、第二预设间距，第三预设间距以及第四预设间距可以根据制备过程中所需要的精度进行确定，在此不作限定。
下面以制备图7a所示的显示面板为例，对上述制备方法进行说明。本公开实施例提供的制备方法可以包括如下步骤：
(1)在一个衬底基板100中每个显示区AA(即AA-1、AA-2)内，依次形成缓冲层、有源层和栅绝缘层。
(2)在栅绝缘层背离衬底基板100一侧形成第一信号驱动线111和栅极层。
(3)在第一信号驱动线111和栅极层背离衬底基板100一侧依次形成层间介质层、电容电极层和层间绝缘层。
(4)在层间绝缘层背离衬底基板100一侧形成第二信号驱动线112和源漏极层。
(5)采用同一构图工艺，在衬底基板100背离第一信号驱动线111的一侧形成多条第一信号传输线121和多条第二信号传输线122。
(6)在第一信号传输线121的一端和第二信号传输线122的一端进行刻蚀，以形成贯穿栅绝缘层、层间绝缘层以及衬底基板100的第一过孔141和第二过孔142。
(7)在衬底基板100面向第一信号驱动线111的一侧形成第一光刻胶层，以及在衬底基板100背离第一信号驱动线111的一侧形成第二光刻胶层；其中，第一光刻胶层具有多个第三过孔143和多个第四过孔144，第二光刻胶层具有多个第五过孔和多个第六过孔；一个第三过孔143在衬底基板100的正投影覆盖一个第一过孔141在衬底基板100的正投影，一个第四过孔144在衬底基板100的正投影覆盖一个第二过孔142在衬底基板100的正投影，一个第五过孔在衬底基板100的正投影覆盖一个第一过孔141在衬底基板100的正投影，一个第六过孔在衬底基板100的正投影覆盖一个第二过孔142在衬底基板100的正投影。
(8)采用溅射工艺、原子层淀积工艺、蒸镀工艺、电子束蒸发工艺以及电化学沉积工艺中的一种，在各第一过孔141、各第二过孔142、各第三过孔143、各第四过孔144、各第五过孔以及各第六过孔中填充导电材料。
(9)去除第一光刻胶层和第二光刻胶层。
基于同一发明构思，本公开实施例还提供了拼接显示面板，如图9与图10所示，可以包括：多个本公开实施例提供的上述的显示面板300-k(1≤k≤K，k与K均为整数，K为显示面板的总数，图9以K＝2为例，图10以K＝4为例)；其中，
沿行方向F1最近邻的显示面板的显示区AA之间的间隙在沿行方向F1上具有第五间距W5，第五间距W5与第一间距W1大致相同；和/或，沿列方向F2最近邻的显示面板的显示区AA之间的间隙在沿列方向F2上具有第六间距W6，第六间距W6与第二间距W2大致相同。需要说明的是，第一间距W1和第二间距W2可以参见上述对第一间距W1和第二间距W2的描述，在 此不作赘述。
本发明实施例提供的上述拼接显示面板，可以将上述设置有多个显示区的多个显示面板进行拼接，可以实现更大尺寸的拼接显示面板的产品。这样相比采用独立的显示区进行多次拼接，可以大幅降低拼接缝的数量，从而降低由于拼接缝导致的拼接缝可视性及信赖性的问题。
示例性地，在制备过程中，在显示面板超过110英寸时，可以将上述一个具有多个显示区的显示面板作为一个拼接单元，以通过对这些显示面板进行拼接，实现更大尺寸的显示面板的产品。这样相比采用独立的显示区AA进行多次拼接，可以大幅降低拼接缝的数量，从而降低由于拼接缝导致的拼接缝可视性及信赖性的问题。
示例性地，如图9所示，可以采用两个上述显示面板进行拼接，以形成拼接显示面板。例如，采用显示面板300-1和300-2进行拼接以形成拼接显示面板，每个显示面板300-1和300-2包括相邻的两个显示区AA。即显示面板300-1包括两个显示区AA，显示面板300-2包括两个显示区AA。
示例性地，如图10所示，可以采用四个上述显示面板进行拼接，以形成拼接显示面板。例如，采用显示面板300-1～300-4，形成拼接显示面板。每个显示面板300-1～300-4可以包括相邻的六个显示区AA。并且，显示面板300-1中的显示区AA共用一个衬底基板100，显示面板300-2中的显示区AA共用一个衬底基板100，显示面板300-3中的显示区AA共用一个衬底基板100，显示面板300-4中的显示区AA共用一个衬底基板100。当然，也可以采用更多个显示面板，以拼接形成拼接显示面板，在此不作限定。
在采用本公开提供的上述显示面板进行拼接时，在具体实施时，在本公开实施例中，如图10所示，沿行方向F1相邻的显示面板中最近邻的显示区AA之间的间隙在沿行方向F1上具有第五间距W5，可以使第五间距W5与第一间距W1大致相同。这样通过使第五间距W5与第一间距W1大致相同，可以将沿行方向F1相邻的面板组中最近邻的显示区AA之间的间隙与显示区AA中相邻两列像素单元PX之间的间隙在沿行方向F1的间隙制备的大致相 同，也就是说，可以将同一衬底基板100的相邻两个显示区AA之间的间隙与像素单元PX之间的间隙大致相同，从而可以进一步降低拼接缝可视性的问题。
需要说明的是，实际工艺中，由于工艺条件的限制或其他因素，上述第五间距W5与第一间距W1并不能完全相同，可能会有一些偏差。在具体实施时，可以使第五间距W5与第一间距W1之间的比值
Figure PCTCN2019118919-appb-000009
满足
Figure PCTCN2019118919-appb-000010
时可以说明第五间距W5与第一间距W1是相同的。例如，在实际应用中，例如在W1＝500μm时，那么W5选取300μm～700μm之间的数值，即可以说明第五间距W5与第一间距W1是相同的。
由于人眼的识别能力，若显示区之间的间隙在一定范围内时，人眼可能不会识别出显示区之间存在明显的间隙，因此，第五间距W5与第一间距W1之间的比值
Figure PCTCN2019118919-appb-000011
还可以根据人眼能识别出显示区之间存在明显的间隙大小的临界值进行设定。
当然，还可以根据上述两个方式共同设定第五间距W5与第一间距W1之间的比值
Figure PCTCN2019118919-appb-000012
以满足第五间距W5与第一间距W1大致相同的条件。这些均属于本公开的保护范围。
在采用面板组进行拼接时，在具体实施时，在本公开实施例中，如图10所示，沿列方向F2相邻的面板组中最近邻的显示区AA的显示区AA之间的间隙在沿列方向F2上具有第六间距W6，第六间距W6与第二间距W2大致相同。这样通过使第六间距W6与第二间距W2大致相同，可以将沿列方向F2相邻的面板组中最近邻的显示区AA的显示区AA之间的间隙与显示区AA中相邻两行像素单元PX之间的间隙在沿列方向F2的间隙制备的大致相同，也就是说，可以将同一衬底基板100的相邻两个显示区AA之间的间隙与像素单元PX之间的间隙大致相同，从而可以进一步降低拼接缝可视性的问题。
需要说明的是，实际工艺中，由于工艺条件的限制或其他因素，上述第 六间距W6与第二间距W2并不能完全相同，可能会有一些偏差。在具体实施时，可以使第六间距W6与第二间距W2之间的比值
Figure PCTCN2019118919-appb-000013
满足
Figure PCTCN2019118919-appb-000014
时可以说明第六间距W6与第二间距W2是相同的。例如，在实际应用中，例如在W2＝500μm时，那么W6选取300μm～700μm之间的数值，即可以说明第六间距W6与第二间距W2是相同的。
由于人眼的识别能力，若显示区之间的间隙在一定范围内时，人眼可能不会识别出显示区之间存在明显的间隙，因此，第六间距W6与第二间距W2之间的比值
Figure PCTCN2019118919-appb-000015
还可以根据人眼能识别出显示区之间存在明显的间隙大小的临界值进行设定。
当然，还可以根据上述两个方式共同设定第六间距W6与第二间距W2之间的比值
Figure PCTCN2019118919-appb-000016
以满足第六间距W6与第二间距W2大致相同的条件。这些均属于本公开的保护范围。
本公开实施例提供的上述显示面板和拼接显示面板中的至少一种可以应用在大尺寸的显示装置中。在具体实施时，在本公开实施例中，显示装置可以为：显示器等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的显示面板、拼接显示面板、其制备方法，通过在一个衬底基板上设置多个显示区，并且，每个显示区设置有多个发光芯片，这样在制备显示面板时，可以在一个衬底基板上制备发光芯片后，形成多个显示区。这样可以使第三间距与第一间距大致相同和/或第四间距与第二间距大致相同，以使显示区与显示区之间均匀过渡，从而可以降低由于拼接工艺的拼接精度导致的拼接缝较大的问题，提高显示效果。并且，由于采用一个衬底基板即可以形成多个用于拼接的显示区，可以不用再先制备多个独立的显示区，再将这些独立的显示区进行拼接成显示面板，从而可以不采用拼接工 艺即可以形成大尺寸显示面板，提高生产效率。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (17)

  1. 一种显示面板，其中，包括：
    衬底基板，所述衬底基板上设置有多个显示区；各所述显示区包括多个像素单元；所述像素单元包括多个子像素；所述子像素包括发光芯片；
    其中，同一所述显示区中，相邻两列像素单元之间的间隙在沿行方向上具有第一间距，并且，相邻两行像素单元之间的间隙在沿列方向上具有第二间距；
    沿所述行方向最近邻的显示区之间的间隙在沿所述行方向上具有第三间距，所述第三间距与所述第一间距大致相同；和/或，
    沿所述列方向最近邻的显示区之间的间隙在沿所述列方向上具有第四间距，所述第四间距与所述第二间距大致相同。
  2. 如权利要求1所述的显示面板，其中，所述显示区中的子像素阵列排布，并且所述子像素还包括被配置为驱动所述发光芯片的驱动电路。
  3. 如权利要求2所述的显示面板，其中，每一所述显示区包括：位于所述衬底基板与所述发光芯片之间的多条第一信号驱动线和多条第二信号驱动线；其中，所述第一信号驱动线和所述第二信号驱动线交叉且绝缘设置；
    一行子像素中的驱动电路电连接一条所述第一信号驱动线，一列子像素中的驱动电路电连接一条所述第二信号驱动线。
  4. 如权利要求3所述的显示面板，其中，每一所述显示区包括：位于所述衬底基板背离所述发光芯片一侧的多条第一信号传输线、多条第二信号传输线以及分别与所述第一信号传输线和所述第二信号传输线电连接的驱动芯片；
    一条所述第一信号驱动线通过对应贯穿所述衬底基板的第一过孔与一条所述第一信号传输线电连接；且一条所述第二信号驱动线通过对应贯穿所述衬底基板的第二过孔与一条所述第二信号传输线电连接。
  5. 如权利要求4所述的显示面板，其中，一条所述第一信号驱动线对应 一个所述第一过孔；各所述第一过孔位于所述第一信号驱动线的同一端。
  6. 如权利要求4所述的显示面板，其中，一条所述第一信号驱动线对应一个所述第一过孔；部分所述第一过孔位于所述第一信号驱动线的一端，其余部分所述第一过孔位于所述第一信号驱动线的另一端。
  7. 如权利要求6所述的显示面板，其中，奇数行第一信号驱动线对应的第一过孔位于所述第一信号驱动线的一端，偶数行第一信号驱动线对应的第一过孔位于所述第一信号驱动线的另一端。
  8. 如权利要求4所述的显示面板，其中，一条所述第一信号驱动线对应两个所述第一过孔；一个所述第一过孔位于所述第一信号驱动线的一端，另一个所述第一过孔位于所述第一信号驱动线的另一端。
  9. 如权利要求4-8任一项所述的显示面板，其中，一条所述第二信号驱动线对应一个所述第二过孔；各所述第二过孔位于所述第二信号驱动线的同一端。
  10. 如权利要求4-8任一项所述的显示面板，其中，一条所述第二信号驱动线对应一个所述第二过孔；部分所述第二过孔位于所述第二信号驱动线的一端，其余部分所述第二过孔位于所述第二信号驱动线的另一端。
  11. 如权利要求10所述的显示面板，其中，奇数列第二信号驱动线对应的第二过孔位于所述第二信号驱动线的一端，偶数列第二信号驱动线对应的第二过孔位于所述第二信号驱动线的另一端。
  12. 如权利要求4-8任一项所述的显示面板，其中，一条所述第二信号驱动线对应两个所述第二过孔；一个所述第二过孔位于所述第二信号驱动线的一端，另一个所述第二过孔位于所述第二信号驱动线的另一端。
  13. 一种如权利要求1-12任一项所述的显示面板的制备方法，其中，包括：
    在同一所述衬底基板上形成多个所述显示区；其中，各所述显示区包括多个像素单元；所述像素单元包括多个子像素；所述子像素包括发光芯片；
    其中，同一所述显示区中，相邻两列像素单元之间的间隙在沿行方向上 具有第一间距，并且，相邻两行像素单元之间的间隙在沿列方向上具有第二间距；
    沿所述行方向最近邻的显示区之间的间隙在沿所述行方向上具有第三间距，所述第三间距与所述第一间距大致相同；和/或，
    沿所述列方向最近邻的显示区之间的间隙在沿所述列方向上具有第四间距，所述第四间距与所述第二间距大致相同。
  14. 如权利要求13所述的制备方法，其中，所述形成多个所述显示区，包括：
    在同一所述衬底基板中的每个所述显示区内，形成多条第一信号驱动线和多条第二信号驱动线；其中，所述第一信号驱动线和所述第二信号驱动线交叉且绝缘设置；
    在所述衬底基板背离所述第一信号驱动线的一侧形成多条第一信号传输线和多条第二信号传输线；
    形成多个第一过孔和多个第二过孔；
    在各所述第一过孔和各所述第二过孔中形成导电材料，使一条所述第一信号驱动线通过对应的第一过孔与一条所述第一信号传输线电连接，一条所述第二信号驱动线通过对应的第二过孔与一条所述第二信号传输线电连接。
  15. 如权利要求14所述的制备方法，其中，所述在各所述第一过孔和各所述第二过孔中形成导电材料，包括：
    在所述衬底基板面向所述第一信号驱动线的一侧形成第一光刻胶层，以及在所述衬底基板背离所述第一信号驱动线的一侧形成第二光刻胶层；其中，所述第一光刻胶层具有多个第三过孔和多个第四过孔，所述第二光刻胶层具有多个第五过孔和多个第六过孔；一个所述第三过孔在所述衬底基板的正投影覆盖一个所述第一过孔在所述衬底基板的正投影，一个所述第四过孔在所述衬底基板的正投影覆盖一个所述第二过孔在所述衬底基板的正投影，一个所述第五过孔在所述衬底基板的正投影覆盖一个所述第一过孔在所述衬底基板的正投影，一个所述第六过孔在所述衬底基板的正投影覆盖一个所述第二 过孔在所述衬底基板的正投影；
    采用溅射工艺、原子层淀积工艺、蒸镀工艺、电子束蒸发工艺以及电化学沉积工艺中的一种，在各所述第一过孔、各所述第二过孔、各所述第三过孔、各所述第四过孔、各所述第五过孔以及各所述第六过孔中填充导电材料。
  16. 如权利要求15所述的制备方法，其中，在所述在各所述第一过孔、各所述第二过孔、各所述第三过孔、各所述第四过孔、各所述第五过孔以及各所述第六过孔中填充导电材料之后，还包括：
    去除所述第一光刻胶层和所述第二光刻胶层。
  17. 一种拼接显示面板，包括：多个如权利要求1-12任一项所述的显示面板；
    沿所述行方向最近邻的显示面板的显示区之间的间隙在所述沿行方向上具有第五间距，所述第五间距与所述第一间距大致相同；和/或，
    沿所述列方向最近邻的显示面板的显示区之间的间隙在沿列方向上具有第六间距，所述第六间距与所述第二间距大致相同。
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