WO2016106825A1 - 低温多晶硅薄膜晶体管及薄膜晶体管基板 - Google Patents

低温多晶硅薄膜晶体管及薄膜晶体管基板 Download PDF

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Publication number
WO2016106825A1
WO2016106825A1 PCT/CN2015/070520 CN2015070520W WO2016106825A1 WO 2016106825 A1 WO2016106825 A1 WO 2016106825A1 CN 2015070520 W CN2015070520 W CN 2015070520W WO 2016106825 A1 WO2016106825 A1 WO 2016106825A1
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gate
thin film
film transistor
low temperature
disposed
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English (en)
French (fr)
Inventor
陈秋权
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/433,650 priority Critical patent/US9673334B2/en
Publication of WO2016106825A1 publication Critical patent/WO2016106825A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a low temperature polysilicon thin film transistor and a thin film transistor substrate.
  • LTPS TFT low temperature poly-silicon thin film Transistor Liquid Crystal Display (Liquid Crystal) Display, referred to as LCD
  • LCD Liquid Crystal Display
  • the silicon crystal arrangement of the LCD has an order, and the electron mobility is relatively high, and the peripheral driving circuit can be simultaneously fabricated on the glass substrate to achieve the goal of system integration, space saving, and reduction of the cost of the driving IC.
  • the light-shielding layer only has a light-shielding effect, which forms a parasitic capacitance with other conductive layers, causing the gate's Vfeed-through voltage, which in turn affects the TFT performance.
  • the technical problem to be solved by the present invention is to provide a low-temperature polysilicon thin film transistor and a thin film transistor substrate, which can reduce the kick-back voltage and improve the TFT performance.
  • a technical solution adopted by the present invention is to provide a low temperature polysilicon thin film transistor, comprising:
  • a first gate disposed on the substrate
  • the polysilicon layer disposed on the substrate and covering the first gate, wherein the polysilicon layer includes a source region, a drain region, and a trench formed between the source region and the drain region Road area
  • the first gate and the second gate respectively apply a first voltage and a second voltage having opposite polarities.
  • the first gate, the channel region, and the second gate at least partially overlap each other.
  • a gate insulating layer covering the polysilicon layer and the second gate
  • a source disposed on the gate insulating layer, and connected to the source region through a first via disposed in the gate insulating layer;
  • a drain electrode is disposed on the gate insulating layer and connected to the drain region through a second via hole disposed in the gate insulating layer.
  • a passivation layer covering the gate insulating layer, the source, and the drain;
  • a third via hole is disposed in the passivation layer, and when a pixel electrode is disposed on the passivation layer, the pixel electrode is connected to the drain through the third via hole.
  • a thin film transistor substrate including a substrate and a plurality of pixels disposed on the substrate, the plurality of pixel arrays being arranged, And each of the pixels includes a low temperature polysilicon thin film transistor and a pixel electrode electrically connected to the low temperature polysilicon thin film transistor, wherein the low temperature polysilicon thin film transistor comprises:
  • a first gate disposed on the substrate
  • the polysilicon layer disposed on the substrate and covering the first gate, wherein the polysilicon layer includes a source region, a drain region, and a trench formed between the source region and the drain region Road area
  • the first gate and the second gate respectively apply a first voltage and a second voltage having opposite polarities.
  • the first gate, the channel region, and the second gate at least partially overlap each other.
  • the low temperature polysilicon thin film transistor further comprises:
  • a gate insulating layer covering the polysilicon layer and the second gate
  • a source disposed on the gate insulating layer, and connected to the source region through a first via disposed in the gate insulating layer;
  • drain electrode disposed on the gate insulating layer and connected to the drain region through a second via hole disposed in the gate insulating layer;
  • a passivation layer covering the gate insulating layer, the source, and the drain;
  • the pixel electrode is disposed on the passivation layer and connected to the drain through a third via provided in the passivation layer.
  • the thin film transistor substrate further includes: a plurality of first scan lines, wherein the first gates of the low temperature polysilicon thin film transistors in each pixel are electrically connected to a corresponding one of the first scan lines Providing the first voltage to the first gate through the first scan line;
  • the source of the low temperature polysilicon thin film transistor in each pixel is electrically connected to a corresponding one of the data lines, respectively, when the low temperature polysilicon thin film transistor is turned on,
  • the data line and the turned-on low temperature polysilicon thin film transistor provide a data voltage to the pixel electrode.
  • the first scan line and the first gate of the low temperature polysilicon thin film transistor are respectively disposed in the same layer; and the second scan line and the second gate of the low temperature polysilicon thin film transistor Set in the same layer separately.
  • the thin film transistor substrate further includes a gate driver, the gate driver includes a plurality of gate driving units, wherein each of the gate driving units is electrically connected to the first scan line and the second scan respectively a plurality of the low temperature polysilicon thin film transistors arranged to drive the same row at the same time, and each of the gate driving units respectively comprises:
  • a first switching element comprising: a control end, an input end and an output end, wherein the control end is electrically connected to the clock signal, and the input end is electrically connected to the input end of the gate driving unit to receive the gate driving signal And the output end serves as a first output end of the gate driving unit, and is electrically connected to the second scan line to output the second voltage to the second scan line;
  • An inverter comprising:
  • a second switching element comprising: a control end, an input end and an output end, wherein the control end is electrically connected to the input end of the gate driving unit to receive a gate driving signal, and the input end is electrically connected to the first power source;
  • a third switching element includes a control end, an input end, and an output end, wherein the control end is electrically connected to the input end of the gate driving unit to receive a gate driving signal, and the input end is electrically connected to the second power source;
  • the second switching element is electrically connected to the output end of the third switching element and serves as a second output end of the gate driving unit, and is electrically connected to the first scan line to output The first voltage is applied to the first scan line.
  • the second switching element is a p-type transistor and the third switching element is an n-type transistor; and the voltage provided by the second voltage source and the gate input to the input end of the gate driving unit The polarity of the pulse signal of the pole drive signal is reversed.
  • the low temperature polysilicon thin film transistor of the present invention comprises: a substrate; a first gate disposed on the substrate; a polysilicon layer disposed on the substrate and covering the a first gate, wherein the polysilicon layer includes a source region, a drain region, and a channel region formed between the source region and the drain region; and a second gate disposed on the polysilicon On the layer; wherein, when the low temperature polysilicon thin film transistor is driven, the first gate and the second gate respectively apply a first voltage and a second voltage of opposite polarities. Since the low temperature polysilicon thin film transistor includes two gates and two gates apply voltages of opposite polarities, in this way, the kickback voltage can be lowered and the TFT performance can be improved.
  • FIG. 1 is a schematic structural view of an embodiment of a low temperature polysilicon thin film transistor of the present invention
  • FIG. 2 is a schematic structural view of another embodiment of a low temperature polysilicon thin film transistor of the present invention.
  • FIG. 3 is a schematic view showing the design of a low temperature polysilicon thin film transistor of the present invention and a gate in the prior art;
  • FIG. 4 is a schematic structural view of an embodiment of a low temperature polysilicon thin film transistor in a thin film transistor substrate of the present invention
  • Fig. 5 is a structural schematic view showing an embodiment of a gate driving unit in a thin film transistor substrate of the present invention.
  • FIG. 1 is a low temperature poly-silicon transistor of the present invention.
  • Thin film transistor (LTPS TFT) is a schematic structural view of an embodiment.
  • the low temperature polysilicon thin film transistor includes: a substrate 1, a first gate 2, a polysilicon layer 3, and a second gate 4; a first gate 2 is disposed on the substrate 1; and a polysilicon layer 3 is disposed on the substrate 1 and covers the first gate 2, wherein the polysilicon layer 1 includes a source region 11, a drain region 12, and a channel region 13 formed between the source region 11 and the drain region 12; the second gate 4 is disposed on the polysilicon layer 3.
  • the first gate 2 and the second gate 4 respectively apply a first voltage and a second voltage of opposite polarities.
  • the low temperature polysilicon thin film transistor includes the first gate 2 and the second gate 4, when driving, the first gate 2 and the second gate 4 respectively apply a first voltage and a second voltage of opposite polarities, such that The kick voltage is effectively reduced, thereby improving the TFT performance; in the case where the driving voltage of the low temperature polysilicon thin film transistor is the same, since the forward voltage of the gate to which the forward voltage is applied is compared with the case where the original low temperature polysilicon thin film transistor has only one gate It is reduced, so the width of the gate circuit to which the forward voltage is applied can be reduced, thereby increasing the aperture ratio and resolution; since the gate to which the negative voltage is applied can also serve as a light shielding layer at the same time, the shading effect can be kept unchanged; Since the manufacturing process can utilize existing processes and equipment, there is no need to increase the investment cost.
  • the low-voltage polysilicon thin film transistor has a turn-on voltage of at least 8V
  • the voltage applied to the gate is 10V
  • the low temperature polysilicon thin film transistor is affected by the kickback voltage.
  • the actual turn-on voltage is just 8V, that is, the kickback voltage is 2V
  • the low temperature polysilicon thin film transistor of the present invention includes two gates, if one applied voltage is 5V, then the kickback voltage is 1V, and the other applied The voltage is -5V, and the actual turn-on voltage of the low-temperature polysilicon thin film transistor is 5V-1V-(-5V), which is 9V. Therefore, in this way, the kickback voltage can be effectively reduced, thereby improving the TFT performance.
  • the first gate 2, the channel region 13, and the second gate 4 are at least partially overlapped, respectively.
  • the first gate 2, the channel region 13 and the second gate 4 may completely overlap each other or may partially overlap; when completely overlapped, the first gate 2 and/or the second gate 4 may also The channel region 13 can be exceeded.
  • the low temperature polysilicon thin film transistor further includes: a gate insulating layer 5, a source 6 and a drain 7; a gate insulating layer 5 covering the polysilicon layer 3 and the second gate 4; and a source 6 disposed on the gate insulating layer 5, and connected to the source region 11 through the first via 51 provided in the gate insulating layer 5; the drain 7 is disposed on the gate insulating layer 5, and is disposed in the gate insulating layer 5 The second via 52 is connected to the drain region 12.
  • Fig. 3 is a schematic view showing the design of a low temperature polysilicon thin film transistor of the present invention and a gate in the prior art.
  • the forward voltage of the gate to which the forward voltage is applied is reduced as compared with the case where the original low temperature polysilicon thin film transistor has only one gate.
  • the forward voltage applied to the gate is 10 V
  • the low temperature polysilicon thin film transistor of the present invention includes two gates, it is applied to one of the gate electrodes.
  • the forward voltage can be 5V.
  • the present invention also provides a thin film transistor substrate comprising a substrate and a plurality of pixels disposed on the substrate, the plurality of pixel arrays being arranged, and each of the pixels respectively comprising a low temperature polysilicon thin film transistor and electrically connected to the low temperature polysilicon thin film transistor a pixel electrode, wherein, referring to FIG.
  • the low temperature polysilicon thin film transistor includes: a first gate 2, a polysilicon layer 3, and a second gate 4; a first gate 2 is disposed on the substrate 1; and a polysilicon layer 3 is disposed on the substrate 1 And covering the first gate 2, wherein the polysilicon layer 3 includes a source region 11, a drain region 12, and a channel region 13 formed between the source region 11 and the drain region 12; the second gate 4 is disposed On the polysilicon layer 3; wherein, when the low temperature polysilicon thin film transistor is driven, the first gate 2 and the second gate 4 respectively apply a first voltage and a second voltage of opposite polarities.
  • the low temperature polysilicon thin film transistor includes the first gate 2 and the second gate 4, when driving, the first gate 2 and the second gate 4 respectively apply a first voltage and a second voltage of opposite polarities, such that The kick voltage is effectively reduced, thereby improving the TFT performance; in the case where the driving voltage of the low temperature polysilicon thin film transistor is the same, since the forward voltage of the gate to which the forward voltage is applied is compared with the case where the original low temperature polysilicon thin film transistor has only one gate It is reduced, so the width of the gate circuit to which the forward voltage is applied can be reduced, thereby increasing the aperture ratio and resolution; since the gate to which the negative voltage is applied can also serve as a light shielding layer at the same time, the shading effect can be kept unchanged; Since the manufacturing process can utilize existing processes and equipment, there is no need to increase the investment cost.
  • the first gate 2, the channel region 13, and the second gate 4 are at least partially overlapped, respectively.
  • the first gate 2, the channel region 13 and the second gate 4 may completely overlap each other or may partially overlap; when completely overlapped, the first gate 2 and/or the second gate 4 may also The channel region 13 can be exceeded.
  • the low temperature polysilicon thin film transistor further includes: a gate insulating layer 5, a source 6, a drain 7, and a passivation layer 8; a gate insulating layer 5 covering the polysilicon layer 3 and the second gate 4; and a source 6 setting On the gate insulating layer 5, and through the first via 51 provided in the gate insulating layer 5, is connected to the source region 11; the drain 7 is disposed on the gate insulating layer 5, and is disposed at the gate a second via 52 in the insulating layer 5 is connected to the drain region 12; the passivation layer 8 covers the gate insulating layer 5, the source 6 and the drain 7; wherein the pixel electrode 9 is disposed on the passivation layer 8 The drain electrode 7 is connected through a third via 81 provided in the passivation layer 8.
  • the thin film transistor substrate further includes: a plurality of first scan lines, a plurality of second scan lines, and a plurality of data lines.
  • the first gate of the low temperature polysilicon thin film transistor in each pixel is electrically connected to a corresponding first scan line, respectively, to provide a first voltage to the first gate through the first scan line; a second gate of the low temperature polysilicon thin film transistor is electrically connected to a corresponding second scan line to provide a second voltage to the second gate through the second scan line; a source of the low temperature polysilicon thin film transistor in each pixel
  • Each of the corresponding data lines is electrically connected to provide a data voltage to the pixel electrode through the data line and the turned-on low temperature polysilicon thin film transistor when the low temperature polysilicon thin film transistor is turned on.
  • the first scan line and the first gate of the low temperature polysilicon thin film transistor are respectively disposed in the same layer; and the second scan line and the second gate of the low temperature polysilicon thin film transistor are respectively disposed in the same layer. In this way, the goal of system integration and space saving can be further achieved.
  • the thin film transistor substrate further includes a gate driver, and the gate driver includes a plurality of gate driving units, wherein each gate driving unit is electrically connected to the first scan line and the second scan line to drive the same row at the same time.
  • the gate driver includes a plurality of gate driving units, wherein each gate driving unit is electrically connected to the first scan line and the second scan line to drive the same row at the same time.
  • each of the gate driving units includes a first switching element 10 and an inverter 20, respectively.
  • the first switching element 10 includes a control terminal 101, an input terminal 102 and an output terminal 103.
  • the control terminal 101 is electrically connected to the clock signal, and the input terminal 102 is electrically connected to the input terminal 301 of the gate driving unit to receive the gate driving signal.
  • the output terminal 103 serves as the first output end 302 of the gate driving unit, and is electrically connected to the second scan line to output the second voltage to the second scan line;
  • the inverter 20 includes a second switching element 21 and a third switching element 22.
  • Using gate drive circuit substrate technology (Gate on Array, abbreviated as GOA), can add the inverter circuit to the peripheral line area.
  • the second switching element 21 includes a control terminal 211, an input terminal 212 and an output terminal 213.
  • the control terminal 211 is electrically connected to the input terminal 301 of the gate driving unit to receive the gate driving signal, and the input terminal 212 is electrically connected to the first voltage.
  • the third switching element 22 includes a control terminal 221, an input terminal 222 and an output terminal 223.
  • the control terminal 221 is electrically connected to the input terminal 301 of the gate driving unit to receive the gate driving signal, and the input terminal 222 is electrically connected.
  • the inverter can reverse the phase of the input signal by 180 degrees. In practical applications, other inverters can also be used, and no limitation is imposed here.
  • the second switching element 21 is a p-type transistor
  • the third switching element 22 is an n-type transistor; and the voltage provided by the second voltage source and the pulse of the gate driving signal input by the input terminal 301 of the gate driving unit The polarity of the signal is reversed.

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Abstract

提供了一种低温多晶硅薄膜晶体管及薄膜晶体管基板，该低温多晶硅薄膜晶体管包括：基底（1）；第一栅极（2），设置在基底（1）上；多晶硅层（3），设置在基底（1）上并覆盖第一栅极（2），其中，多晶硅层（3）包括源极区域（11）、漏极区域（12）以及形成在源极区域（11）与漏极区域（12）之间的沟道区域（13）；第二栅极（4），设置在多晶硅层（3）上；其中，低温多晶硅薄膜晶体管在驱动时，第一栅极（2）与第二栅极（4）分别施加极性相反的第一电压和第二电压。通过上述方式，能够降低回踢电压，提升TFT效能。

Description

低温多晶硅薄膜晶体管及薄膜晶体管基板
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种低温多晶硅薄膜晶体管及薄膜晶体管基板。
【背景技术】
LTPS TFT (low temperature poly-silicon thin film transistor)液晶显示器（Liquid Crystal Display，简称为LCD）具有高分辨率、反应速度快、高亮度、高开口率等优点；另外，由于LTPS TFT LCD的硅结晶排列有次序，电子移动率相对高，可以将外围驱动电路同时制作在玻璃基板上，达到系统整合、节省空间及降低驱动IC成本的目标。
目前的LTPS TFT 结构中，为了避免背光源（back light）的照光，在导电通道（channel）产生光电流（photo current）而造成漏电流（leakage current），一般在玻璃基板上先镀上一层金属，作为遮光层（Light shielding layer）。
但是，遮光层仅有遮光效果，其与其他导电层形成寄生电容，造成闸极的回踢电压（Vfeed-through），进而影响TFT效能。
【发明内容】
本发明主要解决的技术问题是提供一种低温多晶硅薄膜晶体管及薄膜晶体管基板，能够降低回踢电压，提升TFT效能。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种低温多晶硅薄膜晶体管，包括：
基底；
第一栅极，设置在所述基底上；
多晶硅层，设置在所述基底上并覆盖所述第一栅极，其中，所述多晶硅层包括源极区域、漏极区域以及形成在所述源极区域与所述漏极区域之间的沟道区域；
第二栅极，设置在所述多晶硅层上；
其中，所述低温多晶硅薄膜晶体管在驱动时，所述第一栅极与所述第二栅极分别施加极性相反的第一电压和第二电压。
其中，所述第一栅极、所述沟道区域以及所述第二栅极分别至少部分重叠。
其中，进一步包括：
栅极绝缘层，覆盖所述多晶硅层以及所述第二栅极；
源极，设置在所述栅极绝缘层上，并通过设置在所述栅极绝缘层中的第一通孔，连接至所述源极区域；
漏极，设置在所述栅极绝缘层上，并通过设置在所述栅极绝缘层中的第二通孔，连接至所述漏极区域。
其中，进一步包括：
钝化层，覆盖所述栅极绝缘层、所述源极以及所述漏极；
其中，所述钝化层中设置有第三通孔，当所述钝化层上设置像素电极时，所述像素电极通过所述第三通孔连接所述漏极。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种薄膜晶体管基板，所述薄膜晶体管基板包括基底以及设置在所述基底上的多个像素，所述多个像素阵列排列，且每个所述像素分别包括低温多晶硅薄膜晶体管以及与所述低温多晶硅薄膜晶体管电性连接的像素电极，其中，所述低温多晶硅薄膜晶体管包括：
第一栅极，设置在所述基底上；
多晶硅层，设置在所述基底上并覆盖所述第一栅极，其中，所述多晶硅层包括源极区域、漏极区域以及形成在所述源极区域与所述漏极区域之间的沟道区域；
第二栅极，设置在所述多晶硅层上；
其中，所述低温多晶硅薄膜晶体管在驱动时，所述第一栅极与所述第二栅极分别施加极性相反的第一电压和第二电压。
其中，所述所述第一栅极、所述沟道区域以及所述第二栅极分别至少部分重叠。
其中，所述低温多晶硅薄膜晶体管进一步包括：
栅极绝缘层，覆盖所述多晶硅层以及所述第二栅极；
源极，设置在所述栅极绝缘层上，并通过设置在所述栅极绝缘层中的第一通孔，连接至所述源极区域；
漏极，设置在所述栅极绝缘层上，并通过设置在所述栅极绝缘层中的第二通孔，连接至所述漏极区域；
钝化层，覆盖所述栅极绝缘层、所述源极以及所述漏极；
其中，所述像素电极设置在所述钝化层上并通过设置在所述钝化层中的第三通孔连接所述漏极。
其中，所述薄膜晶体管基板进一步包括：多条第一扫描线，其中，每个像素中的所述低温多晶硅薄膜晶体管的所述第一栅极分别电性连接一条对应的所述第一扫描线，以通过所述第一扫描线而提供所述第一电压至所述第一栅极；
多条第二扫描线，其中，每个像素中的所述低温多晶硅薄膜晶体管的所述第二栅极分别电性连接一条对应的所述第二扫描线，以通过所述第二扫描线而提供所述第二电压至所述第二栅极；
多条数据线，其中，每个像素中的所述低温多晶硅薄膜晶体管的所述源极分别电性连接一条对应的所述数据线，以在所述低温多晶硅薄膜晶体管导通时，通过所述数据线以及导通的所述低温多晶硅薄膜晶体管而将数据电压提供至所述像素电极。
其中，所述第一扫描线与所述低温多晶硅薄膜晶体管的所述第一栅极分别设置在同一层中；而所述第二扫描线与所述低温多晶硅薄膜晶体管的所述第二栅极分别设置在同一层中。
所述薄膜晶体管基板进一步包括闸极驱动器，所述闸极驱动器包括多个闸极驱动单元，其中，每个所述闸极驱动单元分别电性连接所述第一扫描线与所述第二扫描线以同时驱动同一行排列的多个所述低温多晶硅薄膜晶体管，且每个所述闸极驱动单元分别包括：
第一开关元件，其包括控制端，输入端以及输出端，其中，所述控制端电性连接时钟信号，所述输入端电性连接所述闸极驱动单元的输入端以接收闸极驱动信号，而所述输出端作为所述闸极驱动单元的第一输出端，其电性连接所述第二扫描线以输出所述第二电压至所述第二扫描线；
反相器，其包括：
第二开关元件，其包括控制端，输入端以及输出端，其中，所述控制端电性连接所述闸极驱动单元的输入端以接收闸极驱动信号，所述输入端电性连接第一电压源；
第三开关元件，其包括控制端，输入端以及输出端，其中，所述控制端电性连接所述闸极驱动单元的输入端以接收闸极驱动信号，所述输入端电性连接第二电压源；
其中，所述第二开关元件与所述第三开关元件的输出端电性连接在一起并作为所述闸极驱动单元的第二输出端，其电性连接所述第一扫描线以输出所述第一电压至所述第一扫描线。
其中，所述第二开关元件为p型晶体管，而所述第三开关元件为n型晶体管；且所述第二电压源所提供的电压与所述闸极驱动单元的输入端所输入的闸极驱动信号的脉冲信号的极性相反。
本发明的有益效果是：区别于现有技术的情况，本发明低温多晶硅薄膜晶体管包括：基底；第一栅极，设置在所述基底上；多晶硅层，设置在所述基底上并覆盖所述第一栅极，其中，所述多晶硅层包括源极区域、漏极区域以及形成在所述源极区域与所述漏极区域之间的沟道区域；第二栅极，设置在所述多晶硅层上；其中，所述低温多晶硅薄膜晶体管在驱动时，所述第一栅极与所述第二栅极分别施加极性相反的第一电压和第二电压。由于低温多晶硅薄膜晶体管包括两个栅极，且两个栅极施加极性相反的电压，通过这种方式，能够降低回踢电压，提升TFT效能。
【附图说明】
图1是本发明低温多晶硅薄膜晶体管一实施例的结构示意图；
图2是本发明低温多晶硅薄膜晶体管另一实施例的结构示意图；
图3是本发明低温多晶硅薄膜晶体管和现有技术中一个栅极的情况的设计示意图；
图4是本发明薄膜晶体管基板中低温多晶硅薄膜晶体管一实施例的结构示意图；
图5是本发明薄膜晶体管基板中闸极驱动单元一实施例的结构示意图。
【具体实施方式】
下面结合附图和实施方式对本发明进行详细说明。
参阅图1，图1是本发明低温多晶硅薄膜晶体管(low temperature poly-silicon thin film transistor, LTPS TFT)一实施例的结构示意图。
低温多晶硅薄膜晶体管包括：基底1、第一栅极2、多晶硅层3以及第二栅极4；第一栅极2设置在基底1上；多晶硅层3设置在基底1上并覆盖第一栅极2，其中，多晶硅层1包括源极区域11、漏极区域12以及形成在源极区域11与漏极区域12之间的沟道区域13；第二栅极4设置在多晶硅层3上。
其中，低温多晶硅薄膜晶体管在驱动时，第一栅极2与第二栅极4分别施加极性相反的第一电压和第二电压。
由于低温多晶硅薄膜晶体管包括第一栅极2和第二栅极4，在驱动时，第一栅极2与第二栅极4分别施加极性相反的第一电压和第二电压，这样使得回踢电压有效降低，进而提高TFT效能；在低温多晶硅薄膜晶体管的驱动电压相同的情况下，由于施加正向电压的栅极的正向电压和原来低温多晶硅薄膜晶体管只有一个栅极的情况相比，是减小的，因此施加正向电压的栅极电路宽度可以缩小，进而能够提升开口率及解析度；由于施加负向电压的栅极也可以同时作为遮光层，因此遮光效果能够保持不变；由于制作工艺可以利用现有的制程及设备，因此不需要额外增加投资成本。
例如：如果低温多晶硅薄膜晶体管的导通电压最低为8V，在现有技术中，只有一个栅极的时候，施加在栅极上的电压为10V，由于回踢电压的影响，低温多晶硅薄膜晶体管的实际导通电压刚刚为8V，也就是说回踢电压为2V；本发明的低温多晶硅薄膜晶体管包括两个栅极，假如一个施加的电压为5V，此时回踢电压为1V，另一个施加的电压为-5V，低温多晶硅薄膜晶体管的实际导通电压为5V-1V-（-5V），即9V。因此通过这种方式，可以有效降低回踢电压，进而提高TFT效能。
其中，第一栅极2、沟道区域13以及第二栅极4分别至少部分重叠。一般来说，第一栅极2、沟道区域13以及第二栅极4可以相互之间完全重叠，也可以部分重叠；完全重叠时，第一栅极2和/或第二栅极4还可以超过沟道区域13。
参阅图2，低温多晶硅薄膜晶体管进一步包括：栅极绝缘层5、源极6以及漏极7；栅极绝缘层5覆盖多晶硅层3以及第二栅极4；源极6设置在栅极绝缘层5上，并通过设置在栅极绝缘层5中的第一通孔51，连接至源极区域11；漏极7设置在栅极绝缘层5上，并通过设置在栅极绝缘层5中的第二通孔52，连接至漏极区域12。
参见图3，图3是本发明低温多晶硅薄膜晶体管和现有技术中一个栅极的情况的设计示意图。由图可以看出，在低温多晶硅薄膜晶体管的驱动电压相同的情况下，施加正向电压的栅极的正向电压和原来低温多晶硅薄膜晶体管只有一个栅极的情况相比，是减小的。例如，原来低温多晶硅薄膜晶体管只有一个栅极的情况，施加在栅极上的正向电压是10V,在本发明的低温多晶硅薄膜晶体管包括两个栅极的情况下，施加在其中一个栅极上的正向电压可以是5V。
本发明还提供一种薄膜晶体管基板，薄膜晶体管基板包括基底以及设置在基底上的多个像素，多个像素阵列排列，且每个像素分别包括低温多晶硅薄膜晶体管以及与低温多晶硅薄膜晶体管电性连接的像素电极，其中，参见图1，低温多晶硅薄膜晶体管包括：第一栅极2、多晶硅层3以及第二栅极4；第一栅极2设置在基底1上；多晶硅层3设置在基底1上并覆盖第一栅极2，其中，多晶硅层3包括源极区域11、漏极区域12以及形成在源极区域11与漏极区域12之间的沟道区域13；第二栅极4设置在多晶硅层3上；其中，低温多晶硅薄膜晶体管在驱动时，第一栅极2与第二栅极4分别施加极性相反的第一电压和第二电压。
由于低温多晶硅薄膜晶体管包括第一栅极2和第二栅极4，在驱动时，第一栅极2与第二栅极4分别施加极性相反的第一电压和第二电压，这样使得回踢电压有效降低，进而提高TFT效能；在低温多晶硅薄膜晶体管的驱动电压相同的情况下，由于施加正向电压的栅极的正向电压和原来低温多晶硅薄膜晶体管只有一个栅极的情况相比，是减小的，因此施加正向电压的栅极电路宽度可以缩小，进而能够提升开口率及解析度；由于施加负向电压的栅极也可以同时作为遮光层，因此遮光效果能够保持不变；由于制作工艺可以利用现有的制程及设备，因此不需要额外增加投资成本。
其中，第一栅极2、沟道区域13以及第二栅极4分别至少部分重叠。一般来说，第一栅极2、沟道区域13以及第二栅极4可以相互之间完全重叠，也可以部分重叠；完全重叠时，第一栅极2和/或第二栅极4还可以超过沟道区域13。
参见图4，低温多晶硅薄膜晶体管进一步包括：栅极绝缘层5、源极6、漏极7以及钝化层8；栅极绝缘层5覆盖多晶硅层3以及第二栅极4；源极6设置在栅极绝缘层5上，并通过设置在栅极绝缘层5中的第一通孔51，连接至源极区域11；漏极7设置在栅极绝缘层5上，并通过设置在栅极绝缘层5中的第二通孔52，连接至漏极区域12；钝化层8覆盖栅极绝缘层5、源极6以及漏极7；其中，像素电极9设置在钝化层8上并通过设置在钝化层8中的第三通孔81连接漏极7。
其中，薄膜晶体管基板进一步包括：多条第一扫描线、多条第二扫描线以及多条数据线。
其中，每个像素中的低温多晶硅薄膜晶体管的第一栅极分别电性连接一条对应的第一扫描线，以通过第一扫描线而提供第一电压至第一栅极；每个像素中的低温多晶硅薄膜晶体管的第二栅极分别电性连接一条对应的第二扫描线，以通过第二扫描线而提供第二电压至第二栅极；每个像素中的低温多晶硅薄膜晶体管的源极分别电性连接一条对应的数据线，以在低温多晶硅薄膜晶体管导通时，通过数据线以及导通的低温多晶硅薄膜晶体管而将数据电压提供至像素电极。
其中，第一扫描线与低温多晶硅薄膜晶体管的第一栅极分别设置在同一层中；而第二扫描线与低温多晶硅薄膜晶体管的第二栅极分别设置在同一层中。通过这种方式，可以进一步地达到系统整合、节省空间的目标。
其中，薄膜晶体管基板进一步包括闸极驱动器，闸极驱动器包括多个闸极驱动单元，其中，每个闸极驱动单元分别电性连接第一扫描线与第二扫描线以同时驱动同一行排列的多个低温多晶硅薄膜晶体管。
参见图5，每个闸极驱动单元分别包括：第一开关元件10和反相器20。
第一开关元件10包括控制端101，输入端102以及输出端103，其中，控制端101电性连接时钟信号，输入端102电性连接闸极驱动单元的输入端301以接收闸极驱动信号，而输出端103作为闸极驱动单元的第一输出端302，其电性连接第二扫描线以输出第二电压至第二扫描线；
反相器20包括第二开关元件21和第三开关元件22。利用闸极驱动电路基板技术（Gate on Array，简写为GOA），可以将反相器电路增加在外围线路区。
第二开关元件21包括控制端211，输入端212以及输出端213，其中，控制端211电性连接闸极驱动单元的输入端301以接收闸极驱动信号，输入端212电性连接第一电压源；第三开关元件22其包括控制端221，输入端222以及输出端223，其中，控制端221电性连接闸极驱动单元的输入端301以接收闸极驱动信号，输入端222电性连接第二电压源；其中，第二开关元件21与第三开关元件22的输出端213、223电性连接在一起并作为闸极驱动单元的第二输出端303，其电性连接第一扫描线以输出第一电压至第一扫描线。
反相器可以将输入信号的相位反转180度，在实际应用中，还可以使用其它的反相器，在此不做限制。
其中，第二开关元件21为p型晶体管，而第三开关元件22为n型晶体管；且第二电压源所提供的电压与闸极驱动单元的输入端301所输入的闸极驱动信号的脉冲信号的极性相反。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (11)

  1. 一种低温多晶硅薄膜晶体管，其中，包括：
    基底；
    第一栅极，设置在所述基底上；
    多晶硅层，设置在所述基底上并覆盖所述第一栅极，其中，所述多晶硅层包括源极区域、漏极区域以及形成在所述源极区域与所述漏极区域之间的沟道区域；
    第二栅极，设置在所述多晶硅层上；
    其中，所述低温多晶硅薄膜晶体管在驱动时，所述第一栅极与所述第二栅极分别施加极性相反的第一电压和第二电压。
  2. 根据权利要求1所述的低温多晶硅薄膜晶体管，其中，所述第一栅极、所述沟道区域以及所述第二栅极分别至少部分重叠。
  3. 根据权利要求2所述的低温多晶硅薄膜晶体管，其中，进一步包括：
    栅极绝缘层，覆盖所述多晶硅层以及所述第二栅极；
    源极，设置在所述栅极绝缘层上，并通过设置在所述栅极绝缘层中的第一通孔，连接至所述源极区域；
    漏极，设置在所述栅极绝缘层上，并通过设置在所述栅极绝缘层中的第二通孔，连接至所述漏极区域。
  4. 根据权利要求3所述的低温多晶硅薄膜晶体管，其中，进一步包括：
    钝化层，覆盖所述栅极绝缘层、所述源极以及所述漏极；
    其中，所述钝化层中设置有第三通孔，当所述钝化层上设置像素电极时，所述像素电极通过所述第三通孔连接所述漏极。
  5. 一种薄膜晶体管基板，其中，所述薄膜晶体管基板包括基底以及设置在所述基底上的多个像素，所述多个像素阵列排列，且每个所述像素分别包括低温多晶硅薄膜晶体管以及与所述低温多晶硅薄膜晶体管电性连接的像素电极，其中，所述低温多晶硅薄膜晶体管包括：
    第一栅极，设置在所述基底上；
    多晶硅层，设置在所述基底上并覆盖所述第一栅极，其中，所述多晶硅层包括源极区域、漏极区域以及形成在所述源极区域与所述漏极区域之间的沟道区域；
    第二栅极，设置在所述多晶硅层上；
    其中，所述低温多晶硅薄膜晶体管在驱动时，所述第一栅极与所述第二栅极分别施加极性相反的第一电压和第二电压。
  6. 根据权利要求5所述的薄膜晶体管基板，其中，所述所述第一栅极、所述沟道区域以及所述第二栅极分别至少部分重叠。
  7. 根据权利要求6所述的薄膜晶体管基板，其中，所述低温多晶硅薄膜晶体管进一步包括：
    栅极绝缘层，覆盖所述多晶硅层以及所述第二栅极；
    源极，设置在所述栅极绝缘层上，并通过设置在所述栅极绝缘层中的第一通孔，连接至所述源极区域；
    漏极，设置在所述栅极绝缘层上，并通过设置在所述栅极绝缘层中的第二通孔，连接至所述漏极区域；
    钝化层，覆盖所述栅极绝缘层、所述源极以及所述漏极；
    其中，所述像素电极设置在所述钝化层上并通过设置在所述钝化层中的第三通孔连接所述漏极。
  8. 根据权利要求7所述的薄膜晶体管基板，其中，所述薄膜晶体管基板进一步包括：
    多条第一扫描线，其中，每个像素中的所述低温多晶硅薄膜晶体管的所述第一栅极分别电性连接一条对应的所述第一扫描线，以通过所述第一扫描线而提供所述第一电压至所述第一栅极；
    多条第二扫描线，其中，每个像素中的所述低温多晶硅薄膜晶体管的所述第二栅极分别电性连接一条对应的所述第二扫描线，以通过所述第二扫描线而提供所述第二电压至所述第二栅极；
    多条数据线，其中，每个像素中的所述低温多晶硅薄膜晶体管的所述源极分别电性连接一条对应的所述数据线，以在所述低温多晶硅薄膜晶体管导通时，通过所述数据线以及导通的所述低温多晶硅薄膜晶体管而将数据电压提供至所述像素电极。
  9. 根据权利要求8所述的薄膜晶体管基板，其中，所述第一扫描线与所述低温多晶硅薄膜晶体管的所述第一栅极分别设置在同一层中；而所述第二扫描线与所述低温多晶硅薄膜晶体管的所述第二栅极分别设置在同一层中。
  10. 根据权利要求8所述的薄膜晶体管基板，其中，所述薄膜晶体管基板进一步包括闸极驱动器，所述闸极驱动器包括多个闸极驱动单元，其中，每个所述闸极驱动单元分别电性连接所述第一扫描线与所述第二扫描线以同时驱动同一行排列的多个所述低温多晶硅薄膜晶体管，且每个所述闸极驱动单元分别包括：
    第一开关元件，其包括控制端，输入端以及输出端，其中，所述控制端电性连接时钟信号，所述输入端电性连接所述闸极驱动单元的输入端以接收闸极驱动信号，而所述输出端作为所述闸极驱动单元的第一输出端，其电性连接所述第二扫描线以输出所述第二电压至所述第二扫描线；
    反相器，其包括：
    第二开关元件，其包括控制端，输入端以及输出端，其中，所述控制端电性连接所述闸极驱动单元的输入端以接收闸极驱动信号，所述输入端电性连接第一电压源；
    第三开关元件，其包括控制端，输入端以及输出端，其中，所述控制端电性连接所述闸极驱动单元的输入端以接收闸极驱动信号，所述输入端电性连接第二电压源；
    其中，所述第二开关元件与所述第三开关元件的输出端电性连接在一起并作为所述闸极驱动单元的第二输出端，其电性连接所述第一扫描线以输出所述第一电压至所述第一扫描线。
  11. 根据权利要求10所述的薄膜晶体管基板，其中，所述第二开关元件为p型晶体管，而所述第三开关元件为n型晶体管；且所述第二电压源所提供的电压与所述闸极驱动单元的输入端所输入的闸极驱动信号的脉冲信号的极性相反。
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