WO2016101707A1 - 窄边框及配置有窄边框的显示器 - Google Patents

窄边框及配置有窄边框的显示器 Download PDF

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Publication number
WO2016101707A1
WO2016101707A1 PCT/CN2015/093290 CN2015093290W WO2016101707A1 WO 2016101707 A1 WO2016101707 A1 WO 2016101707A1 CN 2015093290 W CN2015093290 W CN 2015093290W WO 2016101707 A1 WO2016101707 A1 WO 2016101707A1
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Prior art keywords
integrated circuit
custom integrated
circuit chips
pixel data
circuit chip
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PCT/CN2015/093290
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English (en)
French (fr)
Inventor
刘安昱
李国盛
肖政东
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小米科技有限责任公司
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Application filed by 小米科技有限责任公司 filed Critical 小米科技有限责任公司
Priority to RU2016101388A priority Critical patent/RU2636273C2/ru
Priority to KR1020157036877A priority patent/KR101780351B1/ko
Priority to MX2016000472A priority patent/MX357246B/es
Priority to JP2016565549A priority patent/JP2017506369A/ja
Publication of WO2016101707A1 publication Critical patent/WO2016101707A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance

Definitions

  • the present disclosure relates to the field of displays, and in particular to a narrow bezel and a display configured with a narrow bezel.
  • the narrowing of the upper border, the left border and the right border of the display has been implemented in the related frame design, but an integrated circuit chip for controlling the display of the display is usually required in the lower frame of the display (abbreviation: IC, full name: integrated circuit) , flexible board soldering (ie FPC bonding) and pixel data lines (commonly referred to as source lines) and row control logic lines (referred to as: GIP, full name: Gate In Panel) lines, and integrated circuit chips, flexible circuit board soldering And the traces of the pixel data lines and the row control logic lines are affected by the process technology, which results in the lower border of the current display is usually wider.
  • IC integrated circuit chip for controlling the display of the display
  • GIP gate In Panel
  • the present disclosure provides a narrow bezel and a display configured with a narrow bezel.
  • the technical solution is as follows:
  • a narrow bezel of a display comprising equal length pixel data lines, row control logic lines, and at least two custom integrated circuit chips, each custom integrated circuit chip
  • the circuit on the upper layout is equivalent to the circuit laid out on the standard integrated circuit chip
  • Each of the custom integrated circuit chips is arranged laterally on the same straight line, and the sum of the widths of the respective custom integrated circuit chips in the lateral direction is greater than the width of the standard integrated circuit chip;
  • At least one of the pixel data line and the row control logic line is connected to each of the custom integrated circuit chips.
  • a display configured with a narrow bezel, the display comprising a display screen and the narrow bezel described in the first aspect.
  • FIG. 1 is a schematic diagram of an existing frame in a display according to an exemplary embodiment
  • FIG. 2A is a front elevational view of a narrow bezel in a display, according to an exemplary embodiment
  • FIG. 2B is a schematic perspective view of the narrow bezel pixel data line and the row control logic line of FIG. 2A arranged according to a layer of traces according to an exemplary embodiment
  • FIG. 2C is an enlarged side cross-sectional view of the narrow frame shown in FIG. 2A, according to an exemplary embodiment
  • FIG. 2D is a schematic diagram showing the pixel data lines and the row control logic lines in the narrow bezel shown in FIG. 2A arranged in two layers according to an exemplary embodiment
  • FIG. 2E is a perspective view of the narrow frame shown in FIG. 2D according to an exemplary embodiment
  • FIG. 2F is an enlarged side cross-sectional view of the narrow frame shown in FIG. 2D, according to an exemplary embodiment
  • FIG. 3A is a front elevational view showing a narrow bezel in a display according to another exemplary embodiment
  • FIG. 3B is an enlarged side cross-sectional view of the narrow frame shown in FIG. 3A according to an exemplary embodiment
  • FIG. 3C is a schematic diagram showing the pixel data lines and the row control logic lines in the narrow bezel shown in FIG. 3A arranged in two layers according to an exemplary embodiment
  • FIG. 3D is an enlarged side cross-sectional view of the narrow frame shown in FIG. 3C according to an exemplary embodiment
  • FIG. 4 is a front elevational view of a narrow bezel in a display according to still another exemplary embodiment
  • FIG. 5 is a schematic diagram of a display configured with a narrow bezel, according to an exemplary embodiment.
  • narrow border generally refers to the lower border of the display that is narrowed, and the display includes at least a display screen and a lower border.
  • FIG. 1 is a schematic diagram of an existing frame in a display according to an exemplary embodiment.
  • the standard integrated circuit chip 10 has a height C and a width A.
  • the frame further includes a pixel data line 12 and a row control logic line 14.
  • the number of row control logic lines 14 is small.
  • the number of pixel data lines 12, and the pixel data line 12 has a relatively high requirement for synchronous transmission when transmitting signals, and therefore it is necessary to seriously consider the wiring of the pixel data lines 12.
  • LTPs Low-temperature polysilicon technology
  • the integrated circuit chip is thinner and longer to implement, but the integrated circuit chip can be made shorter and thinner, so in order to reduce the width of the lower frame of the display as much as possible,
  • the standard integrated circuit chip can be changed to at least two shorter and thinner custom integrated circuit chips, as shown in FIG. 2A.
  • FIG. 2A is a schematic front view of a narrow bezel in a display according to an exemplary embodiment.
  • the narrow bezel 200 includes at least two custom integrated circuit chips 20, equal length pixel data lines 22, rows.
  • Control logic line 24 the circuitry laid down on each custom integrated circuit chip 20 is equivalent to the circuitry laid out on a standard integrated circuit chip.
  • Each of the custom integrated circuit chips 20 is sequentially arranged laterally on the same straight line L1, and the sum of the widths of the respective custom integrated circuit chips 20 in the lateral direction is greater than the width of the standard integrated circuit chip.
  • the sum of the widths D1+D2 of the two custom integrated circuits 20 will typically be greater than the width A of the standard integrated circuit chip 10 of FIG.
  • the layouts of the respective custom integrated circuit chips are the same, that is, the planes formed by the width and height of each of the custom integrated circuit chips are located on the same plane; and the arrangement of the custom integrated circuit chips is The direction is set to the first type of arrangement.
  • the first arrangement is that the width and height of the custom integrated circuit chip are parallel to the plane of the narrow frame.
  • 2B is a perspective view showing the narrow bezel pixel data line and the row control logic line of FIG.
  • the left custom integrated circuit chip 20 and The layout of the custom integrated circuit chip 20 on the right side is the same, that is, the surface formed by the width D1 and the high F of the custom integrated circuit chip 20 on the left side and the width D2 and the height of the custom integrated circuit chip 20 on the right side.
  • the faces formed by F are located on the same plane and are parallel to the face of the narrow bezel 200.
  • the line of the thickness H of the custom integrated circuit chip 20 is perpendicular to the face of the narrow bezel 200.
  • FIG. 2C is an enlarged side cross-sectional view of the narrow frame shown in FIG. 2A according to an exemplary embodiment.
  • the surface and the narrow frame formed by the width and height F of the custom integrated circuit chip 20 can be seen.
  • the faces of the 200 are parallel, and the thickness H of the custom integrated circuit chip 20 is perpendicular to the face of the narrow frame 200, wherein the face of the narrow frame 200 is the same or parallel to the face on which the display screen is located.
  • each adjacent two custom integrated circuit chips 20 are arranged in contact or not in contact with each other. That is, the distance between two adjacent custom integrated circuit chips 20 is greater than or equal to zero.
  • the sum of the widths of the respective custom integrated circuit chips 20 is greater than the width of the standard integrated circuit chip; when two adjacent custom integrated circuit chips 20 are adjacent.
  • there is no contact between the arrangements that is, there is a certain distance between adjacent custom integrated circuit chips 20, from the left side of the leftmost custom integrated circuit 20 to the right of the rightmost custom integrated circuit 20
  • the distance between the sides is typically greater than the width A of the standard integrated circuit chip 10 of FIG.
  • each of the custom integrated circuit chips 20 can be arranged laterally on the same straight line, that is, each custom integrated
  • the lateral center line of the circuit chip 20 is located on the same straight line L1. Obviously, it is an idealized state to position the horizontal center lines of the respective custom integrated circuit chips 20 on the same straight line L1. In actual layout, it is possible to These custom integrated circuit chips 20 are sequentially arranged side by side on the same straight line.
  • the circuits in the standard integrated circuit chip are distributed in the plurality of custom integrated circuit chips 20, in order to be as possible as possible.
  • the sum of the widths of the respective custom integrated circuit chips 20 in the lateral direction may be set to be larger than the width of the standard integrated circuit chip. Since the area occupied by the pixel data line 22 and the row control logic line 24 is constant, when the width of the occupyable trace area is widened, the pixel data line 22 and the row control logic line 24 are being traced.
  • the occupied height becomes smaller, that is, the height E1 in FIG. 2A is smaller than the height B in FIG. 1, so that the lower frame of the display is narrowed, and the narrowing of the lower frame of the display is achieved.
  • At least one of the pixel data line 22 and the row control logic line 24 is connected to each of the custom integrated circuit chips when the lower border of the display is actually narrowed. That is to say, a custom integrated circuit chip can be connected only to the pixel data line 22, or only the row control logic line 24 can be connected, or the pixel data line 22 and the row control logic line 24 can be connected at the same time, which can be integrated according to a custom.
  • the layout of the internal circuits in the circuit chip 20 is determined.
  • the pins on the upper side of each of the custom integrated circuit chips 20 are evenly arranged, and the pins are connected in one-to-one correspondence with the pixel data lines 22 and the row control logic lines 24.
  • the number of pins on the upper side of each of the custom integrated circuit chips 20 is the same as the number of the pixel data lines 22 and the row control logic lines 24.
  • the upper side of the custom integrated circuit chip 20 can also be set according to actual needs. For other purpose pins, this conceivable solution should not be used to limit the scope of protection of this embodiment.
  • each of the custom integrated circuit chips 20 Since the pins on the upper side of each of the custom integrated circuit chips 20 are evenly arranged, and the pins are in one-to-one correspondence with the pixel data lines 22 and the row control logic lines 24, the custom integrated circuits can be reduced as much as possible.
  • the upper side of the chip 20 is used to waste the area where the pixel data line 22 and the row control logic line 24 are wired, so that the pixel data line 22 and the row control logic line 24 are laid out as uniformly as possible to minimize the reduction in FIG. 2A.
  • Wiring height E1 is used to waste the area where the pixel data line 22 and the row control logic line 24 are wired, so that the pixel data line 22 and the row control logic line 24 are laid out as uniformly as possible to minimize the reduction in FIG. 2A.
  • the pixels in the display screen has certain requirements, that is, the pixels are required to be simultaneously displayed or simultaneously turned off, the pixels have high requirements on aging, and thus the pixel data lines 22
  • the length needs to be set to the same length.
  • the pixel data lines 22 need to be controlled at the same time, so that each adjacent two custom integrated circuit chips are connected by wires.
  • each of the custom integrated circuit chips 20 is used to control simultaneous transmission of signals to all of the connected pixel data lines 22.
  • each customization is performed.
  • the sum of the areas of the integrated circuit chips is typically equal to the area of the standard integrated circuit chip.
  • the sum of the areas of the individual integrated integrated circuit chips 20 may also be slightly larger than the area of the standard integrated circuit chip.
  • the height F of each of the custom integrated circuit chips 20 is the same, since the circuits in the respective custom integrated circuit chips 20 are dispersed by the standard integrated circuit chips into the respective custom integrated circuit chips 20, in each custom integration.
  • the height F of each of the custom integrated circuit chips 20 is smaller than the height C of the standard integrated circuit chip 10 of FIG. 1, and the width of each of the custom integrated circuit chips is They may be the same or different, for example, D1 and D2 may be the same or different.
  • each of the pixel data lines and the row control logic lines connected to the custom integrated circuit chip may be arranged in two or more layers. The corresponding port on the display is connected.
  • each of the pixel data lines and the row control logic lines connected to the custom integrated circuit are connected to corresponding ports on the display screen according to one or more arrangement manners, that is, all Both the pixel data line and the row control logic line are on the same level. Because the number of pixel data lines is too large, in order to further reduce the occupation of the height of the lower border of the pixel data lines, the first or both of the pixel data lines and the row control logic lines may be arranged at least respectively. On two levels. For example, in FIG.
  • a portion of the pixel data line 22 and the row control logic line 24 are evenly arranged on the first level and connected to the corresponding port 26 on the display screen, and the pixel data line 22 and the row control logic line 24 are The other part is evenly arranged on the second level and connected to the corresponding port 26 on the display.
  • FIG. 2D it is a schematic diagram of the pixel data lines and the row control logic lines in the narrow bezel shown in FIG. 2A arranged in two layers according to an exemplary embodiment.
  • the lines indicated by the solid lines in the pixel data line 22 and the row control logic line 24 are located on the first level, and the lines indicated by the broken lines are located on the second level.
  • FIG. 2E which is a perspective view of the narrow frame shown in FIG. 2D according to an exemplary embodiment.
  • the pixel data line 22 and the row control logic line 24 are indicated by solid lines.
  • the lines and the lines indicated by dashed lines are respectively located on two levels, but the custom integrated circuit chip 20 and the pins thereon are the same as those in FIGS. 2A and 2B.
  • FIG. 2F is an enlarged side cross-sectional view of the narrow frame shown in FIG. 2D according to an exemplary embodiment.
  • the pixel data lines 22 and the row control logic lines 24 respectively located on two levels are connected.
  • the surface formed by the width and height F of the custom integrated circuit chip 20 and the corresponding port on the custom integrated circuit chip 20 and the display screen Parallel to the face of the narrow bezel 200, the thickness H of the custom integrated circuit chip 20 is perpendicular to the face of the narrow bezel 200.
  • each pixel data line 22 and row control logic line 24 in FIG. 2B are located on the same level for routing, and each pixel data line 22 and row control logic line 24 in FIG. 2E are located at two levels.
  • the thickness of the lower border can be occupied, and the number of lines on the same layer can be reduced, thereby reducing the same line.
  • the layer faces the occupation of the layout area.
  • the line can reduce the occupation of the height of each layer, that is, the occupation of the height of the lower frame is reduced, thereby further narrowing the lower border. That is, the wiring height E2 in FIG.
  • 2D is smaller than the wiring height E1 in FIG. 2A, and thus the straight line L2 of the center line of the custom integrated circuit chip 20 on the left side and the custom integrated circuit chip 20 on the right side in FIG. 2D and FIG. 2A
  • the straight line L1 is different, and the straight line L2 is closer to the upper edge of the lower bezel 200 than the straight line L1, or closer to the display screen of the display.
  • the narrow frame of the display replaces the standard integrated circuit chip in the frame with at least two integrated circuit chips arranged side by side in parallel; since the total width of the integrated circuit chips arranged side by side is greater than The width of the standard integrated circuit chip, so that the width of the pixel data line and the row control logic line can be widened when the line is routed, thereby reducing the occupation of the height, thereby solving the problem of wide border in the related art; The effect of narrowing the display frame.
  • the arrangement direction of the custom integrated circuit chip is set to the second arrangement mode, and the second arrangement mode is: setting the custom integrated circuit chip perpendicular to the surface on which the display screen is located. That is, the layout of the custom integrated circuit chip is the same, and the width of the custom integrated circuit chip occupies the thickness of the lower frame of the display, and the thickness of the custom integrated circuit chip occupies the width of the lower frame of the display. That is to say, the width and height of the surface of each of the custom integrated circuit chips are all located on the same plane, and the width and height of each of the custom integrated circuit chips are perpendicular to the plane of the narrow frame.
  • FIG. 3A is a front view of a narrow bezel in a display according to another exemplary embodiment
  • the custom integrated circuit chip 20 disposed in the lower frame 200 of the display in FIG. 3A is still horizontally arranged.
  • a line L3 is disposed, and each of the custom integrated circuit chips 20 is disposed perpendicular to the surface on which the display screen is located, that is, the custom integrated circuit chip 20 is disposed at 90 degrees to the reference integrated circuit chip 10 of FIG. Since the thickness H of the custom integrated circuit chip 20 is much smaller than the width of the custom integrated circuit chip 20 (i.e., the width F in FIG. 2A), the lower bezel of the display can be narrowed. In order to more easily show the difference between FIG. 3A and FIG.
  • FIG. 3B is an enlarged side cross-sectional view of the narrow frame shown in FIG. 3A according to an exemplary embodiment.
  • the thickness H of the custom integrated circuit chip 20 occupies the height of the lower frame 200
  • the height F of the custom integrated circuit chip 20 occupies the thickness of the lower frame 200.
  • the custom integrated circuit chip The thickness H of the 20 is much smaller than the height F of the custom integrated circuit chip 20, so that the height of the custom integrated circuit chip 20 for the lower bezel 200 can be reduced, and the lower frame of the display can be narrowed.
  • the lower border can also connect each pixel data line and row control logic line connected to the custom integrated circuit to the corresponding port on the display screen in two or more layers.
  • each of the pixel data lines and the row control logic lines connected to the custom integrated circuit are connected to corresponding ports on the display screen in a layer or more arrangement manner, that is, all pixel data lines and row control.
  • the logic lines are all on the same level. Because the number of pixel data lines is too large, in order to further reduce the occupation of the height of the lower border of the pixel data lines, the first or both of the pixel data lines and the row control logic lines may be arranged at least respectively. On two levels. For example, a part of the pixel data line and the row control logic line are evenly arranged on the first layer and connected to the corresponding port on the display screen, and the other part of the pixel data line and the row control logic line are evenly arranged in the second. At the level, it is connected to the corresponding port on the display.
  • FIG. 3C it is a schematic diagram of the pixel data lines and the row control logic lines in the narrow bezel shown in FIG. 3A arranged in two layers according to an exemplary embodiment.
  • the line indicated by the solid line in the pixel data line 22 and the row control logic line 24 arranged in the lower frame 200 is located on the first level, and the line indicated by the broken line is located on the second level, and the lower frame 200 is located.
  • the rest of the arrangement and settings are the same as in Figure 3A, see in particular for the description in Figure 3A.
  • FIG. 3D is an enlarged side cross-sectional view of the narrow frame shown in FIG. 3C according to an exemplary embodiment.
  • the lower frame 200 is respectively located on two levels.
  • the pixel data line 22 and the row control logic line 24 are both connected to the custom integrated circuit chip 20 and the corresponding port on the display screen.
  • the thickness H of the custom integrated circuit chip 20 occupies the height of the lower frame 200, and the custom integrated circuit chip 20
  • the height F occupies the thickness of the lower frame 200.
  • each pixel data line 22 and row control logic line 24 in FIG. 3B are located on the same level for routing, and each pixel data line 22 and row control logic line 24 in FIG. 3D are located at two levels.
  • the thickness of the lower border can be occupied, and the number of lines on the same layer can be reduced, thereby reducing the same line.
  • the layer faces the occupation of the layout area.
  • the line can reduce the occupation of the height of each layer, that is, the occupation of the height of the lower frame is reduced, thereby further narrowing the lower border. That is, the height E4 in FIG.
  • 3C is smaller than the height E3 in FIG. 3A, and thus the line L4 of the center line of the custom integrated circuit chip 20 on the left side and the custom integrated circuit chip 20 on the right side in FIG. 3C is the same as that in FIG. 3A.
  • the line L3 is different, and the line L4 is closer to the upper edge of the lower frame 200 than the line L3, or closer to the display screen of the display.
  • the narrow frame of the display replaces the standard integrated circuit chip in the frame with at least two integrated circuit chips arranged side by side in parallel; since the total width of the integrated circuit chips arranged side by side is greater than The width of the standard integrated circuit chip, so that the width of the pixel data line and the row control logic line can be widened when the line is routed, thereby reducing the occupation of the height, thereby solving the problem of wide border in the related art; The effect of narrowing the display frame.
  • the configuration of the lower bezel shown in FIG. 3A is applicable to the configuration in FIG. 2A except that the arrangement direction of the custom integrated circuit chip is different from that in FIG. 2A.
  • the configuration of the lower bezel shown in FIG. 3A is applicable to the configuration in FIG. 2A except that the arrangement direction of the custom integrated circuit chip is different from that in FIG. 2A.
  • the description of FIG. 2A refer to the description of FIG. 2A, and details are not described herein again.
  • FIG. 4 it is a schematic diagram of a narrow bezel in a display according to still another exemplary embodiment.
  • the standard custom integrated circuit chip is split into three shorter and thinner custom integrated circuit chips 40, and the split custom integrated circuit chips 40 are arranged laterally on a straight line L5.
  • the sum of the areas of the custom integrated circuit chips 40 is equal to the area of the standard custom integrated circuit chip 10 of FIG. 1.
  • the sum of the widths of the custom integrated circuit chips 40 is greater than the width A of the standard custom integrated circuit chip 10 of FIG.
  • the height F' of these custom integrated circuit chips 40 is smaller than the height C of the standard custom integrated circuit chip 10 of FIG.
  • the pins on the upper side of these custom integrated circuit chips 40 are still evenly arranged, and these pins are connected one by one to the pixel data lines 42 and the row control logic lines 44, respectively.
  • the wiring height E5 in FIG. 4 is smaller than the wiring height B in FIG. 1, that is, the lower frame of the display is narrowed.
  • the narrow frame of the display replaces the standard integrated circuit chip in the frame with at least two integrated circuit chips arranged side by side in parallel; since the total width of the integrated circuit chips arranged side by side is greater than The width of the standard integrated circuit chip, so that the width of the pixel data line and the row control logic line can be widened when the line is routed, thereby reducing the occupation of the height, thereby solving the problem of wide border in the related art; The effect of narrowing the display frame.
  • FIG. 5 is a schematic diagram of a display configured with a narrow bezel according to an exemplary embodiment.
  • the display includes a display screen 520 and a narrow bezel 540, wherein the narrow bezel 540 is FIG. 2A to FIG. 2F. 3A to 3D or the narrow frame shown in FIG. 4, for details, refer to the description of FIG. 2A to FIG. 2F, FIG. 3A to FIG. 3D or FIG. 4, and details are not described herein again.
  • the display provided with the narrow bezel replaces the standard integrated circuit chip in the bezel with at least two integrated circuit chips arranged side by side in parallel; the total of the integrated circuit chips arranged side by side
  • the width is larger than the width of the standard integrated circuit chip, so that the width of the pixel data line and the row control logic line can be widened when the line is routed, thereby reducing the occupation of the height, thereby solving the problem of wide border in the related art. ; achieved the effect of narrowing the display frame.

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Abstract

本公开揭示了一种窄边框及配置有窄边框的显示器，属于显示器领域。所述显示器的窄边框包括：等长的像素数据线、行控制逻辑线以及至少两个自定义集成电路芯片，各个自定义集成电路芯片上布局的电路等同于标准集成电路芯片上布局的电路；各个自定义集成电路芯片依次横向排布在同一条直线上，各个自定义集成电路芯片在横向上的宽度之和大于所述标准集成电路芯片的宽度；每个自定义集成电路芯片上均连接有所述像素数据线和所述行控制逻辑线中的至少一种。通过将边框中标准集成电路芯片替换为至少两个横向并排排布的集成电路芯片；解决了相关技术中边框较宽的问题；达到了可以使显示器边框窄化的效果。

Description

窄边框及配置有窄边框的显示器
本申请要求于2015年1月26日提交中国专利局、申请号为201510038519.3的中国专利申请的优先权，以及2014年12月26日提交中国专利局、申请号为201410834739.2的中国专利申请的优先权，以上全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示器领域，特别涉及一种窄边框及配置有窄边框的显示器。
背景技术
随着显示器分辨率越来越大，为了尽可能的降低显示器边框的占用，各个生产厂商均致力于窄化显示器的边框。
相关边框设计中已经实现了对显示器的上边框、左边框和右边框的窄化，但由于显示器的下边框中通常需要布置有控制显示器显示的集成电路芯片(简称：IC，全称：integrated circuit)、软性电路板焊接(即FPC bonding)以及像素数据线(通常称为source线)和行控制逻辑线(简称：GIP，全称：Gate In Panel)线，且集成电路芯片、软性电路板焊接以及像素数据线和行控制逻辑线的走线均受到制程工艺的影响，因此导致了目前的显示器的下边框通常比较宽。
发明内容
为了解决相关技术中的问题，本公开提供一种窄边框及配置有窄边框的显示器。所述技术方案如下：
根据本公开实施例的第一方面，提供一种显示器的窄边框，所述窄边框包括等长的像素数据线、行控制逻辑线以及至少两个自定义集成电路芯片，各个自定义集成电路芯片上布局的电路等同于标准集成电路芯片上布局的电路；
各个自定义集成电路芯片依次横向排布在同一条直线上，各个自定义集成电路芯片在横向上的宽度之和大于所述标准集成电路芯片的宽度；
每个自定义集成电路芯片上均连接有所述像素数据线和所述行控制逻辑线中的至少一种。
根据本公开实施例的第二方面，提供一种配置有窄边框的显示器，所述显示器包括显示屏和第一方面所述的窄边框。
本公开的实施例提供的技术方案可以包括以下有益效果：
通过将边框中标准集成电路芯片替换为至少两个横向并排排布的集成电路芯片；由于并排排布的集成电路芯片的总宽度大于标准集成电路芯片的宽度，从而使得像素数据线和行控制逻辑线在走线时所能够占用的宽度变宽，从而可以减少对高度的占用，因此解决了 相关技术中边框较宽的问题；达到了可以使显示器边框窄化的效果。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并于说明书一起用于解释本公开的原理。
图1是根据一示例性实施例示出的一种显示器中现有边框的示意图；
图2A是根据一示例性实施例示出的一种显示器中窄边框的正面示意图；
图2B是根据一示例性实施例示出的图2A所示窄边框像素数据线和行控制逻辑线按照一层走线排布的立体示意图；
图2C是根据一示例性实施例示出的图2A所示窄边框放大后的侧剖面示意图；
图2D是根据一示例性实施例示出的图2A所示窄边框中像素数据线和行控制逻辑线按照两层走线排布的示意图；
图2E是根据一示例性实施例示出的图2D所示窄边框的立体示意图；
图2F是根据一示例性实施例示出的图2D所示窄边框放大后的侧剖面示意图；
图3A是根据另一示例性实施例示出的一种显示器中窄边框的正面示意图；
图3B是根据一示例性实施例示出的图3A所示窄边框放大后的侧剖面示意图；
图3C是根据一示例性实施例示出的图3A所示窄边框中像素数据线和行控制逻辑线按照两层走线排布的示意图；
图3D是根据一示例性实施例示出的图3C所示窄边框放大后的侧剖面示意图；
图4是根据再一示例性实施例示出的一种显示器中窄边框的正面示意图；
图5是根据一示例性实施例示出的一种配置有窄边框的显示器的示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。文中所讲的“窄边框”通常指显示器被窄化后的下边框，显示器至少包括显示屏和下边框。
请参见图1所示，其根据一示例性实施例示出的一种显示器中现有边框的示意图。在图1所示的边框中，标准集成电路芯片10的高度为C，宽度为A，该边框中还包含有像素数据线12和行控制逻辑线14，通常行控制逻辑线14的数量远少于像素数据线12的数量，且像素数据线12在传输信号时对同步传输的要求比较高，因此需要着重考虑像素数据线12的布线。对于a硅和铟镓锌氧化物(简称：igzo，全称：indium gallium zinc oxide) 材质的高清显示屏来说，每根像素数据线12和每根行控制逻辑线14都与标准集成电路芯片10的管脚相连，以分辨率为1280*1024的显示屏来讲，由于每个像素均由三个晶体管(分别对应红、绿、蓝三种颜色)组成，且每一列需要一条像素数据线，因此需要有1280*3＝3840根像素数据线在有限的宽度内进行布线，即便是低温多晶硅技术(简称：LTPs，全称：Low Temperature Poly-silicon)具备mux电路，也需要大约1280根像素数据线。
所以，从有限的宽度A连接到显示屏面板内的像素数据线端需要占用一定的高度，同时显示屏进行显示时，还需要保证像素数据线12所连接的像素点能够在显示时保持同步，也即需要将这些像素数据线12做成等长，这样就不得不占用更高的高度B，所以显示器的下边框就比较宽。
由于受到现有制程工艺的限制，集成电路芯片要做的更细更长不太容易实现，但可以将集成电路芯片做的更短更细，因此为了尽可能的减少显示器的下边框的宽度，可以将标准集成电路芯片变更为至少两个更短更细的自定义集成电路芯片，具体可以参见图2A所示。
图2A是根据一示例性实施例示出的一种显示器中窄边框的正面示意图，在图2A中，该窄边框200包括至少两个自定义集成电路芯片20、等长的像素数据线22、行控制逻辑线24，各个自定义集成电路芯片20上布局的电路等同于标准集成电路芯片上布局的电路。
各个自定义集成电路芯片20依次横向排布在同一条直线上L1，各个自定义集成电路芯片20在横向上的宽度之和大于标准集成电路芯片的宽度。如图2A中的两个自定义集成电路芯片20，两个自定义集成电路20的宽度之和D1+D2通常会大于图1中的标准集成电路芯片10的宽度A。
在本实施例中，各个自定义集成电路芯片的排布相同，也即，各个自定义集成电路芯片的宽和高形成的面均位于同一个平面上；且将自定义集成电路芯片的排布方向设置为第一种排布方式，第一种排布方式为：自定义集成电路芯片的宽和高形成的面与窄边框所在面平行。请参见图2B，其是根据一示例性实施例示出的图2A所示窄边框像素数据线和行控制逻辑线按照一层走线排布的立体示意图，左侧的自定义集成电路芯片20和右侧的自定义集成电路芯片20的排布相同，也即左侧的自定义集成电路芯片20的宽D1和高F所形成的面和右侧的自定义集成电路芯片20的宽D2和高F所形成的面位于同一个平面上，且均与窄边框200所在面平行，自定义集成电路芯片20的厚H所在的线垂直于窄边框200所在面。
请进一步参见图2C所示，其是根据一示例性实施例示出的图2A所示窄边框放大后的侧剖面示意图，可见自定义集成电路芯片20的宽和高F所形成的面与窄边框200所在面平行，自定义集成电路芯片20的厚H垂直于窄边框200所在面，其中窄边框200所在面与所在显示器上显示屏所在的面相同或平行。
可选的，每相邻两个自定义集成电路芯片20之间接触排布或不接触排布。也就是说，两个相邻的自定义集成电路芯片20之间的距离大于或等于0。当每相邻两个自定义集成电路芯片20之间均接触排布时，各个自定义集成电路芯片20的宽度之和大于标准集成电路芯片的宽度；当相邻两个自定义集成电路芯片20之间均不接触排布时，即相邻的自定义集成电路芯片20之间存在一定的距离，则从最左边的自定义集成电路20的左侧边到最右边自定义集成电路20的右侧边之间的距离通常会大于图1中的标准集成电路芯片10的宽度A。
为了减少自定义集成电路芯片在纵向上占用的高度，以尽可能的窄化显示器的下边框，各个自定义集成电路芯片20可以依次横向排布在同一条直线上，也即，各个自定义集成电路芯片20的横向中心线位于同一条直线L1上，显然，将各个自定义集成电路芯片20的横向中心线均位于同一条直线L1上是理想化的状态，在实际布局时，可以尽可能的将这些自定义集成电路芯片20依次横向排布在同一条直线上。
由于各个自定义集成电路芯片20上布局的电路等同于标准集成电路芯片上布局的电路，也即将标准集成电路芯片中的电路分布在了多个自定义集成电路芯片20中，为了能够尽可能的缩小像素数据线22、行控制逻辑线24走线时所占用的高度，可以将各个自定义集成电路芯片20在横向上的宽度之和设置为大于标准集成电路芯片的宽度。由于像素数据线22、行控制逻辑线24在走线时所占用的面积是一定的，当可占用的走线面积的宽度变宽后，像素数据线22、行控制逻辑线24在走线时所占用的高度就会变小，也即图2A中的高度E1小于图1中的高度B，从而使得显示器的下边框变窄，实现了对显示器下边框的窄化。
在实际窄化显示器的下边框时，每个自定义集成电路芯片上均连接有像素数据线22和行控制逻辑线24中的至少一种。也就是说，一个自定义集成电路芯片可以仅连接像素数据线22，也可以仅连接行控制逻辑线24，也可以同时连接像素数据线22和行控制逻辑线24，具体的可以根据自定义集成电路芯片20中内部电路的布局决定。
可选的，各个自定义集成电路芯片20上侧的管脚均匀排布，且这些管脚与像素数据线22和行控制逻辑线24一一对应连接。一般的，各个自定义集成电路芯片20上侧的管脚的数量与像素数据线22和行控制逻辑线24的数量相同，显然，根据实际需要，自定义集成电路芯片20的上侧还可以设置其他用途的管脚，这种易于思及的方案不应当用于限制本实施例所要保护的范围。
由于各个自定义集成电路芯片20上侧的管脚是均匀排布的，且这些管脚与像素数据线22和行控制逻辑线24一一对应的，因此可以尽可能地降低对自定义集成电路芯片20上侧用于对像素数据线22和行控制逻辑线24进行布线的区域的浪费，使得像素数据线22和行控制逻辑线24尽可能的均匀布局，以最大化的减少图2A中的布线高度E1。
在一种可能的实现方式中，由于显示屏中对像素的显示有一定的要求，即需要这些像素同时显示或同时关闭显示，因此像素对时效具有很高的要求，也因此像素数据线22的 长度需要设置为等长。为了能够保证这些像素能被在同一时刻控制，在像素数据线22等长的前提下，需要在同一时刻控制像素数据线22，因此每相邻两个自定义集成电路芯片之间通过导线连接，以便于各个自定义集成电路芯片20可以同时向连接着的像素数据线22发送信号。也即，各个自定义集成电路芯片20用于控制向连接的所有像素数据线22同时发送信号。
此外，由于各个自定义集成电路芯片20中的电路是由标准集成电路芯片分散到各个自定义集成电路芯片20中的，且电路中的元器件占用的排布空间是固定的，因此各个自定义集成电路芯片的面积之和通常等于所述标准集成电路芯片的面积。可选的，考虑到各个自定义集成电路芯片20边缘对面积的损耗，各个自定义集成电路芯片20的面积之和通常还可以略大于标准集成电路芯片的面积。
可选的，各个自定义集成电路芯片20的高度F相同，由于各个自定义集成电路芯片20中的电路是由标准集成电路芯片分散到各个自定义集成电路芯片20中的，在各个自定义集成电路芯片20的面积之和等于标准集成电路芯片的面积时，各个自定义集成电路芯片20的高度F均小于图1中标准集成电路芯片10的高度C，而各个自定义集成电路芯片的宽度则可以相同或不同，比如，D1和D2可以相同，也可以不同。
一种可能的实现方式中，为了进一步窄化显示器的下边框，还可以将与自定义集成电路芯片连接的各条像素数据线和行控制逻辑线按照两层或两层以上的排布方式与显示屏上的对应端口连接。
在图2A、图2B以及图2C中，与自定义集成电路连接的各条像素数据线和行控制逻辑线是按照一层以上的排布方式与显示屏上的对应端口连接，也即，所有像素数据线和行控制逻辑线均位于同一层面上。而由于像素数据线的数量过多，为了能够进一步减少这些像素数据线对下边框高度的占用，还可以将像素数据线和行控制逻辑线中的前一种或全部两种分别排布在至少两个层面上。比如，图2B中，像素数据线22和行控制逻辑线24中的一部分均匀排布在第一层面上并与显示屏上的对应端口26连接，将像素数据线22和行控制逻辑线24中的另一部分均匀排布在第二层面上并与显示屏上的对应端口26连接。
请参见图2D所示，其是根据一示例性实施例示出的图2A所示窄边框中像素数据线和行控制逻辑线按照两层走线排布的示意图。在图2D中，像素数据线22和行控制逻辑线24中用实线表示的线路位于第一层面上，用虚线表示的线路位于第二层面上。为了更容易展示两个层面，请参见图2E所示，其是根据一示例性实施例示出的图2D所示窄边框的立体示意图，像素数据线22和行控制逻辑线24中用实线表示的线路与用虚线表示的线路分别位于两个层面上，但自定义集成电路芯片20以及其上的管脚均与图2A和图2B中的相同。
请进一步参见图2F所示，其是根据一示例性实施例示出的图2D所示窄边框放大后的侧剖面示意图，分别位于两个层面上的像素数据线22和行控制逻辑线24均连接于自定义集成电路芯片20和显示屏上的对应端口自定义集成电路芯片20的宽和高F所形成的面 与窄边框200所在面平行，自定义集成电路芯片20的厚H垂直于窄边框200所在面。
结合图2B和图2E可知，图2B中各个像素数据线22和行控制逻辑线24位于同一个层面上进行走线，而图2E中各个像素数据线22和行控制逻辑线24位于两个层面上进行走线，由于各个像素数据线22和行控制逻辑线24位于两个层面上进行走线时，可以占用下边框的厚度，且可以减少同一个层面上线路的数量，从而可以减少同一个层面对布局面积的占用，在每个层面的宽度不变的情况下，线路可以减少对每个层面的高度的占用，也即减少了对下边框高度的占用，从而进一步窄化了下边框，即图2D中布线高度E2小于图2A中的布线高度E1，也因此图2D中左侧的自定义集成电路芯片20和右侧的自定义集成电路芯片20的中心线所在的直线L2与图2A中的直线L1不同，直线L2与直线L1相比，更靠近下边框200的上边沿，或者更靠近显示器的显示屏。
综上所述，本公开实施例提供的显示器的窄边框，通过将边框中标准集成电路芯片替换为至少两个横向并排排布的集成电路芯片；由于并排排布的集成电路芯片的总宽度大于标准集成电路芯片的宽度，从而使得像素数据线和行控制逻辑线在走线时所能够占用的宽度变宽，从而可以减少对高度的占用，因此解决了相关技术中边框较宽的问题；达到了可以使显示器边框窄化的效果。
在一种可选的实现方式中，为了尽可能的缩小自定义集成电路芯片的宽度对显示器下边框宽度的占用，以进一步窄化显示器的下边框，在设计显示器的下边框时，还可以将自定义集成电路芯片的排布方向设置为第二种排布方式，第二种排布方式为：将自定义集成电路芯片垂直于显示屏所在的面进行设置。也即自定义集成电路芯片的排布相同，且自定义集成电路芯片的宽度对显示器下边框的厚度进行占用，而自定义集成电路芯片的厚度对显示器下边框的宽度进行占用。也就是说，各个自定义集成电路芯片的宽和高形成的面均位于同一个平面上，且每个自定义集成电路芯片的宽和高形成的面与窄边框所在面垂直。
请参见图3A所示，其是根据另一示例性实施例示出的一种显示器中窄边框的正面示意图，图3A中显示器下边框200中设置的自定义集成电路芯片20仍旧横向排布在同一条直线L3上，且各个自定义集成电路芯片20垂直于显示屏所在的面进行设置，也即自定义集成电路芯片20与图1中的基准集成电路芯片10成90°设置。由于自定义集成电路芯片20的厚度H远小于自定义集成电路芯片20的宽度(即图2A中的宽度F)，因此可以窄化显示器的下边框。为了更容易展示图3A与图2A的区别，请进一步参见图3B所示，其是根据一示例性实施例示出的图3A所示窄边框放大后的侧剖面示意图。在图3B中，自定义集成电路芯片20的厚度H占用下边框200的高度，自定义集成电路芯片20的高度F占用下边框200的厚度，结合图3B和图2C可知，自定义集成电路芯片20的厚度H远小于自定义集成电路芯片20的高度F，因此可以减少自定义集成电路芯片20对下边框200高度的占用，窄化了显示器的下边框。
同样的，在根据图3A所示对自定义集成电路芯片20进行排布时，为了进一步地窄化 下边框，还可以将与自定义集成电路连接的各条像素数据线和行控制逻辑线按照两层或两层以上的排布方式与显示屏上的对应端口连接。
在图3A中，与自定义集成电路连接的各条像素数据线和行控制逻辑线是按照一层以上的排布方式与显示屏上的对应端口连接，也即，所有像素数据线和行控制逻辑线均位于同一层面上。而由于像素数据线的数量过多，为了能够进一步减少这些像素数据线对下边框高度的占用，还可以将像素数据线和行控制逻辑线中的前一种或全部两种分别排布在至少两个层面上。比如，像素数据线和行控制逻辑线中的一部分均匀排布在第一层面上并与显示屏上的对应端口连接，将像素数据线和行控制逻辑线中的另一部分均匀排布在第二层面上并与显示屏上的对应端口连接。
请参见图3C所示，其是根据一示例性实施例示出的图3A所示窄边框中像素数据线和行控制逻辑线按照两层走线排布的示意图。在图3C中，下边框200中排布的像素数据线22和行控制逻辑线24中用实线表示的线路位于第一层面上，用虚线表示的线路位于第二层面上，下边框200中其余的排布以及设置均与图3A中的相同，具体参见对图3A中的描述。为了更容易展示两个层面，请进一步参见图3D所示，其是根据一示例性实施例示出的图3C所示窄边框放大后的侧剖面示意图，下边框200中分别位于两个层面上的像素数据线22和行控制逻辑线24均连接于自定义集成电路芯片20和显示屏上的对应端口，自定义集成电路芯片20的厚度H占用下边框200的高度，自定义集成电路芯片20的高度F占用下边框200的厚度。
结合图3B和图3D可知，图3B中各个像素数据线22和行控制逻辑线24位于同一个层面上进行走线，而图3D中各个像素数据线22和行控制逻辑线24位于两个层面上进行走线，由于各个像素数据线22和行控制逻辑线24位于两个层面上进行走线时，可以占用下边框的厚度，且可以减少同一个层面上线路的数量，从而可以减少同一个层面对布局面积的占用，在每个层面的宽度不变的情况下，线路可以减少对每个层面的高度的占用，也即减少了对下边框高度的占用，从而进一步窄化了下边框，即图3C中高度E4小于图3A中的高度E3，也因此图3C中左侧的自定义集成电路芯片20和右侧的自定义集成电路芯片20的中心线所在的直线L4与图3A中的直线L3不同，直线L4与直线L3相比，更靠近下边框200的上边沿，或者更靠近显示器的显示屏。
综上所述，本公开实施例提供的显示器的窄边框，通过将边框中标准集成电路芯片替换为至少两个横向并排排布的集成电路芯片；由于并排排布的集成电路芯片的总宽度大于标准集成电路芯片的宽度，从而使得像素数据线和行控制逻辑线在走线时所能够占用的宽度变宽，从而可以减少对高度的占用，因此解决了相关技术中边框较宽的问题；达到了可以使显示器边框窄化的效果。
需要补充说明的是，图3A中所示的下边框的构造除了自定义集成电路芯片的排布方向与图2A中的不同之外，其余适用于图2A中的构造均适用于图3A中，具体的构造均可以参见对图2A的描述，这里就不再赘述。
还需要补充说明的是，图2A和图3A中仅示例性示出了2个更短更细的自定义集成电路芯片20，在实际应用中，还可以将标准自定义集成电路芯片拆分为3个或3个以上更短更细的自定义集成电路芯片。请参见图4所示，其是根据再一示例性实施例示出的一种显示器中窄边框的示意图。在图4中，将标准自定义集成电路芯片拆分为3个更短更细的自定义集成电路芯片40，拆分后的这些自定义集成电路芯片40依次横向排布在一条直线L5上，这些自定义集成电路芯片40的面积之和等于图1中标准自定义集成电路芯片10的面积，这些自定义集成电路芯片40的宽度之和大于图1中标准自定义集成电路芯片10的宽度A，这些自定义集成电路芯片40的高度F’小于图1中标准自定义集成电路芯片10的高度C。这些自定义集成电路芯片40上侧的管脚仍旧均匀排布，且这些管脚分别与像素数据线42和行控制逻辑线44一一连接。类似的，图4中的布线高度E5小于图1中的布线高度B，即窄化了显示器的下边框。
综上所述，本公开实施例提供的显示器的窄边框，通过将边框中标准集成电路芯片替换为至少两个横向并排排布的集成电路芯片；由于并排排布的集成电路芯片的总宽度大于标准集成电路芯片的宽度，从而使得像素数据线和行控制逻辑线在走线时所能够占用的宽度变宽，从而可以减少对高度的占用，因此解决了相关技术中边框较宽的问题；达到了可以使显示器边框窄化的效果。
图5是根据一示例性实施例示出的一种配置有窄边框的显示器的示意图，在图中，该显示器包括显示屏520和窄边框540，其中的窄边框540为图2A至图2F、图3A至图3D或图4中示出的窄边框，具体可以参见对图2A至图2F、图3A至图3D或图4的描述，这里就不再赘述。
综上所述，本公开实施例提供的配置有窄边框的显示器，通过将边框中标准集成电路芯片替换为至少两个横向并排排布的集成电路芯片；由于并排排布的集成电路芯片的总宽度大于标准集成电路芯片的宽度，从而使得像素数据线和行控制逻辑线在走线时所能够占用的宽度变宽，从而可以减少对高度的占用，因此解决了相关技术中边框较宽的问题；达到了可以使显示器边框窄化的效果。
还需要补充说明的是，本公开各个实施例中在描述自定义集成电路芯片中的“高”、“宽”和“厚”时，均基于上述各个附图中所示，同一个自定义集成电路芯片中的宽度值大于高度值，且高度值大于厚度值。本公开各个实施例中自定义集成电路芯片中的“高”、“宽”和“厚”仅用于方便描述，并不用于限定本公开的保护范围。在实际应用中，还可以将自定义集成电路芯片中的“高”称为“宽”，将自定义集成电路芯片中的“宽”称为“长”等。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (9)

  1. 一种显示器的窄边框，其特征在于，所述窄边框包括等长的像素数据线、行控制逻辑线以及至少两个自定义集成电路芯片，各个自定义集成电路芯片上布局的电路等同于标准集成电路芯片上布局的电路；
    各个自定义集成电路芯片依次横向排布在同一条直线上，各个自定义集成电路芯片在横向上的宽度之和大于所述标准集成电路芯片的宽度；
    每个自定义集成电路芯片上均连接有所述像素数据线和所述行控制逻辑线中的至少一种。
  2. 根据权利要求1所述的窄边框，其特征在于，每相邻两个自定义集成电路芯片之间通过导线连接，各个自定义集成电路芯片用于控制向连接的所有所述像素数据线同时发送信号。
  3. 根据权利要求1所述的窄边框，其特征在于，各个自定义集成电路芯片的面积之和等于所述标准集成电路芯片的面积。
  4. 根据权利要求3所述的窄边框，其特征在于，各个自定义集成电路芯片的高度相同，且均小于所述标准集成电路芯片的高度，各个自定义集成电路芯片的宽度相同或不同。
  5. 根据权利要求1所述的窄边框，其特征在于，每相邻两个自定义集成电路芯片之间接触排布或不接触排布。
  6. 根据权利要求1所述的窄边框，其特征在于，各个自定义集成电路芯片上侧的管脚均匀排布，且所述管脚与所述像素数据线和所述行控制逻辑线一一对应连接。
  7. 根据权利要求1所述的窄边框，其特征在于，各个自定义集成电路芯片的宽和高形成的面均位于同一个平面上；
    且每个自定义集成电路芯片的宽和高形成的面与所述窄边框所在面平行；或者，每个自定义集成电路芯片的宽和高形成的面与所述窄边框所在面垂直。
  8. 根据权利要求1至7中任一所述的窄边框，其特征在于，与各个自定义集成电路芯片连接的所述像素数据线和所述行控制逻辑线按照至少一层排布方式与显示屏上的对应端口连接。
  9. 一种配置有窄边框的显示器，其特征在于，所述显示器包括显示屏和如权利要求 1至8中任一所述的窄边框。
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