WO2016074349A1 - 一种薄膜晶体管和阵列基板的制作方法及相应装置 - Google Patents

一种薄膜晶体管和阵列基板的制作方法及相应装置 Download PDF

Info

Publication number
WO2016074349A1
WO2016074349A1 PCT/CN2015/071977 CN2015071977W WO2016074349A1 WO 2016074349 A1 WO2016074349 A1 WO 2016074349A1 CN 2015071977 W CN2015071977 W CN 2015071977W WO 2016074349 A1 WO2016074349 A1 WO 2016074349A1
Authority
WO
WIPO (PCT)
Prior art keywords
active layer
drain
source
pattern
thin film
Prior art date
Application number
PCT/CN2015/071977
Other languages
English (en)
French (fr)
Inventor
刘圣烈
宋泳锡
金熙哲
崔承镇
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/785,397 priority Critical patent/US9923085B2/en
Publication of WO2016074349A1 publication Critical patent/WO2016074349A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method and a device for fabricating a thin film transistor and an array substrate.
  • the structure mainly includes: a gate 1, an active layer 2, a source 3 and a drain 4; A gate insulating layer 5 is disposed between the gate 1 and the active layer 2.
  • the source 3 and the drain 4 are disposed in the same layer, and the source 3 and the drain 4 are electrically connected to the active layer 2, respectively.
  • the resistance at the ohmic contact a of the active layer and the source and the drain has a great influence on the reliability and uniformity of the TFT, and therefore, in the process of fabricating the TFT Those skilled in the art have attempted to reduce the resistance at the ohmic contact a of the active layer with the source and drain using a variety of methods.
  • One of the methods is to reduce the composition of oxygen atoms in the active layer by plasma treatment, thereby bringing the active layer to an n+ layer having amorphous silicon, thereby reducing the active layer and the source and drain.
  • the ohmic contact resistance at a however, the implementation of the plasma processing process is complicated, which increases the complexity of the TFT fabrication process, and affects the uniformity and stability of the active layer, which is disadvantageous for ensuring the production efficiency of the TFT.
  • Various embodiments of the present invention provide a method and a device for fabricating a thin film transistor and an array substrate for reducing ohmic of an active layer and a source and a drain in a thin film transistor. Resistance at the contact.
  • An embodiment of the present invention provides a method of fabricating a thin film transistor, including: forming a pattern including a gate, an active layer, a source, and a drain on a substrate; wherein the source and the drain are respectively
  • the active layer is electrically connected, and further includes:
  • the substrate is annealed to make the source at the ohmic contact of the active layer with the source and the drain And ions of the drain are thermally diffused to the active layer.
  • the substrate is annealed to make
  • the ions of the source and the drain at the ohmic contact of the active layer and the source and the drain are thermally diffused to the active layer, thereby causing ions having a source and a drain in the active layer, thereby changing the active layer
  • the composition reduces the resistance of the active layer to the ohmic contact of the source and the drain, which provides a guarantee for the uniformity and reliability of the thin film transistor.
  • the annealing process is relatively simple to implement with respect to the plasma processing, does not increase the complexity of the fabrication process of the entire thin film transistor, and is advantageous for ensuring the production efficiency of the thin film transistor.
  • annealing the substrate substrate specifically includes: lining the lining in a protective gas or vacuum atmosphere The base substrate is heated for a predetermined period of time and then naturally cooled to room temperature.
  • the predetermined duration of the annealing process is 20 minutes to 60 minutes.
  • the material of the source and the drain is copper, titanium or molybdenum; the material of the active layer is Semiconductor oxide material.
  • the heating temperature of the substrate is 300. Degree to 350 degrees;
  • the heating temperature to the substrate is 300 degrees or less.
  • a pattern of the active layer is formed after the pattern of the source and drain electrodes is formed.
  • a pattern of an insulating layer is formed on the base substrate on which the pattern of the active layer is formed, and the source and the drain are electrically connected to the active layer through via holes in the insulating layer, respectively.
  • One embodiment of the present invention provides a thin film transistor fabricated using the above-described method of fabricating a thin film transistor of the present invention.
  • An embodiment of the present invention provides a method for fabricating an array substrate, comprising: forming a pattern of a thin film transistor on a substrate, and sequentially forming a pattern of a passivation layer and a pixel electrode on the pattern of the thin film transistor, the forming
  • the pattern of the passivation layer specifically includes:
  • the annealed film of the passivation layer is patterned to form a pattern of the passivation layer.
  • the base substrate is annealed to make the source at the ohmic contact between the active layer and the source and the drain.
  • the ions of the drain are thermally diffused to the active layer, thereby causing ions having source and drain in the active layer to change the composition of the active layer, reducing ohmic contact between the active layer and the source and drain.
  • the resistance at the place provides a guarantee for the uniformity and reliability of the thin film transistor.
  • the passivation layer film isolates the source and the drain from oxygen, and the oxidation reaction of the source and the drain during the annealing process can be avoided.
  • One embodiment of the present invention provides an array substrate fabricated using the above-described array substrate manufacturing method of the present invention.
  • 1 is a schematic structural view of a conventional thin film transistor
  • FIG. 2a is a schematic structural view of a bottom gate type thin film transistor according to an embodiment of the present invention.
  • FIG. 2b is a schematic structural view of a top gate type thin film transistor according to another embodiment of the present invention.
  • FIG. 3 is a flow chart of a method of fabricating a thin film transistor according to still another embodiment of the present invention.
  • 4a to 4d are schematic structural views of a method for fabricating a thin film transistor according to still another embodiment of the present invention after performing each step;
  • FIG. 5 is a flow chart of a method of fabricating a passivation layer in an array substrate according to an embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of a method for fabricating an array substrate according to another embodiment of the present invention after performing each step.
  • each film layer in the drawings do not reflect the true proportions of the thin film transistor and the components of the array substrate, and the purpose is only to illustrate the contents of the present invention.
  • An embodiment of the present invention provides a method of fabricating a thin film transistor, comprising: forming a pattern including a gate, an active layer, a source, and a drain on a substrate; wherein the source and the drain are respectively
  • the source layer is electrically connected and also includes:
  • the substrate is annealed to thermally diffuse the ions of the source and the drain at the ohmic contact of the active layer with the source and the drain to Active layer.
  • an underlying substrate is annealed so that The ions of the source and the drain at the ohmic contact of the active layer and the source and the drain are thermally diffused to the active layer, thereby causing ions having a source and a drain in the active layer to thereby change the active layer.
  • the composition reduces the resistance of the active layer to the ohmic contact of the source and the drain, which provides a guarantee for the uniformity and reliability of the thin film transistor.
  • the annealing process is relatively simple to implement with respect to the plasma processing, does not increase the complexity of the fabrication process of the entire thin film transistor, and is advantageous for ensuring the production efficiency of the thin film transistor.
  • the method for fabricating the above thin film transistor provided by one embodiment of the present invention is used.
  • the thin film transistor fabricated by the method may be a bottom gate thin film transistor or a top gate thin film transistor, which is not limited herein.
  • the structure of the bottom gate type thin film transistor specifically includes: a gate electrode 01, an active layer 02, a source electrode 03, and a drain electrode 04 sequentially disposed on the substrate substrate; wherein, the gate electrode 01 A gate insulating layer 05 is generally disposed between the active layer 02 and the active layer 02.
  • an insulating layer may be disposed between the active layer 02 and the film layer where the source 03 and the drain 04 are located, and the source 03 And the drain electrode 04 is electrically connected to the active layer 02 through via holes in the insulating layer respectively; or, the active layer 02 is selectively in contact with the film layer where the source 03 and the drain 04 are located.
  • the relative positional relationship between the active layer 02 and the film layer where the source 03 and the drain 04 are located may be interchanged, that is, the pattern of the active layer 02 may be formed first, and then the patterns of the source 03 and the drain 04 may be formed; First, the patterns of the source 03 and the drain 04 are formed, and then the pattern of the active layer 02 is formed, which is not limited herein.
  • the structure of the top gate type thin film transistor specifically includes: an active layer 02, a gate 01, a source 03, and a drain 04 which are sequentially disposed on a substrate; wherein the active layer A gate insulating layer 05 is generally disposed between 02 and the gate electrode 01.
  • an insulating layer may be disposed between the active layer 02 and the film layer where the source 03 and the drain 04 are located, the source 03 and The drain electrode 04 is electrically connected to the active layer 02 through via holes in the insulating layer, respectively; or, the active layer 02 is selectively in contact with the film layer where the source 03 and the drain 04 are located.
  • the relative positional relationship between the gate electrode 01 and the film layer where the source electrode 03 and the drain electrode 04 are located may be interchanged, that is, the pattern of the gate electrode 01 may be formed first, and then the pattern of the source electrode 03 and the drain electrode 04 may be formed; The pattern of the source 03 and the drain 04 is then patterned by the gate 01, which is not limited herein.
  • the method for fabricating the above-mentioned thin film transistor according to an embodiment of the present invention after forming a pattern of an active layer, a source and a drain in the thin film transistor, the lining
  • the base substrate is annealed to thermally diffuse ions of the source and the drain at the ohmic contact of the active layer and the source and the drain to the active layer, thereby causing the source and the drain in the active layer.
  • the ions which change the composition of the active layer, reduce the resistance at the ohmic contact between the active layer and the source and drain, which provides a guarantee for the uniformity and reliability of the thin film transistor.
  • the method for manufacturing the above thin film transistor provided by one embodiment of the present invention
  • the substrate substrate in order to avoid the oxidation reaction of the source 03 and the drain 04 in the annealing process, when the substrate substrate is annealed, the substrate substrate is generally heated for a predetermined period of time in a protective gas or vacuum atmosphere, after which Cool naturally to room temperature.
  • the protective gas means nitrogen gas or an inert gas such as helium gas, which is not limited herein; room temperature generally means about 20 degrees.
  • the diffusion to the active layer 02 is generally set to a predetermined period of time from 20 minutes to 60 minutes for the annealing treatment of the substrate.
  • the source 03 and the drain 04 can be made of a metal material such as copper, titanium or molybdenum; indium gallium zinc oxide, indium tin zinc oxide or
  • the active layer 02 is formed of a semiconductor oxide material such as amorphous silicon, which is not limited herein.
  • the heating temperature of the annealing treatment of the base substrate is generally set to be between 300 and 350 degrees; the source 03 and the drain are made of titanium or molybdenum. In the case of the pole 04, it is preferable to set the heating temperature of the annealing treatment performed on the base substrate to 300 degrees or less.
  • the method for fabricating the above-mentioned thin film transistor provided by an embodiment of the present invention, different materials are used for the source 03 and the drain 04, and different heating temperatures are used for annealing the substrate.
  • the ions of the source 03 and the drain 04 at the ohmic contact of the active layer 02 and the source 03 and the drain 04 can be thermally diffused to the active layer 02, thereby causing the active layer 02 to have the source 03 and
  • the ions of the drain 04 thus change the composition of the active layer 02, reducing the resistance at the ohmic contact of the active layer 02 with the source 03 and the drain 04, which provides a guarantee for the uniformity and reliability of the thin film transistor.
  • another embodiment of the present invention provides a thin film transistor fabricated using the method of fabricating the thin film transistor of the present invention as described above.
  • another embodiment of the present invention provides a method for fabricating an array substrate, comprising: forming a pattern of a thin film transistor on a substrate, and sequentially forming a pattern of a passivation layer and a pixel electrode on the pattern of the thin film transistor;
  • the pattern forming the passivation layer as shown in FIG. 5, specifically includes the following steps:
  • FIG. 6d An array substrate fabricated by the above method for fabricating an array substrate provided by an embodiment of the present invention is shown in FIG. 6d.
  • another embodiment of the present invention provides an array substrate fabricated using the above-described method of fabricating the array substrate of the present invention.
  • Various embodiments of the present invention provide a method for fabricating a thin film transistor and an array substrate, and a corresponding device.
  • the substrate is The substrate is annealed to thermally diffuse ions of the source and the drain at the ohmic contact of the active layer and the source and the drain to the active layer, thereby causing ions having source and drain in the active layer
  • the annealing process is relatively simple to implement with respect to the plasma processing, and does not increase the complexity of the fabrication process of the entire thin film transistor, which is beneficial to ensure Thin film transistor production efficiency.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种薄膜晶体管和阵列基板的制作方法及相应装置，在薄膜晶体管的制作工艺中，在形成薄膜晶体管中有源层(02)、源极(03)和漏极(04)的图形之后，对衬底基板进行退火处理，以使在有源层(02)与源极(03)和漏极(04)的欧姆接触处的源极(03)和漏极(04)的离子热扩散至有源层(02)，进而使有源层(02)中具有源极(03)和漏极(04)的离子从而改变了有源层(02)的组分，降低了有源层(02)与源极(03)和漏极(04)的欧姆接触处的电阻，为薄膜晶体管的均匀性与可靠性提供了保障。并且，退火处理相对于等离子体处理实施相对简单，不会增加整个薄膜晶体管的制作工艺的复杂度，有利于保证薄膜晶体管的生产效率。

Description

一种薄膜晶体管和阵列基板的制作方法及相应装置
交叉申请
本发明要求于2014年11月13日在中国提交的申请号为CN.201410641116.3的中国申请的优先权，其内容包含在此作为参考。
技术领域
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管和阵列基板的制作方法及相应装置。
背景技术
目前，液晶显示面板(LCD，Liquid Crystal Display)、电致发光(EL，electroluminescence)显示面板以及电子纸等显示装置已为人所熟知。在这些显示装置中具有控制各像素开关的薄膜晶体管(TFT，Thin Film Transistor)，如图1所示，其结构主要包括：栅极1、有源层2、源极3和漏极4；其中，在栅极1与有源层2之间设置有栅绝缘层5，源极3和漏极4同层设置，源极3和漏极4分别与有源层2电性相连。
在TFT的结构中，如图1所示，有源层与源极和漏极的欧姆接触a处的电阻对TFT的可靠性和均匀性有很大的影响，因此，在TFT的制作过程中，本领域技术人员采用多种方法试图减小有源层与源极和漏极的欧姆接触a处的电阻。其中一种方法是，通过等离子体处理来减小有源层内氧原子的成分，从而使有源层达到具有非晶硅的n+层的效果，以减小有源层与源极和漏极的欧姆接触a处的电阻，然而，等离子体处理工艺实施复杂，增加了TFT制作工艺的复杂度，且会影响有源层的均匀性和稳定性，不利于保证TFT的生产效率。
因此，如何在保证不增加TFT的制作工艺复杂度的基础上，减小有源层与源极和漏极的欧姆接触处的电阻，是本领域技术人员亟待解决的问题。
发明内容
本发明的各个实施例提供了一种薄膜晶体管和阵列基板的制作方法及相应装置，用以减小薄膜晶体管中的有源层与源极和漏极的欧姆 接触处的电阻。
本发明一个实施例提供了一种薄膜晶体管的制作方法，包括：在衬底基板上形成包括栅极、有源层、源极和漏极的图形；其中，所述源极和漏极分别与所述有源层电性相连，还包括：
在形成所述有源层、源极和漏极的图形之后，对所述衬底基板进行退火处理，以使在所述有源层与源极和漏极的欧姆接触处的所述源极和漏极的离子热扩散至所述有源层。
本发明一个实施例提供的上述薄膜晶体管的制作方法，在薄膜晶体管制作工艺中，在形成薄膜晶体管中有源层、源极和漏极的图形之后，对衬底基板进行退火处理，以使在有源层与源极和漏极的欧姆接触处的源极和漏极的离子热扩散至有源层，进而使有源层中具有源极和漏极的离子，从而改变了有源层的组分，降低了有源层与源极和漏极的欧姆接触处的电阻，为薄膜晶体管的均匀性与可靠性提供了保障。并且，退火处理相对于等离子体处理实施相对简单，不会增加整个薄膜晶体管的制作工艺的复杂度，有利于保证薄膜晶体管的生产效率。
在一种可能的实施方式中，本发明一个实施例提供的上述薄膜晶体管的制作方法中，对所述衬底基板进行退火处理，具体包括：在保护气体或真空的氛围中，对所述衬底基板加热预设时长，之后自然冷却至室温。
在一种可能的实施方式中，本发明一个实施例提供的上述薄膜晶体管的制作方法中，所述退火处理的预设时长为20分钟到60分钟。
在一种可能的实施方式中，本发明一个实施例提供的上述薄膜晶体管的制作方法中，所述源极和所述漏极的材料为铜、钛或钼；所述有源层的材料为半导体氧化物材料。
在一种可能的实施方式中，本发明一个实施例提供的上述薄膜晶体管的制作方法中，所述源极和所述漏极的材料为铜时，对所述衬底基板的加热温度为300度至350度；
所述源极和所述漏极的材料为钛或钼时，对所述衬底基板的加热温度为300度以下。
在一种可能的实施方式中，本发明一个实施例提供的上述薄膜晶体管的制作方法中，在形成所述有源层的图形之后，形成所述源极和漏极的图形；或，
在形成所述源极和漏极的图形之后，形成所述有源层的图形。
在一种可能的实施方式中，本发明一个实施例提供的上述薄膜晶体管的制作方法中，在形成所述有源层的图形之后，且形成所述源极和漏极的图形之前，还包括：
在形成有所述有源层的图形的衬底基板上形成绝缘层的图形，所述源极和漏极分别通过所述绝缘层中的过孔与所述有源层电性连接。
本发明一个实施例提供了一种薄膜晶体管，该薄膜晶体管是使用本发明上述的薄膜晶体管的制作方法制作的。
本发明一个实施例提供了一种阵列基板的制作方法，包括：在衬底基板上形成薄膜晶体管的图形，在所述薄膜晶体管的图形上依次形成钝化层和像素电极的图形，所述形成钝化层的图形，具体包括：
在所述薄膜晶体管的图形上形成钝化层薄膜；
对形成有所述钝化层薄膜的衬底基板进行退火处理，以使在所述薄膜晶体管的有源层与源极和漏极的欧姆接触处的所述源极和漏极的离子热扩散至所述有源层；
对经过退火处理后的所述钝化层薄膜进行构图，形成钝化层的图形。
本发明一个实施例提供的上述阵列基板的制作方法中，在形成钝化层薄膜之后，对衬底基板进行退火处理，以使在有源层与源极和漏极的欧姆接触处的源极和漏极的离子热扩散至有源层，进而使有源层中具有源极和漏极的离子从而改变了有源层的组分，降低了有源层与源极和漏极的欧姆接触处的电阻，为薄膜晶体管的均匀性与可靠性提供了保障。并且，在形成钝化层薄膜之后进行退火处理过程中，钝化层薄膜将源极和漏极与氧气隔绝，可以避免源极和漏极在退火处理过程中发生氧化反应。
本发明一个实施例提供了一种阵列基板，该阵列基板是使用本发明上述的阵列基板的制作方法制作的。
附图说明
图1为现有的薄膜晶体管的结构示意图；
图2a为根据本发明一个实施例而提供的底栅型薄膜晶体管的结构示意图；
图2b为根据本发明另一个实施例而提供的顶栅型薄膜晶体管的结构示意图；
图3为根据本发明又一个实施例提供的薄膜晶体管的制作方法的流程图；
图4a至图4d分别为根据本发明再一实施例而提供的薄膜晶体管的制作方法在执行各步骤后的结构示意图；
图5为根据本发明一个实施例而提供的阵列基板中钝化层的制作方法的流程图；
图6a至图6d分别为根据本发明另一实施例而提供的阵列基板制作方法在执行各步骤后的结构示意图。
具体实施方式
下面结合附图，对本发明实施例提供的薄膜晶体管、阵列基板及其制作方法的具体实施方式进行详细地说明。
附图中各膜层的厚度和区域的大小形状不反映薄膜晶体管和阵列基板各部件的真实比例，目的只是示意说明本发明内容。
本发明的一个实施例提供了一种薄膜晶体管的制作方法，包括：在衬底基板上形成包括栅极、有源层、源极和漏极的图形；其中，源极和漏极分别与有源层电性相连，还包括：
在形成有源层、源极和漏极的图形之后，对衬底基板进行退火处理，以使在有源层与源极和漏极的欧姆接触处的源极和漏极的离子热扩散至有源层。
根据本发明一个实施例提供的上述薄膜晶体管的制作方法，在薄膜晶体管制作工艺中，在形成薄膜晶体管中有源层、源极和漏极的图形之后，对衬底基板进行退火处理，以使在有源层与源极和漏极的欧姆接触处的源极和漏极的离子热扩散至有源层，进而使有源层中具有源极和漏极的离子从而改变了有源层的组分，降低了有源层与源极和漏极的欧姆接触处的电阻，为薄膜晶体管的均匀性与可靠性提供了保障。并且，退火处理相对于等离子体处理实施相对简单，不会增加整个薄膜晶体管的制作工艺的复杂度，有利于保证薄膜晶体管的生产效率。
具体地，采用本发明一个实施例提供的上述薄膜晶体管的制作方 法制作的薄膜晶体管可以为底栅型薄膜晶体管，也可以为顶栅型薄膜晶体管，在此不做限定。
其中，底栅型的薄膜晶体管的结构，如图2a所示，具体包括：依次设置在衬底基板上的栅极01、有源层02、源极03和漏极04；其中，栅极01与有源层02之间一般设置有栅绝缘层05。在具体实施时，可以根据制作有源层02以及源极03和漏极04的材料，选择在有源层02与源极03和漏极04所在膜层之间设置有绝缘层，源极03和漏极04分别通过绝缘层中的过孔与有源层02电性相连；或者，选择将有源层02与源极03和漏极04所在膜层直接接触。并且，有源层02与源极03和漏极04所在膜层的相对位置关系可以互换，即可以先制作有源层02的图形，然后制作源极03和漏极04的图形；也可以先制作源极03和漏极04的图形，然后制作有源层02的图形，在此不做限定。
具体地，顶栅型薄膜晶体管的结构，如图2b所示，具体包括：依次设置在衬底基板上的有源层02、栅极01、源极03和漏极04；其中，有源层02与栅极01之间一般设置有栅绝缘层05。在具体实施时，可以根据制作有源层02以及源极03和漏极04的材料，选择有源层02与源极03和漏极04所在膜层之间设置有绝缘层，源极03和漏极04分别通过绝缘层中的过孔与有源层02电性相连；或者，选择将有源层02与源极03和漏极04所在膜层直接接触。并且，栅极01与源极03和漏极04所在膜层的相对位置关系可以互换，即可以先制作栅极01的图形，然后制作源极03和漏极04的图形；也可以先制作源极03和漏极04的图形，然后制作栅极01的图形，在此不做限定。
采用本发明一个实施例提供的上述薄膜晶体管的制作方法不论是制作顶栅型薄膜晶体管还是制作底栅型薄膜晶体管，在形成薄膜晶体管中有源层、源极和漏极的图形之后，对衬底基板进行退火处理，可以使在有源层与源极和漏极的欧姆接触处的源极和漏极的离子热扩散至有源层，进而使有源层中具有源极和漏极的离子，从而改变了有源层的组分，降低了有源层与源极和漏极的欧姆接触处的电阻，为薄膜晶体管的均匀性与可靠性提供了保障。
下面以底栅型薄膜晶体管的结构为例，对本发明一个实施例提供的上述薄膜晶体管的制作方法进行具体说明。
在具体实施时，在本发明一个实施例提供的上述薄膜晶体管的制 作方法中，为了避免源极03和漏极04在退火处理中发生氧化反应，在对衬底基板进行退火处理时，一般在保护气体或真空的氛围中对衬底基板加热预设时长，之后自然冷却到室温。其中，保护气体是指氮气，或诸如氦气的惰性气体，在此不作限定；室温一般是指20度左右。
进一步地，在本发明一个实施例提供的上述薄膜晶体管的制作方法中，为了使在有源层02与源极03和漏极04的欧姆接触处的源极03和漏极04的离子充分热扩散至有源层02，一般将衬底基板的退火处理预设时长设定在20分钟到60分钟为佳。
在具体实施时，本发明实施例上述薄膜晶体管的制作方法中，可以采用铜、钛或钼等金属材料制作源极03和漏极04；可以采用铟镓锌氧化物、铟锡锌氧化物或非晶硅等半导体氧化物材料制作有源层02，在此不作限定。
具体地，当采用铜制作源极03和漏极04时，一般将衬底基板的退火处理的加热温度设定在300度至350度之间为佳；采用钛或钼制作源极03和漏极04时，一般将衬底基板进行的退火处理的加热温度设定在300度以下为佳。
这样，在具体实施时，在本发明一个实施例提供的上述薄膜晶体管的制作方法中，针对源极03和漏极04采用不同的材料，对衬底基板进行退火处理时，采用不同的加热温度，可以使在有源层02与源极03和漏极04的欧姆接触处的源极03和漏极04的离子热扩散至有源层02，进而使有源层02中具有源极03和漏极04的离子从而改变了有源层02的组分，降低了有源层02与源极03和漏极04的欧姆接触处的电阻，为薄膜晶体管的均匀性与可靠性提供了保障。
下面以图2a所示的结构为例具体说明本发明实施例提供的上述方法，如图3所示，具体步骤如下：
S101、在衬底基板上沉积金属层薄膜，对金属层薄膜进行构图，形成栅极01的图形，如图4a所示；
S102、在形成有栅极01的图形的衬底基板上，先制备一层栅绝缘层薄膜，再制备有源层薄膜，并对有源层薄膜进行构图，形成有源层02的图形，如图4b所示；
S103、在形成有有源层02的图形的衬底基板上，沉积金属层薄膜，并对金属层薄膜进行构图，形成源极03和漏极04的图形，如图4c所 示；
S104、对形成有栅极01、有源层02、源极03和漏极04的图形的衬底基板进行退火处理，以使在有源层02与源极03和漏极04的欧姆接触处的源极03和漏极04的离子热扩散至有源层02，如图4d所示。
基于同一发明构思，本发明另一实施例提供了一种薄膜晶体管，该薄膜晶体管使用本发明如上所述的薄膜晶体管的制作方法制作。
基于同一发明构思，本发明又一实施例提供了一种阵列基板的制作方法，包括：在衬底基板上形成薄膜晶体管的图形，在薄膜晶体管的图形上依次形成钝化层和像素电极的图形；其中，形成钝化层的图形，如图5所示，具体包括以下步骤：
S201、在薄膜晶体管的图形上形成钝化层薄膜08，如图6a所示；
S202、对形成有钝化层薄膜08的衬底基板进行退火处理，以使在薄膜晶体管的有源层02与源极03和漏极04的欧姆接触处的源极03和漏极04的离子热扩散至有源层02，如图6b所示；在形成钝化层薄膜08之后进行退火处理过程中，钝化层薄膜08将源极03和漏极04与氧气隔绝，避免了源极03和漏极04在退火处理过程中发生氧化反应；
S203、对经过退火处理后的钝化层薄膜08进行构图，形成钝化层的图形，如图6c所示；其中，钝化层中具有用于连接漏极04和之后形成的像素电极09的过孔10。
通过本发明一个实施例提供的上述阵列基板的制作方法制成的阵列基板如图6d所示。
基于同一发明构思，本发明另一实施例提供了一种阵列基板，该阵列基板使用本发明上述的阵列基板的制作方法制作。
本发明的各个实施例提供了一种薄膜晶体管和阵列基板的制作方法及相应装置，在薄膜晶体管制作工艺中，在形成薄膜晶体管中有源层、源极和漏极的图形之后，对衬底基板进行退火处理，以使在有源层与源极和漏极的欧姆接触处的源极和漏极的离子热扩散至有源层，进而使有源层中具有源极和漏极的离子从而改变了有源层的组分，降低了有源层与源极和漏极的欧姆接触处的电阻，为薄膜晶体管的均匀性与可靠性提供了保障。并且，退火处理相对于等离子体处理实施相对简单，不会增加整个薄膜晶体管的制作工艺的复杂度，有利于保证 薄膜晶体管的生产效率。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

  1. 一种薄膜晶体管的制作方法，包括：在衬底基板上形成包括栅极、有源层、源极和漏极的图形；其中，所述源极和漏极分别与所述有源层电性相连，其特征在于，还包括：
    在形成所述有源层、源极和漏极的图形之后，对所述衬底基板进行退火处理，以使在所述有源层与所述源极和漏极的欧姆接触处的所述源极和漏极的离子热扩散至所述有源层。
  2. 如权利要求1所述的方法，其特征在于，对所述衬底基板进行退火处理，具体包括：
    在保护气体或真空的氛围中，对所述衬底基板加热预设时长，之后自然冷却至室温。
  3. 如权利要求2所述的方法，其特征在于，所述预设时长为20分钟到60分钟。
  4. 如权利要求2所述的方法，其特征在于，所述源极和所述漏极的材料为铜、钛或钼；所述有源层的材料为半导体氧化物材料。
  5. 如权利要求4所述的方法，其特征在于，所述源极和所述漏极的材料为铜时，对所述衬底基板的加热温度为300度至350度；
    所述源极和所述漏极的材料为钛或钼时，对所述衬底基板的加热温度为300度以下。
  6. 如权利要求1-5任一项所述的方法，其特征在于，在形成所述有源层的图形之后，形成所述源极和漏极的图形；或，
    在形成所述源极和漏极的图形之后，形成所述有源层的图形。
  7. 如权利要求6所述的方法，其特征在于，在形成所述有源层的图形之后，且形成所述源极和漏极的图形之前，还包括：
    在形成有所述有源层的图形的衬底基板上形成绝缘层的图形，所述源极和漏极分别通过所述绝缘层中的过孔与所述有源层电性连接。
  8. 一种薄膜晶体管，其特征在于，所述薄膜晶体管使用如权利要求1-7任一项所述的制作方法制作。
  9. 一种阵列基板的制作方法，包括：在衬底基板上形成薄膜晶体管的图形，在所述薄膜晶体管的图形上依次形成钝化层和像素电极的图形，其特征在于，所述形成钝化层的图形具体包括：
    在所述薄膜晶体管的图形上形成钝化层薄膜；
    对形成有所述钝化层薄膜的衬底基板进行退火处理，以使在所述薄膜晶体管的有源层与源极和漏极的欧姆接触处的所述源极和漏极的离子热扩散至所述有源层；
    对经过退火处理后的所述钝化层薄膜进行构图，形成钝化层的图形。
  10. 一种阵列基板，其特征在于，所述阵列基板使用如权利要求9所述的制作方法制作。
PCT/CN2015/071977 2014-11-13 2015-01-30 一种薄膜晶体管和阵列基板的制作方法及相应装置 WO2016074349A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/785,397 US9923085B2 (en) 2014-11-13 2015-01-30 Method for manufacturing a thin film transistor and an array substrate, and corresponding devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410641116.3 2014-11-13
CN201410641116.3A CN104409362A (zh) 2014-11-13 2014-11-13 一种薄膜晶体管和阵列基板的制作方法及相应装置

Publications (1)

Publication Number Publication Date
WO2016074349A1 true WO2016074349A1 (zh) 2016-05-19

Family

ID=52646978

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/071977 WO2016074349A1 (zh) 2014-11-13 2015-01-30 一种薄膜晶体管和阵列基板的制作方法及相应装置

Country Status (3)

Country Link
US (1) US9923085B2 (zh)
CN (1) CN104409362A (zh)
WO (1) WO2016074349A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110299103A (zh) * 2019-06-28 2019-10-01 上海天马有机发光显示技术有限公司 一种显示面板及显示装置
CN112530978B (zh) * 2020-12-01 2024-02-13 京东方科技集团股份有限公司 开关器件结构及其制备方法、薄膜晶体管膜层、显示面板
CN114023697A (zh) * 2021-10-26 2022-02-08 Tcl华星光电技术有限公司 基板及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102683423A (zh) * 2012-05-08 2012-09-19 东莞彩显有机发光科技有限公司 一种顶栅结构金属氧化物薄膜晶体管及其制作方法
CN103000530A (zh) * 2012-11-13 2013-03-27 深圳丹邦投资集团有限公司 顶栅氧化物薄膜晶体管的制造方法
CN103050412A (zh) * 2012-12-20 2013-04-17 深圳丹邦投资集团有限公司 氧化物薄膜晶体管的制造方法
CN103730346A (zh) * 2013-12-24 2014-04-16 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0945925A (ja) * 1995-07-31 1997-02-14 Sanyo Electric Co Ltd トランジスタの製造方法，薄膜トランジスタの製造方法，表示装置
KR100858088B1 (ko) * 2007-02-28 2008-09-10 삼성전자주식회사 박막 트랜지스터 및 그 제조 방법
TWI626744B (zh) * 2008-07-31 2018-06-11 半導體能源研究所股份有限公司 半導體裝置及半導體裝置的製造方法
CN103283029B (zh) * 2010-12-27 2016-03-30 夏普株式会社 半导体装置及其制造方法
US9240491B2 (en) * 2011-07-07 2016-01-19 Sharp Kabushiki Kaisha Semiconductor device and method for manufacturing same
CN102651401B (zh) * 2011-12-31 2015-03-18 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及其制造方法和显示器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102683423A (zh) * 2012-05-08 2012-09-19 东莞彩显有机发光科技有限公司 一种顶栅结构金属氧化物薄膜晶体管及其制作方法
CN103000530A (zh) * 2012-11-13 2013-03-27 深圳丹邦投资集团有限公司 顶栅氧化物薄膜晶体管的制造方法
CN103050412A (zh) * 2012-12-20 2013-04-17 深圳丹邦投资集团有限公司 氧化物薄膜晶体管的制造方法
CN103730346A (zh) * 2013-12-24 2014-04-16 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置

Also Published As

Publication number Publication date
US20160343835A1 (en) 2016-11-24
CN104409362A (zh) 2015-03-11
US9923085B2 (en) 2018-03-20

Similar Documents

Publication Publication Date Title
US9761447B2 (en) Method for manufacturing TFT substrate and TFT substrate manufactured thereof
US20160133755A1 (en) Low temperature poly-silicon thin film transistor and manufacturing method thereof, array substrate and display device
US20190103420A1 (en) Array substrate, display device, and manufacturing method thereof
EP2735629B1 (en) Method of manufacturing low temperature polysilicon film, thin film transistor and manufacturing method thereof
CN107425044B (zh) 一种柔性显示面板、其制作方法及显示装置
WO2015180450A1 (zh) 低温多晶硅薄膜晶体管及其制备方法和显示器件
JP2014106539A (ja) アレイ基板及びアレイ基板の製造方法、並びにディスプレイデバイス
CN106783628B (zh) 薄膜晶体管的制作方法、薄膜晶体管及显示器
US20180190490A1 (en) Thin film transistor and method for fabricating the same
CN103839825A (zh) 一种低温多晶硅薄膜晶体管、阵列基板及其制作方法
CN107482066A (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
JP2010114412A (ja) 薄膜トランジスタ、その製造方法及びそれを含む有機電界発光表示装置
CN105097666B (zh) 低温多晶硅tft基板的制作方法及低温多晶硅tft基板
WO2016206239A1 (zh) 低温多晶硅薄膜晶体管及其制备方法
JP2010145984A (ja) 有機電界発光表示装置及びその製造方法
JP2006024887A (ja) 半導体装置及びその製造方法
WO2016074349A1 (zh) 一种薄膜晶体管和阵列基板的制作方法及相应装置
WO2020192703A1 (zh) 显示基板及其制备方法、显示装置
WO2015192558A1 (zh) 低温多晶硅薄膜晶体管、其制备方法及阵列基板与显示装置
US9040988B2 (en) Thin film transistor and manufacturing method thereof, and array substrate
CN104617151B (zh) 低温多晶硅薄膜晶体管及制作方法、阵列基板及显示装置
US9837542B2 (en) Polycrystalline silicon thin-film transistor
WO2016138715A1 (zh) 低温多晶硅薄膜及薄膜晶体管的制备方法、薄膜晶体管、显示面板及显示装置
US20150004776A1 (en) Polysilicon layer preparing method
CN108231794B (zh) 阵列基板的制备方法、阵列基板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14785397

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15859955

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 31/10/2017)

122 Ep: pct application non-entry in european phase

Ref document number: 15859955

Country of ref document: EP

Kind code of ref document: A1