WO2016065785A1 - 一种移位寄存单元、显示面板和显示装置 - Google Patents

一种移位寄存单元、显示面板和显示装置 Download PDF

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Publication number
WO2016065785A1
WO2016065785A1 PCT/CN2015/073765 CN2015073765W WO2016065785A1 WO 2016065785 A1 WO2016065785 A1 WO 2016065785A1 CN 2015073765 W CN2015073765 W CN 2015073765W WO 2016065785 A1 WO2016065785 A1 WO 2016065785A1
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Prior art keywords
signal
shift register
register unit
gate
output
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PCT/CN2015/073765
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English (en)
French (fr)
Inventor
青海刚
祁小敬
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to EP15750617.1A priority Critical patent/EP3214614B1/en
Priority to KR1020157023587A priority patent/KR101718831B1/ko
Priority to JP2017542237A priority patent/JP6414920B2/ja
Priority to US14/771,129 priority patent/US9542878B2/en
Publication of WO2016065785A1 publication Critical patent/WO2016065785A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/023—Power management, e.g. power saving using energy recovery or conservation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a display panel, and a display device.
  • the conventional low temperature poly-silicon (LTPS) shift register unit uses a D flip-flop composed of an inverter and a transfer gate.
  • a conventional LTPS shift register unit typically has two D flip-flops.
  • the LTPS shift register unit can utilize a D flip-flop to latch the output signal and utilize the clock signal to control the transmission and shift of the signal.
  • Figure 1 shows a typical structure of a conventional LTPS shift register unit.
  • the transfer gate TG1, the NAND gate Nand1, the inverter INV1, and the transfer gate TG2 constitute the first D flip-flop, and the transfer gate TG3 and the NAND gate Nand2 are inverted.
  • the INV2 and the transfer gate TG4 constitute a second D flip-flop. After the clock signal CLK is at a low level and the inverted clock signal CLKB is at a high level to turn on the first D flip-flop, the signal output from the previous stage shift register unit enters the first D flip-flop.
  • the transmission gate TD3 at the front end of the second D flip-flop since the transmission gate TD3 at the front end of the second D flip-flop is turned off, the signal output from the NAND gate Nand1 cannot enter the second D flip-flop.
  • the first D flip-flop will be in the previous clock.
  • the state of the trigger is latched. That is, when the clock signal CLK is high and the inverted clock signal CLKB is low, the first D flip-flop will be the first D flip-flop at the clock signal CLK low and the inverted clock signal CLKB The signal output is latched at a high level.
  • the transfer gate TG3 in the second D flip-flop is turned on, and the signal outputted by the first D flip-flop enters the second D flip-flop and outputs the signal, thereby realizing the signal from the shift register unit of the previous stage to Lower shift register unit Shift operation.
  • the reset signal RST is at a high level.
  • each shift register unit is used only once during the display of one frame of image.
  • a display device has a total of N lines of pixels.
  • the display time of one frame of image is T seconds, and then one shift register unit is only used for T/N seconds in a frame display time. That is to say, in the time when one frame of image is displayed, the working phase of one shift register unit is only T/N seconds, and the non-working phase has T-T/N seconds. That is to say, in the time when one frame of image is displayed, the time when one shift register unit is in the working state is only T/N seconds, and the time in the non-operating state is T-T/N seconds.
  • the turn-on and turn-off of all the transfer gates in the conventional shift register unit are controlled by the clock signal CLK and the inverted clock signal CLKB. Even in the non-working phase, the clock signal CLK and the inverted clock signal CLKB will turn the transmission gate on and off.
  • the transfer gate is formed by parallelizing complementary transistors. When the clock signal CLK and the inverted clock signal CLKB control the transfer gate to be turned on and off, the clock signal CLK and the inverted clock signal CLKB need to be loaded on the gate of the transistor.
  • Below the gate of the transistor is a gate insulating layer, and under the gate insulating layer is a substrate, so a capacitance is formed between the gate and the substrate, and the formed capacitance is called a gate capacitance.
  • the signal loaded on the gate of the transistor will charge the gate capacitance of the transistor when it is high level, and the gate capacitance will be discharged when it is low level, and in the non-working phase, this charge and discharge will cause unnecessary circuit power consumption.
  • display devices generally have hundreds or even thousands of shift register units, and only one shift register unit circuit is working at the same time, and other shift register units are in a non-working phase.
  • both the clock signal CLK and the inverted clock signal CLKB are loaded onto the transfer gates in the shift register units in the non-working phase, thus causing a large unnecessary power consumption.
  • the complementary clocked two clock signals control the transfer gate in the conventional shift register unit to switch between on and off during the non-working phase, that is, the transistor in the transfer gate in the non-working phase
  • the gate capacitance is charged and discharged, which causes a large amount of unnecessary power consumption.
  • Embodiments of the present disclosure provide a shift register unit, a display panel, and a display device for solving the problem that an existing shift register unit controls shift by using two clock signals of complementary inversion.
  • the transfer gate in the bit register unit switches between on and off, which causes the non-working phase of the shift register unit to charge and discharge the gate capacitance of the transistor in the transfer gate, resulting in a large unnecessary power consumption. The problem.
  • a shift register unit provided by an embodiment of the present disclosure includes a latch circuit and a transmission circuit
  • the latch circuit outputs a clock signal received by the first clock signal end of the shift register unit and a low level signal after the selection signal is at a high level, wherein the selection signal is at a high level.
  • the clock signal received by the first clock signal terminal is at a low level; after the first low level period of the selection signal, the signal output by the latch circuit when the selection signal is at a high level is not calculated.
  • the obtained signal is outputted with the feedback signal after the NAND operation; and the low-level signal is outputted in a period other than the first low-level period of the selection signal in the period in which the selection signal is low;
  • the transmission circuit outputs a signal related to a clock signal received by the first clock signal terminal when a signal output by the latch circuit is a high level; and when a signal output by the latch circuit is a low level, Output level signal;
  • the feedback signal is capable of causing the latch circuit to output a signal during a period in which the selection signal is at a high level and a signal output in a first low period of the selection signal; At the end of the first low level period of the signal, the feedback signal changes from a low level to a high level; the first low level period of the selection signal is that the selection signal changes from a high level The time of the low level, the time period between the time when the level of the signal output from the shift register unit of the next stage of the shift register unit is changed from the low level to the high level.
  • a display panel includes a plurality of shift register units provided by the embodiments of the present disclosure.
  • a display device includes a display panel provided by an embodiment of the present disclosure.
  • the shift register unit, the display panel, and the display device provided by the embodiments of the present disclosure are moved
  • the latch circuit in the bit register unit can output a high level signal after the clock signal received by the first clock signal terminal and the low level signal pass the NAND signal when the selection signal is at a high level, and is in the selection signal
  • a low-level period maintains the state of the latch circuit when the select signal is high. That is, the latch circuit can latch the state when the selection signal is at a high level, and change the state of the latch circuit by the feedback signal, and the signal output from the latch circuit controls the signal output from the transmission circuit, thereby Implement the function of shift register.
  • the shift register unit provided according to the embodiment of the present disclosure controls the shift register unit to implement the shift register function by the selection signal, so that the two clock signals with complementary inversion can be avoided to control the shift register unit.
  • the transfer gate in the middle implements the shift function, thereby reducing the unnecessary power consumption of the shift register unit during the non-working period.
  • 1 is a schematic structural view of a conventional shift register unit
  • FIG. 2 is a structural block diagram of a shift register unit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a latch circuit in a shift register unit according to an embodiment of the present disclosure
  • FIG. 4 is a second schematic structural diagram of a latch circuit in a shift register unit according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a transmission circuit in a shift register unit according to an embodiment of the present disclosure
  • FIG. 6 is a second schematic structural diagram of a transmission circuit in a shift register unit according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a buffer circuit in a shift register unit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a scan direction selection circuit in a shift register unit according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 10 is a second schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • Figure 11 is a timing chart showing the operation of the shift register unit shown in Figure 9 or Figure 10 during forward scanning;
  • Figure 12 is a timing chart showing the operation of the shift register unit shown in Figure 9 or Figure 10 in reverse scan;
  • FIG. 13 is a third schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 14 is a fourth schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • Figure 15 is a timing chart showing the operation of the shift register unit shown in Figure 13 or Figure 14 in the forward scan;
  • Figure 16 is a timing chart showing the operation of the shift register unit shown in Figure 13 or Figure 14 in reverse scan;
  • FIG. 17 is a fifth schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 18 is a sixth structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • Figure 19 is a timing chart showing the operation of the shift register unit shown in Figure 17 or Figure 18 in the forward scan;
  • Figure 20 is a timing chart showing the operation of the shift register unit shown in Figure 17 or Figure 18 when it is reverse-scanned;
  • FIG. 21 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 22 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 23 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 24 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 25 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 26 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 27 is a schematic diagram showing a connection relationship when the shift register units shown in any one of FIG. 9, FIG. 10, FIG. 13, and FIG. 14 are cascaded;
  • FIG. 28 is a second schematic diagram showing a connection relationship when the shift register units shown in any one of FIG. 9, FIG. 10, FIG. 13, and FIG. 14 are cascaded;
  • FIG. 29 is a schematic diagram showing a connection relationship when the shift register units shown in FIG. 17 or FIG. 18 are cascaded;
  • FIG. 30 is a second schematic diagram of the connection relationship when the shift register units shown in FIG. 17 or FIG. 18 are cascaded;
  • FIG. 31 is a schematic diagram showing a connection relationship when the shift register units shown in any one of FIG. 21, FIG. 22, FIG. 23, and FIG. 24 are cascaded;
  • Fig. 32 is a view showing the connection relationship when the shift register units shown in Fig. 25 or Fig. 26 are cascaded.
  • the latch circuit in the shift register unit is capable of latching the circuit state when the latch selection signal is at a high level, and changing the lock by the feedback signal
  • the state of the memory circuit and the signal outputted by the latch circuit control the signal output from the transmission circuit, thereby realizing the function of shift register. This can avoid the transfer gates in the shift register unit being controlled by the complementary two inverted clock signals to implement the shift function, thereby reducing the unnecessary power consumption of the shift register unit during the non-working period.
  • a shift register unit provided by an embodiment of the present disclosure includes a latch circuit 21 and a transfer circuit 22.
  • the latch circuit 21 outputs a clock signal received by the first clock signal terminal of the shift register unit and a low-level signal after the selection signal is at a high level.
  • the selection signal is high
  • the clock signal received by the first clock signal terminal is at a low level.
  • the signal obtained by the latch circuit 21 after the non-operation of the signal outputted when the selection signal is at the high level is outputted by performing a NAND operation with the feedback signal.
  • a low level signal is outputted during a period other than the first low period of the selection signal in the period in which the selection signal is low.
  • the transmission circuit 22 outputs a signal related to the clock signal received by the first clock signal terminal when the signal output from the latch circuit 21 is at a high level; and when the signal output from the latch circuit 21 is at a low level , output level signal.
  • the feedback signal can enable the latch circuit 21 to output a signal in a period in which the selection signal is at a high level and a signal output in a first low-level period of the selection signal; Determining an end time of a first low level period of the selection signal, the feedback signal is changed from a low level to a high level; and a first low level period of the selection signal is from the selection signal by a high level The time when the level is changed to the low level, to the time period between the time when the signal output from the shift register unit of the next stage of the shift register unit is changed from the low level to the high level.
  • the selection signal received by the kth stage shift register unit may be the signal output by the k-1th stage shift register unit, and at this time, the next stage shift register of the kth stage shift register unit The unit is the k+1th shift register unit.
  • the selection signal received by the kth stage shift register unit may be the signal output by the k+1th stage shift register unit, and at this time, the next stage of the kth stage shift register unit
  • the stage shift register unit is the k-1th stage shift register unit.
  • the kth stage shift register unit is in an active state during a period in which the selection signal is high and a first low period of the selection signal.
  • the selection signal When the selection signal is at a high level, since the selection signal is at a high level, the signal received by the first clock signal terminal of the shift register unit is at a low level, and the signal output from the latch circuit 21 is at a high level. In addition, in the first low level period of the selection signal, since the selection signal is at a low level, the signal received by the first clock signal terminal of the shift register unit is at a high level, and the signal output by the latch circuit 21 remains Is high. That is, at the first low level period of the selection signal, the latch circuit 21 can latch its state when the selection signal is at the high level.
  • the latch circuit 21 when the first low level of the selection signal In the segment, the latch circuit 21 outputs a signal obtained by performing a non-operation on the signal outputted by the latch circuit 21 when the selection signal is at a high level, and a feedback signal. Therefore, once the feedback signal is at a high level, the signal output from the latch circuit 21 becomes a low level. That is to say, when the selection signal is at a low level, the signal of the output of the latch circuit can be changed by the feedback signal, so that the shift register unit can be brought into an inoperative state from the operating state.
  • the feedback signal changes from a low level to a high level, and therefore, at the end of the first low-level period of the selection signal, the output of the latch circuit The signal will go low. That is, at the end of the first low period of the selection signal, the shift register unit enters the inactive state from the active state.
  • the transmission circuit 22 When the signal output from the latch circuit 21 is at a high level, the transmission circuit 22 outputs a signal related to the clock signal received by the first clock signal terminal of the shift register unit. Specifically, the transmission circuit 22 outputs the same signal as the clock signal received by the first clock signal terminal of the shift register unit when the signal output from the latch circuit 21 is at a high level, or may be output at the latch circuit 21 When the signal is high, the transmission circuit 22 outputs a signal inverted from the clock signal received by the clock signal terminal of the shift register unit, thereby causing the shift register unit to implement the function of shift register. When the signal output from the latch circuit 21 is at a low level, the transmission circuit 22 outputs a level signal.
  • the transmission circuit 22 outputs a high level signal when the signal outputted by the latch circuit 21 is at a low level, or the transmission circuit 22 outputs a low level signal when the signal output by the latch circuit 21 is at a low level. Thereby, the shift register unit enters a non-operation state.
  • the shift register unit provided by the embodiment of the present disclosure adopts a selection signal to control the latch circuit to latch the state of the latch circuit when the select signal is at the high level during the first low level period of the selection signal.
  • the transfer circuit is controlled by the state of the latch circuit, thereby causing the shift register unit to implement the shift register function.
  • the state of the latch circuit is changed by the change in the level of the feedback signal when the selection signal is low, thereby causing the shift register unit to enter the inactive state. In this way, it is not necessary to use the complementary clocked two clock signals to control the transfer gate so that the shift register unit realizes the shift register function and puts it into an inactive state, thereby reducing the unnecessary work of the shift register unit in the non-working phase. Consumption.
  • the latch circuit includes a first inverter INV1, a tri-state inverter T_INV, The first transfer gate TG1, the second transfer gate TG2, the first NOR gate Nor1, and the first transistor T1.
  • the first inverter INV1 receives the selection signal CHO and outputs the selection signal CHO after the non-operation. If the selection signal CHO is high, the signal output by the first inverter INV1 is low. In contrast, if the selection signal CHO is at a low level, the signal output from the first inverter INV1 is at a high level.
  • the low-level active control terminal of the first transmission gate TG1 receives the signal output by the first inverter INV1, and the high-level active control terminal of the first transmission gate TG1 receives the selection signal CHO, the input terminal of the first transmission gate TG1.
  • the first transfer gate TG1 outputs a clock signal received by the input terminal of the first transfer gate TG1 when the first transfer gate TG1 is turned on.
  • the selection signal CHO is at a high level
  • the first transfer gate TG1 is turned on.
  • the selection signal CHO is at a low level
  • the first transfer gate TG1 is turned off.
  • the low-level active control terminal of the second transmission gate TG2 receives the selection signal CHO
  • the high-level active control terminal of the second transmission gate TG2 receives the signal output by the first inverter INV1
  • the second transmission gate TG2 receives the feedback signal. FB, and outputs the feedback signal FB when the second transfer gate TG2 is turned on.
  • the selection signal CHO is low
  • the second transmission gate TG2 is turned on.
  • the selection signal CHO is at a high level
  • the second transfer gate TG2 is turned off.
  • the signal output by the first NOR gate Nor1 is a signal OUT_Latch output by the latch circuit.
  • the first pole of the first transistor T1 refers to the source (SOURCE) or the drain (DRAIN) of the first transistor T1.
  • the low-level active control terminal of the tri-state inverter T_INV receives the selection signal CHO
  • the high-level active control terminal of the tri-state inverter T_INV receives the signal output by the first inverter INV1
  • the tri-state inverter T_INV Receiving the signal outputted by the first NOR gate Nor1, and after the selection signal CHO is low level and the signal output by the first inverter INV1 is high level, the signal output by the first NOR gate Nor1 is non-calculated Output.
  • the selection signal CHO when the selection signal CHO is high, the three-state inverse The phase comparator T_INV is in a high impedance state.
  • the selection signal CHO is low, the tri-state inverter T_INV is turned on, and the tri-state inverter T_INV outputs the received signal after non-operation.
  • the gate of the first transistor T1 receives the selection signal CHO, and the drain of the first transistor T1 receives the low level signal VSS.
  • the drain of the first transistor T1 can also receive the selection signal CHO, and the source of the first transistor T1 can also receive the low level signal VSS, which is not limited by this disclosure. .
  • the selection signal CHO When the selection signal CHO is at a high level, the selection signal CHO is at a high level, the signal received by the first clock signal terminal CLKIN1 of the shift register unit is at a low level, and the feedback signal FB is at a high level, the first The signal output from the phaser INV1 is low. Therefore, the first transfer gate TG1 is turned on, the second transfer gate TG2 is turned off, the first transistor T1 is turned on, and the tri-state inverter T_INV is in a high impedance state. Therefore, the two signals received by the first NOR gate Nor1 are all low, and the signal output by the first NOR gate Nor1 is high.
  • the selection signal CHO is at a low level
  • the signal received by the first clock signal terminal CLKIN1 of the shift register unit is at a high level
  • the feedback signal FB is at a low level.
  • the signal output from an inverter INV1 is at a high level. Therefore, the first transfer gate TG1 is turned off, the second transfer gate TG2 is turned on, the first transistor T1 is turned off, the tri-state inverter T_INV is turned on, and the tri-state inverter T_INV is when the select signal CHO is high level, the first NOR gate
  • the signal output by Nor1, that is, the high level signal is non-operated, and output to one input terminal of the first NOR gate Nor1.
  • the second transfer gate TG2 Since the first transistor T1 is turned off, the second transfer gate TG2 is turned on. Therefore, the other input of the first NOR gate Nor1 receives the feedback signal FB of a low level. Therefore, during the first low period of the selection signal CHO, the first NOR gate Nor1 still outputs a high level signal.
  • the signals output by the latch circuit are both a high level signal, the signal output by the transmission circuit and the first clock of the shift register unit
  • the clock signal received by the signal terminal is related, and the shift register unit is in an active state.
  • the selection signal CHO is always at a low level after the end of the first low-level period of the selection signal CHO until the selection signal CHO is again high. Therefore, the first transfer gate TG1 is turned off, the second transfer gate TG2 is turned on, the first transistor T1 is turned off, and the tri-state inverter T_INV is turned on.
  • the first NOR gate Nor1 receives the high voltage.
  • the flat signal will output a low level signal, which will cause the tristate inverter T_INV to output a high level signal, thereby making the latched
  • the circuit remains in the state of outputting a low level signal until the selection signal CHO is again high, and the signal output from the latch circuit changes.
  • the latch circuit outputs a high-level signal.
  • the state changes to a state in which a low-level signal is output, and when the latch circuit outputs a low-level signal, the signal output from the transmission circuit is a level signal, and the shift register unit is in a non-operation state.
  • the feedback signal FB changes from a low level to a high level at the end time of the first low level period of the selection signal CHO, the shift register unit ends at the first low level period of the selection signal CHO. The moment enters the non-working state from the working state.
  • the latch circuit includes a second inverter INV2, a third inverter INV3, a third transmission gate TG3, and a fourth transmission gate TG4.
  • the second inverter INV2 receives the selection signal CHO and outputs the selection signal CHO after the non-operation. If the selection signal CHO is high, the signal output from the second inverter INV2 is low. In contrast, if the selection signal CHO is at a low level, the signal output from the second inverter INV2 is at a high level.
  • the low-level effective control terminal of the third transmission gate TG3 receives the signal output by the second inverter INV2, and the high-level active control terminal of the third transmission gate TG3 receives the selection signal CHO, and the input terminal of the third transmission gate TG3
  • the first clock signal terminal CLKIN1 of the shift register unit is connected, and the third transfer gate TG3 outputs a clock signal received by the input terminal of the third transfer gate TG3 when the third transfer gate TG3 is turned on.
  • the selection signal CHO is at a high level
  • the third transfer gate TG3 is turned on.
  • the selection signal CHO is at a low level
  • the third transfer gate TG3 is turned off.
  • the low-level active control terminal of the fourth transmission gate TG4 receives the selection signal CHO
  • the high-level active control terminal of the fourth transmission gate TG4 receives the signal output by the second inverter INV2
  • the fourth transmission gate TG4 receives the feedback signal. FB, and outputs the feedback signal FB when the fourth transfer gate TG4 is turned on.
  • the selection signal CHO is low
  • the fourth transmission gate TG4 is turned on.
  • the selection signal CHO is at a high level
  • the fourth transfer gate TG4 is turned off.
  • One input end of the second NOR gate Nor2 is respectively connected to the output end of the third transfer gate TG3 and the output end of the fifth transfer gate TG5, and the other input end of the second NOR gate Nor2 is respectively connected to the fourth pass
  • the output of the output terminal TG4 and the first electrode of the second transistor T2, and the signal output by the second NOR gate Nor2 is the signal OUT_Latch outputted by the latch circuit.
  • the first pole of the second transistor T2 refers to the source or the drain of the second transistor T2.
  • the second transistor T2 has a second drain.
  • the first transistor of the second transistor T2 is extremely drained, the second transistor of the second transistor T2 is extremely source.
  • the third inverter INV3 receives the signal output from the second NOR gate Nor2, and outputs the signal output from the second NOR gate Nor2. When the second NOR gate Nor2 outputs a high level signal, the third inverter INV3 outputs a low level signal. In contrast, when the second NOR gate Nor2 outputs a low level signal, the third inverter INV3 outputs a high level signal.
  • the low-level active control terminal of the fifth transmission gate TG5 receives the selection signal CHO
  • the high-level active control terminal of the fifth transmission gate TG5 receives the signal output by the second inverter INV2
  • the fifth transmission gate TG5 receives the third signal.
  • the signal output from the inverter INV3 outputs a signal output from the third inverter INV3 when the selection signal CHO is at a low level.
  • the fifth transmission gate TG5 is turned on.
  • the selection signal CHO is at a high level
  • the fifth transfer gate TG5 is turned off.
  • the gate of the second transistor T2 receives the selection signal CHO, and the drain of the second transistor T2 receives the low level signal VSS.
  • the drain of the second transistor T2 can also receive the selection signal CHO, and the source of the second transistor T2 can also receive the low level signal VSS, which is not limited by this disclosure. .
  • the selection signal CHO is at a high level
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is at a low level
  • the feedback signal FB is at a high level.
  • the signal output from the two inverters INV2 is at a low level. Therefore, the third transfer gate TG3 is turned on, the fourth transfer gate TG4 is turned off, the fifth transfer gate TG5 is turned off, and the second transistor T2 is turned on. Therefore, the two signals received by the second NOR gate Nor2 are both low, and the signal output by the second NOR gate Nor2 is high.
  • the selection signal CHO is at a low level
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is at a high level
  • the feedback signal FB is at a low level.
  • the signal output by the second inverter INV2 is at a high level, and therefore, the third transmission gate TG3
  • the fourth transmission gate TG4 is turned on
  • the fifth transmission gate TG5 is turned on
  • the second transistor T2 is turned off
  • the third inverter INV3 outputs the signal of the second NOR gate Nor2 when the selection signal CHO is high level, that is, the high voltage After the flat signal is non-operated, it is output to one input terminal of the second NOR gate Nor2 through the fifth transfer gate TG5.
  • the second transistor T2 is turned off, the fourth transfer gate TG4 is turned on, and therefore, the second NOR gate Nor2
  • the other input receives a low level feedback signal FB. Therefore, during the first low period of the selection signal CHO, the second NOR gate Nor2 still outputs a high level signal.
  • the signals output by the latch circuit are both a high level signal, the signal output by the transmission circuit and the first clock of the shift register unit
  • the clock signal received by the signal terminal is related, and the shift register unit is in an active state.
  • the selection signal CHO is always at a low level after the end of the first low-level period of the selection signal CHO until the selection signal CHO is again high. Therefore, the third transmission gate TG3 is turned off, and the fourth transmission gate TG4 When turned on, the fifth transfer gate TG5 is turned on, and the second transistor T2 is turned off.
  • the second NOR gate Nor2 receives a high level signal, and a low level signal is output, which causes the third inverter INV3 to output a high level signal, thereby causing the latch circuit
  • the state of the output low level signal is maintained until the selection signal CHO is again high, and the signal output by the latch circuit changes.
  • the latch circuit After the end of the first low-level period of the selection signal CHO until the selection signal CHO is again high, once the feedback signal FB is high, the latch circuit outputs a high-level signal.
  • the state changes to a state in which a low-level signal is output, and when the latch circuit outputs a low-level signal, the signal output from the transmission circuit is a level signal, and the shift register unit is in a non-operation state.
  • the transmission circuit includes a sixth transmission gate TG6, a third transistor T3, and a first NAND gate Nand1.
  • the high-level effective control terminal of the sixth transmission gate TG6 receives the signal OUT_Latch outputted by the latch circuit, and the low-level effective control terminal of the sixth transmission gate TG6 receives the signal OUT_Latch outputted by the latch circuit through the non-operated signal OUT_Latch_Inv
  • the input end of the sixth transfer gate TG6 is connected to the first clock signal terminal CLKIN1 of the shift register unit, and the sixth transfer gate TG6 inputs the input of the sixth transfer gate TG6 when the signal OUT_Latch outputted by the latch circuit is high level.
  • the clock signal output received by the terminal is connected to the first clock signal terminal CLKIN1 of the shift register unit
  • An input terminal of the first NAND gate Nand1 receives an enable signal EN, and the other input terminal of the first NAND gate Nand is respectively connected to the output end of the sixth transmission gate TG6 and the first pole of the third transistor T3, the first The signal output by the non-gate Nand1 is the signal OUT_Trans output from the transmission circuit.
  • the enable signal EN is at a high level for a period of time during which one frame of image is displayed.
  • the signal OUT_Latch outputted by the gate of the third transistor T3 receives the non-operated signal OUT_Latch_Inv, and the second electrode of the third transistor T3 receives the low level signal VSS.
  • the second transistor of the third transistor T3 when the first transistor of the third transistor T3 is extremely source, the second transistor of the third transistor T3 is extremely drained. In contrast, when the first transistor of the third transistor T3 is extremely drained, the second source of the third transistor T3 is extremely source.
  • the sixth transfer gate TG6 When the signal OUT_Latch outputted by the latch circuit is high level, the sixth transfer gate TG6 is turned on, the third transistor T3 is turned off, and the sixth transfer gate TG6 outputs the clock signal received at the input end thereof to the first NAND gate Nand1. An input. At this time, since the time energy signal EN is at a high level, if the clock signal received at the input end of the sixth transmission gate TG6 is at a low level, the first NAND gate Nand1 outputs a high level signal. In contrast, if the clock signal received at the input terminal of the sixth transmission gate TG6 is at a high level, the first NAND gate Nand1 outputs a low level signal.
  • the sixth transfer gate TG6 When the signal OUT_Latch outputted by the latch circuit is low, the sixth transfer gate TG6 is turned off, and the third transistor T3 is turned on. Therefore, the low level signal VSS is transmitted to the input of the first NAND gate Nand1 through the third transistor T3. At this time, the first NAND gate Nand1 outputs a high level signal.
  • the transmission circuit includes a second NAND gate Nand2.
  • An input terminal of the second NAND gate Nand2 receives the signal OUT_Latch outputted by the latch circuit, and the other input terminal of the second NAND gate Nand2 is connected to the first clock signal terminal CLKIN1 of the shift register unit, and the second NAND gate Nand2 output The signal is the signal OUT_Trans output from the transmission circuit.
  • the signal output by the second NAND gate Nand2 is a non-operated signal of the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit, that is, when shifting When the clock signal received by the first clock signal terminal CLKIN1 of the register unit is at a high level, the second NAND gate Nand2 outputs a low level signal. In contrast, when the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is at a low level, the second NAND gate Nand2 outputs a high level signal.
  • the shift register unit provided by the embodiment of the present disclosure further includes a buffer circuit.
  • the buffer circuit receives the signal OUT_Trans outputted by the transmission circuit, and outputs a signal OUT_Trans outputted by the transmission circuit after non-operation. That is to say, when the signal OUT_Trans outputted by the transmission circuit is at a high level, the signal OUT_Buffer outputted by the buffer circuit is a low level signal. When the signal OUT_Trans outputted by the transmission circuit is low, the signal OUT_Buffer output by the buffer circuit is a high level signal.
  • the buffer register circuit is provided in the shift register unit provided by the embodiment of the present disclosure, the signal OUT_Buffer output by the buffer circuit is the signal OUT output by the shift register unit.
  • the buffer circuit includes 2k+1 fourth inverters INV4.
  • 2k+1 fourth inverters INV4 are connected in series, and the input of the first fourth inverter INV4 after the series connection
  • the terminal receives the signal OUT_Trans outputted by the transmission circuit, and the output of the previous fourth inverter INV4 of the fourth inverter INV4 other than the first fourth inverter INV4 is connected to the fourth inverter.
  • the output of the last fourth inverter INV4 is the output of the buffer circuit.
  • the shift register unit provided in the embodiment of the present disclosure further includes a scan direction selection circuit.
  • the scan direction selection circuit outputs a forward selection signal CHOF as the selection signal CHO when the forward control signal FS is at a high level and the reverse control signal BS is at a low level.
  • the reverse selection signal CHOB is output as a selection signal CHO when the forward control signal FS is at a low level and the reverse control signal BS is at a high level.
  • the scan direction selection circuit includes a seventh transfer gate TG7 and an eighth transfer gate TG8.
  • the active-high control terminal of the seventh transmission gate TG7 receives the forward control signal FS
  • the low-level active control terminal of the seventh transmission gate TG7 receives the reverse control signal BS
  • the seventh transmission gate TG7 receives the forward selection signal. CHOF
  • the forward selection signal CHOF is output.
  • the seventh transfer gate TG7 is turned on. With this In contrast, when the forward control signal FS is at a low level and the reverse control signal BS is at a high level, the seventh transfer gate TG7 is turned off.
  • the high-level effective control terminal of the eighth transmission gate TG8 receives the reverse control signal BS
  • the low-level active control terminal of the eighth transmission gate TG8 receives the forward control signal FS
  • the eighth transmission gate TG8 receives the reverse selection signal. CHOB
  • the forward control signal FS is at a low level and the reverse control signal BS is at a high level
  • the reverse selection signal CHOB is output.
  • the eighth transfer gate TG8 is turned off.
  • the eighth transfer gate TG8 is turned on.
  • the clock signal received by the first clock signal terminal of the shift register unit provided by the embodiment of the present disclosure is the first clock signal CLK1 or the second clock signal CLK2.
  • the first clock signal CLK1 when the first clock signal CLK1 is at a high level, the second clock signal CLK2 is at a low level.
  • the second clock signal CLK2 when the second clock signal CLK2 is at a high level, the first clock signal CLK1 is at a low level.
  • the feedback signal FB is a signal obtained by performing an OR operation between the forward selection signal CHOF and the reverse selection signal CHOB.
  • the forward selection signal CHOF is the selection signal CHO at the time of forward scanning
  • the reverse selection signal CHOB is the selection signal CHO at the time of reverse scanning.
  • the feedback signal FB is a clock signal received by the second clock signal terminal CLKIN2 of the shift register unit.
  • the clock signal received by the first clock terminal CLKIN1 of the shift register unit is at a high level
  • the clock signal received by the second clock terminal CLKIN2 of the shift register unit is at a low level.
  • the clock signal received by the first clock terminal CLKIN1 of the shift register unit is at a low level.
  • the feedback signal FB that is, the signal received by the second clock signal terminal CLKIN2 of the shift register unit is the second clock.
  • the feedback signal FB that is, the clock signal received by the second clock signal terminal CLKIN2 of the shift register unit is the first clock.
  • the feedback signal FB is a signal OUT_Trans output by the transmission circuit.
  • the shift register unit provided by the embodiment of the present disclosure includes a latch circuit, a transmission circuit, a buffer circuit, and a scanning direction. Selecting the circuit, and the latch circuit adopts the structure shown in FIG. 3, the transmission circuit adopts the structure shown in FIG. 5, the buffer circuit includes only one fourth inverter, and the scan direction selection circuit adopts the structure shown in FIG.
  • the shift register unit provided by the embodiment of the present disclosure is as shown in FIG.
  • the shift register unit provided by the embodiment of the present disclosure includes a latch circuit, a transmission circuit, a buffer circuit, and a scanning direction. Selecting the circuit, and the latch circuit adopts the structure shown in FIG. 4, the transmission circuit adopts the structure shown in FIG. 5, the buffer circuit includes only one fourth inverter, and the scan direction selection circuit adopts the structure shown in FIG.
  • the shift register unit provided by the embodiment of the present disclosure is as shown in FIG.
  • the third NOR gate Nor3 and the fifth inverter INV5 in FIGS. 9 and 10 are for ORing the forward selection signal CHOF and the reverse selection signal CHOB.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit shown in FIG. 9 or FIG. 10 is taken as an example of the first clock signal CLK1.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit shown in FIG. 9 or FIG. 10 may also be the second clock signal CLK2.
  • the forward control signal FS is at a high level
  • the reverse control signal BS is at a low level. Therefore, the seventh transfer gate TG7 is turned on, and the eighth transfer is performed.
  • the gate TG8 is turned off, the forward selection signal CHOF is used as the selection signal CHO, and the operation timing chart of the shift register unit is as shown in FIG.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit shown in FIG. 9 or FIG. 10 is taken as an example for the first clock signal CLK1.
  • the shift register shown in FIG. 9 or FIG. 10 is used.
  • the clock signal received by the first clock signal terminal CLKIN1 of the unit may also be the second clock signal CLK2.
  • the signal OUT_Latch outputted by the latch circuit is at a high level, and therefore, the sixth transmission gate TG6 in FIG. 9 or FIG. 10 is turned on.
  • the third transistor T3 is turned off. Therefore, the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is transmitted to an input terminal of the first NAND gate Nand1 (the signal of the input terminal of the first NAND gate Nand1) For Mid_OUT).
  • the shift register The clock signal received by the first clock signal terminal CLKIN1 of the element is at a low level, and the enable signal EN is at a high level. Therefore, in the first period, the signal OUT output by the shift register unit shown in FIG. 9 or FIG. Is low.
  • the signal OUT_Latch outputted by the latch circuit is still at a high level, and therefore, the sixth transmission gate TG6 in FIG. 9 or FIG.
  • the third transistor T3 When the third transistor T3 is turned off, the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is transmitted to one input terminal of the first NAND gate Nand1.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is at a high level, and the enable signal EN is at a high level. Therefore, in the second period, FIG. 9 or FIG.
  • the signal OUT output by the shift register unit is at a high level.
  • the forward selection signal CHOF When the third period is entered into the third period, since the reverse selection signal CHOB becomes a high level, the forward selection signal CHOF remains at a low level, and therefore, the forward selection signal CHOF and the reverse selection signal CHOB pass through the The signal obtained after the three-OR gate NO3 and the fifth inverter INV5 changes from a low level to a high level, which causes the signal OUT_Latch output from the latch circuit to change from a high level to a low level. That is, when the third period is entered from the second period, since the reverse selection signal CHOB changes from the low level to the high level, this causes the signal OUT_Latch outputted by the latch circuit to change from the high level to the low level. Thereby, the sixth transfer gate TG6 in FIG.
  • the third transistor T3 is turned on, and the low level signal VSS is transmitted to one input terminal of the first NAND gate Nand1. Therefore, in the third period, one input terminal of the first NAND gate Nand1 receives the low level signal VSS, the other input terminal of the first NAND gate Nand1 receives the enable signal EN, and in the third period, the enable signal EN is high. Therefore, in the third period, the signal OUT output from the shift register unit shown in FIG. 9 or FIG. 10 is at a low level.
  • the shift register unit shown in FIG. 9 or FIG. 10 is always in the third period until the forward selection signal CHOF is again at the high level, and the shift register unit shown in FIG. 9 or FIG. 10 can enter through the third period.
  • the first time period In the first period and the second period, the shift register units shown in FIGS. 9 and 10 are all in the active state, and in the third period, the shift register units shown in FIGS. 9 and 10 are all in the non-operation state.
  • the reverse control signal BS is at a high level
  • the forward control signal FS is at a low level. Therefore, the seventh transfer gate TG7 is turned off, and the eighth transfer is performed.
  • the gate TG8 is turned on, the reverse selection signal CHOB is used as the selection signal CHO, and the operation timing chart of the shift register unit is as shown in FIG.
  • the shift register unit shown in FIG. 9 or FIG. 10 is in reverse scan, the latch circuit, the transfer circuit, and the buffer circuit are exactly the same as the shift register unit in the forward scan, and will not be described herein. .
  • the shift register unit provided by the embodiment of the present disclosure includes a latch circuit, a transmission circuit, a buffer circuit and a scan direction selection circuit, and the latch circuit is as shown in FIG.
  • the structure of the transmission circuit adopts the structure shown in FIG. 5
  • the buffer circuit includes only one fourth inverter
  • the scanning direction selection circuit adopts the structure shown in FIG. 8.
  • the shift register unit provided by the embodiment of the present disclosure is as Figure 13 shows.
  • the shift register unit provided by the embodiment of the present disclosure includes a latch circuit, a transmission circuit, a buffer circuit, and a scan direction selection circuit, and the latch circuit is as shown in FIG.
  • the structure of the transmission circuit adopts the structure shown in FIG. 5
  • the buffer circuit includes only one fourth inverter
  • the scanning direction selection circuit adopts the structure shown in FIG. 8.
  • the shift register unit provided by the embodiment of the present disclosure is as Figure 14 shows.
  • the forward control signal FS is at a high level
  • the reverse control signal BS is at a low level. Therefore, the seventh transfer gate TG7 is turned on, and the eighth transfer is performed.
  • the gate TG8 is turned off, the forward selection signal CHOF is used as the selection signal CHO, and the operation timing chart of the shift register unit is as shown in FIG.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit shown in FIG. 13 or FIG. 14 is taken as an example for the first clock signal CLK1.
  • the shift register shown in FIG. 13 or FIG. 14 The clock signal received by the first clock signal terminal CLKIN1 of the unit may also be the second clock signal CLK2.
  • the signal OUT_Latch outputted by the latch circuit is at a high level, and therefore, the sixth transmission in FIG. 13 or FIG.
  • the gate TG6 is turned on, and the third transistor T3 is turned off. Therefore, the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is transmitted to an input terminal of the first NAND gate Nand1 (the first NAND gate Nand1) The signal at this input is Mid_OUT).
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is at a low level, and the enable signal EN is at a high level. Therefore, in the first period, FIG. 13 or FIG. 14 is shown.
  • the signal OUT output by the shift register unit is at a low level.
  • the signal OUT_Latch outputted by the latch circuit is still at a high level, and therefore, the sixth transmission gate TG6 in FIG. 13 or FIG.
  • the third transistor T3 is turned off, and therefore, the signal received by the first clock signal terminal CLKIN1 of the shift register unit is transmitted to one input terminal of the first NAND gate Nand1.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is at a high level, and the enable signal EN is at a high level. Therefore, in the second period, FIG. 13 or FIG. 14 is shown.
  • the signal OUT output by the shift register unit is at a high level.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is changed from the high level to the low level, and the sixth transmission gate TG6 and the third transistor T3 remain The state at the second time period, that is, the sixth transfer gate TG6 is turned on, and the third transistor T3 is turned off, and therefore, the signal OUT output from the shift register unit shown in FIG. 13 or FIG. 14 is changed from the high level to the low level.
  • the signal OUT_Trans outputted by the transmission circuit that is, the signal outputted by the first NAND gate Nand1 changes from a low level to a high level, that is, the feedback signal FB changes from a low level to a high level, which causes the lock
  • the signal OUT_Latch output from the memory circuit changes from a high level to a low level. That is, when the third period is entered by the second period, since the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit changes from the high level to the low level, this causes the signal output from the latch circuit.
  • OUT_Latch changes from a high level to a low level, so that the sixth transfer gate TG6 in FIG. 13 or FIG.
  • the third transistor T3 is turned on, and the low level signal VSS is transmitted to an input of the first NAND gate Nand1. Therefore, in the third period, one input terminal of the first NAND gate Nand1 receives the low level signal VSS, and the other input terminal of the first NAND gate Nand1 receives the enable signal EN. In the third period, the enable signal EN is at a high level. Therefore, in the third period, the signal OUT output from the shift register unit shown in FIG. 13 or FIG. 14 is at a low level.
  • the shift register unit shown in FIG. 13 or FIG. 14 is always in the third period until the forward direction.
  • the selection signal CHOF is again at a high level
  • the shift register unit shown in FIG. 13 or FIG. 14 can enter the first period from the third period.
  • the shift register units shown in Figs. 13 and 14 are all in an active state
  • the shift register units shown in Figs. 13 and 14 are all in a non-operation state.
  • the reverse selection signal CHOB does not affect the various circuits in the shift register unit.
  • the reverse control signal BS is at a high level
  • the forward control signal FS is at a low level. Therefore, the seventh transfer gate TG7 is turned off, and the eighth transfer is performed.
  • the gate TG8 is turned on, the reverse selection signal CHOB is used as the selection signal CHO, and the operation timing chart of the shift register unit is as shown in FIG. 16.
  • the shift register unit shown in FIG. 13 or FIG. 14 is in the reverse scan
  • the latch circuit, the transfer circuit, and the buffer circuit are exactly the same as the shift register unit in the forward scan, and details are not described herein again.
  • the forward selection signal CHOF does not affect the various circuits in the shift register unit.
  • the shift register unit provided by the embodiment of the present disclosure includes a latch circuit, a transmission circuit, a buffer circuit, and a scan direction selection circuit
  • the latch circuit adopts the structure shown in FIG. 3
  • the transmission circuit adopts the structure shown in FIG. 5
  • the buffer circuit includes only one fourth inverter
  • the scan direction selection circuit adopts the structure shown in FIG. 8, then the present disclosure
  • the shift register unit provided by the text embodiment is as shown in FIG.
  • the shift register unit provided by the embodiment of the present disclosure includes a latch circuit, a transmission circuit, a buffer circuit, and a scan direction selection circuit
  • the latch circuit adopts the structure shown in FIG. 4
  • the transmission circuit adopts the structure shown in FIG. 5
  • the buffer circuit includes only one fourth inverter, the scanning direction
  • the selection circuit adopts the structure shown in FIG. 8, and then the shift register unit provided by the embodiment of the present disclosure is as shown in FIG. 18.
  • the forward control signal FS is at a high level
  • the reverse control signal BS is at a low level. Therefore, the seventh transfer gate TG7 is turned on, and the eighth transfer is performed.
  • the gate TG8 is turned off, the forward selection signal CHOF is used as the selection signal CHO, and the operation timing chart of the shift register unit is as shown in FIG.
  • the signal OUT_Latch outputted by the latch circuit is at a high level, and therefore, the sixth transmission gate TG6 in FIG. 17 or FIG. 18 is turned on.
  • the third transistor T3 is turned off. Therefore, the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is transmitted to an input terminal of the first NAND gate Nand1 (the signal of the input terminal of the first NAND gate Nand1) For Mid_OUT).
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is at a low level, and the enable signal EN is at a high level. Therefore, in the first period, FIG. 17 or FIG. 18 is shown.
  • the signal OUT output by the shift register unit is at a low level.
  • the signal OUT_Latch outputted by the latch circuit is still at a high level, and therefore, the sixth transmission gate TG6 in FIG. 17 or FIG.
  • the third transistor T3 is turned off, and therefore, the signal received by the first clock signal terminal CLKIN1 of the shift register unit is transmitted to one input terminal of the first NAND gate Nand.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is at a high level, and the enable signal EN is at a high level. Therefore, in the second period, FIG. 17 or FIG. 18 is shown.
  • the signal OUT output by the shift register unit is at a high level.
  • the selection signal CHO that is, the forward selection signal CHOF is at a low level, and therefore, the fourth transmission gate TG4 is turned on, and the second inverted clock signal terminal CLKIN2 of the shift register unit is received.
  • the clock signal changes from a low level to a high level, which causes the signal OUT_Latch outputted by the latch circuit to change from a high level to a low level, thereby causing the sixth transmission gate TG6 in FIG. 17 or FIG. 18 to be turned off,
  • the three transistor T3 is turned on, and the low level signal VSS is transmitted to one input terminal of the first NAND gate Nand1.
  • one input terminal of the first NAND gate Nand1 receives the low level signal VSS, the other input terminal of the first NAND gate Nand1 receives the enable signal EN, and in the third period, the enable signal EN is high, therefore, in the third period, Figure 17 or Figure 18
  • the signal OUT output from the shift register unit shown is low.
  • the shift register unit shown in FIG. 17 or FIG. 18 is always in the third period until the forward selection signal CHOF is again at the high level, and the shift register unit shown in FIG. 17 or FIG. 18 can be entered by the third period.
  • the first time period In the first period and the second period, the shift register units shown in Figs. 17 and 18 are in an active state, and in the third period, the shift register units shown in Figs. 17 and 18 are in a non-operation state. Since the reverse selection signal CHOB does not affect the respective portions of the circuits in the shift register unit due to the forward scanning, the reverse selection signal CHOB is not shown in FIG.
  • the reverse control signal BS is at a high level
  • the forward control signal FS is at a low level. Therefore, the seventh transfer gate TG7 is turned off, and the eighth transfer is performed.
  • the gate TG8 is turned on, the reverse selection signal CHOB is used as the selection signal CHO, and the operation timing chart of the shift register unit is as shown in FIG.
  • the latch circuit, the transfer circuit, and the buffer circuit are exactly the same as the shift register unit in the forward scan, and details are not described herein again.
  • the forward selection signal CHOF does not affect the various circuits in the shift register unit.
  • the clock signal received by the second clock signal terminal CLKIN2 of the shift register unit is loaded to the NOR gate when the shift register unit is in the non-operation state. At the input, this also charges and discharges the gate capacitance in the NAND gate, but the shift register unit does not need to use a pair of inverted complementary clock signals to control the transmission gate opening and closing, thus, compared to the conventional The power consumption of the shift register unit in the non-operating state, the unnecessary power consumption of the shift register unit in the non-operating state is still reduced.
  • the shift register unit provided by the embodiment of the present disclosure includes a latch circuit, a transmission circuit, a buffer circuit, and a scanning direction. Selecting the circuit, and the latch circuit adopts the structure shown in FIG. 3, the transmission circuit adopts the structure shown in FIG. 6, the buffer circuit includes only one fourth inverter, and the scan direction selection circuit adopts the structure shown in FIG.
  • the shift register unit provided by the embodiment of the present disclosure is as shown in FIG. 21.
  • the shift register unit provided by the embodiment of the present disclosure includes a latch circuit, a transmission circuit, a buffer circuit and a scan direction selection circuit, and the latch circuit adopts the structure shown in FIG. 4, the transmission circuit adopts In the structure shown in FIG. 6, the buffer circuit includes only one fourth inverter, and the scan direction selection circuit adopts the structure shown in FIG. 8. Then, the shift register unit provided by the embodiment of the present disclosure is as shown in FIG.
  • the forward control signal FS is at a high level
  • the reverse control signal BS is at a low level. Therefore, the seventh transfer gate TG7 is turned on, and the eighth transfer is performed.
  • the gate TG8 is turned off, the forward selection signal CHOF is used as the selection signal CHO, and the operation timing chart of the shift register unit is as shown in FIG.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit shown in FIG. 21 or FIG. 22 will be described as an example of the first clock signal CLK1.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit shown in FIG. 21 or FIG. 22 may also be the second clock signal CLK2.
  • the signal OUT_Latch outputted by the latch circuit is at a high level, and therefore, the second NAND gate Nand2 in FIG. 21 or FIG. One input is high.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is at a low level. Therefore, in the first period, the signal OUT output from the shift register unit shown in FIG. 21 or FIG. Is low.
  • the signal OUT_Latch outputted by the latch circuit is still at a high level, and therefore, the second NAND gate in FIG. 21 or FIG. One input of Nand2 is high.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is at a high level. Therefore, in the second period, the signal OUT output from the shift register unit shown in FIG. 21 or FIG. Is high.
  • the forward selection signal CHOF When the third period is entered into the third period, since the reverse selection signal CHOB becomes a high level, the forward selection signal CHOF remains at a low level, and therefore, the forward selection signal CHOF and the reverse selection signal CHOB pass through the The signal obtained after the three-OR gate NO3 and the fifth inverter INV5 changes from a low level to a high level, which causes the signal OUT_Latch output from the latch circuit to change from a high level to a low level. That is, when the third period is entered from the second period, since the reverse selection signal CHOB changes from the low level to the high level, this causes the signal OUT_Latch outputted by the latch circuit to change from the high level to the low level.
  • the clock signal received by CLKIN1 changes from a high level to a low level, which causes the signal OUT outputted by the shift register unit shown in FIG. 21 or FIG. 22 to change from a high level to a low level, and therefore, at the third level During the period, the signal OUT output from the shift register unit shown in FIG. 21 or FIG. 22 is at a low level.
  • the shift register unit shown in FIG. 21 or FIG. 22 is always in the third period until the forward selection signal CHOF is again at the high level, and the shift register unit shown in FIG. 21 or FIG. 22 can be entered by the third period.
  • the first time period In the first period and the second period, the shift register units shown in Figs. 21 and 22 are all in the active state, and in the third period, the shift register units shown in Figs. 21 and 22 are in the non-operation state.
  • the reverse control signal BS is at a high level
  • the forward control signal FS is at a low level. Therefore, the seventh transfer gate TG7 is turned off, and the eighth transfer is performed.
  • the gate TG8 is turned on, the reverse selection signal CHOB is used as the selection signal CHO, and the operation timing chart of the shift register unit is as shown in FIG.
  • the latch circuit, the transfer circuit, and the buffer circuit are exactly the same as the shift register unit in the forward scan, and will not be described herein. .
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is loaded into the NAND gate when the shift register unit is in the non-operation state. At the input, this will charge and discharge the gate capacitance in the NAND gate, but the shift register unit does not need to use a pair of complementary inverted clock signals to control the transmission gate opening and closing, therefore, compared to the conventional The power consumption of the shift register unit in the non-operating state, the unnecessary power consumption of the shift register unit in the non-operating state is still reduced.
  • the shift register unit provided by the embodiment of the present disclosure includes a latch circuit, a transmission circuit, a buffer circuit and a scan direction selection circuit, and the latch circuit is as shown in FIG.
  • the structure of the transmission circuit adopts the structure shown in FIG. 6.
  • the buffer circuit includes only one fourth inverter, and the scanning direction selection circuit adopts the structure shown in FIG. 8.
  • the shift register unit provided by the embodiment of the present disclosure is as Figure 23 shows.
  • the shift register unit provided by the embodiment of the present disclosure includes a latch circuit, a transmission circuit, a buffer circuit, and a scan direction selection circuit, and the latch circuit is as shown in FIG. Structure
  • the transmission circuit uses the structure shown in Figure 6
  • the buffer circuit includes only one fourth inverter, and the scan direction selection circuit adopts the structure shown in FIG. 8. Then, the shift register unit provided by the embodiment of the present disclosure is as shown in FIG.
  • the forward control signal FS is at a high level
  • the reverse control signal BS is at a low level. Therefore, the seventh transfer gate TG7 is turned on, and the eighth transfer is performed.
  • the gate TG8 is turned off, the forward selection signal CHOF is used as the selection signal CHO, and the operation timing chart of the shift register unit is as shown in FIG.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit shown in FIG. 23 or FIG. 24 will be described as an example of the first clock signal CLK1.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit shown in FIG. 23 or FIG. 24 may also be the second clock signal CLK2.
  • the signal OUT_Latch outputted by the latch circuit is at a high level, and therefore, the second NAND gate Nand2 in FIG. 23 or FIG. One input is high.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is at a low level. Therefore, in the first period, the signal OUT output by the shift register unit shown in FIG. 23 or FIG. Is low.
  • the signal OUT_Latch outputted by the latch circuit is still at a high level, and therefore, the second NAND gate in FIG. 23 or FIG. One input of Nand2 is high.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is at a high level. Therefore, in the second period, the signal OUT output from the shift register unit shown in FIG. 23 or FIG. Is high.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit changes from a high level to a low level, and the latch circuit remains in the state at the second time period. That is, the latch circuit still outputs a high level signal. Therefore, the signal OUT outputted by the shift register unit shown in FIG. 23 or FIG.
  • OUT_Latch changes from a high level to a low level, so that the signal OUT outputted by the shift register unit shown in FIG. 23 or FIG. 24 is changed from a high level to a low level.
  • the level therefore, in the third period, the signal OUT output from the shift register unit shown in Fig. 23 or Fig. 24 is at a low level.
  • the shift register unit shown in FIG. 23 or FIG. 24 is always in the third period until the forward selection signal CHOF is again at the high level, and the shift register unit shown in FIG. 23 or FIG. 24 can enter by the third period.
  • the first time period In the first period and the second period, the shift register units shown in Figs. 23 and 24 are all in the active state, and in the third period, the shift register units shown in Figs. 23 and 24 are in the inoperative state.
  • the reverse control signal BS is at a high level
  • the forward control signal FS is at a low level. Therefore, the seventh transfer gate TG7 is turned off, and the eighth transfer is performed.
  • the gate TG8 is turned on, the reverse selection signal CHOB is used as the selection signal CHO, and the operation timing chart of the shift register unit is as shown in FIG. 16.
  • the shift register unit shown in FIG. 23 or FIG. 24 is in reverse scan, the latch circuit, the transfer circuit, and the buffer circuit are exactly the same as the shift register unit in the forward scan, and will not be described herein. .
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is loaded into the NAND gate when the shift register unit is in a non-operation state. At the input, this will charge and discharge the gate capacitance in the NAND gate, but the shift register unit does not need to use a pair of complementary inverted clock signals to control the transmission gate opening and closing, therefore, compared to the conventional The power consumption of the shift register unit in the non-operating state, the unnecessary power consumption of the shift register unit in the non-operating state is still reduced.
  • the shift register unit shown in FIG. 23 or FIG. 24 has a duty ratio of the clock signal of less than 50%, there is a risk of logical competition.
  • the shift register unit provided by the embodiment of the present disclosure includes a latch circuit, a transmission circuit, a buffer circuit, and a scan direction selection circuit
  • the latch circuit adopts the structure shown in FIG. 3
  • the transmission circuit adopts the structure shown in FIG. 6
  • the buffer circuit includes only one fourth inverter
  • the scan direction selection circuit adopts the structure shown in FIG. 8, then the present disclosure
  • the shift register unit provided by the text embodiment is as shown in FIG.
  • the shift register unit provided by the embodiment of the present disclosure includes a latch circuit and transmits power
  • the circuit, the buffer circuit and the scanning direction selection circuit, and the latch circuit adopts the structure shown in FIG. 4, and the transmission circuit adopts the structure shown in FIG. 6.
  • the buffer circuit includes only one fourth inverter, and the scanning direction selection circuit adopts a diagram.
  • the structure shown in Fig. 8, then the shift register unit provided by the embodiment of the present disclosure is as shown in Fig. 26.
  • the forward control signal FS is at a high level
  • the reverse control signal BS is at a low level. Therefore, the seventh transfer gate TG7 is turned on, and the eighth transfer is performed.
  • the gate TG8 is turned off, the forward selection signal CHOF is used as the selection signal CHO, and the operation timing chart of the shift register unit is as shown in FIG.
  • the signal OUT_Latch outputted by the latch circuit is at a high level, and therefore, the second NAND gate Nand2 in FIG. 25 or FIG. One input is high.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is at a low level. Therefore, in the first period, the signal OUT output from the shift register unit shown in FIG. 25 or FIG. Is low.
  • the signal OUT_Latch outputted by the latch circuit is still at a high level, and therefore, the second NAND gate in FIG. 25 or FIG. One input of Nand2 is high.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is at a high level. Therefore, in the second period, the signal OUT output from the shift register unit shown in FIG. 25 or FIG. Is high.
  • the selection signal CHO that is, the forward selection signal CHOF is at a low level, and therefore, the fourth transmission gate TG4 is turned on, and the clock received by the second clock signal terminal CLKIN2 of the shift register unit
  • the signal changes from low level to high level, which causes the signal OUT_Latch outputted by the latch circuit to change from high level to low level, thereby making one input of the second NAND gate Nand2 in FIG. 25 or FIG. Receive a low level signal.
  • the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is at a low level. Therefore, in the third period, the signal OUT output from the shift register unit shown in FIG. 25 or FIG. Is low.
  • the reverse control signal BS is at a high level
  • the forward control signal FS is at a low level. Therefore, the seventh transfer gate TG7 is turned off, and the eighth transfer is performed.
  • the gate TG8 is turned on, the reverse selection signal CHOB is used as the selection signal CHO, and the operation timing chart of the shift register unit is as shown in FIG.
  • the shift register unit shown in FIG. 25 or FIG. 26 is in the reverse scan,
  • the latch circuit, the transmission circuit and the buffer circuit are exactly the same as those of the shift register unit in the forward scan, and are not described herein again.
  • the clock signal received by the second clock signal terminal CLKIN2 of the shift register unit is loaded to the NOR gate when the shift register unit is in the non-operation state. At the input end, this will charge and discharge the gate capacitance in the NOR gate, and the clock signal received by the first clock signal terminal CLKIN1 of the shift register unit is also loaded into the NAND gate when the shift register unit is in the non-operation state.
  • a display panel provided by an embodiment of the present disclosure includes a shift register unit provided by a plurality of stages of the present disclosure.
  • the forward selection signal CHOF received by the m-th stage shift register unit SRm other than the first-stage shift register unit SR1 is the m-1th-stage shift register unit SRm-1.
  • the forward selection signal CHOF received by the first stage shift register unit SR1 is the initial trigger signal STV.
  • the reverse selection signal CHOB received by the kth stage shift register unit SRk other than the Nth stage shift register unit SRN is the k+1th shift register unit SRk+1.
  • the reverse selection signal CHOB received by the Nth stage shift register unit SR1 is also the initial trigger signal STV.
  • the clock signal received by the first clock signal terminal CLKIN1 of the p-th stage shift register unit SRp is the first clock signal CLK1.
  • the clock signal received by the first clock signal terminal CLKIN1 of the p-th stage shift register unit SRp is the second clock signal CLK2, where p is greater than or equal to 1, less than or equal to N.
  • the power supply signal VDD received by each of the shift register units in Fig. 27 is supplied to the active device in the shift register unit.
  • the forward selection signal CHOF received by the m-th stage shift register unit SRm other than the first-stage shift register unit SR1 is the output of the m-1th-stage shift register unit SRm-1.
  • the forward selection signal CHOF received by the first stage shift register unit SR1 is the initial trigger signal STV.
  • the reverse selection signal CHOB received by the kth stage shift register unit SRk other than the Nth stage shift register unit SRN is the k+1th shift register unit SRk+1 output.
  • the reverse selection signal CHOB received by the Nth stage shift register unit SR1 is also the initial trigger signal STV.
  • the clock signal received by the first clock signal terminal CLKIN1 of the p-th stage shift register unit SRp is the first clock signal CLK1.
  • the clock signal received by the first clock signal terminal CLKIN1 of the p-th stage shift register unit SRp is the second clock signal CLK2, where p is greater than or equal to 1, less than or equal to N.
  • the power supply signal VDD received by each of the shift register units in Fig. 28 is supplied to the active device in the shift register unit.
  • the connection manner of each shift register unit is as shown in FIG. 29 or FIG.
  • the connection relationship of the shift register units shown in FIG. 29 is different from the connection relationship of the shift register units shown in FIG. 27 only in that the shift register units shown in FIG. 29 also have the second clock.
  • Signal terminal CLKIN2 In FIG. 29, when p is an odd number, the clock signal received by the second clock signal terminal CLKIN2 of the p-th stage shift register unit SRp is the second clock signal CLK2.
  • the clock signal received by the second clock signal terminal CLKIN2 of the p-th stage shift register unit SRp is the first clock signal CLK1, where p is greater than or equal to 1, less than or equal to N.
  • the connection relationship of the shift register units shown in FIG. 30 is different from the connection relationship of the shift register units shown in FIG. 28 only in that the shift register units shown in FIG. 30 also have the second clock.
  • the clock signal received by the second clock signal terminal CLKIN2 of the p-th stage shift register unit SRp is the second clock signal CLK2.
  • the clock signal received by the second clock signal terminal CLKIN2 of the p-th stage shift register unit SRp is the first clock signal CLK1, where p is greater than or equal to 1, less than or equal to N.
  • the connection manner of each shift register unit is as shown in FIG.
  • the connection relationship of the shift register units of the stages shown in FIG. 31 is different from the connection relationship of the shift register units shown in FIG. 28 only in that the shift register units of each stage shown in FIG. 28 need to receive the enable signal. EN, the shift register unit of each stage shown in FIG. 31 may not receive the enable signal EN.
  • the connection manner of each shift register unit is as shown in FIG.
  • the connection relationship between the shift register units shown in FIG. 32 is different from the connection relationship of the shift register units shown in FIG. 29 only in that the shift register units shown in FIG. 29 need to receive the enable signal. EN, the shift register unit of each stage shown in FIG. 32 may not receive the enable signal EN.
  • the embodiment of the present disclosure further provides a display device including the display panel provided by the embodiment of the present disclosure.
  • modules in the apparatus in the embodiments may be distributed in the apparatus of the embodiment according to the description of the embodiments, or the corresponding changes may be located in one or more apparatuses different from the embodiment.
  • the modules of the above embodiments may be combined into one module, or may be further split into multiple sub-modules.

Abstract

移位寄存单元包括锁存电路（21）和传输电路（22）。该锁存电路（21），在选择信号为高电平时，将其第一时钟信号端接收到的时钟信号与低电平信号经过或非运算后输出；并在选择信号的第一个低电平时段，将锁存电路（21）在选择信号为高电平时输出的信号进行非运算后得到的信号，与反馈信号进行或非运算后输出；以及在选择信号为低电平的时间段中除所述选择信号的第一个低电平时段以外的时间段，输出低电平信号。该传输电路（22），在锁存电路（21）输出为高电平时，输出与其第一时钟信号端接收到的时钟信号相关的信号；并在锁存电路（21）输出为低电平时，输出电平信号。

Description

一种移位寄存单元、显示面板和显示装置
相关申请的交叉参考
本申请主张在2014年10月29日在中国提交的中国专利申请号No.201410594095.4的优先权，其全部内容通过引用包含于此。
技术领域
本公开文本涉及显示技术领域，尤其涉及一种移位寄存单元、显示面板和显示装置。
背景技术
传统的低温多晶硅(LTPS，Low Temperature Poly-Silicon)移位寄存单元采用的是反相器、和传输门组成的D触发器。一个传统的LTPS移位寄存单元一般具有两个D触发器。LTPS移位寄存单元可以利用D触发器来锁存输出信号，并利用时钟信号来控制信号的传输和移位。
图1为传统的LTPS移位寄存单元的典型结构。在图1所示的LTPS移位寄存单元中，传输门TG1、与非门Nand1、反相器INV1和传输门TG2构成第一个D触发器，而传输门TG3、与非门Nand2、反相器INV2和传输门TG4构成第二个D触发器。在时钟信号CLK为低电平并且反相时钟信号CLKB为高电平以开启第一个D触发器之后，前一级移位寄存单元输出的信号进入第一个D触发器。此时，由于处于第二个D触发器前端的传输门TD3关闭，因此与非门Nand1输出的信号不能进入第二个D触发器。另一方面，在时钟信号CLK为高电平并且反相时钟信号CLKB为低电平以关闭第一个D触发器中的传输门TG1之后，第一个D触发器将上一个时钟内该D触发器的状态锁存。也就是说，当时钟信号CLK为高电平并且反相时钟信号CLKB为低电平时，第一个D触发器将第一个D触发器在时钟信号CLK为低电平和反相时钟信号CLKB为高电平时所输出的信号锁存。此时，第二个D触发器中的传输门TG3开启，第一个D触发器输出的信号进入第二个D触发器并输出该信号，由此信号实现了从前一级移位寄存单元到下一级移位寄存单元的 移位操作。当移位寄存单元工作时，复位信号RST为高电平。
但是对显示装置来说，每个移位寄存单元在一帧图像显示的时间内只会被使用一次。例如，一个显示装置中共有N行像素，在该显示装置中，一帧图像的显示时间为T秒，那么一个移位寄存单元在一帧图像显示的时间内只会被使用T/N秒。也就是说，在一帧图像显示的时间内，一个移位寄存单元的工作阶段只有T/N秒，而非工作阶段有T-T/N秒。也就是说，在一帧图像显示的时间内，一个移位寄存单元处于工作状态的时间只有T/N秒，而处于非工作状态的时间有T-T/N秒。
而传统移位寄存单元中的所有的传输门的开启和关闭都是由时钟信号CLK以及反相时钟信号CLKB来控制。即使在非工作阶段，时钟信号CLK和反相时钟信号CLKB仍然会开启和关闭传输门。而传输门是由互补的晶体管并联而成，当时钟信号CLK和反相时钟信号CLKB控制传输门开启和关闭时，时钟信号CLK和反相时钟信号CLKB需要加载在晶体管的栅极上。而晶体管的栅极下面是栅绝缘层，栅绝缘层下面是衬底，因此栅极和衬底之间会形成电容，所形成的电容被称为栅电容。这样，加载在晶体管的栅极上的信号在高电平时会对晶体管栅电容充电，而在低电平时会对栅电容放电，而在非工作阶段，这种充放电会造成无谓的电路功耗。而目前的显示装置一般都有成百乃至上千级移位寄存单元，而同一时间只有一级移位寄存单元电路在工作，其它移位寄存单元都处于非工作阶段。同时，时钟信号CLK和反相时钟信号CLKB都会加载到这些处于非工作阶段的移位寄存单元中的传输门上，因此会造成很大的无谓的功耗。
综上所述，由于互补反相的两个时钟信号在非工作阶段会控制传统的移位寄存单元中的传输门在开启和关闭之间切换，也就是在非工作阶段对传输门中的晶体管的栅电容进行充放电，这会造成很大的无谓的功耗。
发明内容
(一)要解决的技术问题
本公开文本实施例提供了一种移位寄存单元、显示面板和显示装置，用以解决现有的移位寄存单元由于需要采用互补反相的两个时钟信号来控制移 位寄存单元中的传输门在开启和关闭之间切换，这会导致移位寄存单元的非工作阶段对其中的传输门中的晶体管的栅电容进行充放电，从而造成很大的无谓的功耗的问题。
(二)技术方案
基于上述问题，本公开文本实施例提供的一种移位寄存单元，包括锁存电路和传输电路；
所述锁存电路，在选择信号为高电平时，将移位寄存单元的第一时钟信号端接收到的时钟信号与低电平信号经过或非运算后输出，其中在选择信号为高电平时，所述第一时钟信号端接收到的时钟信号为低电平；在选择信号的第一个低电平时段，将所述锁存电路在选择信号为高电平时输出的信号进行非运算后得到的信号，与反馈信号进行或非运算后输出；并且在选择信号为低电平的时间段中除所述选择信号的第一个低电平时段以外的时间段，输出低电平信号；
所述传输电路，在所述锁存电路输出的信号为高电平时，输出与所述第一时钟信号端接收到的时钟信号相关的信号；并且在锁存电路输出的信号为低电平时，输出电平信号；
其中，所述反馈信号能够使得所述锁存电路在所述选择信号为高电平的时段输出的信号和在所述选择信号的第一个低电平时段输出的信号相同；在所述选择信号的第一个低电平时段的结束时刻，所述反馈信号由低电平变为高电平；所述选择信号的第一个低电平时段是所述选择信号由高电平变为低电平的时刻，到所述移位寄存单元的下一级移位寄存单元输出的信号的电平由低电平跳变为高电平的时刻之间的时间段。
另外，根据本公开文本实施例提供的一种显示面板，包括多级本公开文本实施例提供的移位寄存单元。
另外，根据本公开文本实施例提供的一种显示装置，包括本公开文本实施例提供的显示面板。
(三)有益效果
本公开文本实施例至少具有如下有益效果：
本公开文本实施例提供的移位寄存单元、显示面板和显示装置，由于移 位寄存单元中的锁存电路在选择信号为高电平时，能够将第一时钟信号端接收到的时钟信号与低电平信号经过或非运算后输出高电平信号，并在选择信号的第一个低电平时段，维持选择信号为高电平时的锁存电路的状态。也就是说，锁存电路能够将选择信号为高电平时的状态的锁存，并由反馈信号来改变锁存电路的状态，并且由锁存电路输出的信号来控制传输电路输出的信号，从而实现移位寄存的功能。也就是说，根据本公开文本实施例提供的移位寄存单元由选择信号来控制移位寄存单元实现移位寄存的功能，这样可以避免采用互补反相的两个时钟信号来控制移位寄存单元中的传输门以实现移位功能，从而降低了移位寄存单元在非工作时段的无谓的功耗。
附图说明
为了更清楚地说明本公开文本实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开文本的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为传统的移位寄存单元的结构示意图；
图2为本公开文本实施例所提供的移位寄存单元的结构框图；
图3为本公开文本实施例所提供的移位寄存单元中的锁存电路的结构示意图之一；
图4为本公开文本实施例所提供的移位寄存单元中的锁存电路的结构示意图之二；
图5为本公开文本实施例所提供的移位寄存单元中的传输电路的结构示意图之一；
图6为本公开文本实施例所提供的移位寄存单元中的传输电路的结构示意图之二；
图7为本公开文本实施例所提供的移位寄存单元中的缓冲电路的结构示意图；
图8为本公开文本实施例所提供的移位寄存单元中的扫描方向选择电路的结构示意图；
图9为本公开文本实施例所提供的移位寄存单元的结构示意图之一；
图10为本公开文本实施例所提供的移位寄存单元的结构示意图之二；
图11为图9或图10所示的移位寄存单元正向扫描时的工作时序图；
图12为图9或图10所示的移位寄存单元反向扫描时的工作时序图；
图13为本公开文本实施例所提供的移位寄存单元的结构示意图之三；
图14为本公开文本实施例所提供的移位寄存单元的结构示意图之四；
图15为图13或图14所示的移位寄存单元正向扫描时的工作时序图；
图16为图13或图14所示的移位寄存单元反向扫描时的工作时序图；
图17为本公开文本实施例所提供的移位寄存单元的结构示意图之五；
图18为本公开文本实施例所提供的移位寄存单元的结构示意图之六；
图19为图17或图18所示的移位寄存单元正向扫描时的工作时序图；
图20为图17或图18所示的移位寄存单元反向扫描时的工作时序图；
图21为本公开文本实施例所提供的移位寄存单元的结构示意图之七；
图22为本公开文本实施例所提供的移位寄存单元的结构示意图之八；
图23为本公开文本实施例所提供的移位寄存单元的结构示意图之九；
图24为本公开文本实施例所提供的移位寄存单元的结构示意图之十；
图25为本公开文本实施例所提供的移位寄存单元的结构示意图之十一；
图26为本公开文本实施例所提供的移位寄存单元的结构示意图之十二；
图27为图9、图10、图13、图14中任一个所示的移位寄存单元级联时的连接关系的示意图之一；
图28为图9、图10、图13、图14中任一个所示的移位寄存单元级联时的连接关系的示意图之二；
图29为图17或图18所示的移位寄存单元级联时的连接关系的示意图之一；
图30为图17或图18所示的移位寄存单元级联时的连接关系的示意图之二；
图31为图21、图22、图23、图24中任一个所示的移位寄存单元级联时的连接关系的示意图；以及
图32为图25或图26所示的移位寄存单元级联时的连接关系的示意图。
具体实施方式
下面结合附图和实施例，对本公开文本的具体实施方式做进一步描述。以下实施例仅用于说明本公开文本，但不用来限制本公开文本的范围。
为使本公开文本实施例的目的、技术方案和优点更加清楚，下面将结合本公开文本实施例的附图，对本公开文本实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开文本的一部分实施例，而不是全部的实施例。基于所描述的本公开文本的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开文本保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开文本所属领域内具有一般技能的人士所理解的通常意义。本公开文本专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
根据本公开文本实施例提供的移位寄存单元、显示面板和显示装置，移位寄存单元中的锁存电路能够当锁存选择信号为高电平时锁存电路状态，并由反馈信号来改变锁存电路的状态，以及由锁存电路输出的信号来控制传输电路输出的信号，从而实现移位寄存的功能。这样可以避免由互补反相的两个时钟信号来控制移位寄存单元中的传输门以实现移位功能，从而降低移位寄存单元在非工作时段的无谓的功耗。
下面结合说明书附图，对本公开文本实施例提供的一种移位寄存单元、显示面板和显示装置的具体实施方式进行说明。
关于总体电路结构
本公开文本实施例提供的一种移位寄存单元，如图2所示，包括锁存电路21和传输电路22。
锁存电路21，在选择信号为高电平时，将移位寄存单元的第一时钟信号端接收到的时钟信号与低电平信号经过或非运算后输出。当选择信号为高电平时，所述第一时钟信号端接收到的时钟信号为低电平。此后，在选择信号的第一个低电平时段内，将所述锁存电路21在选择信号为高电平时输出的信号进行非运算后得到的信号，与反馈信号进行或非运算后输出。此外在选择信号为低电平的时间段当中除所述选择信号的第一个低电平时段以外的时间段内，输出低电平信号。
传输电路22，在所述锁存电路21输出的信号为高电平时，输出与所述第一时钟信号端接收到的时钟信号相关的信号；并在锁存电路21输出的信号为低电平时，输出电平信号。
具体的，所述反馈信号能够使得所述锁存电路21在所述选择信号为高电平的时段输出的信号和在所述选择信号的第一个低电平时段输出的信号相同；在所述选择信号的第一个低电平时段的结束时刻，所述反馈信号由低电平变为高电平；所述选择信号的第一个低电平时段是从所述选择信号由高电平变为低电平的时刻，到所述移位寄存单元的下一级移位寄存单元输出的信号由低电平跳变为高电平的时刻之间的时间段。
在正向扫描时，第k级移位寄存单元接收到的选择信号可以为第k-1级移位寄存单元输出的信号，此时，第k级移位寄存单元的下一级移位寄存单元为第k+1级移位寄存单元。与此相反，在反向扫描时，第k级移位寄存单元接收到的选择信号可以为第k+1级移位寄存单元输出的信号，此时，第k级移位寄存单元的下一级移位寄存单元为第k-1级移位寄存单元。在选择信号为高电平的时段和该选择信号的第一个低电平时段内，第k级移位寄存单元处于工作状态。
在选择信号为高电平的时段，由于选择信号为高电平，移位寄存单元的第一时钟信号端接收到的信号为低电平，锁存电路21输出的信号为高电平。此外，在选择信号的第一个低电平时段内，由于选择信号为低电平，移位寄存单元的第一时钟信号端接收到的信号为高电平，锁存电路21输出的信号依然为高电平。也就是说，在选择信号的第一个低电平时段，锁存电路21能够锁存其在选择信号为高电平时的状态。并且，在选择信号的第一个低电平时 段，锁存电路21会将锁存电路21在选择信号为高电平时输出的信号进行非运算后得到的信号与反馈信号进行或非运算后输出。因此，一旦反馈信号为高电平，锁存电路21输出的信号就会变为低电平。也就是说，在选择信号为低电平时，可以由反馈信号来改变锁存电路的输出的信号，这样，可以使移位寄存单元由工作状态进入非工作状态。而在选择信号的第一个低电平时段的结束时刻，反馈信号由低电平变为高电平，因此，在选择信号的第一个低电平时段的结束时刻，锁存电路输出的信号就会变为低电平。也就是说，在选择信号的第一个低电平时段的结束时刻，移位寄存单元由工作状态进入非工作状态。
在锁存电路21输出的信号为高电平时，传输电路22输出与移位寄存单元的第一时钟信号端接收到的时钟信号相关的信号。具体的，可以是在锁存电路21输出的信号为高电平时传输电路22输出与移位寄存单元的第一时钟信号端接收到的时钟信号相同的信号，也可以是在锁存电路21输出的信号为高电平时传输电路22输出与移位寄存单元的时钟信号端接收到的时钟信号反相的信号，从而使该移位寄存单元实现移位寄存的功能。在锁存电路21输出的信号为低电平时，传输电路22输出电平信号。具体的，可以是在锁存电路21输出的信号为低电平时传输电路22输出高电平信号，也可以是在锁存电路21输出的信号为低电平时传输电路22输出低电平信号，从而使该移位寄存单元进入非工作状态。
也就是说，本公开文本实施例提供的移位寄存单元采用选择信号来控制锁存电路在选择信号的第一个低电平时段锁存其在选择信号为高电平时的锁存电路的状态，并由锁存电路的状态来控制传输电路，从而使移位寄存单元实现移位寄存功能。此外，由选择信号为低电平时的反馈信号的电平的改变来改变锁存电路的状态，从而使移位寄存单元进入非工作状态。这样，无需采用互补反相的两个时钟信号来控制传输门使得移位寄存单元实现移位寄存功能，并使其进入非工作状态，从而降低了移位寄存单元在非工作阶段的无谓的功耗。
关于锁存电路的第一和第二实施例
可选地，如图3所示，锁存电路包括第一反相器INV1、三态反相器T_INV、 第一传输门TG1、第二传输门TG2、第一或非门Nor1和第一晶体管T1。
第一反相器INV1接收选择信号CHO，并将选择信号CHO经过非运算后输出。如果选择信号CHO为高电平，那么第一反相器INV1输出的信号为低电平。与此相反，如果选择信号CHO为低电平，那么第一反相器INV1输出的信号为高电平。
第一传输门TG1的低电平有效的控制端接收第一反相器INV1输出的信号，第一传输门TG1的高电平有效的控制端接收选择信号CHO，第一传输门TG1的输入端为所述移位寄存单元的的第一时钟信号端CLKIN1，第一传输门TG1在第一传输门TG1开启时将第一传输门TG1的输入端接收到的时钟信号输出。当选择信号CHO为高电平时，第一传输门TG1开启。与此相反，当选择信号CHO为低电平时，第一传输门TG1关闭。
第二传输门TG2的低电平有效的控制端接收选择信号CHO，第二传输门TG2的高电平有效的控制端接收第一反相器INV1输出的信号，第二传输门TG2接收反馈信号FB，并在第二传输门TG2开启时将反馈信号FB输出。当选择信号CHO为低电平时，第二传输门TG2开启。与此相反，当选择信号CHO为高电平时，第二传输门TG2关闭。
第一或非门Nor1的一个输入端分别连接第一传输门TG1的输出端和三态反相器T_INV的输出端，第一或非门Nor1的另一个输入端分别连接第二传输门TG2的输出端和第一晶体管T1的第一极，第一或非门Nor1输出的信号为锁存电路输出的信号OUT_Latch。这里，第一晶体管T1的第一极指的是第一晶体管T1的源极(SOURCE)或漏极(DRAIN)。其中，当第一晶体管T1的第一极为源极时，第一晶体管T1的第二极为漏极。当第一晶体管T1的第一极为漏极时，第一晶体管T1的第二极为源极。本领域技术人员能够理解的是，本公开文本并不以此为限。
三态反相器T_INV的低电平有效的控制端接收选择信号CHO，三态反相器T_INV的高电平有效的控制端接收第一反相器INV1输出的信号，三态反相器T_INV接收第一或非门Nor1输出的信号，并在选择信号CHO为低电平、且第一反相器INV1输出的信号为高电平时，将第一或非门Nor1输出的信号进行非运算后输出。如图3所示，当选择信号CHO为高电平时，三态反 相器T_INV为高阻态。与此相反，当选择信号CHO为低电平时，三态反相器T_INV开启，三态反相器T_INV将接收到的信号进行非运算后输出。
如图3所示，第一晶体管T1的栅极接收选择信号CHO，第一晶体管T1的漏极接收低电平信号VSS。当然，本领域技术人员能够理解的是，第一晶体管T1的漏极也可以接收选择信号CHO，第一晶体管T1的源极也可以接收低电平信号VSS，本公开文本并不以此为限。
在选择信号CHO为高电平的时段，选择信号CHO为高电平，移位寄存单元的第一时钟信号端CLKIN1接收到的信号为低电平，反馈信号FB为高电平，第一反相器INV1输出的信号为低电平。因此，第一传输门TG1开启，第二传输门TG2关闭，第一晶体管T1导通，三态反相器T_INV为高阻态。因此，第一或非门Nor1接收到的两个信号均为低电平，第一或非门Nor1输出的信号为高电平。
在选择信号CHO的第一个低电平时段，选择信号CHO为低电平，移位寄存单元的第一时钟信号端CLKIN1接收到的信号为高电平，反馈信号FB为低电平，第一反相器INV1输出的信号为高电平。因此，第一传输门TG1关闭，第二传输门TG2开启，第一晶体管T1关断，三态反相器T_INV开启，三态反相器T_INV将选择信号CHO为高电平时第一或非门Nor1输出的信号，即高电平信号进行非运算后，输出至第一或非门Nor1的一个输入端，由于第一晶体管T1关断，第二传输门TG2开启。因此，第一或非门Nor1的另一个输入端接收低电平的反馈信号FB。因此，在选择信号CHO的第一个低电平时段，第一或非门Nor1仍然输出高电平信号。
在选择信号CHO为高电平的时段和选择信号CHO的第一个低电平时段，锁存电路输出的信号均为高电平信号，传输电路输出的信号与移位寄存单元的第一时钟信号端接收到的时钟信号相关，移位寄存单元处于工作状态。
在选择信号CHO的第一个低电平时段结束后至选择信号CHO再次为高电平之前的时段，选择信号CHO一直为低电平。因此，第一传输门TG1关闭，第二传输门TG2开启，第一晶体管T1关断，三态反相器T_INV开启，一旦反馈信号FB为高电平，第一或非门Nor1接收到高电平信号，就会输出低电平信号，这会导致三态反相器T_INV输出高电平信号，从而使得锁存电 路保持在输出低电平信号的状态，直至选择信号CHO再次为高电平时，锁存电路输出的信号才会发生改变。
也就是说，在选择信号CHO的第一个低电平时段结束之后至选择信号CHO再次为高电平之前的时段，一旦反馈信号FB为高电平，锁存电路就由输出高电平信号的状态变为输出低电平信号的状态，而在锁存电路输出低电平信号时，传输电路输出的信号为电平信号，移位寄存单元处于非工作状态。而由于反馈信号FB在选择信号CHO的第一个低电平时段的结束时刻由低电平变为高电平，因此，移位寄存单元在选择信号CHO的第一个低电平时段的结束时刻由工作状态进入非工作状态。
可选地，作为图3所示的示例的变形例，如图4所示，锁存电路包括第二反相器INV2、第三反相器INV3、第三传输门TG3、第四传输门TG4、第五传输门TG5、第二或非门Nor2和第二晶体管T2。
第二反相器INV2接收选择信号CHO，并将选择信号CHO经过非运算后输出。如果选择信号CHO为高电平，那么第二反相器INV2输出的信号为低电平。与此相反，如果选择信号CHO为低电平，那么第二反相器INV2输出的信号为高电平。
第三传输门TG3的低电平有效的控制端接收第二反相器INV2输出的信号，第三传输门TG3的高电平有效的控制端接收选择信号CHO，第三传输门TG3的输入端连接移位寄存单元的第一时钟信号端CLKIN1，第三传输门TG3在第三传输门TG3开启时将第三传输门TG3的输入端接收到的时钟信号输出。当选择信号CHO为高电平时，第三传输门TG3开启。与此相反，当选择信号CHO为低电平时，第三传输门TG3关闭。
第四传输门TG4的低电平有效的控制端接收选择信号CHO，第四传输门TG4的高电平有效的控制端接收第二反相器INV2输出的信号，第四传输门TG4接收反馈信号FB，并在第四传输门TG4开启时将反馈信号FB输出。当选择信号CHO为低电平时，第四传输门TG4开启。与此相反，当选择信号CHO为高电平时，第四传输门TG4关闭。
第二或非门Nor2的一个输入端分别连接第三传输门TG3的输出端和第五传输门TG5的输出端，第二或非门Nor2的另一个输入端分别连接第四传 输门TG4的输出端和第二晶体管T2的第一极，第二或非门Nor2输出的信号为锁存电路输出的信号OUT_Latch。这里，第二晶体管T2的第一极指的是第二晶体管T2的源极或漏极。其中，当第二晶体管T2的第一极为源极时，第二晶体管T2的第二极为漏极。当第二晶体管T2的第一极为漏极时，第二晶体管T2的第二极为源极。本领域技术人员能够理解的是，本公开文本并不以此为限。
第三反相器INV3接收第二或非门Nor2输出的信号，并将第二或非门Nor2输出的信号进行非运算后输出。当第二或非门Nor2输出高电平信号时，第三反相器INV3输出低电平信号。与此相反，当第二或非门Nor2输出低电平信号时，第三反相器INV3输出高电平信号。
第五传输门TG5的低电平有效的控制端接收选择信号CHO，第五传输门TG5的高电平有效的控制端接收第二反相器INV2输出的信号，第五传输门TG5接收第三反相器INV3输出的信号，并在选择信号CHO为低电平时，将第三反相器INV3输出的信号输出。在选择信号CHO为低电平时，第五传输门TG5开启。与此相反，在选择信号CHO为高电平时，第五传输门TG5关闭。
如图4所示，第二晶体管T2的栅极接收选择信号CHO，第二晶体管T2的漏极接收低电平信号VSS。当然，本领域技术人员能够理解的是，第二晶体管T2的漏极也可以接收选择信号CHO，第二晶体管T2的源极也可以接收低电平信号VSS，本公开文本并不以此为限。
在选择信号CHO为高电平的时段，由于选择信号CHO为高电平，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为低电平，反馈信号FB为高电平，第二反相器INV2输出的信号为低电平，因此，第三传输门TG3开启，第四传输门TG4关闭，第五传输门TG5关闭，第二晶体管T2导通。因此，第二或非门Nor2接收到的两个信号均为低电平，第二或非门Nor2输出的信号为高电平。
在选择信号CHO的第一个低电平时段，选择信号CHO为低电平，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为高电平，反馈信号FB为低电平，第二反相器INV2输出的信号为高电平，因此，第三传输门TG3 关闭，第四传输门TG4开启，第五传输门TG5开启，第二晶体管T2关断，第三反相器INV3将选择信号CHO为高电平时第二或非门Nor2输出的信号，即高电平信号进行非运算后，通过第五传输门TG5输出至第二或非门Nor2的一个输入端，由于第二晶体管T2关断，第四传输门TG4开启，因此，第二或非门Nor2的另一个输入端接收低电平的反馈信号FB。因此，在选择信号CHO的第一个低电平时段，第二或非门Nor2仍然输出高电平信号。
在选择信号CHO为高电平的时段和选择信号CHO的第一个低电平时段，锁存电路输出的信号均为高电平信号，传输电路输出的信号与移位寄存单元的第一时钟信号端接收到的时钟信号相关，移位寄存单元处于工作状态。
在选择信号CHO的第一个低电平时段结束后至选择信号CHO再次为高电平之前的时段，选择信号CHO一直为低电平，因此，第三传输门TG3关闭，第四传输门TG4开启，第五传输门TG5开启，第二晶体管T2关断。一旦反馈信号FB为高电平，第二或非门Nor2接收到高电平信号，就会输出低电平信号，这会导致第三反相器INV3输出高电平信号，从而使得锁存电路保持在输出低电平信号的状态，直至选择信号CHO再次为高电平时，锁存电路输出的信号才会发生改变。
也就是说，在选择信号CHO的第一个低电平时段结束后至选择信号CHO再次为高电平之前的时段，一旦反馈信号FB为高电平，锁存电路就由输出高电平信号的状态变为输出低电平信号的状态，而在锁存电路输出低电平信号时，传输电路输出的信号为电平信号，移位寄存单元处于非工作状态。
关于传输电路的第三和第四实施例
可选地，如图5所示，传输电路包括第六传输门TG6、第三晶体管T3和第一与非门Nand1。
第六传输门TG6的高电平有效的控制端接收锁存电路输出的信号OUT_Latch，第六传输门TG6的低电平有效的控制端接收锁存电路输出的信号OUT_Latch经过非运算后的信号OUT_Latch_Inv，第六传输门TG6的输入端连接到所述移位寄存单元的第一时钟信号端CLKIN1，第六传输门TG6在锁存电路输出的信号OUT_Latch为高电平时将第六传输门TG6的输入端接收到的时钟信号输出。
第一与非门Nand1的一个输入端接收使能信号EN，第一与非门Nand的另一个输入端分别连接第六传输门TG6的输出端和第三晶体管T3的第一极，第一与非门Nand1输出的信号为传输电路输出的信号OUT_Trans。这里，使能信号EN在一帧图像显示的时间段内为高电平。
第三晶体管T3的栅极接收锁存电路输出的信号OUT_Latch经过非运算后的信号OUT_Latch_Inv，第三晶体管T3的第二极接收低电平信号VSS。其中，当第三晶体管T3的第一极为源极时，第三晶体管T3的第二极为漏极。与此相反，当第三晶体管T3的第一极为漏极时，第三晶体管T3的第二极为源极。
当锁存电路输出的信号OUT_Latch为高电平时，第六传输门TG6开启，第三晶体管T3关断，第六传输门TG6将其输入端接收到的时钟信号输出至第一与非门Nand1的一个输入端。此时，由于时能信号EN为高电平，若第六传输门TG6的输入端接收到的时钟信号为低电平，则第一与非门Nand1输出高电平信号。与此相反，若第六传输门TG6的输入端接收到的时钟信号为高电平，则第一与非门Nand1输出低电平信号。当锁存电路输出的信号OUT_Latch为低电平时，第六传输门TG6关闭，第三晶体管T3导通，因此，低电平信号VSS通过第三晶体管T3传输至第一与非门Nand1的一个输入端，此时，第一与非门Nand1输出高电平信号。
可选地，作为图5所示的示例的变形例，如图6所示，传输电路包括第二与非门Nand2。第二与非门Nand2的一个输入端接收锁存电路输出的信号OUT_Latch，第二与非门Nand2的另一个输入端连接移位寄存单元的第一时钟信号端CLKIN1，第二与非门Nand2输出的信号为传输电路输出的信号OUT_Trans。
当锁存电路输出的信号OUT_Latch为高电平时，第二与非门Nand2输出的信号为移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号进行非运算后的信号，即当移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为高电平时，第二与非门Nand2输出低电平信号。与此相反，当移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为低电平时，第二与非门Nand2输出高电平信号。
关于缓冲电路的第五实施例
为了增强移位寄存单元的驱动能力，作为一个可选示例，本公开文本实施例提供的移位寄存单元中还包括缓冲电路。缓冲电路接收传输电路输出的信号OUT_Trans，并将传输电路输出的信号OUT_Trans经过非运算后输出。也就是说，当传输电路输出的信号OUT_Trans为高电平时，缓冲电路输出的信号OUT_Buffer为低电平信号。当传输电路输出的信号OUT_Trans为低电平时，缓冲电路输出的信号OUT_Buffer为高电平信号。当本公开文本实施例提供的移位寄存单元中包括缓冲电路时，缓冲电路输出的信号OUT_Buffer为移位寄存单元输出的信号OUT。
可选地，如图7所示，缓冲电路包括2k+1个第四反相器INV4。2k+1个第四反相器INV4串联，串联后的第一个第四反相器INV4的输入端接收传输电路输出的信号OUT_Trans，除第一个第四反相器INV4以外的其它的第四反相器INV4中的前一个第四反相器INV4的输出端连接后一个第四反相器INV4的输入端，最后一个第四反相器INV4的输出端为缓冲电路的输出端。串联后的2k+1个第四反相器将传输电路输出的信号OUT_Trans经过非运算后输出，其中，k为非负整数。当k＝0时，缓冲电路仅包括一个第四反相器。
关于扫描方向选择电路的第六实施例
为了使移位寄存单元可以正向扫描，也可以反向扫描，本公开文本实施例提供的移位寄存单元中还包括扫描方向选择电路。扫描方向选择电路，在正向控制信号FS为高电平、且反向控制信号BS为低电平时，将正向选择信号输出CHOF，作为选择信号CHO。与此相反，在正向控制信号FS为低电平、且反向控制信号BS为高电平时，将反向选择信号CHOB输出，作为选择信号CHO。
可选地，如图8所示，扫描方向选择电路包括第七传输门TG7和第八传输门TG8。第七传输门TG7的高电平有效的控制端接收正向控制信号FS，第七传输门TG7的低电平有效的控制端接收反向控制信号BS，第七传输门TG7接收正向选择信号CHOF，并在正向控制信号FS为高电平、且反向控制信号BS为低电平时，将正向选择信号CHOF输出。另外，在正向控制信号FS为高电平、且反向控制信号BS为低电平时，第七传输门TG7开启。与此 相反，在正向控制信号FS为低电平、且反向控制信号BS为高电平时，第七传输门TG7关闭。
第八传输门TG8的高电平有效的控制端接收反向控制信号BS，第八传输门TG8的低电平有效的控制端接收正向控制信号FS，第八传输门TG8接收反向选择信号CHOB，并在正向控制信号FS为低电平、且反向控制信号BS为高电平时，将反向选择信号CHOB输出。另外，在正向控制信号FS为高电平、且反向控制信号BS为低电平时，第八传输门TG8关闭。与此相反，在正向控制信号FS为低电平、且反向控制信号BS为高电平时，第八传输门TG8开启。
本公开文本实施例提供的移位寄存单元的第一时钟信号端接收的时钟信号为第一时钟信号CLK1或者第二时钟信号CLK2。其中，第一时钟信号CLK1为高电平时，第二时钟信号CLK2为低电平。第二时钟信号CLK2为高电平时，第一时钟信号CLK1为低电平。
可选地，反馈信号FB为正向选择信号CHOF与反向选择信号CHOB进行或运算后得到的信号。正向选择信号CHOF为正向扫描时的选择信号CHO，反向选择信号CHOB为反向扫描时的选择信号CHO。
可选地，反馈信号FB为所述移位寄存单元第二时钟信号端CLKIN2接收到的时钟信号。当所述移位寄存单元的第一时钟端CLKIN1接收到的时钟信号为高电平时，所述移位寄存单元的第二时钟端CLKIN2接收到的时钟信号为低电平。此外，所述移位寄存单元的第二时钟端CLKIN2接收到的时钟信号为高电平时，所述移位寄存单元的第一时钟端CLKIN1接收到的时钟信号为低电平。因此，当移位寄存单元的第一时钟信号端CLKIN1接收到的信号为第一时钟信号CLK1时，反馈信号FB，即移位寄存单元的第二时钟信号端CLKIN2接收到的信号为第二时钟信号CLK2。当移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为第二时钟信号CLK2时，反馈信号FB，即移位寄存单元的第二时钟信号端CLKIN2接收到的时钟信号为第一时钟信号CLK1。
可选地，反馈信号FB为传输电路输出的信号OUT_Trans。
关于移位寄存单元的第七和第八实施例
当反馈信号FB为正向选择信号CHOF与反向选择信号CHOB进行或运算后得到的信号时，若本公开文本实施例提供的移位寄存单元包括锁存电路、传输电路，缓冲电路和扫描方向选择电路，并且锁存电路采用图3所示的结构，传输电路采用图5所示的结构，缓冲电路中仅包括一个第四反相器，扫描方向选择电路采用图8所示的结构，那么本公开文本实施例提供的移位寄存单元如图9所示。
当反馈信号FB为正向选择信号CHOF与反向选择信号CHOB进行或运算后得到的信号时，若本公开文本实施例提供的移位寄存单元包括锁存电路、传输电路，缓冲电路和扫描方向选择电路，并且锁存电路采用图4所示的结构，传输电路采用图5所示的结构，缓冲电路中仅包括一个第四反相器，扫描方向选择电路采用图8所示的结构，那么本公开文本实施例提供的移位寄存单元如图10所示。
图9和图10中的第三或非门Nor3和第五反相器INV5是为了将正向选择信号CHOF和反向选择信号CHOB进行或运算。以图9或图10所示的移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为第一时钟信号CLK1为例进行说明。当然，图9或图10所示的移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号也可以是第二时钟信号CLK2。
图9或图10所示的移位寄存单元在正向扫描时，正向控制信号FS为高电平，反向控制信号BS为低电平，因此，第七传输门TG7开启，第八传输门TG8关闭，正向选择信号CHOF作为选择信号CHO，移位寄存单元的工作时序图如图11所示。下面以图9或图10所示的移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为第一时钟信号CLK1为例进行说明，当然，图9或图10所示的移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号也可以是第二时钟信号CLK2。
在第1时段，即选择信号CHO、即正向选择信号CHOF为高电平的时段，锁存电路输出的信号OUT_Latch为高电平，因此，图9或图10中的第六传输门TG6开启，第三晶体管T3关断，因此，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号传输至第一与非门Nand1的一个输入端(第一与非门Nand1的该输入端的信号为Mid_OUT)。而在第1时段，移位寄存单 元的第一时钟信号端CLKIN1接收到的时钟信号为低电平，使能信号EN为高电平，因此，在第1时段，图9或图10所示的移位寄存单元输出的信号OUT为低电平。
在第2时段，即选择信号CHO、即正向选择信号CHOF为低电平的时段，锁存电路输出的信号OUT_Latch仍然为高电平，因此，图9或图10中的第六传输门TG6开启，第三晶体管T3关断，因此，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号传输至第一与非门Nand1的一个输入端。而在第2时段，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为高电平，使能信号EN为高电平，因此，在第2时段，图9或图10所示的移位寄存单元输出的信号OUT为高电平。
在由第2时段进入第3时段时，由于反向选择信号CHOB变为高电平，正向选择信号CHOF依然为低电平，因此，由正向选择信号CHOF和反向选择信号CHOB经过第三或非门Nor3和第五反相器INV5之后得到的信号由低电平变为高电平，这会使得锁存电路输出的信号OUT_Latch由高电平变为低电平。也就是说，在由第2时段进入第3时段时，由于反向选择信号CHOB由低电平变为高电平，这导致锁存电路输出的信号OUT_Latch由高电平变为低电平，从而使得图9或图10中的第六传输门TG6关闭、第三晶体管T3导通，低电平信号VSS传输至第一与非门Nand1的一个输入端。因此，在第3时段，第一与非门Nand1的一个输入端接收低电平信号VSS，第一与非门Nand1的另一个输入端接收使能信号EN，而在第3时段，使能信号EN为高电平。因此，在第3时段，图9或图10所示的移位寄存单元输出的信号OUT为低电平。
之后，图9或图10所示的移位寄存单元一直处于第3时段，直到正向选择信号CHOF再次为高电平时，图9或图10所示的移位寄存单元才能由第3时段进入第1时段。在第1时段和第2时段，图9和图10所示的移位寄存单元均处于工作状态，而在第3时段，图9和图10所示的移位寄存单元均处于非工作状态。
图9或图10所示的移位寄存单元在反向扫描时，反向控制信号BS为高电平，正向控制信号FS为低电平，因此，第七传输门TG7关闭，第八传输 门TG8开启，反向选择信号CHOB作为选择信号CHO，移位寄存单元的工作时序图如图12所示。图9或图10所示的移位寄存单元在反向扫描时，其中的锁存电路、传输电路和缓冲电路与该移位寄存单元在正向扫描时的情况完全相同，在此不再赘述。
采用图9或图10所示的移位寄存单元进行扫描时，完全不需要采用一对互补反相的时钟信号来控制传输门开启和关闭，并且，时钟信号也不会加载到逻辑门(或非门、与非门、反相器)的输入端，因此，在移位寄存单元处于非工作状态时，不会对栅电容进行充放电，这降低了移位寄存单元在非工作状态下的无谓的功耗。
关于移位寄存单元的第九和第十实施例
当反馈信号FB为传输电路输出的信号OUT_Trans时，若本公开文本实施例提供的移位寄存单元包括锁存电路、传输电路，缓冲电路和扫描方向选择电路，并且锁存电路采用图3所示的结构，传输电路采用图5所示的结构，缓冲电路中仅包括一个第四反相器，扫描方向选择电路采用图8所示的结构，那么本公开文本实施例提供的移位寄存单元如图13所示。
当反馈信号FB为传输电路输出的信号OUT_Trans时，若本公开文本实施例提供的移位寄存单元包括锁存电路、传输电路，缓冲电路和扫描方向选择电路，并且锁存电路采用图4所示的结构，传输电路采用图5所示的结构，缓冲电路中仅包括一个第四反相器，扫描方向选择电路采用图8所示的结构，那么本公开文本实施例提供的移位寄存单元如图14所示。
图13或图14所示的移位寄存单元在正向扫描时，正向控制信号FS为高电平，反向控制信号BS为低电平，因此，第七传输门TG7开启，第八传输门TG8关闭，正向选择信号CHOF作为选择信号CHO，移位寄存单元的工作时序图如图15所示。下面以图13或图14所示的移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为第一时钟信号CLK1为例进行说明，当然，图13或图14所示的移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号也可以是第二时钟信号CLK2。
在第1时段，即选择信号CHO、即正向选择信号CHOF为高电平的时段，锁存电路输出的信号OUT_Latch为高电平，因此，图13或图14中的第六传 输门TG6开启，第三晶体管T3关断，因此，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号传输至第一与非门Nand1的一个输入端(第一与非门Nand1的该输入端的信号为Mid_OUT)。而在第1时段，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为低电平，使能信号EN为高电平，因此，在第1时段，图13或图14所示的移位寄存单元输出的信号OUT为低电平。
在第2时段，即选择信号CHO、即正向选择信号CHOF为低电平的时段，锁存电路输出的信号OUT_Latch仍然为高电平，因此，图13或图14中的第六传输门TG6开启，第三晶体管T3关断，因此，移位寄存单元的第一时钟信号端CLKIN1接收到的信号传输至第一与非门Nand1的一个输入端。而在第2时段，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为高电平，使能信号EN为高电平，因此，在第2时段，图13或图14所示的移位寄存单元输出的信号OUT为高电平。
在由第2时段进入第3时段时，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号由高电平变为低电平，而第六传输门TG6和第三晶体管T3仍然保持第2时段时的状态，即第六传输门TG6开启，第三晶体管T3关断，因此，图13或图14所示的移位寄存单元输出的信号OUT由高电平变为低电平，也就是说传输电路输出的信号OUT_Trans，即第一与非门Nand1输出的信号由低电平变为高电平，也就是说反馈信号FB由低电平变为高电平，这会使得锁存电路输出的信号OUT_Latch由高电平变为低电平。也就是说，在由第2时段进入第3时段时，由于移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号由高电平变为低电平，这导致锁存电路输出的信号OUT_Latch由高电平变为低电平，从而使得图13或图14中的第六传输门TG6关闭、第三晶体管T3导通，低电平信号VSS传输至第一与非门Nand1的一个输入端，因此，在第3时段，第一与非门Nand1的一个输入端接收低电平信号VSS，第一与非门Nand1的另一个输入端接收使能信号EN。而在第3时段，使能信号EN为高电平，因此，在第3时段，图13或图14所示的移位寄存单元输出的信号OUT为低电平。
之后，图13或图14所示的移位寄存单元一直处于第3时段，直到正向 选择信号CHOF再次为高电平时，图13或图14所示的移位寄存单元才能由第3时段进入第1时段。在第1时段和第2时段，图13和图14所示的移位寄存单元均处于工作状态，而在第3时段，图13和图14所示的移位寄存单元均处于非工作状态。正向扫描时，反向选择信号CHOB不会对移位寄存单元中的各部分电路产生影响。
图13或图14所示的移位寄存单元在反向扫描时，反向控制信号BS为高电平，正向控制信号FS为低电平，因此，第七传输门TG7关闭，第八传输门TG8开启，反向选择信号CHOB作为选择信号CHO，移位寄存单元的工作时序图如图16所示。图13或图14所示的移位寄存单元在反向扫描时，其中的锁存电路、传输电路和缓冲电路与该移位寄存单元在正向扫描时的情况完全相同，在此不再赘述。反向扫描时，正向选择信号CHOF不会对移位寄存单元中的各部分电路产生影响。
采用图13或图14所示的移位寄存单元进行扫描时，完全不需要采用时钟信号CLK来控制传输门开启和关闭，并且，时钟信号也不会加载到逻辑门(或非门、与非门、反相器)的输入端，因此，在移位寄存单元处于非工作状态时，不会对栅电容进行充放电，这降低了移位寄存单元在非工作状态下的无谓的功耗。但是，当图13或图14所示的移位寄存单元在时钟信号的占空比小于50％时，会存在逻辑竞争的风险。
关于移位寄存单元的第十一和第十二实施例
当反馈信号FB为移位寄存单元的第二时钟信号端CLKIN2接收到的时钟信号时，若本公开文本实施例提供的移位寄存单元包括锁存电路、传输电路，缓冲电路和扫描方向选择电路，并且锁存电路采用图3所示的结构，传输电路采用图5所示的结构，缓冲电路中仅包括一个第四反相器，扫描方向选择电路采用图8所示的结构，那么本公开文本实施例提供的移位寄存单元如图17所示。
当反馈信号FB为移位寄存单元的第二时钟信号端CLKIN2接收到的时钟信号时，若本公开文本实施例提供的移位寄存单元包括锁存电路、传输电路，缓冲电路和扫描方向选择电路，并且锁存电路采用图4所示的结构，传输电路采用图5所示的结构，缓冲电路中仅包括一个第四反相器，扫描方向 选择电路采用图8所示的结构，那么本公开文本实施例提供的移位寄存单元如图18所示。
图17或图18所示的移位寄存单元在正向扫描时，正向控制信号FS为高电平，反向控制信号BS为低电平，因此，第七传输门TG7开启，第八传输门TG8关闭，正向选择信号CHOF作为选择信号CHO，移位寄存单元的工作时序图如图19所示。
在第1时段，即选择信号CHO、即正向选择信号CHOF为高电平的时段，锁存电路输出的信号OUT_Latch为高电平，因此，图17或图18中的第六传输门TG6开启，第三晶体管T3关断，因此，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号传输至第一与非门Nand1的一个输入端(第一与非门Nand1的该输入端的信号为Mid_OUT)。而在第1时段，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为低电平，使能信号EN为高电平，因此，在第1时段，图17或图18所示的移位寄存单元输出的信号OUT为低电平。
在第2时段，即选择信号CHO、即正向选择信号CHOF为低电平的时段，锁存电路输出的信号OUT_Latch仍然为高电平，因此，图17或图18中的第六传输门TG6开启，第三晶体管T3关断，因此，移位寄存单元的第一时钟信号端CLKIN1接收到的信号传输至第一与非门Nand的一个输入端。而在第2时段，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为高电平，使能信号EN为高电平，因此，在第2时段，图17或图18所示的移位寄存单元输出的信号OUT为高电平。
在由第2时段进入第3时段时，选择信号CHO、即正向选择信号CHOF为低电平，因此，第四传输门TG4开启，移位寄存单元的第二反相时钟信号端CLKIN2接收到的时钟信号由低电平变为高电平，这会使得锁存电路输出的信号OUT_Latch由高电平变为低电平，从而使得图17或图18中的第六传输门TG6关闭、第三晶体管T3导通，低电平信号VSS传输至第一与非门Nand1的一个输入端。因此，在第3时段，第一与非门Nand1的一个输入端接收低电平信号VSS，第一与非门Nand1的另一个输入端接收使能信号EN，而在第3时段，使能信号EN为高电平，因此，在第3时段，图17或图18 所示的移位寄存单元输出的信号OUT为低电平。
之后，图17或图18所示的移位寄存单元一直处于第3时段，直到正向选择信号CHOF再次为高电平时，图17或图18所示的移位寄存单元才能由第3时段进入第1时段。在第1时段和第2时段，图17和图18所示的移位寄存单元均处于工作状态，在第3时段，图17和图18所示的移位寄存单元均处于非工作状态。由于正向扫描时，反向选择信号CHOB不会对移位寄存单元中的各部分电路产生影响，因此，反向选择信号CHOB并未在图19中示出。
图17或图18所示的移位寄存单元在反向扫描时，反向控制信号BS为高电平，正向控制信号FS为低电平，因此，第七传输门TG7关闭，第八传输门TG8开启，反向选择信号CHOB作为选择信号CHO，移位寄存单元的工作时序图如图20所示。图17或图18所示的移位寄存单元在反向扫描时，其中的锁存电路、传输电路和缓冲电路与该移位寄存单元在正向扫描时的情况完全相同，在此不再赘述。反向扫描时，正向选择信号CHOF不会对移位寄存单元中的各部分电路产生影响。
采用图17或图18所示的移位寄存单元进行扫描时，移位寄存单元的第二时钟信号端CLKIN2接收到的时钟信号在移位寄存单元处于非工作状态时会加载到或非门的输入端，这也会对或非门中的栅电容进行充放电，但是该移位寄存单元完全不需要采用一对反相互补的时钟信号来控制传输门开启和关闭，因此，相比于传统的移位寄存单元在非工作状态下的功耗，该移位寄存单元在非工作状态下的无谓的功耗还是降低了。
关于移位寄存单元的第十三和第十四实施例
当反馈信号FB为正向选择信号CHOF与反向选择信号CHOB进行或运算后得到的信号时，若本公开文本实施例提供的移位寄存单元包括锁存电路、传输电路，缓冲电路和扫描方向选择电路，并且锁存电路采用图3所示的结构，传输电路采用图6所示的结构，缓冲电路中仅包括一个第四反相器，扫描方向选择电路采用图8所示的结构，那么本公开文本实施例提供的移位寄存单元如图21所示。
当反馈信号FB为正向选择信号CHOF与反向选择信号CHOB进行或运 算后得到的信号时，若本公开文本实施例提供的移位寄存单元包括锁存电路、传输电路，缓冲电路和扫描方向选择电路，并且锁存电路采用图4所示的结构，传输电路采用图6所示的结构，缓冲电路中仅包括一个第四反相器，扫描方向选择电路采用图8所示的结构，那么本公开文本实施例提供的移位寄存单元如图22所示。
图21或图22所示的移位寄存单元在正向扫描时，正向控制信号FS为高电平，反向控制信号BS为低电平，因此，第七传输门TG7开启，第八传输门TG8关闭，正向选择信号CHOF作为选择信号CHO，移位寄存单元的工作时序图如图11所示。下面以图21或图22所示的移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为第一时钟信号CLK1为例进行说明。当然，图21或图22所示的移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号也可以为第二时钟信号CLK2。
在第1时段，即选择信号CHO、即正向选择信号CHOF为高电平的时段，锁存电路输出的信号OUT_Latch为高电平，因此，图21或图22中的第二与非门Nand2的一个输入端为高电平。而在第1时段，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为低电平，因此，在第1时段，图21或图22所示的移位寄存单元输出的信号OUT为低电平。
在第2时段，即选择信号CHO、即正向选择信号CHOF为低电平的时段，锁存电路输出的信号OUT_Latch仍然为高电平，因此，图21或图22中的第二与非门Nand2的一个输入端为高电平。而在第2时段，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为高电平，因此，在第2时段，图21或图22所示的移位寄存单元输出的信号OUT为高电平。
在由第2时段进入第3时段时，由于反向选择信号CHOB变为高电平，正向选择信号CHOF依然为低电平，因此，由正向选择信号CHOF和反向选择信号CHOB经过第三或非门Nor3和第五反相器INV5之后得到的信号由低电平变为高电平，这会使得锁存电路输出的信号OUT_Latch由高电平变为低电平。也就是说，在由第2时段进入第3时段时，由于反向选择信号CHOB由低电平变为高电平，这导致锁存电路输出的信号OUT_Latch由高电平变为低电平，而在由第2时段进入第3时段时移位寄存单元的第一时钟信号端 CLKIN1接收到的时钟信号由高电平变为低电平，这使得图21或图22所示的移位寄存单元输出的信号OUT为由高电平变为低电平，因此，在第3时段，图21或图22所示的移位寄存单元输出的信号OUT为低电平。
之后，图21或图22所示的移位寄存单元一直处于第3时段，直到正向选择信号CHOF再次为高电平时，图21或图22所示的移位寄存单元才能由第3时段进入第1时段。在第1时段和第2时段，图21和图22所示的移位寄存单元均处于工作状态，而在第3时段，图21和图22所示的移位寄存单元均处于非工作状态。
图21或图22所示的移位寄存单元在反向扫描时，反向控制信号BS为高电平，正向控制信号FS为低电平，因此，第七传输门TG7关闭，第八传输门TG8开启，反向选择信号CHOB作为选择信号CHO，移位寄存单元的工作时序图如图12所示。图21或图22所示的移位寄存单元在反向扫描时，其中的锁存电路、传输电路和缓冲电路与该移位寄存单元在正向扫描时的情况完全相同，在此不再赘述。
采用图21或图22所示的移位寄存单元进行扫描时，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号在移位寄存单元处于非工作状态时会加载到与非门的输入端，这会对与非门中的栅电容进行充放电，但是该移位寄存单元完全不需要采用一对互补反相的时钟信号来控制传输门开启和关闭，因此，相比于传统的移位寄存单元在非工作状态下的功耗，该移位寄存单元在非工作状态下的无谓的功耗还是降低了。
关于移位寄存单元的第十五和第十六实施例
当反馈信号FB为传输电路输出的信号OUT_Trans时，若本公开文本实施例提供的移位寄存单元包括锁存电路、传输电路，缓冲电路和扫描方向选择电路，并且锁存电路采用图3所示的结构，传输电路采用图6所示的结构，缓冲电路中仅包括一个第四反相器，扫描方向选择电路采用图8所示的结构，那么本公开文本实施例提供的移位寄存单元如图23所示。
当反馈信号FB为传输电路输出的信号OUT_Trans时，若本公开文本实施例提供的移位寄存单元包括锁存电路、传输电路，缓冲电路和扫描方向选择电路，并且锁存电路采用图4所示的结构，传输电路采用图6所示的结构， 缓冲电路中仅包括一个第四反相器，扫描方向选择电路采用图8所示的结构，那么本公开文本实施例提供的移位寄存单元如图24所示。
图23或图24所示的移位寄存单元在正向扫描时，正向控制信号FS为高电平，反向控制信号BS为低电平，因此，第七传输门TG7开启，第八传输门TG8关闭，正向选择信号CHOF作为选择信号CHO，移位寄存单元的工作时序图如图15所示。下面以图23或图24所示的移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为第一时钟信号CLK1为例进行说明。当然，图23或图24所示的移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号也可以为第二时钟信号CLK2。
在第1时段，即选择信号CHO、即正向选择信号CHOF为高电平的时段，锁存电路输出的信号OUT_Latch为高电平，因此，图23或图24中的第二与非门Nand2的一个输入端为高电平。而在第1时段，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为低电平，因此，在第1时段，图23或图24所示的移位寄存单元输出的信号OUT为低电平。
在第2时段，即选择信号CHO、即正向选择信号CHOF为低电平的时段，锁存电路输出的信号OUT_Latch仍然为高电平，因此，图23或图24中的第二与非门Nand2的一个输入端为高电平。而在第2时段，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为高电平，因此，在第2时段，图23或图24所示的移位寄存单元输出的信号OUT为高电平。
在由第2时段进入第3时段时，移位寄存单元的地第一时钟信号端CLKIN1接收到的时钟信号由高电平变为低电平，锁存电路仍然保持第2时段时的状态，即锁存电路仍然输出高电平信号，因此，图23或图24所示的移位寄存单元输出的信号OUT由高电平变为低电平，也就是说传输电路输出的信号OUT_Trans，即第二与非门Nand2输出的信号由低电平变为高电平，也就是说反馈信号FB由低电平变为高电平，这会使得锁存电路输出的信号OUT_Latch由高电平变为低电平。也就是说，在由第2时段进入第3时段时，由于移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号由高电平变为低电平，这导致锁存电路输出的信号OUT_Latch由高电平变为低电平，从而使得图23或图24所示的移位寄存单元输出的信号OUT为由高电平变为低 电平，因此，在第3时段，图23或图24所示的移位寄存单元输出的信号OUT为低电平。
之后，图23或图24所示的移位寄存单元一直处于第3时段，直到正向选择信号CHOF再次为高电平时，图23或图24所示的移位寄存单元才能由第3时段进入第1时段。在第1时段和第2时段，图23和图24所示的移位寄存单元均处于工作状态，而在第3时段，图23和图24所示的移位寄存单元均处于非工作状态。
图23或图24所示的移位寄存单元在反向扫描时，反向控制信号BS为高电平，正向控制信号FS为低电平，因此，第七传输门TG7关闭，第八传输门TG8开启，反向选择信号CHOB作为选择信号CHO，移位寄存单元的工作时序图如图16所示。图23或图24所示的移位寄存单元在反向扫描时，其中的锁存电路、传输电路和缓冲电路与该移位寄存单元在正向扫描时的情况完全相同，在此不再赘述。
采用图23或图24所示的移位寄存单元进行扫描时，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号在移位寄存单元处于非工作状态时会加载到与非门的输入端，这会对与非门中的栅电容进行充放电，但是该移位寄存单元完全不需要采用一对互补反相的时钟信号来控制传输门开启和关闭，因此，相比于传统的移位寄存单元在非工作状态下的功耗，该移位寄存单元在非工作状态下的无谓的功耗还是降低了。但是，当图23或图24所示的移位寄存单元在时钟信号的占空比小于50％时，会存在逻辑竞争的风险。
关于移位寄存单元的第十七和第十八实施例
当反馈信号FB为移位寄存单元的第二时钟信号端CLKIN2接收到的时钟信号时，若本公开文本实施例提供的移位寄存单元包括锁存电路、传输电路，缓冲电路和扫描方向选择电路，并且锁存电路采用图3所示的结构，传输电路采用图6所示的结构，缓冲电路中仅包括一个第四反相器，扫描方向选择电路采用图8所示的结构，那么本公开文本实施例提供的移位寄存单元如图25所示。
当反馈信号FB为移位寄存单元的第二时钟信号端CLKIN2接收到的时钟信号时，若本公开文本实施例提供的移位寄存单元包括锁存电路、传输电 路，缓冲电路和扫描方向选择电路，并且锁存电路采用图4所示的结构，传输电路采用图6所示的结构，缓冲电路中仅包括一个第四反相器，扫描方向选择电路采用图8所示的结构，那么本公开文本实施例提供的移位寄存单元如图26所示。
图25或图26所示的移位寄存单元在正向扫描时，正向控制信号FS为高电平，反向控制信号BS为低电平，因此，第七传输门TG7开启，第八传输门TG8关闭，正向选择信号CHOF作为选择信号CHO，移位寄存单元的工作时序图如图19所示。
在第1时段，即选择信号CHO、即正向选择信号CHOF为高电平的时段，锁存电路输出的信号OUT_Latch为高电平，因此，图25或图26中的第二与非门Nand2的一个输入端为高电平。而在第1时段，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为低电平，因此，在第1时段，图25或图26所示的移位寄存单元输出的信号OUT为低电平。
在第2时段，即选择信号CHO、即正向选择信号CHOF为低电平的时段，锁存电路输出的信号OUT_Latch仍然为高电平，因此，图25或图26中的第二与非门Nand2的一个输入端为高电平。而在第2时段，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为高电平，因此，在第2时段，图25或图26所示的移位寄存单元输出的信号OUT为高电平。
在由第2时段进入第3时段时，选择信号CHO、即正向选择信号CHOF为低电平，因此，第四传输门TG4开启，移位寄存单元的第二时钟信号端CLKIN2接收到的时钟信号由低电平变为高电平，这会使得锁存电路输出的信号OUT_Latch由高电平变为低电平，从而使得图25或图26中的第二与非门Nand2的一个输入端接收低电平信号。而在第3时段，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号为低电平，因此，在第3时段，图25或图26所示的移位寄存单元输出的信号OUT为低电平。
图25或图26所示的移位寄存单元在反向扫描时，反向控制信号BS为高电平，正向控制信号FS为低电平，因此，第七传输门TG7关闭，第八传输门TG8开启，反向选择信号CHOB作为选择信号CHO，移位寄存单元的工作时序图如图20所示。图25或图26所示的移位寄存单元在反向扫描时， 其中的锁存电路、传输电路和缓冲电路与该移位寄存单元在正向扫描时的情况完全相同，在此不再赘述。
采用图25或图26所示的移位寄存单元进行扫描时，移位寄存单元的第二时钟信号端CLKIN2接收到的时钟信号在移位寄存单元处于非工作状态时会加载到或非门的输入端，这会对或非门中的栅电容进行充放电，移位寄存单元的第一时钟信号端CLKIN1接收到的时钟信号在移位寄存单元处于非工作状态时也会加载到与非门的输入端，这会对与非门中的栅电容进行充放电，但是该移位寄存单元完全不需要采用一对互补反相的时钟信号来控制传输门开启和关闭，因此，相比于传统的移位寄存单元在非工作状态下的功耗，该移位寄存单元在非工作状态下的无谓的功耗还是降低了。
关于显示面板的第十九和第二十实施例
本公开文本实施例提供的一种显示面板包括多级本公开文本实施例提供的移位寄存单元。
当显示面板中的移位寄存单元为图9、图10、图13或图14所示的移位寄存单元时，各级移位寄存单元的连接方式如图27或图28所示。
在图27所示的连接关系中，除第一级移位寄存单元SR1以外的第m级移位寄存单元SRm接收的正向选择信号CHOF为第m-1级移位寄存单元SRm-1中的传输电路中的第一与非门Nand1的一个输入端的信号Mid_OUT，其中m大于等于2，小于等于N。第一级移位寄存单元SR1接收的正向选择信号CHOF为初始触发信号STV。在图27所示的连接关系中，除第N级移位寄存单元SRN以外的第k级移位寄存单元SRk接收的反向选择信号CHOB为第k+1级移位寄存单元SRk+1中的传输电路中的第一与非门Nand1的一个输入端的信号Mid_OUT，其中k大于等于1，小于等于N-1。第N级移位寄存单元SR1接收的反向选择信号CHOB也为初始触发信号STV。在图27中，当p为奇数时，第p级移位寄存单元SRp的第一时钟信号端CLKIN1接收的时钟信号为第一时钟信号CLK1。当p为偶数时，第p级移位寄存单元SRp的第一时钟信号端CLKIN1接收的时钟信号为第二时钟信号CLK2，其中p大于等于1，小于等于N。图27中的各个移位寄存单元接收到的电源信号VDD是为移位寄存单元中的有源器件供电的。
在图28所示的连接关系中，除第一级移位寄存单元SR1以外的第m级移位寄存单元SRm接收的正向选择信号CHOF为第m-1级移位寄存单元SRm-1输出的信号OUT(m-1)，其中m大于等于2，小于等于N。第一级移位寄存单元SR1接收的正向选择信号CHOF为初始触发信号STV。在图28所示的连接关系中，除第N级移位寄存单元SRN以外的第k级移位寄存单元SRk接收的反向选择信号CHOB为第k+1级移位寄存单元SRk+1输出的信号OUT(k+1)，其中k大于等于1，小于等于N-1。第N级移位寄存单元SR1接收的反向选择信号CHOB也为初始触发信号STV。在图28中，当p为奇数时，第p级移位寄存单元SRp的第一时钟信号端CLKIN1接收的时钟信号为第一时钟信号CLK1。当p为偶数时，第p级移位寄存单元SRp的第一时钟信号端CLKIN1接收的时钟信号为第二时钟信号CLK2，其中p大于等于1，小于等于N。图28中的各个移位寄存单元接收到的电源信号VDD是为移位寄存单元中的有源器件供电的。
关于显示面板的第二十一和第二十二实施例
当显示面板中的移位寄存单元为图17或图18所示的移位寄存单元时，各级移位寄存单元的连接方式如图29或图30所示。图29所示的各级移位寄存单元的连接关系与图27所示的各级移位寄存单元的连接关系的区别仅在于：图29所示的各级移位寄存单元还具有第二时钟信号端CLKIN2。在图29中，当p为奇数时，第p级移位寄存单元SRp的第二时钟信号端CLKIN2接收的时钟信号为第二时钟信号CLK2。当p为偶数时，第p级移位寄存单元SRp的第二时钟信号端CLKIN2接收的时钟信号为第一时钟信号CLK1，其中p大于等于1，小于等于N。图30所示的各级移位寄存单元的连接关系与图28所示的各级移位寄存单元的连接关系的区别仅在于：图30所示的各级移位寄存单元还具有第二时钟信号端CLKIN2。在图30中，当p为奇数时，第p级移位寄存单元SRp的第二时钟信号端CLKIN2接收的时钟信号为第二时钟信号CLK2。当p为偶数时，第p级移位寄存单元SRp的第二时钟信号端CLKIN2接收的时钟信号为第一时钟信号CLK1，其中p大于等于1，小于等于N。
关于显示面板的第二十三和第二十四实施例
当显示面板中的移位寄存单元为图21、图22、图23或图24所示的移位寄存单元时，各级移位寄存单元的连接方式如图31所示。图31所示的各级移位寄存单元的连接关系与图28所示的各级移位寄存单元的连接关系的区别仅在于：图28所示的各级移位寄存单元需要接收使能信号EN，图31所示的各级移位寄存单元可以不用接收使能信号EN。
当显示面板中的移位寄存单元为图25或图26所示的移位寄存单元时，各级移位寄存单元的连接方式如图32所示。图32所示的各级移位寄存单元的连接关系与图29所示的各级移位寄存单元的连接关系的区别仅在于：图29所示的各级移位寄存单元需要接收使能信号EN，图32所示的各级移位寄存单元可以不用接收使能信号EN。
关于显示装置的第二十五实施例
本公开文本实施例还提供一种显示装置，包括本公开文本实施例提供的显示面板。
本领域技术人员可以理解附图只是一个优选实施例的示意图，附图中的模块或流程并不一定是实施本公开文本所必须的。
本领域技术人员可以理解实施例中的装置中的模块可以按照实施例描述进行分布于实施例的装置中，也可以进行相应变化位于不同于本实施例的一个或多个装置中。上述实施例的模块可以合并为一个模块，也可以进一步拆分成多个子模块。
上述本公开文本实施例序号仅仅为了描述，不代表实施例的优劣。
显然，本领域的技术人员可以对本公开文本进行各种改动和变型而不脱离本公开文本的精神和范围。这样，倘若本公开文本的这些修改和变型属于本公开文本权利要求及其等同技术的范围之内，则本公开文本也意图包含这些改动和变型在内。

Claims (14)

  1. 一种移位寄存单元，包括：
    锁存电路，在选择信号为高电平时，将移位寄存单元的第一时钟信号端接收到的时钟信号与低电平信号经过或非运算后输出，其中在选择信号为高电平时，所述第一时钟信号端接收到的时钟信号为低电平；在选择信号的第一个低电平时段内，将所述锁存电路在选择信号为高电平时输出的信号进行非运算后得到的信号，与反馈信号进行或非运算后输出；并且在选择信号为低电平的时间段中除所述选择信号的第一个低电平时段以外的时间段，输出低电平信号；以及
    传输电路，在所述锁存电路输出的信号为高电平时，输出与所述第一时钟信号端接收到的时钟信号相关的信号；并且在所述锁存电路输出的信号为低电平时，输出电平信号；
    其中，所述反馈信号能够使得所述锁存电路在所述选择信号为高电平的时段输出的信号和在所述选择信号的第一个低电平时段输出的信号相同；在所述选择信号的第一个低电平时段的结束时刻，所述反馈信号由低电平变为高电平；所述选择信号的第一个低电平时段是所述选择信号由高电平变为低电平的时刻，到所述移位寄存单元的下一级移位寄存单元输出的信号由低电平跳变为高电平的时刻之间的时间段。
  2. 如权利要求1所述的移位寄存单元，其中，所述锁存电路包括第一反相器、三态反相器、第一传输门、第二传输门、第一或非门和第一晶体管；
    所述第一反相器接收所述选择信号，并将所述选择信号经过非运算后输出；
    所述第一传输门的低电平有效的控制端接收所述第一反相器输出的信号，所述第一传输门的高电平有效的控制端接收所述选择信号，所述第一传输门的输入端为所述移位寄存单元的第一时钟信号端，所述第一传输门在所述第一传输门开启时将其输入端接收到的时钟信号输出；
    所述第二传输门的低电平有效的控制端接收所述选择信号，所述第二传输门的高电平有效的控制端接收所述第一反相器输出的信号，所述第二传输 门接收所述反馈信号，并在所述第二传输门开启时将所述反馈信号输出；
    所述第一或非门的一个输入端分别连接所述第一传输门的输出端和所述三态反相器的输出端，所述第一或非门的另一个输入端分别连接所述第二传输门的输出端和所述第一晶体管的第一极，所述第一或非门输出的信号为所述锁存电路输出的信号；
    所述三态反相器的低电平有效的控制端接收所述选择信号，所述三态反相器的高电平有效的控制端接收所述第一反相器输出的信号，所述三态反相器接收所述第一或非门输出的信号，并在所述选择信号为低电平、且所述第一反相器输出的信号为高电平时，将所述第一或非门输出的信号进行非运算后输出；并且
    所述第一晶体管的栅极接收所述选择信号，所述第一晶体管的第二极接收低电平信号。
  3. 如权利要求1所述的移位寄存单元，其中，所述锁存电路包括第二反相器、第三反相器、第三传输门、第四传输门、第五传输门、第二或非门和第二晶体管；
    所述第二反相器接收所述选择信号，并将所述选择信号经过非运算后输出；
    所述第三传输门的低电平有效的控制端接收所述第二反相器输出的信号，所述第三传输门的高电平有效的控制端接收所述选择信号，所述第三传输门的输入端为所述移位寄存单元的第一时钟信号端，所述第三传输门在所述第三传输门开启时将其输入端接收到的时钟信号输出；
    所述第四传输门的低电平有效的控制端接收所述选择信号，所述第四传输门的高电平有效的控制端接收所述第二反相器输出的信号，所述第四传输门接收所述反馈信号，并在所述第四传输门开启时将所述反馈信号输出；
    所述第二或非门的一个输入端分别连接所述第三传输门的输出端和所述第五传输门的输出端，所述第二或非门的另一个输入端分别连接所述第四传输门的输出端和所述第二晶体管的第一极，所述第二或非门输出的信号为所述锁存电路输出的信号；
    所述第三反相器接收所述第二或非门输出的信号，并将所述第二或非门 输出的信号进行非运算后输出；
    所述第五传输门的低电平有效的控制端接收所述选择信号，所述第五传输门的高电平有效的控制端接收所述第二反相器输出的信号，所述第五传输门接收所述第三反相器输出的信号，并在所述选择信号为低电平时，将所述第三反相器输出的信号输出；并且
    所述第二晶体管的栅极接收所述选择信号，所述第二晶体管的第二极接收低电平信号。
  4. 如权利要求1至3中任一项所述的移位寄存单元，其中，所述传输电路包括第六传输门、第三晶体管和第一与非门；
    所述第六传输门的高电平有效的控制端接收所述锁存电路输出的信号，所述第六传输门的低电平有效的控制端接收所述锁存电路输出的信号经过非运算后的信号，所述第六传输门的输入端连接所述移位寄存单元的第一时钟信号端，所述第六传输门在所述锁存电路输出的信号为高电平时将其输入端接收到的时钟信号输出；
    所述第一与非门的一个输入端接收使能信号，所述第一与非门的另一个输入端分别连接所述第六传输门的输出端和所述第三晶体管的第一极，所述第一与非门输出的信号为传输电路输出的信号；其中所述使能信号在一帧图像显示的时间段内为高电平；并且
    所述第三晶体管栅极接收所述锁存电路输出的信号经过非运算后的信号，所述第三晶体管的第二极接收低电平信号。
  5. 如权利要求1至3中任一项所述的移位寄存单元，其中，所述传输电路包括第二与非门；
    所述第二与非门的一个输入端接收所述锁存电路输出的信号，所述第二与非门的另一个输入端连接所述移位寄存单元的第一时钟信号端，所述第二与非门输出的信号为传输电路输出的信号。
  6. 如权利要求1至5中任一项所述的移位寄存单元，还包括缓冲电路；
    所述缓冲电路接收所述传输电路输出的信号，并将所述传输电路输出的信号经过非运算后输出。
  7. 如权利要求6所述的移位寄存单元，其中，所述缓冲电路包括奇数个 第四反相器；
    所述奇数个第四反相器串联，串联后的第一个第四反相器的输入端接收所述传输电路输出的信号，串联后的奇数个第四反相器将所述传输电路输出的信号经过非运算后输出。
  8. 如权利要求1至7中任一项所述的移位寄存单元，还包括扫描方向选择电路；
    所述扫描方向选择电路，在正向控制信号为高电平、且反向控制信号为低电平时，将正向选择信号输出，作为所述选择信号；并在正向控制信号为低电平、且反向控制信号为高电平时，将反向选择信号输出，作为所述选择信号。
  9. 如权利要求8所述的移位寄存单元，其中，所述扫描方向选择电路包括第七传输门和第八传输门；
    所述第七传输门的高电平有效的控制端接收正向控制信号，所述第七传输门的低电平有效的控制端接收反向控制信号，所述第七传输门接收正向选择信号，并在正向控制信号为高电平、且反向控制信号为低电平时，将正向选择信号输出；并且
    所述第八传输门的高电平有效的控制端接收反向控制信号，所述第八传输门的低电平有效的控制端接收正向控制信号，所述第八传输门接收反向选择信号，并在正向控制信号为低电平、且反向控制信号为高电平时，将反向选择信号输出。
  10. 如权利要求8或9所述的移位寄存单元，其中，所述反馈信号为正向选择信号与反向选择信号进行或运算后得到的信号；所述正向选择信号为正向扫描时的选择信号，所述反向选择信号为反向扫描时的选择信号。
  11. 如权利要求1至9中任一项所述的移位寄存单元，其中，所述反馈信号为所述移位寄存单元的第二时钟信号端接收到的时钟信号；
    所述移位寄存单元的第一时钟端接收到的时钟信号为高电平时，所述移位寄存单元的第二时钟端接收到的时钟信号为低电平；所述移位寄存单元的第二时钟端接收到的时钟信号为高电平时，所述移位寄存单元的第一时钟端接收到的时钟信号为低电平。
  12. 如权利要求1至9中任一项所述的移位寄存单元，其中，所述反馈信号为所述传输电路输出的信号。
  13. 一种显示面板，包括多级如权利要求1至12中任一项所述的移位寄存单元。
  14. 一种显示装置，包括如权利要求13所述的显示面板。
PCT/CN2015/073765 2014-10-29 2015-03-06 一种移位寄存单元、显示面板和显示装置 WO2016065785A1 (zh)

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