WO2016060014A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
WO2016060014A1
WO2016060014A1 PCT/JP2015/078336 JP2015078336W WO2016060014A1 WO 2016060014 A1 WO2016060014 A1 WO 2016060014A1 JP 2015078336 W JP2015078336 W JP 2015078336W WO 2016060014 A1 WO2016060014 A1 WO 2016060014A1
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Prior art keywords
gate electrode
memory
contact
side wall
selection gate
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PCT/JP2015/078336
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English (en)
French (fr)
Japanese (ja)
Inventor
谷口　泰弘
泰彦 川嶋
秀男 葛西
櫻井　良多郎
裕 品川
奥山　幸祐
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株式会社フローディア
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Application filed by 株式会社フローディア filed Critical 株式会社フローディア
Priority to JP2015560114A priority Critical patent/JP5956093B1/ja
Priority to CN201580054929.5A priority patent/CN107112237B/zh
Priority to SG11201703063YA priority patent/SG11201703063YA/en
Priority to KR1020177012617A priority patent/KR101824376B1/ko
Priority to TW104133915A priority patent/TWI610418B/zh
Publication of WO2016060014A1 publication Critical patent/WO2016060014A1/ja
Priority to IL251714A priority patent/IL251714B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H01L29/42344—Gate electrodes for transistors with charge trapping gate insulator with at least one additional gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof.
  • Non-Patent Document 1 As a semiconductor device provided with a plurality of contacts, for example, a memory gate structure in which a lower gate insulating film, a charge storage layer, an upper gate insulating film, and a memory gate electrode are sequentially stacked, and a sidewall of the memory gate structure are provided.
  • a selection gate structure provided via a side wall spacer is provided on an active region (on a substrate surface), and contacts are provided in each part.
  • a predetermined voltage is applied to various parts such as a memory gate electrode and a selection gate electrode of a selection gate structure from various wiring layers through contacts, so that the substrate surface and the memory gate Charges can be injected into the charge storage layer EC by a quantum tunnel effect caused by a voltage difference with the electrode G100.
  • the selection gate structure provided on the side wall of the memory gate structure via the sidewall spacer is applied with a predetermined voltage from the contact setting portion to the selection gate electrode separately from the memory gate electrode.
  • the selection gate electrode can be controlled independently of the memory gate electrode.
  • a contact placement portion integrally formed with a selection gate electrode (not shown) on an element isolation layer 101 adjacent to an active region (not shown). 102 may be provided.
  • the charge storage layer EC, the upper gate insulating film 23b, and the memory gate electrode G100 of the memory gate structure extend to the element isolation layer 101, and these charge storage layers EC,
  • a contact placement portion 102 may be formed on the sidewalls of the upper gate insulating film 23b and the memory gate electrode G100 via the sidewall spacer 105.
  • Each part such as the memory gate electrode G100 and the contact setting part 102 is covered with an interlayer insulating layer 120, and an upper wiring layer 112 is provided on another interlayer insulating layer 121 above the interlayer insulating layer 120. It has been.
  • a contact C100 is erected on a flat contact installation surface 102c, and is electrically connected to the upper wiring layer 112 by the contact C100.
  • the contact placement unit 102 can apply the voltage applied from the upper wiring layer 112 to the selection gate electrode formed in the active region.
  • the contact placement portion 102 and the upper wiring layer 112 are electrically connected by the contact C100, and, for example, an impurity formed on the active region even in an active region (not shown)
  • the diffusion region (not shown) and the other wiring layer 113 on the upper layer are electrically connected also by another contact C101.
  • another interlayer insulating layer 123 is generally formed on the interlayer insulating layer 121 provided with the wiring layers 112 and 113, and another wiring layer 114 is formed on the interlayer insulating layer 123.
  • the wiring layers 113 and 114 are electrically connected by the contact C102.
  • a voltage applied to the uppermost wiring layer 114 is applied to the contact C102, the wiring layer 113, and the contact C101 in order.
  • the side wall is manufactured.
  • the charge storage layer EC, the upper gate insulating film 23b, and the memory gate electrode G100 covered with the sidewall spacer 105 are also formed in the element isolation layer 101. To do.
  • a layered conductive layer is formed on the entire surface of the active region and the element isolation layer 101.
  • the conductive layer is etched back to form a sidewall-shaped selection gate electrode along the sidewall spacer 105 in the active region. Simultaneously with the formation, the conductive layer remains as it is in the resist formation region, and the contact placement portion 102 connected to the selection gate electrode can be formed in the element isolation layer 101.
  • the contact placement portion 102 formed in this way is formed with a base portion 102a having a flat contact placement surface 102c on which the contact C100 can be erected, and from the base portion 102a to the memory gate electrode G100.
  • a ride-up portion 102b that rides up to the top is formed. Therefore, in the semiconductor device 100, the thickness of the interlayer insulating layer 120 on which the memory gate electrode G100 and the contact setting portion 102 are disposed is increased by the amount of the rising portion 102b protruding upward from the top of the memory gate electrode G100. It needs to be thick.
  • the height of the contact C101 connecting the substrate surface of the memory well and the upper wiring layer 113 is increased by increasing the thickness of the interlayer insulating layer 120.
  • the aspect ratio (contact height / contact diameter) increases, and as a result, the contact resistance value increases.
  • the film thickness of the interlayer insulating layer 120 is reduced in order to reduce the aspect ratio in order to prevent an increase in the contact resistance value of the contact C101, the top of the contact installation portion 102 and the upper wiring
  • the distance between the layers 112 and 113 is shortened, and there is a risk that a contact failure may occur between the contact placement portion 102 to which a different voltage is applied and the upper wiring layer 113.
  • the present invention has been made in consideration of the above points, and proposes a semiconductor device that can prevent an increase in contact resistance value and also prevent a contact failure with a wiring layer, and a method of manufacturing the same. Objective.
  • a semiconductor device of the present invention includes a gate structure provided with a gate electrode and an isolation gate electrode formed of the same layer as the gate electrode, and is electrically isolated from the gate structure.
  • the contact mounting structure is formed on the side wall of the gate structure via a side wall spacer, and the side wall of the contact mounting structure is also formed on the side wall via the side wall spacer.
  • a sidewall-type gate electrode continuously provided from the gate structure to the contact installation structure, and standing up from the top of the contact installation structure to the sidewall spacer and the sidewall-type gate electrode. The contact is provided.
  • the method for manufacturing a semiconductor device includes a gate structure including a gate electrode and an isolation gate electrode formed of at least the same layer as the gate electrode, and is electrically isolated from the gate structure.
  • Side wall type gate electrode form to form side wall type gate electrode connected in a side wall shape via A step, characterized in that it comprises a contact forming step of forming a contact erected so as to straddle to said sidewall gate electrode from the top portion of the contact mounting structure.
  • the method for manufacturing a semiconductor device of the present invention is characterized in that the lower gate insulating film, the charge storage layer, the upper gate insulating film, and the memory gate electrode are stacked in this order on the substrate, and then patterned to form the lower gate insulating film.
  • the contact is provided so as to straddle from the top of the contact installation structure having the same configuration as the memory gate structure to the selection gate electrode, the top of the memory gate structure is conventionally provided. Since there is no climbing portion that has been climbed up to, the distance to the upper wiring layer can be shortened to reduce the aspect ratio, thus preventing an increase in contact resistance. In addition, the contact installation structure and the upper wiring layer can be kept away from each other by the absence of the climbing portion that has reached the top of the memory gate structure as in the prior art, thus preventing poor contact with the wiring layer. obtain.
  • FIG. 2 is a cross-sectional view showing a side cross-sectional configuration at the AA ′ portion in FIG. 1.
  • FIG. 2 is a cross-sectional view showing a side cross-sectional configuration at a BB ′ portion in FIG. 1.
  • 4A is a cross-sectional view showing a side cross-sectional configuration at a CC ′ portion in FIG. 1
  • FIG. 4B is a cross-sectional view showing a side cross-sectional configuration at a DD ′ portion in FIG.
  • FIG. 5A is a schematic diagram showing a semiconductor device manufacturing process (1)
  • FIG. 5B is a schematic diagram showing a semiconductor device manufacturing process (2)
  • FIG. 5C is a semiconductor device manufacturing process (3).
  • FIG. 6A is a schematic view showing a manufacturing process (4) of the semiconductor device
  • FIG. 6B is a schematic view showing a manufacturing process (5) of the semiconductor device
  • FIG. 6C is a manufacturing process (6) of the semiconductor device.
  • FIG. FIG. 7 is a cross-sectional view showing a side cross-sectional configuration at a DD ′ portion of FIG. 1 during a semiconductor device manufacturing process (4).
  • FIG. 8A is a schematic diagram showing a semiconductor device manufacturing process (7)
  • FIG. 8B is a schematic diagram showing a semiconductor device manufacturing process (8)
  • FIG. 8C is a semiconductor device manufacturing process (9).
  • FIG. FIG. 9A is a schematic diagram illustrating a semiconductor device manufacturing process (10), and FIG.
  • FIG. 9B is a schematic diagram illustrating a semiconductor device manufacturing process (11).
  • FIG. 2 is a schematic view showing a position where a selection gate electrode cut portion is to be formed by overlapping a selection gate electrode on the planar layout of FIG.
  • FIG. 11 is a cross-sectional view showing a side cross-sectional configuration at a DD ′ portion of FIG. 10.
  • 12A is a cross-sectional view illustrating a side cross-sectional configuration taken along the line AA ′ in FIG. 1 during the semiconductor device manufacturing process (12), and
  • FIG. 12B is a cross-sectional view illustrating the semiconductor device manufacturing process (12) in FIG.
  • FIG. 4 is a cross-sectional view showing a side cross-sectional configuration at a BB ′ portion of FIG. It is sectional drawing which shows the side cross-section structure of the conventional semiconductor device which has a contact installation part.
  • FIG. 1 is a schematic diagram showing a planar layout of a semiconductor device 1 according to the present invention, and a memory gate formed in a memory circuit region ER1. Structures 4a, 4b, first selection gate structures 5a, 5b, second selection gate structures 6a, 6b, contact installation structures 10a, 11a, 10b, 11b, and selection gate electrode cutting parts 13, 14, 15, The figure shows mainly the 16 plane layouts and the plane layouts of the logic gate structures 7a and 7b formed in the peripheral circuit region ER2.
  • FIG. 1 is a schematic diagram showing a planar layout of a semiconductor device 1 according to the present invention, and a memory gate formed in a memory circuit region ER1. Structures 4a, 4b, first selection gate structures 5a, 5b, second selection gate structures 6a, 6b, contact installation structures 10a, 11a, 10b, 11b, and selection gate electrode cutting parts 13, 14, 15, The figure shows mainly the 16 plane layouts and the plane layouts of the logic gate structures 7a and 7b formed in the peripheral circuit region
  • the present invention has a characteristic configuration in the contact installation structures 10a, 11a, 10b, and 11b.
  • a semiconductor device in which these contact installation structures 10a, 11a, 10b, and 11b are formed. 1 will be described in detail, and a specific configuration of the contact installation structures 10a, 11a, 10b, and 11b will be described in detail in “(1-2) Cross-sectional configuration of each part of the semiconductor device” later.
  • the semiconductor device 1 has a memory circuit region ER1 and a peripheral circuit region ER2 on a semiconductor substrate (not shown).
  • a P-type memory well W1 is formed in the memory circuit region ER1
  • a P-type logic well is formed in the peripheral circuit region ER2.
  • W2 and an N-type logic well W3 are formed in the peripheral circuit region ER2.
  • a memory cell region ER11 is provided between the gate contact / cut region ER12, ER13, and a plurality of memory cells 3a, 3b, 3c, 3d, 3e, 3f are provided in the memory cell region ER11.
  • a plurality of memory cells 3a, 3b, 3c, 3d, 3e, 3f are provided in the memory cell region ER11.
  • These memory cells 3a, 3b, 3c, 3d, 3e, and 3f all have the same configuration, here, mainly focusing on the memory cells 3a and 3b arranged in the AA ′ portion. This will be described below.
  • the memory cell 3a has a configuration in which the memory gate structure 4a is disposed between the first selection gate structure 5a and the second selection gate structure 6a via a sidewall spacer (not shown).
  • one memory gate structure 4a forming the memory cells 3a, 3c, 3e in the first column and another memory gate forming the other memory cells 3b, 3d, 3f in the second column
  • the structures 4b are formed in a straight line and are arranged so as to run parallel to each other.
  • a contact C4a (C4b) connected to a memory gate line (not shown) is provided upright from the memory gate line to the memory gate electrode G1a (G1b).
  • a predetermined memory gate voltage can be applied via the contact C4a (C4b).
  • a first selection gate structure 5a (5b) having a first selection gate electrode G2a (G2b) and a second selection gate structure 6a having a second selection gate electrode G3a (G3b) (6b) is formed in a straight line, and the first selection gate structure 5a (5b) and the second selection gate structure 6a (6b) run in parallel with the memory gate structure 4a (4b). Is arranged.
  • the first selection gate electrode G2a (G2b) and the second selection gate electrode G3a (G3b) are formed in a sidewall shape along the sidewall spacer of the sidewall of the memory gate electrode G1a (G1b), and the memory gate electrode G1a (G1b ) And a plurality of selection gate electrode cutting portions 13, 14 (15, 15) in which the first selection gate electrode G2a (G2b) and the second selection gate electrode G3a (G3b) are not formed. 16) Electrically separated by.
  • two source regions D1, D3 are formed symmetrically with a predetermined interval on the surface of the memory well W1 in the memory cell region ER11, and a plurality of drain regions D2 are formed between the source regions D1, D3. Is formed.
  • the memory cells 3a, 3c, 3e in the first column are arranged between the one source region D1 and the drain region D2, and the drain region D2 and the other source region D3
  • the memory cells 3b, 3d, 3f in the second column are arranged between them, and the memory cells 3a, 3c, 3e and the memory cells 3b, 3d, 3f are formed symmetrically with the drain region D2 as the center line. .
  • the memory gate structure 4a is disposed between the first selection gate structure 5a and the second selection gate structure 6a.
  • a memory gate is provided between the second selection gate structure 6b and the first selection gate structure 5b. The structure 4b is arranged.
  • one source region D1 formed on the surface of the memory well W1 is formed along one first selection gate structure 5a, and is aligned with the formation position of the memory cells 3a, 3c, 3e in the first column. Thus, it is formed up to a region adjacent to the first selection gate structure 5a, and is shared by a plurality of memory cells 3a, 3c, 3e arranged in a line.
  • a contact C1 connected to a source line (not shown) is erected in the source region D1, and a predetermined source voltage can be applied from the source line via the contact C1.
  • the plurality of drain regions D2 formed on the surface of the memory well W1 between the second selection gate structures 6a and 6b are aligned with the formation positions of the adjacent memory cells 3a and 3b (3c, 3d, 3e, and 3f).
  • the second select gate structures 6a and 6b are formed in adjacent regions, and the adjacent memory cells 3a and 3b (3c, 3d, 3e, and 3f) share one drain region D2.
  • a contact C2 connected to a bit line (not shown) is erected, and a predetermined bit voltage can be applied from the bit line via the contact C2.
  • the bit lines (not shown) are shared by the memory cells 3a, 3b (3c, 3d) (3e, 3f) arranged in the row direction in FIG. 1, and the memory cells 3a, 3b (3c, 3d) in each row are shared.
  • a predetermined bit voltage can be applied uniformly in units of rows with respect to (3e, 3f).
  • the other source region D3 formed on the surface of the memory well W1 is formed symmetrically with the one source region D1, and similarly to the one source region D1, another first selection gate structure 5b And is shared by the memory cells 3b, 3d, 3f in the second column.
  • this source region D3 a contact C3 is erected, and the same source line as that of one source region D1 is connected to the contact C3.
  • the same source voltage can be uniformly applied to the memory cells 3a, 3b, 3c, 3d, 3e, and 3f arranged in the memory cell region ER11 via the contacts C1 and C3.
  • One gate contact / cutting region ER12 adjacent to the memory cell region ER11 and another gate contact / cutting region ER13 adjacent to the memory cell region ER11 also include two memory gates running in parallel in the memory cell region ER11.
  • the electrodes G1a and G1b extend straight in parallel and run in parallel, and one end of the memory gate electrodes G1a and G1b is arranged in one gate contact / cutting region ER12, and the other gate contact / cutting region ER13
  • the other ends of the memory gate structures 4a and 4b can be arranged.
  • the gate contact / cut regions ER12 and ER13 will be described focusing on the first selection gate electrode G2a, the memory gate electrode G1a, and the second selection gate electrode G3a that constitute 3e.
  • a contact installation structure 10a that is separated from the memory gate electrode G1a and insulated from the memory gate electrode G1a is provided in one gate contact / cut region ER12.
  • the contact installation structure 10a is formed in a strip shape, and is arranged on the same straight line as the longitudinal direction of the memory gate electrode G1a.
  • a first selection gate electrode G2a extending from the memory cell region ER11 is formed in a quadrilateral shape, and the center surrounded by the first selection gate electrode G2a is formed.
  • the contact installation structure 10a is disposed in the region via the side wall spacer, and the first selection gate electrode G2a and the contact installation structure 10a are adjacent to each other through the side wall spacer.
  • a contact C5a is erected in a region extending from the contact installation structure 10a to the substrate surface across the side wall spacer and the first selection gate electrode G2a.
  • a predetermined first selection gate voltage can be applied to the first selection gate electrode G2a from the first selection gate line (not shown) via the contact C5a.
  • a part of the first selection gate electrode G2a formed in a quadrilateral shape and a linear second selection gate electrode extending from the memory cell region ER11 are provided.
  • a selection gate electrode cutting portion 13 is provided between the end of G3a.
  • the selection gate electrode cutting part 13 is arranged so that a part of the first selection gate electrode G2a formed in a quadrilateral shape and the end of the second selection gate electrode G3a are opposed to each other with a predetermined distance therebetween.
  • the gate electrode G2a and the second selection gate electrode G3a are electrically separated.
  • the selection gate electrode cutting unit 13 causes the first selection gate electrode G2a to 2 Voltage application to the select gate electrode G3a can be cut off.
  • the other gate contact / cut region ER13 is also provided with a contact installation structure 11a that is separated from the memory gate electrode G1a and insulated from the memory gate electrode G1a.
  • the contact installation structure 11a is also formed in a strip shape, like the one contact installation structure 10a described above, and is arranged on the same straight line as the longitudinal direction of the memory gate electrode G1a. .
  • a second selection gate electrode G3a extending from the memory cell region ER11 is formed in a quadrilateral shape, and a side wall is formed in the central region surrounded by the second selection gate electrode G3a.
  • a contact installation structure 11a is formed through a spacer, and the second selection gate electrode G3a and the contact installation structure 11a are adjacent to each other through a side wall spacer.
  • the contact C6a is erected in the region from the contact installation structure 11a to the substrate surface across the side wall spacer and the second selection gate electrode G3a.
  • a predetermined second selection gate voltage can be applied to the second selection gate electrode G3a from the second selection gate line (not shown) via the contact C6a.
  • a part of the second selection gate electrode G3a formed in a quadrilateral shape and the linear first selection gate electrode extending from the memory cell region ER11 are also formed in the other gate contact / cutting region ER13.
  • a selection gate electrode cutting portion 14 is provided between the end of G2a.
  • the selection gate electrode cutting unit 14 causes the second selection gate electrode G3a to 1 Voltage application to the select gate electrode G2a can be cut off.
  • the contact installation structure 10a and the first selection gate electrode G2a connected to one contact C5a, and the contact installation structure 11a and the second selection gate electrode G3a connected to the other contact C6a Are electrically separated by the selection gate electrode cutting portions 13 and 14, and the first selection gate electrode G2a and the second selection gate electrode G3a are configured to be independently controllable.
  • the second selection gate electrode G3b, the memory gate electrode G1b, and the first selection gate electrode G2b on the second column side of the gate contact / cut regions ER12 and ER13 are the first selection gate electrode G2a on the first column side described above. It has the same configuration as the structure 5a, the memory gate electrode G1a, and the second selection gate electrode G3a, and is provided with contact installation structures 10b and 11b and selection gate electrode cutting portions 15 and 16 as in the first column. ing.
  • the second selection gate electrode G3b in the second column is arranged adjacent to the second selection gate electrode G3a in the first column, and the first selection gate electrode G2b and the second selection gate The gate electrode G3b is arranged upside down.
  • the contact installation structure 11b to which the contact C6b for applying a voltage to the second selection gate electrode G3b in the second column is connected is disposed in one gate contact / cutting region ER12, while the first column in the second column
  • the contact installation structure 10b to which the contact C5b for applying a voltage to the selection gate electrode G2b is connected is arranged in another gate contact / cutting region ER13.
  • the second selection gate electrode G3b, the memory gate electrode G1b, and the first selection gate electrode G2b are also connected to the contact installation structure 10b and the first selection gate electrode G2b connected to one contact C5b and the other contact C6b.
  • the connected contact installation structure 11b and the second selection gate electrode G3b are separated and electrically separated by the selection gate electrode cutting portions 15 and 16, and the first selection gate electrode G2b and the second selection gate electrode G3b Are configured to be independently controllable.
  • the peripheral circuit region ER2 adjacent to the memory circuit region ER1 having such a configuration will be described below.
  • the peripheral circuit region ER2 is disposed at a position adjacent to the memory cell region ER11 in the memory circuit region ER1, but the present invention is not limited to this, and one gate contact / cutting is performed. It may be provided at various positions such as a position adjacent to the region ER12, a position adjacent to another gate contact / cutting region ER13, or a position adjacent to between the memory cell region ER11 and the gate contact / cutting region ER12. .
  • the peripheral circuit 18 has, for example, an N-type MOS (Metal-Oxide-Semiconductor) transistor structure formed in a P-type logic well W2.
  • a logic gate structure 7a is formed in the logic well W2, and a predetermined logic gate voltage can be applied to the logic gate structure 7a via the contact C8.
  • impurity diffusion regions D4 and D5 are formed in a region adjacent to the logic gate structure 7a so as to sandwich the logic gate structure 7a, and a contact C9 is formed in one impurity diffusion region D4.
  • the other contact C10 is erected in the other impurity diffusion region D5.
  • the other peripheral circuit 19 has, for example, a P-type MOS transistor structure formed in an N-type logic well W3.
  • a logic gate structure 7b is formed in the logic well W3, and a predetermined logic gate voltage can be applied to the logic gate structure 7b via the contact C12.
  • impurity diffusion regions D6 and D7 are formed in a region adjacent to the logic gate structure 7b so as to sandwich the logic gate structure 7b, and a contact C13 is formed in one impurity diffusion region D6.
  • the other contact C14 is erected in the other impurity diffusion region D7.
  • FIG. 2 is a side cross-sectional configuration of the AA ′ portion of FIG. 1, and the memory cells 3a and 3b provided in the memory cell region ER11 and the peripheral circuit region ER2 2 is a cross-sectional view showing a side cross-sectional configuration of provided peripheral circuits 18 and 19.
  • the semiconductor device 1 is provided with the semiconductor substrate S, the memory well W1 is formed on the semiconductor substrate S in the memory circuit region ER1, and the logic wells W2, W3 are formed on the semiconductor substrate S in the peripheral circuit region ER2. Is formed.
  • two memory cells 3a and 3b are arranged in the AA ′ portion, and a drain in which a contact C2 is erected on the substrate surface between the memory cells 3a and 3b. Region D2 is formed.
  • the memory cells 3a and 3b are formed symmetrically, since they have the same configuration, the following description will be given focusing on one memory cell 3a.
  • the memory cell 3a includes, for example, a memory gate structure 4a that forms an N-type transistor structure, a first selection gate structure 5a that forms an N-type MOS transistor structure, and a first that forms an N-type MOS transistor structure.
  • a two-select gate structure 6a is formed in the memory well W1.
  • a source region D1 and a drain region D2 are formed at a predetermined distance on the surface of the memory well W1, and the source voltage from the source line is applied to the source region D1 via the contact C1 (FIG. 1).
  • the bit voltage from the bit line can be applied to the drain region D2 via the contact C2.
  • the source region D1 and the drain region D2 are selected to have an impurity concentration of 1.0E21 / cm 3 or more, while the memory well W1 is formed by impurity implantation performed in the manufacturing process.
  • surface region where a channel layer is formed e.g., region from the surface to 50 [nm]
  • impurity concentration of 1.0E19 / cm 3 or less preferably is selected to be 3.0E18 / cm 3 or less.
  • the memory gate structure 4a is formed on the memory well W1 between the source region D1 and the drain region D2 via a lower gate insulating film 23a made of an insulating member such as SiO 2 , for example, silicon nitride (Si 3 N 4 ), It has a charge storage layer EC made of silicon oxynitride (SiON), alumina (Al 2 O 3 ), etc., and further on the charge storage layer EC via an upper gate insulating film 23b also made of an insulating member.
  • a memory gate electrode G1a is provided.
  • the memory gate structure 4a has a configuration in which the charge storage layer EC is insulated from the memory well W1 and the memory gate electrode G1a by the lower gate insulating film 23a and the upper gate insulating film 23b.
  • a side wall spacer 27a made of an insulating member is formed along the side wall of the memory gate structure 4a, and the first selection gate structure 5a is adjacent to the memory gate structure 4a via the side wall spacer 27a.
  • the sidewall spacer 27a formed between the memory gate structure 4a and the first selection gate structure 5a is formed with a predetermined thickness, and the memory gate structure 4a and the first selection gate structure
  • the body 5a can be insulated.
  • the first selection gate structure 5a is an insulating member on the memory well W1 between the side wall spacer 27a and the source region D1, and has a thickness of 9 [nm] or less, preferably 3 [nm] or less.
  • a gate insulating film 25a is formed, and a first selection gate electrode G2a to which the first selection gate line is connected is formed on the gate insulating film 25a.
  • a side wall spacer 27a made of an insulating member is also formed on the other side wall of the memory gate structure 4a, and the second select gate structure 6a is adjacent to the side wall spacer 27a.
  • the sidewall spacer 27a formed between the memory gate structure 4a and the second selection gate structure 6a is also the same film as the sidewall spacer 27a between the memory gate structure 4a and the first selection gate structure 5a.
  • the memory gate structure 4a and the second selection gate structure 6a can be insulated from each other.
  • the second selection gate structure 6a is made of an insulating member on the memory well W1 between the sidewall spacer 27a and the drain region D2, and has a thickness of 9 [nm] or less, preferably 3 [nm] or less.
  • a gate insulating film 25b is formed, and a second selection gate electrode G3a to which the second selection gate line is connected is formed on the gate insulating film 25b.
  • the first selection gate electrode G2a and the second selection gate electrode G3a formed along the side wall of the memory gate electrode G1a via the side wall spacer 27a are formed by etching back the conductive layer in the manufacturing process described later. Since it is formed, the top is formed in a side wall shape that descends toward the memory well W1 as the distance from the memory gate electrode G1a increases.
  • a sidewall SW formed of an insulating member is formed on the sidewall of the first selection gate structure 5a and the sidewall of the second selection gate structure 6a, and the surface of the memory well W1 below the one sidewall SW
  • the extension region D1a is formed on the surface of the memory well W1 below the other sidewall SW.
  • the impurity concentration in the region from the surface to 50 [nm] of the memory well W1 between the first selection gate electrode G2a and the second selection gate electrode G3a is 1E19 / cm 3 or less.
  • the film thicknesses of the gate insulating films 25a and 25b can be formed to 9 [nm] or less by a subsequent manufacturing process. If the impurity concentration in the region from the surface to 50 [nm] of the memory well W1 between the first selection gate electrode G2a and the second selection gate electrode G3a is 3E18 / cm 3 or less, According to the manufacturing process, each film thickness of the gate insulating films 25a and 25b can be formed to 3 [nm] or less.
  • the other memory cell 3b has the same configuration as the one memory cell 3a, and the first selection gate structure 5b and the second selection are formed on the memory well W1 between the other source region D3 and the drain region D2.
  • a gate structure 6b is provided, and a memory gate structure 4b is formed between the first selection gate structure 5b and the second selection gate structure 6b via a sidewall spacer 27a.
  • sidewalls SW are formed on the opposing side walls of the first selection gate structure 5b, and extension regions D3a and D2b are formed on the surface of the memory well W1 below the sidewall SW.
  • the memory well W1 formed in the memory circuit region ER1 and the one logic well W2 formed in the peripheral circuit region ER2 are electrically separated by one element isolation layer 20, and further formed in the peripheral circuit region ER2.
  • the one logic well W2 and the other logic well W3 are also electrically separated by another element isolation layer 20.
  • a peripheral circuit 18 having an N-type MOS transistor structure is formed in one logic well W2, and a P-type MOS transistor structure is formed in the other logic well W3.
  • the peripheral circuit 19 is formed.
  • one logic well W2 is provided with a logic gate structure 7a in which a logic gate electrode G5 is formed via a gate insulating film 29a between a pair of impurity diffusion regions D4 and D5 formed on the substrate surface. It has been. Note that sidewalls SW are formed on the side walls of the logic gate structure 7a, and extension regions D4a and D5a are formed on the substrate surface below each sidewall SW.
  • another logic well W3 having a conductivity type different from that of one logic well W2 has the same configuration as that of the one logic well W2, and between the pair of impurity diffusion regions D6 and D7 formed on the substrate surface.
  • a logic gate structure 7b in which a logic gate electrode G6 is formed is provided via a gate insulating film 29b. Note that a sidewall SW is formed on the side wall of the logic gate structure 7b, and extension regions D6a and D7a are formed on the substrate surface below each sidewall SW.
  • the first select gate structures 5a, 5b, the memory gate structures 4a, 4b, the second select gate structures 6a, 6b, the contact C2, the logic gate structures 7a, 7b, etc. are interlayer-insulated. Covered by the layer 21, each part is insulated from each other. Further, for example, the surfaces of various other parts such as the source regions D1 and D3 and the drain region D2 are covered with the silicide SC.
  • FIG. 3 is a side cross-sectional configuration of the BB ′ portion of FIG. 1, and is a cross-sectional view showing a side cross-sectional configuration of the selection gate electrode cutting portions 13 and 15 in the gate contact / cutting region ER12 of the memory circuit region ER1. is there.
  • the select gate electrode cutting portions 13 and 15 are formed on the element isolation layer 20 formed in the memory well W1.
  • the second select gate electrode G3b having a sidewall shape is formed on one side wall of the memory gate structure 4b via the side wall spacer 27a, but the memory On the other side wall of the gate structure 4b, the first selection gate electrode G2b and the second selection gate electrode G3b are not formed, but only an insulating wall 27b made of a side wall spacer or a side wall is formed.
  • the sidewall-shaped first selection gate is provided on one side wall of the memory gate structure 4a via the side wall spacer 27a.
  • the electrode G2a is formed, the first selection gate electrode G2a and the second selection gate electrode G3a are not formed on the other side wall of the memory gate structure 4a, and the insulating film is formed of a side wall spacer or a side wall. Only the wall 27b is formed.
  • the select gate electrode cutting parts 13 and 15 are formed, a part of the substrate surface is shaved during the manufacturing process, so that a recess 30 is formed on the surface of the element isolation layer 20.
  • contact installation structures 10a, 11a, 10b, and 11b having the characteristic configuration of the present invention will be described below.
  • These contact installation structures 10a, 11a, 10b, and 11b all have the same configuration. For this reason, the following description will focus on the contact installation structure 10a.
  • 4A is a cross-sectional side view of the CC ′ portion of FIG. 1, showing a side cross-sectional configuration of one contact installation structure 10a formed in the gate contact / cutting region ER12 of the memory circuit region ER1.
  • 4B is a cross-sectional view showing a side cross-sectional configuration of the contact installation structure 10a at a DD ′ portion orthogonal to the CC ′ portion of FIG.
  • the contact installation structure 10a is formed on the substrate surface of the element isolation layer 20 formed in the memory well W1, and the charge storage layer EC constituting the memory gate structure 4a.
  • the upper gate insulating film 23b and the memory gate electrode (isolation memory gate electrode) G8a formed of the same layer as the memory gate electrode G1a are sequentially stacked.
  • the contact installation structure 10a has the same charge storage layer EC, upper gate insulating film 23b, and memory gate electrode G8a as the memory gate structure 4a, but a large voltage is generated below the memory gate electrode G8a. The quantum tunnel effect caused by the difference does not occur, and charge cannot be injected into the charge storage layer EC.
  • the charge storage layer EC, the upper gate insulating film 23b, and the memory gate electrode G8a that form the contact installation structure 10a are the charge storage layer EC, the upper gate that forms the memory gate structure 4a. Since the insulating film 23b and the memory gate electrode G1a are the same layer, each film thickness can be the same as that of the memory gate structure 4a.
  • a sidewall-shaped first selection gate electrode G2a is formed along a sidewall spacer 27c formed on the sidewall, and the memory gate electrode G8a
  • a contact C5a is erected in a region extending from a part of the flat top to one substrate spacer 27c and the first selection gate electrode G2a to the substrate surface.
  • the contact C5a is partly erected on the top of the flat memory gate electrode G8a and partly erected on the substrate surface of the flat element isolation layer 20. Can be installed.
  • the contact C5a is formed so as to straddle the first selection gate electrode G2a from the memory gate electrode G8a of the contact installation structure 10a to the element isolation layer 20, for example, the contact C5a is formed by a photolithography process. At this time, even if misalignment occurs with respect to the first selection gate electrode G2a, the contact C5a can always be brought into contact with the surface of the first selection gate electrode G2a. Thus, the contact installation structure 10a can be electrically connected to the first selection gate electrode G2a, and the electrical resistance can be stabilized without being affected by the photolithography process.
  • the contact installation structure 10a does not have a rising portion that rides on the top of the memory gate electrode as in the prior art, and has the same charge storage layer EC, upper gate insulating film 23b, and memory gate as the memory gate structure 4a. Since it is composed of the layer of the electrode G8a, it is kept at substantially the same height as the memory gate structure 4a, and further, a side wall-like shape formed along the side wall spacer 27a on the side wall of the memory gate structure 4a.
  • the first select gate electrode G2a and the upper wiring layer (not shown) can be reliably connected by the contact C5a.
  • the distance from the substrate surface to the upper wiring layer can be selected based on the height of the memory gate structure 4a, and the top of the memory gate electrode as in the conventional case. Therefore, the thickness of the interlayer insulating layer 21 can be reduced by the amount that does not include the rising portion that runs on the substrate, and the aspect ratio of the contact extending from the substrate surface to the upper wiring layer can be prevented from increasing.
  • the side wall spacer 27a formed along the side wall at the end of the memory gate electrode G1a and the side wall spacer 27c formed along the side wall at the end of the contact installation structure 10a are arranged to face each other. Also in the region GP1, the first selection gate electrode G2a is formed without a gap. Thus, the first selection gate electrode G2a can be connected to the first selection gate electrode G2a from the contact installation structure 10a to the memory gate electrode G1a.
  • the memory gate electrode G1a and the side wall spacer 27a are adjacent to each other.
  • a first selection gate voltage may be applied to the sidewall-shaped first selection gate electrode G2a.
  • the conductive layer is etched back during the manufacturing process. Since the first selection gate electrode G2a is formed, the first selection gate electrode G2a is located near the center between the side wall spacers 27a and 27c, which is farthest from the opposing side wall spacers 27a and 27c. Can be formed to be the thinnest.
  • the side wall spacers 27a and 27c go to the vicinity of the center between the side wall spacers 27a and 27c. Accordingly, the top surface of the first selection gate electrode G2a may be gradually inclined toward the substrate surface and recessed in a “ ⁇ ” shape. Note that silicide SC is formed on each surface of the memory gate electrode G1a, the contact installation structure 10a, the first selection gate electrode G2a, and the like.
  • the semiconductor device 1 is, for example, a region in which a side wall spacer 27a on the side wall of the memory gate electrode G1a and a side wall spacer 27c on the side wall of the contact installation structure 10a are arranged correspondingly.
  • the distance between the side wall of the memory gate electrode G1a and the side wall of the contact mounting structure 10a is Dp, and as shown in FIGS.
  • the side wall spacer formed on the side wall of the memory gate electrode G1a When the thickness of the selection gate electrode G2a from 27c to the sidewall SW is Dsw, and the thickness of the sidewall spacer 27c between the memory gate electrode G8a of the contact installation structure 10a and the first selection gate electrode G2a is Dsp, Dp ⁇ Memory gate electrodes G1a, G1b, contact installation structures 10a, 11a, 10b, 11b, side wall spacers 27a, 27c, first selection gate electrode G2a so that the relationship of (2 ⁇ Dsp) + (2 ⁇ Dsw) is established. , G2b, and 2nd Select gate electrodes G3a and G3b are formed.
  • the sidewall spacer 27a on the sidewall of the memory gate electrode G1a (G1b) and the contact installation structures 10a and 11a (10b and 11b) disposed to face the sidewall spacer 27a are provided.
  • the first selection gate electrode G2a (G2b) and the second selection gate electrode G3a (G3b) can be formed without a gap in the region GP1 between the sidewall spacers 27c.
  • the present invention is not limited to this, and the side wall of the memory gate electrode G1a is described.
  • the first selection gate electrode G1a can be formed without a gap in the region GP1 between the side wall spacer 27a and the side wall spacer 27c on the side wall of the contact installation structure 10a disposed opposite to the side wall spacer 27a, various other arrangement relationships It is also good.
  • the memory gate electrode G1a and the contact installation structure 10a are arranged to face each other, the center line of the memory gate electrode G1a and the center line of the contact installation structure 10a are shifted, or the memory gate electrode G1a
  • the contact installation structure 10a may not be on the same straight line.
  • the present invention is not limited to this, and the contact installation structure 10a may be smaller than the memory gate electrode G1a. Well, it can be big.
  • the contact installation structure 10a is formed in a bar shape in the planar layout, but the present invention is not limited to this, and may have various other outer shapes such as an L shape and a J shape.
  • a 12 [V] charge storage gate voltage is applied to the memory gate electrode G1a of the memory gate structure 4a, and a channel layer (not shown) is formed along the surface of the memory well W1 facing the memory gate electrode G1a. Can be done.
  • a gate-off voltage of 0 [V] is applied to the first selection gate structure 5a from the first selection gate line (not shown) to the first selection gate electrode G2a via the contact C5a (FIG. 1).
  • a source off voltage of 0 [V] can be applied to the source region D1.
  • the first select gate structure 5a does not form a channel layer on the surface of the memory well W1 opposed to the first select gate electrode G2a, and the electric field between the source region D1 and the channel layer of the memory gate structure 4a The connection between the source region D1 and the channel layer of the memory gate structure 4a can be prevented.
  • the second selection gate structure 6a receives a second selection gate voltage of 1.5 [V] from the second selection gate line (not shown) to the second selection gate electrode G3a via the contact C6a (FIG. 1).
  • the charge accumulation bit voltage of 0 [V] can be applied to the drain region D2.
  • a channel layer is formed in the memory well W1 facing the second select gate electrode G2a and becomes conductive, and the drain region D2 and the channel layer of the memory gate structure 4a are electrically connected.
  • the channel layer of the memory gate structure 4a can be set to 0 [V] which is a charge storage bit voltage.
  • the substrate voltage of 0 [V] which is the same as the charge storage bit voltage, can be applied to the memory well W1.
  • the memory gate electrode G1a becomes 12 [V] and the channel layer becomes 0 [V], so that a large voltage difference of 12 [V] occurs between the memory gate electrode G1a and the channel layer.
  • charges can be injected into the charge storage layer EC by the quantum tunnel effect generated thereby, and a state in which data is written can be obtained.
  • the semiconductor device 1 manufactured by the manufacturing method of the present invention 1 the semiconductor device 1 manufactured by the manufacturing method of the present invention 1 Then, for example, when charge is not injected into the charge storage layer EC of the memory cell 3a, the same high voltage charge storage gate voltage as that at the time of data writing is applied to the memory gate electrode G1a, and the source region is formed by the first selection gate structure 5a.
  • the electrical connection between D1 and the channel layer of the memory gate structure 4a is interrupted, and the electrical connection between the drain region D2 and the channel layer of the memory gate structure 4a is interrupted by the second selection gate structure 6a.
  • charge injection into the charge storage layer EC of the memory gate structure 4a can be prevented.
  • the memory gate structure 4a of the memory cell (also referred to as write non-selected memory cell) 3a that does not inject charge into the charge storage layer EC has a charge storage gate voltage of 12 [V] across the memory gate electrode G1a Is applied to the memory well W1, the channel layer can be formed along the surface of the memory well W1 facing the memory gate electrode G1a.
  • a gate off voltage of 0 [V] is applied to the first selection gate structure 5a from the first selection gate line (not shown) to the first selection gate electrode G2a via the contact C5a (FIG. 1), and the source region A source off voltage of 0 [V] can be applied to D1.
  • the first select gate structure 5a of the memory cell 3a becomes non-conductive at the memory well W1 facing the first select gate electrode G2a, and the electrical connection between the source region D1 and the channel layer of the memory gate structure 4a Connection can be interrupted.
  • the second select gate structure 6a includes a 1.5 [V] second select gate electrode G3a from a second select gate line (not shown) via a contact C6a (FIG. 1). Two selection gate voltages are applied, and an off voltage of 1.5 [V] can be applied to the drain region D2. As a result, in this second select gate structure 6a, the memory well W1 facing the second select gate electrode G3a becomes nonconductive, and the electrical connection between the drain region D2 and the channel layer of the memory gate structure 4a Can be cut off.
  • the memory well W1 is in a non-conductive state under the first selection gate structure 5a and the second selection gate structure 6a on both sides, so that the memory gate electrode
  • the channel layer formed on the surface of the memory well W1 by G1a is in a state where the electrical connection from the drain region D2 and the source region D1 is cut off, and a depletion layer can be formed around the channel layer.
  • a capacitance (hereinafter referred to as a gate insulating film capacitance) C2 obtained by a three-layer configuration of the upper gate insulating film 23b, the charge storage layer EC, and the lower gate insulating film 23a, and the memory
  • the capacitance of the depletion layer (hereinafter referred to as depletion layer capacitance) C1 formed in the well W1 and surrounding the channel layer can be regarded as a configuration connected in series.
  • the gate insulating film capacitance C2 is the depletion layer. Assuming that the capacitance is three times the capacitance C1, the channel potential Vch of the channel layer is 9 [V] from the following equation.
  • the channel potential Vch of the channel layer surrounded by the depletion layer in the memory well W1 is 9 [V Therefore, the voltage difference between the memory gate electrode G1a and the channel layer is reduced to 3 [V], and as a result, charge injection into the charge storage layer EC can be prevented without generating a quantum tunnel effect.
  • the region of the memory well W1 between the memory gate structure 4a and the first selection gate structure 5a, and the memory gate structure 4a and the second selection gate structure 6a Since no impurity diffusion region with a high impurity concentration is formed in the region of the memory well W1 between, the depletion layer can be reliably formed around the channel layer formed around the surface of the memory well W1, and the depletion layer Accordingly, the channel potential Vch can be prevented from reaching the gate insulating films 25a and 25b of the first selection gate structure 5a and the second selection gate structure 6a from the channel layer.
  • the gate insulation of the first selection gate structure 5a and the second selection gate structure 6a is adjusted in accordance with the low voltage bit voltage of the drain region D2 and the low voltage source voltage of the source region D1. Even if each of the films 25a and 25b is formed thin, the channel potential Vch of the channel layer can be prevented from reaching the gate insulating films 25a and 25b by the depletion layer. Therefore, the gate insulating films 25a and 25b by the channel potential Vch can be prevented. Insulation breakdown can be prevented.
  • the semiconductor device 1 having the above-described configuration is a first that can be controlled independently from the contact installation structures 10a, 11a, 10b, and 11b by obtaining the following manufacturing process.
  • the selection gate electrodes G2a and G2b and the second selection gate electrodes G3a and G3b can be manufactured with a small number of photomask processes.
  • FIG. 5 shows a side cross-sectional configuration taken along the line AA ′ of FIG.
  • the element isolation layer 20 made of an insulating member is formed by the STI (Shallow Trench Isolation) method or the like into the memory circuit region ER1 and the peripheral circuit region ER2. It is formed at other predetermined places such as the boundary of
  • a sacrificial oxide film 30a is formed on the surface of the semiconductor substrate S by thermal oxidation or the like, and then P-type impurities or N-type impurities are implanted into the peripheral circuit region ER2, for example, by ion implantation. As a result, a P-type logic well W2 and an N-type logic well W3 are formed.
  • the resist is patterned using the photolithography technique and the etching technique, and the same reference numerals are given to the corresponding parts to FIG. 5A.
  • a resist Rm1 that exposes the memory circuit region ER1 and covers the peripheral circuit region ER2 is formed.
  • P-type impurities are implanted only into the memory circuit region ER1 with the patterned resist Rm1, thereby forming the memory well W1. Further, N-type impurities are implanted into the surface of the memory circuit region ER1, and a channel formation layer (not shown) is formed on the substrate surface facing the memory gate electrodes G1a and G1b and the side wall spacer 27a (FIG. 2) to be formed later. Then, using this resist Rm1 as it is, the sacrificial oxide film 30a in the memory circuit region ER1 is removed with hydrofluoric acid or the like (first photomask processing step).
  • the step of injecting P-type impurities into the semiconductor substrate S to form the memory well W1 can be omitted.
  • layered lower gate insulating films 23a are formed on the entire surface of the memory circuit region ER1 and the peripheral circuit region ER2, respectively, as shown in FIG.
  • the layered memory gate electrode conductive layer 35 to be the memory gate electrodes G1a and G1b later is formed on the upper gate insulating film 23b.
  • a protective insulating film 30b made of an insulating member is formed on the memory gate electrode conductive layer 35 by a thermal oxidation method, a CVD (Chemical Vapor Deposition) method, or the like.
  • the resist is patterned using photolithography technology and etching technology, and the same reference numerals are given to corresponding portions to FIG. 5C.
  • the resist Rm2 is formed only at the planned formation positions of the memory gate structures 4a and 4b and the planned formation positions of the contact installation structures 10a, 11a, 10b, and 11b, and the resist Rm2 is used.
  • the memory gate electrode conductive layer 35 By patterning the memory gate electrode conductive layer 35, the memory gate electrodes G1a, G1b and small memory gate electrodes G8a, G9a, G8b, G9b separated from the memory gate electrodes G1a, G1b are formed (second photo).
  • Mask processing step ).
  • the memory gate electrode conductive layer 35 is composed of the memory gate electrode G1a (G1b) and the small memory gate electrodes G8a, G9a (G8b) separated from the memory gate electrode G1a (G1b) by the resist Rm2. , G9b) can be patterned so that they can be arranged on the same straight line.
  • the inter-electrode region GP2 arranged opposite to each other with a predetermined distance may be formed.
  • the memory gate electrodes G1a, G1b and the small pieces of memory gate electrodes G8a, G9a, G8b, G9b are shown in FIG.
  • the upper gate insulating film 23b and the charge storage layer EC exposed outside the formation positions are sequentially removed (the ON film is removed), and the patterned memory gate electrodes G1a and G1b and the small memory gate electrodes G8a, An upper gate insulating film 23b and a charge storage layer EC that are left in accordance with G9a, G8b, and G9b are formed.
  • Contact installation structures 10a and 11a (10b and 11b) stacked in the order of (G1b) can be formed (contact structure formation step).
  • a protective insulating film 30c is formed on the entire surface of the memory circuit region ER1 and the peripheral circuit region ER2.
  • the present invention is not limited thereto, and for example, an oxide film-based insulating film, a nitride film-based insulating film, A two-layer protective insulating film may be formed on the entire surface by sequentially stacking layers.
  • the protective insulating film 30c formed here becomes the side wall spacers 27a and 27c formed on the side walls of the memory gate structure 4a (4b) and the contact installation structures 10a and 11a (10a and 11b) later.
  • Dsp indicating the thickness of the sidewall spacer 27c between the memory gate electrode G8a of the contact installation structure 10a and the first selection gate electrode G2a
  • the protective insulating film 30c can be formed so as to satisfy the above-described formula, Dp ⁇ (2 ⁇ Dsp) + (2 ⁇ Dsw).
  • sidewall spacers 27a covering the periphery of the memory gate structures 4a and 4b are formed as shown in FIG.
  • side wall spacers 27c are formed to cover the periphery of contact installation structures 10a, 11a, 10b, 11b (not shown) (side wall spacer forming step).
  • the resist is patterned using photolithography technology and etching technology, and the same reference numerals are given to corresponding portions to FIG. 8A.
  • a resist Rm3 that covers the entire surface of the peripheral circuit region ER2 and exposes the memory circuit region ER1 is formed.
  • a memory circuit region serving as a planned formation position of the first selection gate structures 5a and 5b (FIG. 2) and a formation planned position of the second selection gate structures 6a and 6b (FIG. 2) Impurities are implanted into ER1, and a channel formation layer (not shown) is formed on the substrate surface facing the first selection gate electrodes G2a and G2b and the second selection gate electrodes G3a and G3b to be formed later (third photomask) Processing step).
  • the gate insulating films 25a and 25b are formed at the positions where the first selection gate electrodes G2a and G2b (FIG. 1) and the second selection gate electrodes G3a and G3b (FIG. 1) are to be formed in the memory circuit region ER1.
  • Gate insulating films 29a and 29b are also formed at positions where logic gate electrodes G5 and G6 (FIG. 1) are to be formed in the circuit region ER2.
  • FIG. 9A in which parts corresponding to those in FIG.
  • the electrodes G3a, G3b, and one logic gate electrode G5 for example, an N-type conductive layer 37 is formed in a layered manner, and a P-type reverse conductive layer 38 that becomes the other logic gate electrode G6 in the peripheral circuit region ER2. are formed in layers.
  • a resist is patterned using photolithography technology and etching technology, and the conductive layer 37 in the memory circuit region ER1 is used using this resist.
  • (4th photomask processing step photomask processing step for forming a selective gate electrode)).
  • the resist Rm4 covers the entire surface of the peripheral circuit region ER2, and the conductive layer 37 (FIG. 9A) exposed in the memory circuit region ER1 is exposed. Etch back.
  • the conductive layer 37 and the reverse conductive layer 38 covered with the resist Rm4 remain as they are.
  • the sidewall spacers 27a on the sidewalls of the memory gate structures 4a and 4b and the contact installation structures 10a, 11a, 10b, and 11b Sidewall-shaped selection gate electrodes Ga and Gb are formed along the side wall spacer 27c on the side wall.
  • FIG. 10 shows each of the memory gate structures 4a and 4b and the contact installation structures 10a, 11a, 10b, and 11b with respect to the planar layout of the memory circuit region ER1 in the completed semiconductor device 1 shown in FIG.
  • FIG. 5 is a schematic diagram when sidewall-shaped selection gate electrodes Ga and Gb formed along the periphery are overlaid.
  • the selection gate electrode Ga in an undivided state circulates around the periphery of the memory gate electrode G1a and the periphery of the contact installation structures 10a and 11a that are electrically separated from the memory gate electrode G1a.
  • the side wall spacer 27a on the side wall of the memory gate electrode G1a and the side wall spacer 27c on the side wall of the contact mounting structure 10a, 11a can be formed without gaps in the region GP1 facing each other. .
  • the non-divided selection gate electrode Ga surrounds the periphery of the memory gate electrode G1a extending in one direction.
  • the long quadrilateral region that circulates and the short quadrilateral regions that circulate so as to surround each of the contact mounting structures 10a and 11a have a shape that is integrally formed.
  • the conductive layer 37 formed in the memory circuit region ER1 and the selection gate electrodes Ga and Gb formed by etching back the conductive layer 37 are expressed by the above formula, Dp ⁇ (2 ⁇ Dsp) + ( The film thickness of the conductive layer 37 and the etch back condition of the conductive layer 37 can be set so that 2 ⁇ Dsw) holds.
  • FIG. 11 showing a side sectional configuration of the DD ′ portion of FIG. 10
  • sidewall spacers on the sidewall of the memory gate electrode G1a are formed.
  • the conductive layer 37 remains without a gap even after the etch back of the conductive layer 37, and as a result, the memory gate electrode G1a
  • the selection gate electrode Ga can be formed from the sidewall spacer 27a on the sidewall to the sidewall spacer 27c on the sidewall of the contact installation structure 10a.
  • the selection gate electrode Ga formed between the sidewall spacer 27a on the sidewall of the memory gate electrode G1a and the sidewall spacer 27c on the sidewall of the contact installation structure 10a is formed by etching back the conductive layer 37. Therefore, the thinnest film is formed in the vicinity of the center between the side wall spacers 27a and 27c, which is farthest from the opposing side wall spacers 27a and 27c, and the top surface near the center between the side wall spacers 27a and 27c. Is recessed in the shape of a " ⁇ " toward the substrate surface.
  • a low concentration N-type impurity is implanted into the memory circuit region ER1 not covered with the resist Rm4 by ion implantation or the like, and the memory well W1 exposed to the outside is exposed.
  • the extension region ETa is formed on the surface, and then the resist Rm4 can be removed.
  • a resist is patterned using a photomask (not shown) using photolithography technology and etching technology, and the conductive layer 37 and reverse conductivity in the peripheral circuit region ER2 are used using this resist.
  • the layer 38 is patterned to form the logic gate electrodes G5 and G6 on the gate insulating films 29a and 29b.
  • the resist used for forming the logic gate electrodes G5 and G6 is used as it is, and at the same time, the memory circuit Part of the select gate electrodes Ga and Gb in the region ER1 can also be removed.
  • the logic gate structures 7a and 7b are formed later.
  • a resist Rr1a formed in accordance with the outline shape of the logic gate structures 7a and 7b can be disposed.
  • logic gate electrodes G5 and G6 are formed according to the outer shape of the resist Rr1a, and the logic gate structures 7a and 7a, in which the logic gate electrodes G5 and G6 are stacked on the gate insulating films 29a and 29b, 7b can be formed.
  • FIG. 10 shows formation planned positions Pf1, Pf2, Pf3, and Pf4 where the selection gate electrodes Ga and Gb are partially removed and the selection gate electrode cutting portions 13, 14, 15, and 16 are formed. ing.
  • the resist Rr1b arranged in the memory circuit region ER1 openings are formed only at the formation positions Pf1, Pf2, Pf3, and Pf4, and the conductive layers of the selection gate electrodes Ga and Gb exposed from the openings of the resist Rr1b.
  • the selection gate electrode cutting portions 13, 14, 15, 16 that divide the selection gate electrodes Ga, Gb in accordance with the outline shape of the opening of the resist Rr1b can be formed.
  • FIG. 12B shows a side cross-sectional configuration when the selection gate electrode cutting portions 13 and 15 are formed in the BB ′ portion of FIG.
  • the exposed selection gate electrodes Ga and Gb are removed, and as shown in FIG. 12B, the selection gate electrode cutting part 13 having an outer shape of the openings H1 and H3 of the resist Rr1b. , 15 can be formed.
  • the side wall spacer 27a and the gate insulating film 29b are exposed in the openings H1 and H3 of the resist Rr1b. Accordingly, at this time, the side wall spacer 27a and the gate insulating film 25a exposed from the openings H1 and H3 of the resist Rr1b can be partially removed. As a result, in the regions exposed from the openings H1 and H3, the side wall spacer 27a is removed, so that a defect 40 is formed near the top of the side wall spacer 27a, and not only the gate insulating film 25a but also the element isolation. A part of the surface of the layer 20 is also removed, and a recess 30 that is recessed in the element isolation layer 20 can be formed.
  • the selection gate electrode Ga (Gb) is divided by removing the selection gate electrode Ga (Gb) at a plurality of locations of the selection gate electrode Ga (Gb).
  • the single selection gate electrode Ga (Gb) surrounds one contact installation structure 10a (10b) and forms a sidewall along the side wall spacer 27a on one side wall of the memory gate electrode G1a (G1b).
  • the formed first selection gate electrode G2a (G2b) and the other contact installation structure 11a (11b) Surrounds the formed first selection gate electrode G2a (G2b) and the other contact installation structure 11a (11b), and forms a side wall along the side wall spacer 27a of the other side wall of the memory gate electrode G1a (G1b)
  • the formed second selection gate electrode G3a (G3b) can be provided.
  • a low-density N-type impurity or P-type is formed by ion implantation or the like in the peripheral circuit region ER2 using a resist patterned for N-type or P-type.
  • FIG. 12A in FIG. 12A, resists Rr1a and Rr1b that should have been removed in this step are shown as they are) in FIG. 12A, one logic well W2 exposed to the outside is implanted.
  • the N-type extension region ETa can be formed on the surface of the other substrate, and the P-type extension region ETb can be formed on the substrate surface of another logic well W3 exposed to the outside.
  • a step of forming a sidewall SW, and other high concentration N-type impurities or P-type impurities are implanted into the necessary locations by ion implantation or the like, and the source regions D1, D3 and drain regions
  • the process of forming the silicide SC, etc. these memory cells 3a, 3b, 3c, 3d, 3e, 3f, contact installation structures 10a, 11a, 10b, 11b, peripheral circuits 18, 19
  • An interlayer insulating layer 21 is formed so as to cover.
  • a contact hole is formed in the interlayer insulating layer 21 across the substrate surface from the top of the one contact installation structure 10a (10b) across the first selection gate electrode G2a (G2b).
  • a contact hole is formed in the interlayer insulating layer 21 from the top of the other contact installation structure 11a (11b) to the substrate surface across the second selection gate electrode G3a (G3b).
  • contact holes are also formed in the interlayer insulating layer 21 at other necessary locations.
  • a conductive member is injected into each contact hole to form columnar contacts C1, C2, C3, etc. in each contact hole.
  • the substrate straddles the first selection gate electrode G2a from the flat top of the contact installation structure 10a.
  • a contact C5a having a rectangular cross section standing over the surface can be formed.
  • the semiconductor device 1 includes the same charge storage layer EC, upper gate insulating film 23b, and memory gate electrodes G8a, G9a (G8b, G9b) as the memory gate structure 4a (4b).
  • Contact arrangement structures 10a and 11a (10b and 11b) having a configuration in which layers are sequentially stacked and electrically separated from the memory gate structure 4a (4b) are provided.
  • the second selection gate electrode G3a (G3b) is provided.
  • one of the contact installation structures 10a (10b) is erected over a region extending from the top to the substrate surface across the side wall spacer 27c and the first selection gate electrode G2a (G2b).
  • Other contacts C5a (C5b) and other contact installation structures 11a (11b) and other regions erected across the region from the top to the substrate surface across the side wall spacer 27c and the second selection gate electrode G3a (G3b) The contact C6a (C6b) is provided, the first selection gate electrode G2a (G2b) and one upper wiring layer are connected by one contact C5a (C5b), and the second contact C6a (C6b) is connected by the second contact C6a (C6b).
  • the selection gate electrode G3a (G3b) is connected to the other wiring layer on the upper layer.
  • the first selection is made from the flat top of the contact installation structure 10a formed of the same charge storage layer EC, upper gate insulating film 23b, and memory gate electrode G8a as the memory gate structure 4a. Since the contact C5a is provided so as to straddle the gate electrode G2a, the distance to the upper wiring layer is as much as there is no riding-up portion 102b that has reached the top of the memory gate structure 110 as in the prior art (FIG. 13). As a result, the aspect ratio of the contact C2 and the like can be reduced, and thus an increase in the contact resistance value can be prevented. Further, in the semiconductor device 1, the contact installation structure 10a and the upper wiring layer can be kept away from each other by the amount of the rising portion 102b that has reached the top of the memory gate structure 110 as in the prior art. The poor contact with the wiring layer can be prevented.
  • the layered memory gate electrode conductive layer 35, the layered upper gate insulating film 23b, and the layered charge storage layer EC are sequentially patterned in the memory circuit region ER1.
  • the memory gate structures 4a, 4b comprising the memory gate electrode G1a, the upper gate insulating film 23b, the charge storage layer EC, and the lower gate insulating film 23a
  • the memory gate structures 4a, 4b Contact installation structures 10a, 11a, 10b, and 11b that are formed by diverting the same layer and are electrically separated from the memory gate structures 4a and 4b are formed (FIGS. 6A and 7).
  • the memory circuit region ER1 (FIG. 8A) in which the memory gate structures 4a and 4b and the contact installation structures 10a, 11a, 10b, and 11b covered with the side wall spacers 27a and 27c are formed.
  • the peripheral circuit region ER2 the gate insulating films 25a, 25b, 25c, 29a, 29b are formed, and then the conductive layer 37 and the reverse conductive layer 38 are formed on the gate insulating films 25a, 25b, 25c, 29a, 29b.
  • the conductive layer 37 in the memory circuit region ER1 is etched back while the conductive layer 37 and the reverse conductive layer 38 in the peripheral circuit region ER2 are left as they are.
  • the memory gate structures 4a, 4b and the contact installation structures 10a, 11a, 10b, 11b are continuously provided around the periphery, and the sidewalls 27a, 27c are arranged along the sidewalls.
  • the selection gate electrodes Ga and Gb formed in the shape can be formed (FIGS. 9B, 10 and 11).
  • the gate insulating films 29a and 29b are formed by patterning the conductive layer 37 and the reverse conductive layer 38 in the peripheral circuit region ER2 using the resist Rr1a patterned by the photomask.
  • the logic gate electrodes G5 and G6 are formed thereon, and the resists Rr1a and Rr1b used for forming the logic gate electrodes G5 and G6 are used as they are, and a part of the selection gate electrodes Ga and Gb in the memory circuit region ER1. And the selection gate electrodes Ga and Gb are divided.
  • the first selection gate electrode G2a (G2b) surrounding the periphery of the one contact installation structure 10a (10b) and the first selection gate electrode G2a (G2b) are electrically connected
  • a second select gate electrode G3a (G3b) that is separated and surrounds the periphery of 11a (11b) can be formed in another contact mounting structure (FIGS. 12 and 13).
  • the selection gate electrodes Ga and Gb in the memory circuit region ER1 are also divided at the same time, thereby The first selection gate electrodes G2a and G2b and the second selection gate electrodes G3a and G3b, which are opposed to each other along the gate electrodes G1a and G1b and are electrically separated, can be formed.
  • the contacts A contact hole is formed from the top of the installation structure 10a, 11a, 10b, 11b across either the first selection gate electrode G2a, G2b or the second selection gate electrode G3a, G3b, and the contact hole is electrically conductive. Fill the part.
  • the contact straddling either the first selection gate structure 5a, 5b or the second selection gate structure 6a, 6b from the top of the contact installation structure 10a, 11a, 10b, 11b C5a, C5b, C6a, C6b can be formed, and the contact C5a, C5b, C6a, C6b can be used to form a wiring layer above the memory gate structures 4a, 4b and the first selection gate electrodes G2a, G2b or the second selection gate.
  • the electrodes G3a and G3b can be connected.
  • the present invention is not limited to this, and the first photomask processing step, the second photomask processing step, and the selection gate electrode formation without impurity implantation in the third photomask processing step A total of three photomask processing steps (corresponding to the fourth photomask processing step) may be used.
  • the threshold voltage (Vth) of the first selection gate structures 5a and 5b and the second selection gate structures 6a and 6b to be finally formed can be obtained without performing impurity implantation in the third photomask processing step.
  • Vth threshold voltage
  • the memory gate electrodes G1a and G1b are sandwiched only by adding a manufacturing process for three photomasks to a general peripheral circuit manufacturing process.
  • the first selection gate electrodes G2a, G2b and the second selection gate electrodes G3a, G3b, and the memory cells 3a which can independently control the first selection gate electrodes G2a, G2b and the second selection gate electrodes G3a, G3b, 3b, 3c, 3d, 3e, 3f can be incorporated. Therefore, in the manufacturing method in which the third photomask processing step is omitted, the cost can be reduced because the photomask can be reduced compared to the manufacturing method according to the above-described embodiment.
  • the present invention is not limited to this embodiment, and various modifications can be made within the scope of the present invention.
  • the memory cells 3a, 3b, The number of 3c, 3d, 3e, 3f, the number of peripheral circuits 18, 19, the number of contact mounting structures 10a, 11a, 10b, 11b, the number of select gate electrode cutting parts 13, 14, 15, 16 and the like are various.
  • the conductivity type of the memory well W1 and the logic wells W2 and W3 may be either N-type or P-type.
  • three or more contact installation structures 10a, 11a,... May be provided, or three or more selection gate electrode cutting portions may be provided.
  • the non-divided selection gate electrodes Ga and Gb are divided by the selection gate electrode cutting portions 13, 14, 15, and 16, and can be controlled independently.
  • the case where the selection gate electrodes G2a and G2b and the second selection gate electrodes G3a and G3b are applied has been described.
  • the present invention is not limited to this, and the selection gate electrodes Ga and Gb that circulate around the memory gate electrodes G1a and G1b without dividing the selection gate electrodes Ga and Gb that are integrally formed in a non-divided manner are used as sidewalls.
  • the type gate electrode may be used as it is.
  • one of the two contact installation structures 10a and 11a may be provided on the selection gate electrode Ga.
  • a voltage is applied from one contact C5a to the selection gate electrode Ga by erecting the contact C5a so as to extend from the top of the contact installation structure 10a to the side wall spacer 27a and the selection gate electrode Ga.
  • the selection gate electrode Ga can be independently controlled separately from the memory gate electrode G1a, and the effect can be obtained as in the above-described embodiment.
  • the selection gate electrode cutting portion by removing a part of the selection gate electrode Ga and physically cutting it, the first selection gate electrode G2a and the second selection gate electrode Ga can be cut.
  • the selection gate electrode G3a has a reverse conductivity type electrode cutting layer having a reverse conductivity type to the selection gate electrode Ga or an intrinsic semiconductor layer.
  • a cutting portion is provided, and the selection gate electrode cutting portion is used to form a PIN junction structure, a NIN junction structure, a PIP junction structure, an NPN junction structure, or a PNP junction structure on the selection gate electrode to electrically isolate the selection gate electrode.
  • the first selection gate electrode G2a and the second selection gate electrode G3a may be formed.
  • the selection gate electrodes the first selection gate electrode G2a and the second selection gate electrode G3a that selectively apply a voltage to the channel layer on the substrate surface facing the memory gate electrode G1a
  • the present invention is not limited to this, the first selection gate electrode G2a or the second selection gate having a function of selecting the memory gate electrode G1a with respect to the memory gate electrode G1a is described. Either one of the electrodes G3a may be provided.
  • the semiconductor device 1 in which the memory gate structure 4a is formed has been described.
  • the present invention is not limited thereto, and a side wall spacer is provided on the side wall of the gate electrode. It can be applied to all the various semiconductor devices in which the sidewall type gate electrode is formed.
  • the memory gate structure 4a is provided with the charge storage layer EC, but the charge storage layer is not provided, and the gate structure has a gate electrode on the substrate with a gate insulating film interposed therebetween.
  • a semiconductor device having an isolation gate electrode formed of the same layer as the electrode and provided with a contact installation structure that is electrically isolated from the gate structure may be used.
  • the semiconductor device is provided with a sidewall-type gate electrode continuously provided from the gate structure to the contact installation structure, and extends from the top of the contact installation structure to the sidewall spacer and the sidewall-type gate electrode. The contact is erected.
  • a charge storage layer is provided via a gate insulating film between a side wall type gate electrode connected from the gate structure to the contact installation structure and the substrate surface.
  • the sidewall gate structure having the sidewall gate electrode has a configuration in which a lower gate insulating film, a charge storage layer, an upper gate insulating film, and a memory gate electrode are sequentially stacked.
  • the gate electrode is disposed on the substrate via the gate insulating film, and the contact installation structure is the same layer as the gate electrode.
  • the isolation gate electrode can be configured.
  • the contact installation structures 10a and 11a, the selection gate electrode cutting portions 13 and 14 and the like may be formed at various positions.
  • the peripheral circuits 18 and 19 include various sense amplifiers, column decoders, row decoders, and the like formed in the same area as the memory cells 3a, 3b, 3c, 3d, 3e, and 3f.
  • a CPU Central Processing Unit
  • ASIC Application-Specific Integrated Circuit
  • Various other peripheral circuits such as an output circuit may be applied.

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JP2019160828A (ja) * 2018-03-07 2019-09-19 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP7026537B2 (ja) 2018-03-07 2022-02-28 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法

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KR20170070123A (ko) 2017-06-21
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