WO2016042880A1 - 抵抗変化メモリ - Google Patents

抵抗変化メモリ Download PDF

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Publication number
WO2016042880A1
WO2016042880A1 PCT/JP2015/068824 JP2015068824W WO2016042880A1 WO 2016042880 A1 WO2016042880 A1 WO 2016042880A1 JP 2015068824 W JP2015068824 W JP 2015068824W WO 2016042880 A1 WO2016042880 A1 WO 2016042880A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor layer
conductive line
fin
layer
resistance change
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Ceased
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PCT/JP2015/068824
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English (en)
French (fr)
Japanese (ja)
Inventor
千加 田中
紘希 野口
藤田　忍
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Toshiba Corp
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Toshiba Corp
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Priority to US15/054,706 priority Critical patent/US9954029B2/en
Publication of WO2016042880A1 publication Critical patent/WO2016042880A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type

Definitions

  • Embodiment relates to a resistance change memory.
  • a resistance change memory such as STT (Spin Transfer Torque) -MRAM (Magnetic Random Access Memory) includes a memory cell including a resistance change element and a selection transistor, for example.
  • a selection transistor for example, a planar type (planar type) or fin type (three-dimensional type) FET is used.
  • the Fin-FET Field Effect Transistor
  • the Fin-FET can use the top and side surfaces of the fin-type active area as the channel region, ensuring a relatively large driving force (channel width) even if the transistor is miniaturized. it can. For this reason, Fin-FETs are considered advantageous for integration.
  • the embodiment proposes a layout of memory cells and word lines, bit lines, and source lines connected to the memory cells, which is advantageous for miniaturization.
  • the resistance change memory has a first surface in a first direction, has a second surface in a second direction intersecting the first direction, and the first and first A first semiconductor layer extending in a third direction intersecting the two directions and having first and second portions, and the first semiconductor layer between the first and second portions of the first semiconductor layer. And a first gate electrode covering the second surface, a first conductive line connected to the first portion of the first semiconductor layer and extending in a direction intersecting the first and third directions A first variable resistance element having first and second terminals, wherein the first terminal is connected to the second portion of the first semiconductor layer, and a second of the first variable resistance element.
  • a second conductive line extending in a direction intersecting the first and third directions, and connected to the first gate electrode,
  • a third conductive line extending in a direction intersecting with the first and second directions, and the first and second conductive lines are disposed between the first semiconductor layer and the third conductive line. Is done.
  • the block diagram which shows the principal part of resistance change memory The perspective view which shows the structural example of a memory cell.
  • 1 is a circuit diagram showing a memory cell array according to a first embodiment.
  • FIG. 7 is a plan view showing a layout of the memory cell array of FIG. 6.
  • FIG. 9 is a plan view showing a layout of the memory cell array of FIG. 8.
  • Resistance change memory (1) Main part FIG. 1 shows an outline of a resistance change memory.
  • the memory cell array 11 includes memory cells MC.
  • the memory cell MC includes a selection transistor (for example, FET) ST and a resistance change element MTJ connected in series.
  • the resistance change element MTJ is, for example, a magnetoresistive effect element.
  • the first driver 12 drives the word line WLi.
  • the word line WLi is connected to the gate of the selection transistor ST.
  • the first driver / sinker 13A drives the source line SLj.
  • Source line SLj is connected to one end of memory cell MC.
  • the second driver / sinker 13B drives the bit line BLj.
  • Bit line BLj is connected to the other end of memory cell MC.
  • the control circuit 14 controls the operations of the first driver 12, the first driver / sinker 13A, and the second driver / sinker 13B when reading / writing data from / to the memory cell MC.
  • the control circuit 14 sets the word line WLi to “H” by the first driver 12.
  • “H” is a potential at which the selection transistor ST is turned on.
  • the control circuit 14 sets, for example, one potential of the source line SLj and the bit line BLj higher than the other potential by the first and second drivers / sinkers 13A and 13B. That is, for example, by flowing a current from the source line SLj to the bit line BLj, “1” is written to the variable resistance element MTJ, and by flowing a current from the bit line BLj to the source line SLj, the variable resistance element MTJ is flowed. Write “0”.
  • control circuit 14 sets, for example, the source line SLj to the ground potential and connects the bit line BLj to the sense amplifier by the first and second drivers / sinkers 13A and 13B.
  • the positions of the selection transistor ST and the resistance change element MTJ in the memory cell MC may be interchanged. Further, the position of the source line SLj and the position of the bit line BLj may be interchanged.
  • Memory cell structure example 2 and 3 show examples of the structure of the memory cell.
  • FIG. 2 is an example in which a Fin-FET is used as the selection transistor ST
  • the example in FIG. 3 is an example in which a Planer-FET is used as the selection transistor ST.
  • the semiconductor substrate 21 is, for example, a single crystal silicon substrate.
  • the fin-type active area AA1 is disposed on the semiconductor substrate 21.
  • the element isolation insulating layer 22 includes an insulating layer (for example, a silicon oxide layer) filled in the trench in the semiconductor substrate 21 and sandwiches the fin-type active area AA1. That is, the element isolation insulating layer 22 has an STI (Shallow Trench Isolation) structure.
  • the fin-type active area AA1 has an upper surface in a first direction (a vertical direction perpendicular to the upper surface of the semiconductor substrate 21), and a second direction (a surface parallel to the upper surface of the semiconductor substrate 21) intersecting the first direction. It has a side surface in the inward direction and extends in a third direction (in-plane direction parallel to the upper surface of the semiconductor substrate 21) intersecting the first and second directions.
  • the contact portion 24 is connected to the first end of the fin-type active area AA1 in the third direction, and the contact portion 25 is connected to the second end of the fin-type active area AA1 in the third direction.
  • the contact portions 24 and 25 and a part of the fin-type active area AA1 include source / drain regions whose resistance is reduced by impurities.
  • Contact plugs P1 and P2 are in contact with contact portions 24 and 25, respectively.
  • the width of the contact portions 24 and 25 in the second direction is wider than the width of the fin-type active area AA1 in the second direction. This is to prevent the collapse of the fin-type active area AA1 when the memory cell is miniaturized, and to prevent contact failure due to misalignment between the contact plugs P1, P2 and the contact portions 24, 25. There is significance in.
  • the selection transistor ST includes a fin-type active area AA1 as a channel, and a gate insulating layer 26 and a gate electrode 27 that cover the upper surface and side surfaces of the fin-type active area AA1.
  • the driving force (channel width) of the selection transistor ST is defined by the sum of the width of the upper surface of the fin-type active area AA1 in the second direction and the width of the side surface of the fin-type active area AA1 in the first direction. Is done.
  • the Fin-FET of this example is advantageous for miniaturization because it can secure a larger driving force than the Planer-FET.
  • the source line (first conductive line) SLj is connected to the contact portion 24 by a contact plug P1.
  • the resistance change element MTJ is connected to the contact portion 25 by a contact plug P2.
  • the bit line (second conductive line) BLj is connected to the resistance change element MTJ by a contact plug P3.
  • Both the source line SLj and the bit line BLj extend in the second direction.
  • both the source line SLj and the bit line BLj extend in the second direction intersecting the third direction in which the fin-type active area AA1 extends.
  • a conductive layer as an intermediate layer between the source line SLj and the contact portion 24 and between the bit line BLj and the contact portion 25. The size can be reduced.
  • the word line (third conductive line) WLi is connected to the gate electrode 27 by a contact plug P4. Word line WLi extends in the third direction.
  • the word line WLi extends in the third direction in which the fin-type active area AA1 extends, and the word line WLi is above the source line SLj and the bit line BLj. There is to be. Thereby, for example, the fin type active area AA1 and the word line WLi can be overlapped with each other in the first direction, so that the size of the memory cell can be reduced.
  • the active area AA is sandwiched between element isolation insulating layers 22 having an STI structure.
  • the active area AA has an upper surface in the first direction, a constant width in the second direction, and extends in the third direction.
  • the selection transistor ST includes an active area AA as a channel, and a gate insulating layer 26 and a gate electrode 27 that cover the upper surface of the active area AA.
  • the source line (first conductive line) SLj is connected to the first end of the active area AA in the third direction by the contact plug P1.
  • the resistance change element MTJ is connected to the second end of the active area AA in the third direction by the contact plug P2.
  • Each of the first and second end portions of the active area AA includes source / drain regions whose resistance is reduced by impurities.
  • the bit line (second conductive line) BLj is connected to the resistance change element MTJ by a contact plug P3.
  • the word line (third conductive line) WLi is connected to the gate electrode 27 by a contact plug P4. Both the source line SLj and the bit line BLj extend in the second direction, and the word line WLi extends in the third direction.
  • FIG. 4 shows a basic structure of a magnetoresistive effect element as a resistance change element.
  • the magnetoresistive effect element MTJ includes a storage layer (ferromagnetic layer) 1 having a perpendicular and variable magnetization, a tunnel barrier layer (insulating layer) 2 in a direction (vertical direction) perpendicular to the film surface (Film surface), and It has a laminated structure in which reference layers (ferromagnetic layers) 3 having perpendicular and invariant magnetization are arranged in this order.
  • variable magnetization means that the magnetization direction does not change before and after writing
  • variable magnetization means that the magnetization direction can change in the opposite direction before and after writing
  • writing means spin transfer writing that applies spin torque to the magnetization of the memory layer 1 by flowing a spin injection current (spin-polarized electrons) through the magnetoresistive element MTJ.
  • the magnetization direction of the storage layer 1 is the same as the magnetization direction of the reference layer 3 (parallel state).
  • the resistance value of the magnetoresistive element MTJ changes depending on the relative magnetization directions of the reference layer 3 and the storage layer 1 due to the magnetoresistive effect. That is, the resistance value of the magnetoresistive element MTJ is low in the parallel state and high in the antiparallel state.
  • the resistance value in the parallel state is R0
  • the resistance value in the anti-parallel state is R1
  • the value defined by (R1-R0) / R0 is called the MR (magnetoresistance) ratio.
  • the magnetization of the reference layer 3 is fixed while facing the storage layer 1 side, but may be fixed while facing the opposite side to the storage layer 1. Further, when the magnetoresistive element MTJ is disposed on the semiconductor substrate, the vertical relationship between the reference layer 3 and the storage layer 1 is not limited.
  • the magnetoresistive element MTJ when the reference layer 3 is above the storage layer 1, the magnetoresistive element MTJ is called a top pin type, and when the reference layer 3 is below the storage layer 1, the magnetoresistive element The MTJ is called a bottom pin type.
  • FIG. 5 shows an example of a magnetoresistive effect element having a shift cancel layer.
  • the magnetoresistive effect element MTJ includes a storage layer (ferromagnetic layer) 1 having a perpendicular and variable magnetization, a tunnel barrier layer (insulating layer) 2 and a reference layer having a perpendicular and invariable magnetization (ferromagnetism). Layer) having a laminated structure arranged in the order of 3.
  • the magnetoresistive effect element MTJ includes a shift cancel layer (ferromagnetic layer) 4 having perpendicular and invariable magnetization on the reference layer 3 side.
  • a nonmagnetic layer (for example, a metal layer) 5 is disposed between the reference layer 3 and the shift cancel layer 4.
  • the reference layer 3 and the storage layer 1 have perpendicular magnetization.
  • the leakage magnetic field (stray magnetic3field) from the reference layer 3 is oriented in the magnetization direction (vertical direction) of the storage layer 1, so that a leakage magnetic field having a large vertical component is applied to the storage layer 1.
  • This leakage magnetic field acts in a direction that makes the magnetization direction of the storage layer 1 the same (parallel state) as the magnetization direction of the reference layer 3.
  • the anti-parallel state becomes unstable due to the leakage magnetic field from the reference layer 3.
  • the storage layer 1 cannot maintain the antiparallel state. Even when the leakage magnetic field is smaller than the coercive force of the storage layer 1, the magnetization of the storage layer 1 is reversed from the antiparallel state to the parallel state by the leakage magnetic field in consideration of the fluctuation of magnetization due to thermal disturbance. Sometimes.
  • the shift cancel layer 4 is provided in order to solve such a problem.
  • the reference layer 3 and the shift cancel layer 4 are stacked on each other.
  • the magnetization direction of the shift cancel layer 4 is set to be opposite to the magnetization direction of the reference layer 3.
  • FIG. 6 shows a memory cell array according to the first embodiment.
  • FIG. 7 shows a layout of the memory cell array of FIG.
  • the first embodiment relates to a so-called two-transistor-two-element type memory cell array in which one memory cell includes two selection transistors and two resistance change elements. That is, in FIGS. 6 and 7, the area X1 corresponds to a memory cell storing 1 bit.
  • the fin-type active area AA1 corresponds to, for example, the fin-type active area AA1 in FIG.
  • the fin-type active area AA2 has the same structure as the fin-type active area AA1.
  • the fin type active area AA3 connects the two fin type active areas AA1 and AA2.
  • the fin-type active areas AA1, AA2, and AA3 are laid out in a straight line and integrally extend in the third direction.
  • Fin-type active areas AA1 and AA2 are each covered with a gate electrode 27.
  • the width L of the gate electrode 27 in the third direction corresponds to the channel length of the selection transistor ST.
  • W is the width of the fin-type active area AA1, AA2 in the second direction.
  • the word line WL0 extends in the third direction while overlapping the fin-type active areas AA1, AA2, and AA3.
  • the word line WL0 is commonly connected to the gate electrode 27 that covers the fin-type active area AA1 and the gate electrode 27 that covers the fin-type active area AA2.
  • the source lines SL0 and SL1 are respectively connected to the first ends of the fin-type active areas AA1 and AA2 in the third direction via contact plugs.
  • the bit lines BL0 and BL1 are connected to the second ends of the fin-type active areas AA1 and AA2 in the third direction via the magnetoresistive effect element MTJ, respectively.
  • the size of one memory cell is 2F (second direction) ⁇ It is defined by 8F (third direction).
  • F is a feature size, for example, and is a minimum processing dimension in each generation of the resistance change memory.
  • FIG. 8 shows a memory cell array according to the second embodiment.
  • FIG. 9 shows a layout of the memory cell array of FIG.
  • the second embodiment also relates to a so-called two-transistor-two-element type memory cell array in which one memory cell includes two selection transistors and two resistance change elements. That is, in FIGS. 8 and 9, the area X2 corresponds to a memory cell storing 1 bit.
  • the second embodiment is different from the first embodiment in that one source line SL0 is commonly connected to two select transistors ST in one memory cell.
  • the fin-type active area AA1 corresponds to, for example, the fin-type active area AA1 in FIG.
  • the fin-type active area AA2 has the same structure as the fin-type active area AA1.
  • the fin-type active areas AA1 and AA2 are laid out in a straight line and integrally extend in the third direction.
  • Fin-type active areas AA1 and AA2 are each covered with a gate electrode 27.
  • the width L of the gate electrode 27 in the third direction corresponds to the channel length of the selection transistor ST.
  • W is the width of the fin-type active area AA1, AA2 in the second direction.
  • the word line WL0 extends in the third direction while overlapping the fin-type active areas AA1 and AA2.
  • the word line WL0 is commonly connected to the gate electrode 27 that covers the fin-type active area AA1 and the gate electrode 27 that covers the fin-type active area AA2.
  • the source line SL0 is connected to the first ends of the fin-type active areas AA1, AA2 in the third direction via contact plugs.
  • the bit lines BL0 and BL1 are connected to the second ends of the fin-type active areas AA1 and AA2 in the third direction via the magnetoresistive effect element MTJ, respectively.
  • the size of one memory cell is 2F (second direction) ⁇ It is defined by 5F (third direction). That is, the second embodiment can reduce the size of one memory cell in the third direction as compared with the first embodiment.
  • the number of conductive lines (bit lines BL0 and BL1 and source line SL0) arranged in the third direction is three in one memory cell. This means that 1.5 conductive lines are connected to one transistor ST and one magnetoresistive element MTJ.
  • the number of conductive lines (bit lines BL0 and BL1 and source lines SL0 and SL1) arranged in the third direction is four. is there. This means that two conductive lines are connected to one transistor ST and one magnetoresistive element MTJ.
  • effect FIG. 10 shows the effect of the MRAM according to the first and second embodiments.
  • the miniaturization of the selection transistor can be effectively linked to the miniaturization of the memory cell.
  • the cell size of the MRAM according to these embodiments can be made smaller than the cell size of the embedded SRAM (Embedded SRAM) or the embedded DRAM (Embedded DRAM).
  • 11 memory cell array
  • 12 first driver
  • 13A first driver / sinker
  • 13B second driver / sinker
  • 14 control circuit
  • 21 semiconductor substrate
  • 22 element isolation insulating layer
  • 23 fin Type semiconductor layer (channel)
  • 24 first part (source / drain)
  • 25 second part (source / drain)
  • AA active area
  • WLi word line
  • BLj bit line
  • SLj source line .

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  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
  • Semiconductor Memories (AREA)
PCT/JP2015/068824 2014-09-17 2015-06-30 抵抗変化メモリ Ceased WO2016042880A1 (ja)

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JP2014-188737 2014-09-17
JP2014188737A JP6121961B2 (ja) 2014-09-17 2014-09-17 抵抗変化メモリ

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JP2016063023A (ja) 2016-04-25
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US9954029B2 (en) 2018-04-24

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