WO2016037575A1 - 晶圆级芯片封装结构及封装方法 - Google Patents
晶圆级芯片封装结构及封装方法 Download PDFInfo
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- WO2016037575A1 WO2016037575A1 PCT/CN2015/089305 CN2015089305W WO2016037575A1 WO 2016037575 A1 WO2016037575 A1 WO 2016037575A1 CN 2015089305 W CN2015089305 W CN 2015089305W WO 2016037575 A1 WO2016037575 A1 WO 2016037575A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D11/00—Component parts of measuring arrangements not specially adapted for a specific variable
- G01D11/24—Housings ; Casings for instruments
- G01D11/245—Housings for sensors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
- G06V40/13—Sensors therefor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
- G06V40/13—Sensors therefor
- G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
Definitions
- the present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a wafer level chip package structure and a packaging method thereof.
- fingerprint identification technology has the characteristics of good security, high reliability and simple and convenient use, which makes fingerprint recognition technology widely used in various fields to protect personal information security.
- information security of various electronic products has always been one of the key points of technology development.
- mobile terminals such as mobile phones, notebook computers, tablet computers, digital cameras, etc.
- the demand for information security is more prominent.
- the sensing method of the fingerprint identification device includes a capacitive (electric field type) and an inductive type, and the fingerprint identification device obtains the fingerprint information of the user by extracting the user fingerprint and converting the user fingerprint into an electrical signal output.
- FIG. 1 is a cross-sectional structural diagram of a fingerprint identification device, including: a substrate 100; a fingerprint identification chip 101 coupled to the surface of the substrate 100; and a glass substrate covering the surface of the fingerprint identification chip 101. 102.
- the fingerprint identification chip 101 has one or more capacitor plates therein. Since the skin or the subcutaneous layer of the user's finger has convex ridges and valleys of depressions, when the user's finger 103 contacts the surface of the glass substrate 102, the distance between the ridge and the valley to the fingerprint recognition chip 101 is different, and therefore, the user's finger 103 The capacitance between the ridge or valley and the capacitor plate is different, and the fingerprint identification core
- the slice 101 is capable of acquiring the different capacitance values and converting them into corresponding electrical signal outputs, and after the fingerprint identification device summarizes the received electrical signals, the fingerprint information of the user can be acquired.
- the sensitivity of the fingerprint recognition chip is high, and the manufacture and application of the fingerprint recognition device are limited.
- Embodiments of the present invention provide a wafer level chip packaging method, including: providing a substrate, the substrate including a plurality of sensing chip regions, the substrate having a first surface, and a second opposite the first surface a surface, the sensing chip region includes a sensing region on the first surface; forming a capping layer on the first surface of the substrate; forming a plug structure in the sensing chip region of the substrate, the plug structure One end is electrically connected to the sensing region, and a second surface of the substrate exposes the other end of the plug structure.
- the cover layer has a Mohs hardness of greater than or equal to 8H; and the cover layer has a dielectric constant greater than or equal to 7.
- the material of the cover layer comprises at least one of an inorganic nano material, a polymer material, a glass material or a ceramic material.
- the polymer material comprises an epoxy resin, a polyimide resin, a benzocyclobutene resin, a polybenzoxazole resin, a polybutylene terephthalate, a polycarbonate, a polyparaphenylene At least one of ethylene glycol dicarboxylate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol.
- the forming process of the cover layer is a screen printing process, a spin coating process or a spraying process.
- the inorganic nano material comprises at least one of aluminum oxide or cobalt oxide.
- the forming process of the cover layer is a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a screen printing process, a spin coating process, or a spray process.
- the forming process of the plug structure includes: forming a mask layer on the second surface of the substrate, the mask layer exposing a corresponding position and shape that needs to form a plug structure; Membrane The layer is a mask, the substrate is etched, a through hole is formed in the substrate, a top of the through hole is located at a second surface of the substrate; a plug structure is formed in the through hole; After the holes, the mask layer is removed.
- the plug structure comprises: an insulating layer on a surface of the sidewall of the through hole; a conductive layer on a surface of the insulating layer and a bottom surface of the through hole, and a conductive layer located at a bottom of the through hole
- the sensing region is electrically connected; a solder resist layer on a surface of the conductive layer, the solder resist layer filling the through hole.
- the method further includes: forming a wiring layer and a metal bump on the second surface of the substrate, the wiring layer is connected to the conductive layer and the metal bump, and the wiring layer and the metal bump are located on the sensing chip In the district.
- the plug structure comprises: an insulating layer on a surface of the sidewall of the through hole; a conductive plug on a surface of the insulating layer and a bottom surface of the through hole, wherein the conductive plug is filled with the through hole hole.
- the method further includes forming a metal bump on a top of the conductive plug exposed on the second surface of the substrate.
- the sensing chip area further includes a peripheral area located on the first surface and surrounding the sensing area.
- a chip circuit and a first pad located in the peripheral region, the chip circuit being electrically connected to the sensing region and the first pad.
- one end of the plug structure is connected to the first pad.
- the method further includes: cutting the substrate and the cover layer to separate the plurality of sensing chip regions from each other to form a plurality of independent sensing chips, the sensing chip having a first surface and opposite to the first surface The second surface, the sensing chip includes a sensing area on the first surface, and the first surface of the sensing chip has a covering layer; providing a substrate; coupling the sensing chip to the substrate, the second of the sensing chip The surface faces the substrate.
- the substrate further includes a scribe lane region between adjacent sensing chip regions.
- the process of cutting the substrate and the cover layer comprises: cutting the substrate and the cover layer in the scribe line region, so that the plurality of sensing chip regions are separated from each other to form a plurality of independent sensing chips.
- coupling the sensing chip to the substrate comprises: soldering one end of the plug structure exposed by the second surface of the substrate to the substrate, and electrically connecting the plug structure to the substrate.
- the sensing chip area further includes a peripheral area located on the first surface and surrounding the sensing area.
- the method further includes forming a chip circuit and a first pad in the peripheral region before forming the cap layer, and the chip circuit is electrically connected to the sensing region and the first pad.
- An optional one end of the plug structure is electrically connected to the sensing region through the first pad.
- the substrate has a first side, the first side of the substrate has a plurality of second pads, and the sensing chip is coupled to the first side of the substrate.
- the plug structure exposed on the second surface of the sensing chip is electrically connected to the second pad.
- one end of the substrate has a connecting portion for electrically connecting the sensing chip to an external circuit.
- the method further includes forming a guard ring on a side of the substrate, the guard ring surrounding the sensing chip and the cover layer.
- the method further includes: forming an outer casing surrounding the sensing chip, the cover layer, and the guard ring, the outer casing exposing a partial cover layer on the sensing area.
- the method further includes: forming an outer casing surrounding the sensing chip and the cover layer, the outer casing exposing a partial cover layer on the sensing area.
- the embodiment of the present invention further provides a wafer level chip package structure formed by using any of the above methods, comprising: a substrate, the substrate comprising a plurality of sensing chip regions, the substrate having a first surface, and The second surface opposite to the first surface, the sensing chip region includes a first surface a sensing layer; a cover layer on the first surface of the substrate; a plug structure in the sensing chip region of the substrate, one end of the plug structure is electrically connected to the sensing region, and the substrate is The other surface exposes the other end of the plug structure.
- the present invention further provides a chip package structure formed by using any of the above methods, comprising: an inductive chip, the inductive chip comprising a first surface, and a second surface opposite to the first surface,
- the sensing chip further includes a sensing area on the first surface, the second surface of the sensing chip faces the substrate; a cover layer on the first surface of the sensing chip; a plug structure in the sensing chip, the plug One end of the plug structure is electrically connected to the sensing region, and the second surface of the sensing chip exposes the other end of the plug structure.
- FIG. 1 is a schematic cross-sectional structural view of a fingerprint recognition device
- FIG. 2 to FIG. 6 are schematic cross-sectional structural views showing a wafer level fingerprint identification chip packaging process according to an embodiment of the present invention
- FIG. 7 to FIG. 14 are schematic cross-sectional views showing a wafer level fingerprint identification chip packaging process according to another embodiment of the present invention.
- the sensitivity of the fingerprint recognition chip is relatively high, so that the manufacture and application of the fingerprint recognition device are limited.
- the inventor of the present invention has found through research that, referring to FIG. 1 , the surface of the fingerprint identification chip 101 is covered with a glass substrate 102 for protecting the fingerprint identification chip 101 , and the user's finger 103 directly faces the glass substrate 102 .
- the thickness of the glass substrate 102 is relatively thick.
- the fingerprint recognition chip 101 is required to have high sensitivity to ensure accurate extraction of the user's fingerprint.
- the high-sensitivity fingerprint identification chip is difficult to manufacture and the manufacturing cost is high, which in turn causes the application and promotion of the fingerprint identification chip to be limited.
- a capacitance can be formed between the user's finger 103 and the capacitor plate in the fingerprint recognition chip 101; wherein the user's finger 103 and the capacitor plate are the two poles of the capacitor, and the glass substrate 102 is between the two poles of the capacitor. Dielectric.
- the capacitance value between the user's finger 103 and the capacitor substrate is large, and the difference in height between the ridge and the valley of the user's finger 103 is small, and therefore, the ridge is The difference between the capacitance value between the capacitor plates and the capacitance value between the valley and the capacitor plate is extremely small, and the fingerprint identification chip 101 is required in order to accurately detect the difference in the capacitance value. Has a higher sensitivity.
- the present invention provides a wafer level fingerprint identification chip package structure and packaging method.
- a cover layer is formed on the first surface of the sensing chip (for example, the fingerprint identification chip) to replace the conventional glass substrate for directly contacting the user's finger and protecting the sensing chip. Since the thickness of the cover layer is thinner than that of the conventional glass substrate, the distance from the first surface of the sensor chip to the surface of the cover layer can be reduced, so that the sensor chip can easily detect the fingerprint of the user, and accordingly, the pair is reduced.
- the sensitivity requirements of the sensing chip make the packaging structure of the fingerprint identification chip more widely used.
- a plug structure is formed in the substrate, the second surface of the substrate exposing the plug structure, enabling the plug structure to be electrically connected to the substrate, thus After the inductive chip is coupled to the substrate, there is no need to form an additional conductive structure on the first surface of the inductive chip, and thus, a cover layer can be formed on the first surface of the substrate before the substrate is cut, the cover layer being used for protection The sensing area, and the cover layer is cut while cutting to form the sensing chip. Therefore, it is not necessary to form the cover layer after coupling the sensing chip to the surface of the substrate, which can simplify the packaging method of the fingerprint identification chip, reduce damage to the sensing area, and ensure accurate fingerprint information acquired by the sensing area.
- the formed package structure can be simplified, which is advantageous for reducing the size of the package structure formed.
- FIG. 2 to FIG. 6 are schematic cross-sectional structural views of a wafer level fingerprint identification chip packaging process according to an embodiment of the present invention.
- the substrate 200 includes a plurality of sensing chip regions 201 having a first surface 210 and a second surface 220 opposite the first surface 210.
- the sensing chip area 201 includes a sensing area 211 on the first surface 210.
- the substrate 200 is a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate; moreover, the substrate 200 is a whole piece of crystal circle.
- the sensing chip area 201 is used to form a sensing chip. Subsequently, by cutting the substrate 200, a plurality of sensing chip areas 201 can be made independent of each other to form an independent sensing chip.
- the sensing chip regions 201 are arranged in an array, and the adjacent sensing chip regions 201 further have a dicing street region 202. By cutting the dicing street regions 202, the sensing chips can be made.
- the areas 201 are separated from each other.
- a sensing area 211 is formed on the first surface 210 of the substrate 200, and the sensing area 211 is used for detecting and receiving fingerprint information of a user, and therefore, it is required to be formed in the sensing area 211 for forming Acquiring a capacitive structure or an inductive structure of the user fingerprint information; and subsequently, forming a cover layer on the sensing area 211, and protecting the sensing area 211 by the cover layer.
- a capacitor structure is formed in the sensing region 211 as an example.
- Forming at least one capacitor plate in the sensing region 211 after subsequently forming a capping layer on the first surface 210 of the substrate 200, and when the user's finger is placed on the surface of the cap layer, the capacitor plate, covering The layer and the user's finger can form a capacitor structure, and the sensing region 211 can obtain a difference in capacitance between the capacitor plate and the surface ridge and valley of the user's finger, and output the difference in capacitance value through the chip circuit to output This gets the user fingerprint data.
- the sensing chip region 201 is further formed on the first surface 210 with a peripheral region 212 surrounding the sensing region 211.
- the peripheral region 212 is formed with a chip circuit and a first pad 213.
- the circuit is electrically connected to the sensing region 211 and the first pad 213.
- the first pad 213 is used for electrical connection with the substrate during the packaging process; the chip circuit is electrically connected to the capacitor structure or the inductor structure in the sensing area 211 for processing the fingerprint information acquired by the sensing area 211 and Output.
- a cover layer 203 is formed on the first surface 210 of the substrate 200, and the cover layer 203 has a thickness of less than 100 micrometers.
- the cover layer 203 is used to protect the surface of the sensing area 211.
- at least one capacitor plate is formed in the sensing region 211.
- the subsequently formed plug structure is located in the sensing chip region 201 of the substrate 200 and penetrates the substrate 200 for enabling the sensing region 211 and the chip circuit to be electrically connected to an external circuit, when subsequently followed by independence
- the sensing chip area 201 is packaged, it is not necessary to additionally form a conductive structure on the first surface 210 of the sensing chip area 201.
- the cover layer 203 is formed on the first surface 210 of the substrate 200, so that the cover layer 203 can be cut together with the substrate 200, and then only need to be
- the second surface 220 of the independent sensing chip region 201 formed by the cutting is fixed on the surface of the substrate, and the plug structure is electrically connected to the substrate, that is, the package structure can be formed, the packaging method of the fingerprint identification chip can be simplified, and the package formed
- the structure is simple, which is advantageous for reducing the size of the package structure.
- the cover layer 203 can be formed in the peripheral region in addition to the surface of the sensing region 211. 212 surface, and does not affect the subsequent packaging process, therefore, after the cover layer 203 is formed on the surface of the substrate 200, the cover layer 203 need not be etched for patterning, which not only simplifies the process, but also reduces the The damage of the first surface 210 of the substrate 200 is advantageous for ensuring accurate fingerprint information acquired by the sensing area 211.
- the material of the cover layer 203 is an inorganic nano material, a polymer material, a glass material or a ceramic material, and the forming process is a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a screen printing process, a spin coating process or a spraying process. Process.
- the material of the cover layer 203 is a polymer material
- the polymer material is an epoxy resin, a polyimide resin, a benzocyclobutene resin, a polybenzoxazole resin, a poly pair.
- the formation process of the cover layer 203 is a screen printing process, a spin coating process or a spray coating process.
- the material of the cover layer 203 is an inorganic nano material, and the inorganic nano
- the rice material is alumina or cobalt oxide;
- the coating layer 203 is formed by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a screen printing process, a spin coating process or a spray process.
- the material of the cover layer 203 is a glass material or a ceramic material. These materials are hard materials, and the cover layer 203 needs to be fixed to the first surface of the substrate 200 by an adhesive layer.
- the adhesive layer has adhesiveness, and the adhesive layer can be a capacitive screen adhesive.
- the cover layer 203 has a Mohs hardness of greater than or equal to 8H.
- the hardness of the cover layer 203 is high. Therefore, even if the thickness of the cover layer 203 is thin, the cover layer 203 is sufficient to protect the sensing area 211 of the sensing chip area 201 when the user's finger is on the surface of the cover layer 203. When moving, no damage is caused to the surface of the sensing chip area 201.
- the hardness of the cover layer 203 is high, the cover layer 203 is difficult to be deformed, and even if the user's finger presses against the surface of the cover layer 203, the thickness of the cover layer 203 is hard to change, thereby ensuring The detection result of the sensing area 211 is accurate.
- the cover layer 203 has a dielectric constant greater than or equal to 7. Since the dielectric constant of the cover layer 203 is large, the electrical isolation capability of the cover layer 203 is strong, and the cover layer 203 has a strong protection capability for the sensing area 211.
- the cover layer 203 has a thickness of 20 micrometers to 200 micrometers.
- the thickness of the cover layer 203 is relatively thin.
- the sensing area 211 is more likely to detect the fingerprint of the user's finger. Thereby the requirement for high sensitivity to the sensing region 211 is reduced.
- the capacitance between the user's finger and the capacitor plate is inversely proportional to the thickness of the cover layer 203, and is proportional to the dielectric constant of the cover layer 203. Therefore, when the thickness of the cover layer 203 is higher than that of the cover layer 203, When the dielectric constant is large, the capacitance between the user's finger and the capacitor plate can be detected within the range that the sensing region 211 can detect, and the detection of the sensing region 211 is prevented from being invalid if the capacitance value is too large or too small.
- the thickness of the cover layer 203 is in the range of 20 ⁇ m to 200 ⁇ m and the dielectric constant is in the range of greater than or equal to 7, the thickness of the cover layer 203 is increased, and the cover layer 203 is The dielectric constant is also increased correspondingly, and the capacitance between the user's finger and the capacitor plate can be made larger. The capacitance value is more easily detected by the sensing area 211.
- a via 250 is formed in the sensing chip region 201 of the substrate 200, and the top of the via 250 is located on the second surface 220 of the substrate 200.
- the through hole 250 is used to form a conductive structure, that is, a conductive layer or a conductive plug, and the conductive layer or the conductive plug is used for a trench plug structure, and the plug structure is used for sensing during the packaging process. Electrical connection between the chip and the substrate.
- the forming process of the via hole 250 includes: forming a mask layer (not shown) on the second surface 220 of the substrate 200, the mask layer exposing a corresponding position and shape that needs to form a plug structure;
- the mask layer is a mask, the substrate 200 is etched, and a via hole 250 is formed in the substrate 200; after the via hole 250 is formed, the mask layer is removed.
- the mask layer is exposed.
- the second surface 220 of the substrate 200 corresponding to the position of the first pad 213, and the process of etching the substrate 200 is performed until the surface of the first pad 213 is exposed.
- the mask layer can be a patterned photoresist layer, and can also be a patterned hard mask.
- the material of the hard mask is one or more of silicon oxide, silicon nitride, and silicon oxynitride.
- the process of etching the substrate 200 is an anisotropic dry etching process, and the etching gas includes one or more of SF 6 , CH 4 , CHF 3 , and CH 3 F;
- the side wall of the 250 is perpendicular to the surface of the substrate 200, or the side wall of the through hole 250 is inclined with respect to the surface of the substrate 200, and the top size of the through hole 250 is larger than the bottom size.
- a plug structure 204 is formed in the through hole 250 (shown in FIG. 4).
- One end of the plug structure 204 is electrically connected to the sensing region 211, and the substrate 202 is The second surface 220 exposes the other end of the plug structure 204.
- the plug structure 204 is formed in the through hole 250 and is located on the surface of the first pad 213.
- the plug structure 204 is electrically connected to the first pad 213, thereby implementing the sensing area. Electrical connection of 211.
- One end surface of the plug structure 204 and the second surface of the substrate 200 220 flushing enables the plug structure 204 to be electrically connected to an external circuit other than the substrate 200, thereby enabling the sensing region 211 and the chip circuit to be electrically connected to an external circuit.
- the plug structure 204 includes: a through hole 250 located in the substrate 200, a top of the through hole 250 is located at the second surface 220 of the substrate 200; An insulating layer 240 on the surface of the sidewall of the 250; a conductive layer 241 on the surface of the insulating layer 240 and a bottom surface of the through hole 250, and a conductive layer 241 located at the bottom of the through hole 241 is electrically connected to the sensing region 211; A solder resist layer 242 on the surface of the conductive layer 241 is filled, and the solder resist layer 242 fills the through hole.
- the forming method of the plug structure 204 includes: forming an insulating layer 240 on a sidewall surface of the through hole 250; on a second surface 220 of the substrate 200, a surface of the insulating layer 240, and a through hole 250 Forming a conductive film on the bottom surface; forming a solder resist film on the surface of the conductive film, the solder resist film filling the through hole 250; polishing the solder resist film and the conductive film until the substrate 200 is exposed A conductive layer 241 and a solder resist layer 242 are formed in the via hole 250 up to the second surface 220.
- the material of the insulating layer 240 is silicon oxide, silicon nitride, silicon oxynitride or a high-k dielectric material, and the insulating layer 240 is used for electrically isolating between the conductive layer 241 and the substrate 200; the conductive layer 241
- the material is a metal, and the metal is one or a combination of copper, tungsten, aluminum, titanium, titanium nitride, tantalum, and tantalum nitride.
- the conductive layer 241 does not fill the through hole. Therefore, it is required to form a solder resist layer 242 on the surface of the conductive layer 241, and the solder resist layer 242 fills the through hole to The stable plug structure 204 is formed.
- the solder resist material is a polymer material or an inorganic insulating material, and the polymer material can be an insulating resin, and the inorganic insulating material can be silicon oxide, silicon nitride or silicon oxynitride.
- the method further includes: forming a wiring layer 221 and a metal bump 222 on the second surface 220 of the substrate 200, the wiring layer 221 being connected to the conductive layer 241 and the metal bump 222 And the wiring layer 221 and the metal bump 222 are located on the surface of the sensing chip region 201.
- the material of the wiring layer 221 and the metal bump 222 is a metal such as copper, tungsten or aluminum for enabling the plug structure 204 to be electrically connected to an external circuit other than the substrate 200.
- the plug structure 204 includes: a through hole in the substrate 200, a top of the through hole is located at the second surface 220 of the substrate 200; Said An insulating layer 240 on the sidewall surface of the via; a conductive plug 243 on the surface of the insulating layer 240 and a bottom surface of the via, the conductive plug 243 filling the via.
- the material of the insulating layer 240 is silicon oxide, silicon nitride, silicon oxynitride or a high-k dielectric material, and the insulating layer 240 is used for electrically isolating between the conductive plug 243 and the substrate 200;
- the material of the plug 243 is a metal, and the metal is one or a combination of copper, tungsten, aluminum, titanium, titanium nitride, tantalum, and tantalum nitride.
- the method further includes forming a metal bump 223 on top of the conductive plug 243 exposed by the second surface 220 of the substrate 200.
- the metal bumps 223 are used to enable the plug structure 204 to be electrically connected to external circuitry external to the substrate 200.
- a cap layer can also be formed on the first surface of the substrate after the plug structure is formed within the substrate.
- an embodiment of the present invention further provides a wafer level fingerprint identification chip package structure formed by the above method.
- a substrate 200 including a plurality of sensing chip regions 201, The substrate 200 has a first surface 210 and a second surface 220 opposite to the first surface 210.
- the sensing chip region 201 includes a sensing region 211 on the first surface 210; on the first surface of the substrate 200.
- a cover layer 203 of 210 has a thickness of less than 100 ⁇ m; a plug structure 204 located in the sensing chip region 201 of the substrate 200, and one end of the plug structure 204 and the sensing region 211 are electrically Connected, and the second surface 220 of the substrate 200 exposes the other end of the plug structure 204.
- the substrate 200 is a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, and the substrate 200 is a whole wafer. .
- the sensing chip area 201 is used to form a sensing chip, and the sensing chip is used for packaging, and several sensing chip areas 201 in the substrate 200 are arranged in an array.
- the substrate 200 further includes a dicing area 202 between the adjacent sensing chip regions 201. By cutting the dicing area 202, the sensing chip regions 201 can be independent of each other to form an induction. chip.
- the sensing area 211 of the first surface 210 of the sensing chip area 201 is used for detecting and receiving fingerprint information of a user, and the sensing area 211 has a capacitor structure or an inductive structure for acquiring user fingerprint information, and is located at the A cover layer 203 of the first surface 210 of the substrate 200 serves to protect the sensing region 211.
- the sensing area 211 has at least one capacitor plate.
- the capacitor plate, the cover layer 203 and the user's finger constitute a capacitor structure, and the sensing The area 211 is capable of acquiring a difference in capacitance value between the surface ridges of the user's finger and the valley and the capacitor plate, and outputting the difference in capacitance value through the chip circuit for output, thereby acquiring user fingerprint data.
- the sensing chip area 201 further includes a peripheral area 212 on the first surface 210 and surrounding the sensing area 211.
- the peripheral area 212 has a chip circuit and a first pad 213 therein.
- the circuit is electrically connected to the capacitive structure or the inductive structure in the sensing region 211 for processing the electrical signal output by the capacitive structure or the inductive structure.
- the chip circuit is electrically connected to the sensing region 211 and the first pad 213, and one end of the plug structure 204 is connected to the first pad 213, thereby implementing the plug structure 204 and the
- the electrical connection between the sensing regions 211 and the second surface 220 of the substrate 200 expose the plug structure 204. Therefore, the first structure of the substrate 200 can be located through the plug structure 204.
- An electrical connection is made between the sensing region 211 of 210 and an external circuit other than the substrate 200.
- the plug structure 204 is located in the substrate 200, and in the embodiment, the plug structure 204 is located in a corresponding area of the peripheral area 212, and the sensing area 211 can be realized by the plug structure 204. Electrical connection with an external circuit other than the substrate 200, therefore, when packaging is performed using the separate sensing chip region 201, there is no need to provide an additional conductive structure on the first surface 210 of the sensing chip region 201, thereby enabling Prior to cutting the substrate 200, the cover layer 203 is covered at a first surface 210 of the substrate 200 such that the cover layer 203 is cut along with the substrate 200.
- the cover layer 203 can be located in the peripheral area 212 and the dicing road in addition to the surface of the sensing area 211.
- the surface of the region 202 because the area covered by the cover layer 203 is large, the formation process of the cover layer 203 is simple, and the process of forming the cover layer 203 does not be the first to the sensing chip area 201.
- the surface 210 causes damage, and the subsequent process of packaging by the separate sensing chip area 201 is simple.
- the package structure is formed by the independent sensing chip region 201, it is not necessary to provide an additional conductive structure on the first surface 210 of the sensing chip region 201. Therefore, the first surface 210 of the sensing chip region 201 is flat. That is, the surface of the sensing region 211 and the peripheral region 212 are flush, and there is no need to form an additional edge groove in the peripheral region 212 to form a conductive structure connected to the sensing region 211, so that the wafer level fingerprint identification chip is formed.
- the structure of the structure is simple and the process is simplified.
- the material of the cover layer 203 is a polymer material, an inorganic nano material or a ceramic material.
- the material of the cover layer 203 is an inorganic nano material, and the inorganic nano material includes aluminum oxide or cobalt oxide; the cover layer 203 can be subjected to a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition. Formed by a process, screen printing process, spray process or spin coating process.
- the material of the cover layer 203 is a polymer material, which is an epoxy resin, a polyimide resin, a benzocyclobutene resin, a polybenzoxazole resin, and a poly Butylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene - Vinyl acetate copolymer, polyvinyl alcohol or other suitable polymeric material; the cover layer 203 can be formed by a screen printing process, a spray coating process or a spin coating process.
- the cover layer 203 has a Mohs hardness of greater than or equal to 8H.
- the hardness of the cover layer 203 is high. Therefore, even if the thickness of the cover layer 203 is thin, the cover layer 203 is sufficient to protect the sensing area 211 of the sensing chip 201 when the user's finger moves on the surface of the cover layer 203. When the surface of the sensor chip 201 is not damaged.
- the hardness of the cover layer 203 is high, the cover layer 203 is difficult to be deformed, and even if the user's finger presses against the surface of the cover layer 203, the thickness of the cover layer 203 is hard to change, thereby ensuring The detection result of the sensing area 211 is accurate.
- the cover layer 203 has a dielectric constant greater than or equal to 7. Since the dielectric constant of the cover layer 203 is large, the electrical isolation capability of the cover layer 203 is strong, and the cover layer 203 has a strong protection capability for the sensing area 211.
- the cover layer 203 has a thickness of 20 micrometers to 200 micrometers.
- the thickness of the cover layer 203 is relatively thin.
- the sensing area 211 is more likely to detect the fingerprint of the user's finger. Thereby, the requirement for high sensitivity of the sensing chip 201 is lowered.
- the capacitance between the user's finger and the capacitor plate is inversely proportional to the thickness of the cover layer 203, and is proportional to the dielectric constant of the cover layer 203. Therefore, when the thickness of the cover layer 203 is higher than that of the cover layer 203, When the dielectric constant is large, the capacitance between the user's finger and the capacitor plate can be detected within the range that the sensing region 211 can detect, and the detection of the sensing region 211 is prevented from being invalid if the capacitance value is too large or too small.
- the thickness of the cover layer 203 is in the range of 20 ⁇ m to 200 ⁇ m and the dielectric constant is in the range of greater than or equal to 7, the thickness of the cover layer 203 is increased, and the cover layer 203 is The dielectric constant is also increased correspondingly, and the capacitance value between the user's finger and the capacitor plate can be made larger, and the capacitance value is more easily detected by the sensing area 211.
- the plug structure 204 includes: a through hole in the substrate 200, a top of the through hole is located at the second surface 220 of the substrate 200; and a sidewall of the through hole
- the surface of the insulating layer 240; the conductive layer 241 on the surface of the insulating layer 240 and the bottom surface of the through hole, the conductive layer 241 located at the bottom of the through hole 241 is electrically connected to the sensing region 211;
- the material of the insulating layer 240 is silicon oxide, silicon nitride, silicon oxynitride or a high-k dielectric material, and the insulating layer 240 is used for electrically isolating between the conductive layer 241 and the substrate 200; the conductive layer 241
- the material is metal, and the metal is one or a combination of copper, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride; in the embodiment, the conductive layer 241 is not filled.
- the through hole therefore, needs to form a solder resist layer 242 on the surface of the conductive layer 241, the solder resist layer 242 fills the through hole to form a stable plug structure 204, and the solder resist material is polymerized Material or inorganic insulating material,
- the polymeric material can be an insulating resin, which can be silicon oxide, silicon nitride or silicon oxynitride.
- the wafer level fingerprint identification chip structure further includes: a wiring layer 221 and a metal bump 222 on the second surface 220 of the substrate 200, and the wiring layer 221 is connected to the conductive layer 241 and the metal bump 222, and The wiring layer 221 and the metal bump 222 are located on the surface of the sensing chip region 201.
- the wiring layer 221 and the metal bumps 222 are used to enable the plug structure 204 to be electrically connected to an external circuit outside the substrate 200.
- the plug structure 204 includes: a through hole in the substrate 200, a top of the through hole is located at the second surface 220 of the substrate 200; An insulating layer 240 on the sidewall surface of the via; a conductive plug 243 on the surface of the insulating layer 240 and a bottom surface of the via, the conductive plug 243 filling the via.
- the material of the insulating layer 240 is silicon oxide, silicon nitride, silicon oxynitride or a high-k dielectric material, and the insulating layer 240 is used for electrically isolating between the conductive layer 241 and the substrate 200; the conductive plug
- the material of 243 is a metal, and the metal is one or a combination of copper, tungsten, aluminum, titanium, titanium nitride, tantalum, and tantalum nitride.
- the wafer level fingerprint identification chip structure further includes a metal bump 223 located on top of the conductive plug 243 exposed by the second surface 220 of the substrate 200.
- the metal bumps 223 are used to enable the plug structure 204 to be electrically connected to external circuitry external to the substrate 200.
- FIG. 7 to FIG. 14 are schematic cross-sectional structural views of a wafer level fingerprint identification chip packaging process according to an embodiment of the present invention.
- a substrate 200 is provided.
- the substrate 200 includes a plurality of sensing chip regions 201 having a first surface 310 and a second surface 320 opposite the first surface 310.
- the sensing chip area 201 includes a sensing area 311 on the first surface 310.
- a plug structure 303 is formed in the sensing chip area 201 of the substrate 200. One end of the plug structure 303 is electrically connected to the sensing area 311. And the second surface 320 of the substrate 200 exposes the other end of the plug structure 303.
- a cover layer 302 is formed on the first surface 310 of the substrate 200, the cover layer 302 having a thickness of less than 100 microns.
- the sensing chip regions 201 are arranged in an array, and the adjacent sensing chip regions 201 further have a dicing street region 202 therebetween.
- the sensing chip region 201 is further formed on the first surface 311 with a peripheral region 312 surrounding the sensing region 311.
- the peripheral region 312 is formed with a chip circuit and a first pad 313.
- the circuit is electrically connected to the sensing region 311 and the first pad 313.
- the plug structure 303 includes: a through hole in the sensing chip 301, a top of the through hole is located at the second surface 320 of the substrate 200; and the sidewall of the through hole is located An insulating layer 330 on the surface; a conductive layer 331 on the surface of the insulating layer 330 and a bottom surface of the through hole; a conductive layer 331 located at the bottom of the through hole is electrically connected to the sensing region 311; and is located on the surface of the conductive layer 331
- the solder resist layer 332 fills the through hole.
- the method further includes: forming a wiring layer 321 and a metal bump 322 on the second surface of the substrate, the wiring layer 321 and the conductive layer 331 and the metal The bumps 322 are connected, and the wiring layer 321 and the metal bumps 322 are located on the surface of the sensing chip region 201.
- the plug structure 303 includes: a through hole in the sensing chip 301, a top of the through hole is located on the second surface 320 of the sensing chip 301; The insulating layer 330 of the sidewall surface of the through hole; the conductive plug 333 on the surface of the insulating layer 330 and the bottom surface of the through hole, and the conductive plug 333 fills the through hole.
- the material, structure and formation process of the substrate 200, the plug structure 303 and the cover layer 302 are as described in the corresponding embodiments of FIGS. 2 to 6 and will not be described herein.
- the substrate 200 (shown in FIG. 7) and the cover layer 302 are cut, so that a plurality of sensing chip regions 201 (shown in FIG. 7) are separated from each other to form a plurality of independent sensing chips 301.
- the sensing chip 301 has a first surface and a second surface 320 opposite to the first surface 310.
- the sensing chip 301 includes a sensing area 311 on the first surface 310, and the first surface of the sensing chip 301 310 has a cover layer 302.
- the process of cutting the substrate 200 and the cover layer 302 includes: in the dicing area 202
- the substrate 200 and the cap layer 302 are diced (as shown in FIG. 7) such that the plurality of sensing chip regions 201 are separated from each other to form a plurality of independent sensing chips 301.
- the cover layer 302 can be cut while the substrate 200 is being cut, so that each of the formed independent sensing chips is formed.
- the first surface 310 of the 301 is covered by the cover layer 302. Therefore, the sensing chip 301 is only required to be electrically connected to the substrate, that is, the package structure can be formed, so that the method for forming the package structure of the fingerprint identification chip is simplified.
- the formed package structure is simple, which is advantageous for reducing the size of the package structure.
- a substrate 300 is provided.
- the substrate 300 is a rigid substrate or a flexible substrate, and the substrate 300 can be adjusted to be a rigid substrate or a flexible substrate by using a device or a terminal of the sensing chip 301 as needed.
- the substrate 300 is a rigid substrate, and the rigid substrate is a PCB substrate, a glass substrate, a metal substrate, a semiconductor substrate, or a polymer substrate.
- the substrate 300 has a first side 330, and the first side 330 of the substrate 300 has a plurality of second pads 331 and a wiring layer (not shown), and the wiring layer is connected to the second pad 331
- the second pad 331 is connected to the chip circuit of the first surface 310 of the sensing chip 301 , so that the sensing chip 301 is coupled to the first side 330 of the substrate 300 .
- one end of the substrate 300 has a connecting portion 304.
- the material of the connecting portion 304 includes a conductive material, and the connecting portion 304 is electrically connected to the wiring layer, so that the sensing region 311 on the surface of the sensing chip 301 can be Electrically connected to an external circuit or device to enable the transmission of electrical signals.
- a sensing chip 301 is coupled to the substrate 300 , and a second surface 320 of the sensing chip 301 faces the substrate 300 .
- the method of coupling the sensing chip 301 on the substrate 300 includes: exposing the second surface 320 of the sensing chip 301 One end of the plug structure 303 is soldered to the substrate 300, and the plug structure 303 is electrically connected to the substrate 300.
- the first side 330 of the substrate 300 has a second pad 331.
- the sensing chip 301 is fixed to the first side 330 of the substrate 300, and the second surface of the sensing chip 301 is The exposed plug structure 303 is soldered to the surface of the second pad 331 to achieve electrical connection between the sensing chip 301 and the substrate 300.
- a guard ring 305 is formed on the substrate 300, and the guard ring 305 surrounds the sensing chip 301 and the cover layer 302.
- the material of the guard ring 305 is metal, and the guard ring 305 is grounded through the substrate 300.
- the guard ring 305 is fixed to the first side 330 of the substrate 300.
- the guard ring 305 is located around the sensing chip 301 and the cover layer 302, and a portion of the guard ring 305 also extends over the cover layer 302 and exposes a partial coverage on the sensing area 311. Layer 305 surface.
- the guard ring is only located around the sensing chip 301 and the cover layer 302 and completely exposes the surface of the cover layer 302.
- the material of the guard ring 305 is a metal, and the metal is copper, tungsten, aluminum, silver or gold.
- the protection ring 305 is used for electrostatic protection of the sensor chip 301. Since the protection ring 305 is metal, the protection ring 305 can conduct electricity. When a user's finger contacts the cover layer 302 to generate static electricity, the electrostatic charge will be Firstly, the protection ring 305 is transmitted from the protection ring 305 to the substrate 300, thereby preventing the cover layer 302 from being broken by an excessive electrostatic voltage, thereby protecting the sensing chip 301, improving the accuracy of fingerprint detection, eliminating signal noise generated by the sensing chip, and making the sensing The signal output from the chip is more accurate.
- a housing 306 is formed surrounding the sensing chip 301, the cover layer 302 and the guard ring 305, and the housing 306 exposes the surface of the sensing area 311.
- the housing 306 can be a housing of a device or terminal provided with the fingerprint identification chip, and can also be a housing of the package structure of the fingerprint identification chip.
- a casing 307 is formed surrounding the sensing chip 301 and the cover layer 302, and the casing 307 exposes the surface of the sensing region 311.
- Cover layer 302. The housing 307 is used to protect the sensing chip 301 and the cover layer 302. Moreover, since the sensing chip 301 is fixed to the substrate 300 through the plug structure 303 in this embodiment, the sensing chip 301 can No need to fix with plastic sealing material, The housing 307 is used to electrically isolate the sensing chip 301 from the external environment.
- a full insulating material such as a molding material, is filled between the sensing chip 301 and the substrate 300 for protecting the wiring layer 321, the metal bumps 322, and the second.
- the pad 331 is used to fix the bonding strength between the enhancement sensor chip 301 and the substrate 300.
- the embodiment of the present invention further provides a fingerprint identification chip package structure.
- a fingerprint identification chip package structure including: a substrate 300; a sensing chip 301 coupled to the substrate 300, the sensing chip 301 having a first surface 310, and The sensing chip 301 includes a sensing area 311 on the first surface 310, the second surface 320 of the sensing chip 301 faces the substrate 300, and the sensing chip 301 is located on the second surface 320 of the first surface 310.
- a cover layer 302 of a surface 310 has a thickness of less than 100 micrometers; a plug structure 303 located in the sensing chip 301, one end of the plug structure 303 is electrically connected to the sensing region 311, The second surface 320 of the sensing chip 301 exposes the other end of the plug structure 303, and the plug structure 303 exposed by the second surface 320 of the sensing chip 301 is connected to the substrate 300.
- the sensing area 311 of the first surface 310 of the sensing chip 301 is used for detecting and receiving fingerprint information of a user.
- the sensing area 311 has a capacitor structure or an inductive structure for acquiring user fingerprint information, and the sensing area is located at the sensing area 311.
- the cover layer 302 of the first surface 310 of the chip 301 is used to protect the sensing area 311.
- the sensing area 311 has at least one capacitor plate.
- the capacitor plate, the cover layer 302 and the user's finger constitute a capacitor structure, and the sensing The area 311 is capable of acquiring a difference in capacitance value between the surface ridges of the user's finger and the valley and the capacitor plate, and outputting the difference in capacitance value through the chip circuit for output, thereby acquiring user fingerprint data.
- the sensing chip 301 further includes a peripheral region 312 on the first surface 310 and surrounding the sensing region 311.
- the peripheral region 312 has a chip circuit and a first pad 313 therein. Electrically connected to the capacitor structure or the inductor structure in the sensing region 311 for the capacitor junction The electrical signal output by the structure or the inductive structure is processed.
- the chip circuit is electrically connected to the sensing region 311 and the first pad 313, and one end of the plug structure 303 is connected to the first pad 313, thereby implementing the plug structure 303 and the
- the electrical connection between the sensing regions 311 and the second surface 320 of the substrate 200 expose the plug structure 303. Therefore, the first structure of the substrate 200 can be located through the plug structure 303.
- the sensing region 311 of 310 is electrically connected to an external circuit other than the substrate 200.
- the sensing chip 301 is fixed to the substrate 300, so that the sensing chip 301 can be electrically connected to other devices or circuits through the substrate 300.
- the second surface 320 of the sensing chip 301 exposes one end of the plug structure 303, and the sensing chip 301 is fixed to the substrate 300 through the plug structure 303.
- the substrate 300 is a rigid substrate or a flexible substrate, and the device or the terminal of the sensor chip 301 can be provided as needed, and the substrate 300 is adjusted to be a rigid substrate or a flexible substrate.
- the substrate 300 is a rigid substrate, and the rigid substrate is a PCB substrate, a glass substrate, a metal substrate, a semiconductor substrate, or a polymer substrate.
- the substrate 300 has a first side 330, and the first side 330 of the substrate 300 has a plurality of second pads 331 and a wiring layer (not shown), and the wiring layer is connected to the second pad 331
- the second pad 331 is connected to the chip circuit of the first surface 310 of the sensing chip 301 , so that the sensing chip 301 is coupled to the first side 330 of the substrate 300 .
- the plug structure 303 exposed by the second surface 320 of the sensing chip 301 is soldered to the surface of the second pad 331 to fix the sensing chip 301 to the first side 330 of the substrate 300, and
- the sensing region 311 located on the first surface 301 of the sensing chip 301 is electrically connected to the wiring layer on the substrate 300 through the plug structure 303.
- one end of the substrate 300 has a connecting portion 304.
- the material of the connecting portion 304 includes a conductive material, and the connecting portion 304 is electrically connected to the wiring layer, so that the sensing region 311 on the surface of the sensing chip 301 can be Electrically connected to an external circuit or device to enable the transmission of electrical signals.
- the material of the cover layer 302 is a polymer material, an inorganic nano material or a ceramic material.
- the material of the cover layer 302 is an inorganic nano material including alumina or cobalt oxide; the cover layer 302 can be formed by a printing process, a spraying process or a spin coating process.
- the material of the cover layer 302 is a polymer material, which is an epoxy resin, a polyimide resin, a benzocyclobutene resin, a polybenzoxazole resin, and a poly Butylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene - Vinyl acetate copolymer, polyvinyl alcohol or other suitable polymeric material; the cover layer 302 can be formed by a printing process, a spray coating process, or a spin coating process.
- the cover layer 302 can be formed by a printing process, a spray coating process, or a spin coating process.
- the cover layer 302 has a Mohs hardness of greater than or equal to 8H.
- the hardness of the cover layer 302 is relatively high. Therefore, even if the thickness of the cover layer 302 is thin, the cover layer 302 is sufficient to protect the sensing area 311 of the sensing chip 301 when the user's finger moves on the surface of the cover layer 302. At the time, damage to the surface of the sensor chip 301 is not caused.
- the hardness of the cover layer 302 is high, the cover layer 302 is difficult to be deformed, and even if the user's finger is pressed against the surface of the cover layer 302, the thickness of the cover layer 302 is hard to change, thereby ensuring that the thickness of the cover layer 302 is changed.
- the detection result of the sensing area 311 is accurate.
- the cover layer 302 has a dielectric constant greater than or equal to 7. Since the dielectric constant of the cover layer 302 is large, the electrical isolation capability of the cover layer 302 is strong, and the cover layer 302 has a strong protection capability for the sensing area 311.
- the cover layer 302 has a thickness of 20 micrometers to 200 micrometers.
- the thickness of the cover layer 302 is relatively thin.
- the sensing area 311 can more easily detect the fingerprint of the user's finger. Thereby, the requirement for high sensitivity of the sensor chip 301 is lowered.
- the capacitance between the user's finger and the capacitor plate is inversely proportional to the thickness of the cover layer 302, and is proportional to the dielectric constant of the cover layer 302. Therefore, when the thickness of the cover layer 302 is greater than When the dielectric constant is large, the capacitance between the user's finger and the capacitor plate can be detected within the range that the sensing region 311 can detect, and the sensing region 311 is prevented from being too large or too small. The detection failed.
- the thickness of the cover layer 302 is in the range of 20 ⁇ m to 200 ⁇ m and the dielectric constant is in the range of greater than or equal to 7, the thickness of the cover layer 302 is increased, and the cover layer 302 is The dielectric constant is also increased correspondingly, and the capacitance value between the user's finger and the capacitor plate can be made larger, and the capacitance value is more easily detected by the sensing area 311.
- the plug structure 303 is located in the sensing chip 301, and in the embodiment, the plug structure 303 is located in a corresponding area of the peripheral area 312, and the sensing area 311 can be realized by the plug structure 303. Electrical connection with the wiring layer on the substrate 300. Therefore, when the sensing chip 301 is packaged, it is not necessary to provide an additional conductive structure on the first surface 310 of the sensing chip 301, so that the fingerprint identification chip package The structure is simple, and it is advantageous to reduce the size of the package structure.
- the cover layer 302 Since the first surface 310 of the sensing chip 301 is completely covered by the cover layer 302, the cover layer 302 is not covered by the first surface 310 of the sensing chip 301 after the sensing chip 301 is fixed to the substrate 300. The process of avoiding the formation of the cap layer 302 causes damage to the first surface 310 of the inductive chip 301.
- the plug structure 303 includes: a through hole in the sensing chip 301, a top of the through hole is located at the second surface 320 of the substrate 200; and the sidewall of the through hole is located An insulating layer 330 on the surface; a conductive layer 331 on the surface of the insulating layer 330 and a bottom surface of the through hole; a conductive layer 331 located at the bottom of the through hole is electrically connected to the sensing region 311; and is located on the surface of the conductive layer 331
- the solder resist layer 332 fills the through hole.
- the material of the insulating layer 330 is silicon oxide, silicon nitride, silicon oxynitride or a high-k dielectric material, and the insulating layer 330 is used for electrically isolating between the conductive layer 331 and the substrate 200; the conductive layer 331
- the material is a metal, and the metal is one or a combination of copper, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride; in the embodiment, the conductive layer 331 is not filled.
- the through hole therefore, needs to form a solder resist layer 332 on the surface of the conductive layer 331, the solder resist layer 332 fills the through hole to form a stable plug structure 303, and the solder resist material is polymerized Material or inorganic insulating material, the polymer material can be an insulating resin, and the inorganic insulating material can be silicon oxide, silicon nitride or Silicon oxynitride.
- the fingerprint identification chip package structure further includes a wiring layer 321 and a metal bump 322 located on the second surface 320 of the sensing chip 301, and the wiring layer 321 is connected to the conductive layer 331 and the metal bump 322 block.
- the wiring layer 321 and the metal bumps 322 are used to enable the plug structure 303 to be electrically connected to an external circuit outside the substrate 200.
- the plug structure 303 includes: a through hole in the sensing chip 301, a top of the through hole is located on the second surface 320 of the sensing chip 301; The insulating layer 330 of the sidewall surface of the through hole; the conductive plug 333 on the surface of the insulating layer 330 and the bottom surface of the through hole, and the conductive plug 333 fills the through hole.
- the material of the insulating layer 330 is silicon oxide, silicon nitride, silicon oxynitride or a high-k dielectric material, and the insulating layer 330 is used for electrically isolating between the conductive plug 333 and the sensing chip 301;
- the material of the plug 333 is a metal, and the metal is one or a combination of copper, tungsten, aluminum, titanium, titanium nitride, tantalum, and tantalum nitride.
- the fingerprint identification chip package structure includes a metal bump 323 located on the top of the conductive plug 333 exposed by the second surface 320 of the sensor chip 301.
- the metal bumps 323 are used to enable the plug structure 303 to be electrically connected to an external circuit outside the substrate 200.
- the fingerprint identification chip package structure further includes a protection ring 305 on the substrate 300 , and the protection ring 305 surrounds the induction chip 301 and the cover layer 302 .
- the material of the guard ring 305 is metal, and the guard ring 305 is grounded through the substrate 300.
- the guard ring 305 is fixed to the first side 330 of the substrate 300.
- the guard ring 305 is located around the sensing chip 301 and the cover layer 302, and a part of the guard ring 305 also extends over the cover layer 302 and exposes a partial coverage on the sensing area 311. Layer 305 surface.
- the guard ring is only located around the sensing chip 301 and the cover layer 302 and completely exposes the surface of the cover layer 302.
- the material of the guard ring 305 is a metal, and the metal is copper, tungsten, aluminum, silver or gold. Said The protection ring 305 is used for electrostatic protection of the sensor chip 301. Since the protection ring 305 is metal, the protection ring 305 can conduct electricity. When the user's finger contacts the cover layer 302, static electricity is generated. The protection ring 305 is transmitted to the substrate 300, thereby preventing the cover layer 302 from being broken by an excessive electrostatic voltage, thereby protecting the sensor chip 301, improving the accuracy of fingerprint detection, eliminating signal noise outputted by the sensor chip, and outputting the sensor chip. The signal is more precise.
- the fingerprint identification chip package structure further includes: a housing 306 surrounding the sensing chip 301, the cover layer 302 and the guard ring 305, the housing 306 exposing the surface of the sensing area 311 Cover layer 302.
- the housing 306 can be a housing of a device or terminal provided with the fingerprint identification chip, and can also be a housing of the package structure of the fingerprint identification chip.
- the fingerprint identification chip package structure further includes: a casing 307 surrounding the sensing chip 301 and the cover layer 302, the casing 307 exposing the surface of the sensing area 311 Layer 302.
- the housing 307 is used to protect the sensing chip 301 and the cover layer 302.
- the sensing chip 301 can There is no need to fix with a molding material that is used to electrically isolate the sensing chip 301 from the external environment.
- the substrate 300 can also have a plastic sealing layer surrounding the sensing chip 301.
- the plastic sealing layer exposes the sensing area 311 of the sensing chip 301, and the plastic sealing layer is used to protect the sensing layer.
- the chip 301 electrically isolates the sensing chip 301 from the external environment.
- the embodiment of the invention can simplify the packaging method of the fingerprint identification chip, reduce the requirement for the sensitivity of the sensing chip, and make the application of the packaging method wider.
- the substrate has a plurality of sensing chip regions, and by cutting the substrate, the plurality of sensing chip regions can be separated from each other to form an independent sensing chip. .
- the sensing area of the first surface of the sensing chip area is used for acquiring fingerprint information
- the cover layer formed on the first surface of the substrate is used to replace the traditional glass substrate, directly contact the user's finger, and protect the sensing chip. Since the thickness of the cover layer is thinner than that of the conventional glass substrate, the distance from the first surface of the sensor chip to the surface of the cover layer can be reduced, so that the sensor chip can easily detect the fingerprint of the user, and accordingly, the pair is reduced. Sensing chip sensitivity requirements
- the package structure of the pattern recognition chip is more widely used.
- the plug structure can be electrically connected to an external circuit through which the plug structure
- the sensing chip can be coupled to the external circuit, so that it is not necessary to form an additional conductive structure on the first surface of the sensing chip, so that a cover layer can be formed on the first surface of the substrate, the cover layer is used to protect the sensing area, and Will not affect the progress of the subsequent process.
- the formed wafer level fingerprint identification chip structure can simplify the packaging process of the fingerprint identification chip, and can reduce damage to the sensing area, and ensure accurate fingerprint information acquired by the sensing area.
- a cover layer is formed on the first surface of the sensing chip to replace the conventional glass substrate for directly contacting the user's finger and protecting the sensing chip. Since the thickness of the cover layer is thinner than that of the conventional glass substrate, the distance from the first surface of the sensor chip to the surface of the cover layer can be reduced, so that the sensor chip can easily detect the fingerprint of the user, and accordingly, the pair is reduced.
- the sensitivity requirements of the sensing chip make the packaging structure of the fingerprint identification chip more widely used.
- a plug structure is formed in the substrate, the second surface of the substrate exposing the plug structure, enabling the plug structure to be electrically connected to the substrate, and thus, After the sensing chip is coupled to the substrate, it is not necessary to form an additional conductive structure on the first surface of the sensing chip, and therefore, a cover layer can be formed on the first surface of the substrate before the substrate is cut, the cover layer being used for protection The sensing area, and the cover layer is cut while cutting to form the sensing chip. Therefore, it is not necessary to form the cover layer after coupling the sensing chip to the surface of the substrate, which can simplify the packaging method of the fingerprint identification chip, reduce damage to the sensing area, and ensure accurate fingerprint information acquired by the sensing area. In addition, the formed package structure can be simplified, which is advantageous for reducing the size of the package structure formed.
- the Mohs hardness of the cover layer is greater than or equal to 8H, and the hardness of the cover layer is high. Even if the cover layer on the surface of the sensing area is thin, the cover layer still has sufficient strength to protect the induction. When the user's finger is placed on the surface of the cover layer on the sensing area, the cover layer is less likely to be deformed or worn, so that the extraction result of the user's fingerprint is more accurate.
- the cover layer has a dielectric constant of 7 to 9.
- the cover layer has a large dielectric constant, so that The electrical isolation property of the cover layer is better, and the cover layer has better protection ability to the sensing area. Even if the cover layer on the surface of the sensing area is thin, the electrical separation between the user's finger and the sensing area can be performed. The ability is strong, and the capacitance between the user's finger and the sensing area is large, and is within a range that can be detected.
- the substrate further has a guard ring surrounding the sensing chip and the cover layer.
- the protection ring is used for electrostatic protection of the sensing chip to prevent the accuracy of the user fingerprint data detected by the sensing area from decreasing, or to eliminate signal noise outputted by the sensing chip, and the data detected by the sensing chip and the output signal. more accurate.
- the sensing chip area of the substrate has a plug structure, one end of the plug structure is electrically connected to the sensing area, and the substrate is The second surface exposes the other end of the plug structure, and thus electrical connection between the sensing region and an external circuit other than the sensing chip region can be achieved by the plug structure.
- the plug structure is located in the substrate, and there is no need to additionally provide a conductive line for electrical connection between the sensing chip area and the external circuit, and thus, the package structure is formed by a separate sensing chip area. In time, it is advantageous to reduce the size of the formed package structure.
- the cover layer can be disposed on the first surface of the substrate, and the cover layer can directly The user touches the finger to protect the sensing area.
- the wafer level fingerprint identification chip has a simple structure, and the subsequent easy to form a package structure with independent sensing chip regions.
- the cover layer is located on the first surface of the sensing chip, and the cover layer is used to replace the traditional glass substrate and can directly contact the user's finger for protecting the sensing chip.
- the cover layer can be thinner, and the cover layer can reduce the distance from the first surface of the sensor chip to the surface of the cover layer, so that the sensor chip can easily detect the user fingerprint, correspondingly
- the package structure reduces the sensitivity of the sensing chip, and the packaging structure of the fingerprint identification chip is more widely used.
- the sensing chip further has a plug structure, one end of the plug structure is electrically connected to the sensing region, and the second surface of the sensing chip exposes the other end of the plug structure, so The plug structure exposed by the second surface of the sensing chip, The sensing chip can be fixed to the substrate, and electrical connection between the sensing region and the substrate can be realized.
- the packaging structure is simple and easy to assemble, the manufacturing cost of the packaging structure is reduced, and the yield is improved.
Abstract
Description
Claims (25)
- 一种芯片封装结构,包括:感应芯片,所述感应芯片包括第一表面、以及与所述第一表面相对的第二表面,所述感应芯片还包括位于第一表面的感应区,所述感应芯片的第二表面面向基板;位于所述感应芯片第一表面上的覆盖层;位于所述感应芯片内的插塞结构,所述插塞结构的一端与所述感应区电连接,所述感应芯片的第二表面暴露出所述插塞结构的另一端。
- 如权利要求1所述的芯片封装结构,其中,所述芯片封装结构还包括基板,所述插塞结构的所述另一端与所述基板电连接。
- 如权利要求2所述的芯片封装结构,其中,所述基板的一端具有连接部,所述连接部用于使感应芯片与外部电路电连接。
- 如权利要求1所述的芯片封装结构,其中,所述覆盖层的莫氏硬度大于或等于8H,所述覆盖层的介电常数大于或等于7。
- 如权利要求1所述的芯片封装结构,其中,所述覆盖层的材料包括无机纳米材料、聚合物材料、玻璃材料和陶瓷材料中的至少一种。
- 如权利要求5所述的芯片封装结构,其中,所述聚合物材料包括环氧树脂、聚酰亚胺树脂、苯并环丁烯树脂、聚苯并恶唑树脂、聚对苯二甲酸丁二酯、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚乙烯、聚丙烯、聚烯烃、聚氨酯、聚烯烃、聚醚砜、聚酰胺、聚亚氨酯、乙烯-醋酸乙烯共聚物和聚乙烯醇中的至少一种。
- 如权利要求5所述的芯片封装结构,其中,所述无机纳米材料包括氧化铝和氧化钴中的至少一种。
- 如权利要求1所述的芯片封装结构,其中,所述感应芯片还包括位于第一表面且包围所述感应区的外围区,所述外围区具有芯片电路和第一焊垫, 所述芯片电路与所述感应区和所述第一焊垫电连接,所述插塞结构的一端与所述第一焊垫电连接。
- 如权利要求2所述的芯片封装结构,其中,所述基板具有第一侧面,所述基板的第一侧面具有多个第二焊垫,所述插塞结构的所述另一端与所述第二焊垫电连接。
- 如权利要求2所述的芯片封装结构,还包括位于所述基板上的保护环,所述保护环包围所述感应芯片和覆盖层。
- 如权利要求10所述的芯片封装结构,还包括包围所述感应芯片、覆盖层和保护环的外壳,所述外壳暴露出感应区上的部分覆盖层。
- 一种晶圆级芯片封装结构,包括:衬底,所述衬底包括多个感应芯片区,所述衬底具有第一表面、以及与所述第一表面相对的第二表面,所述感应芯片区包括位于第一表面的感应区;位于衬底第一表面上的覆盖层;位于所述衬底的感应芯片区的插塞结构,所述插塞结构的一端与所述感应区电连接,且所述衬底的第二表面暴露出所述插塞结构的另一端。
- 一种晶圆级芯片封装方法,包括:提供衬底,所述衬底包括多个感应芯片区,所述衬底具有第一表面、以及与所述第一表面相对的第二表面,所述感应芯片区包括位于第一表面的感应区;在所述衬底的第一表面上形成覆盖层;在所述衬底的感应芯片区形成插塞结构,所述插塞结构的一端与所述感应区电连接,且所述衬底的第二表面暴露出所述插塞结构的另一端。
- 如权利要求13所述的晶圆级芯片封装方法,其中,所述覆盖层的莫氏硬度大于或等于8H,所述覆盖层的介电常数大于或等于7。
- 如权利要求13所述的晶圆级芯片封装方法,其中,所述覆盖层的材料包括 无机纳米材料、聚合物材料、玻璃材料和陶瓷材料中的至少一种。
- 如权利要求15所述的晶圆级芯片封装方法,其中,所述聚合物材料包括环氧树脂、聚酰亚胺树脂、苯并环丁烯树脂、聚苯并恶唑树脂、聚对苯二甲酸丁二酯、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚乙烯、聚丙烯、聚烯烃、聚氨酯、聚烯烃、聚醚砜、聚酰胺、聚亚氨酯、乙烯-醋酸乙烯共聚物和聚乙烯醇中的至少一种。
- 如权利要求16所述的晶圆级芯片封装方法,其中,所述覆盖层通过丝网印刷工艺、旋涂工艺或喷涂工艺形成。
- 如权利要求15所述的晶圆级芯片封装方法,其中,所述无机纳米材料包括氧化铝和氧化钴中的至少一种。
- 如权利要求18所述的晶圆级芯片封装方法,其中,所述覆盖层通过化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺、丝网印刷工艺、旋涂工艺或喷涂工艺形成。
- 如权利要求13所述的晶圆级芯片封装方法,其中,形成插塞结构包括:在所述衬底的第二表面形成掩膜层;以所述掩膜层为掩膜,刻蚀所述衬底,形成通孔;在所述通孔内形成插塞结构。
- 如权利要求13所述的晶圆级芯片封装方法,其中,所述感应芯片区还包括位于第一表面且包围所述感应区的外围区,所述外围区具有芯片电路和第一焊垫,所述芯片电路与所述感应区和所述第一焊垫电连接,所述插塞结构的一端与所述第一焊垫电连接。
- 如权利要求13所述的晶圆级芯片封装方法,还包括:对所述衬底和覆盖层进行切割,使所述多个感应芯片区相互分立,形成独立的感应芯片,所述感应芯片具有第一表面、以及与所述第一表面相对的第二表面,所述感应芯片包括位于第一表面的感应区,且所述感应芯片的第 一表面上具有覆盖层;提供基板;将感应芯片与所述基板耦合,所述感应芯片的第二表面面向基板。
- 如权利要求22所述的晶圆级芯片封装方法,其中,所述基板具有第一侧面,所述基板的第一侧面具有多个第二焊垫,所述插塞结构的所述另一端与所述第二焊垫电连接。
- 如权利要求22所述的晶圆级芯片封装方法,还包括:在所述基板上形成保护环,所述保护环包围所述感应芯片和覆盖层。
- 如权利要求24所述的晶圆级芯片封装方法,还包括:形成包围所述感应芯片、覆盖层和保护环的外壳,所述外壳暴露出感应区上的部分覆盖层。
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CN104201115A (zh) | 2014-12-10 |
KR20170051498A (ko) | 2017-05-11 |
TWI626598B (zh) | 2018-06-11 |
US10126151B2 (en) | 2018-11-13 |
US20170284837A1 (en) | 2017-10-05 |
TW201610862A (zh) | 2016-03-16 |
KR101963395B1 (ko) | 2019-07-31 |
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