WO2015198877A1 - 撮像素子および撮像素子の駆動方法、電子機器、並びにプログラム - Google Patents
撮像素子および撮像素子の駆動方法、電子機器、並びにプログラム Download PDFInfo
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- WO2015198877A1 WO2015198877A1 PCT/JP2015/066831 JP2015066831W WO2015198877A1 WO 2015198877 A1 WO2015198877 A1 WO 2015198877A1 JP 2015066831 W JP2015066831 W JP 2015066831W WO 2015198877 A1 WO2015198877 A1 WO 2015198877A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/767—Horizontal readout lines, multiplexers or registers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
Definitions
- the present technology relates to an imaging device, an imaging device driving method, an electronic device, and a program, and more particularly, to an imaging device, an imaging device driving method, an electronic device, and a program that can improve image quality.
- a conventional CMOS (Complementary Metal Oxide Semiconductor) image sensor has a read control signal line TR (0 to m: m) connected to the gate of the read transistor in order to improve pixel characteristics when the pixel signal read transistor is turned off.
- the negative voltage VRL generated by the charge pump is inputted through an identifier for identifying the readout row. That is, since all the pixel signal readout transistors are OFF except for the readout row, the negative voltage VRL is input to almost all readout control signal lines.
- the vertical transfer line VSL (0 to n: n is an identifier for identifying the vertical transfer line VSL).
- the floating diffusion FD (0 to i: i is an identifier for identifying the floating diffusion FD) and a coupling component, the vertical transfer line VSL (0 to n) and the floating diffusion FD (0 to i)
- the fluctuation component of the negative voltage VRL degrades the pixel data of the vertical transfer lines VSL (0 to n).
- the coupling amount and the transfer load increase in proportion to the number of pixels, which is disadvantageous for increasing the size of the image sensor.
- the present technology has been made in view of such circumstances, and in particular, can improve the image quality by suppressing the fluctuation of the negative voltage without increasing the negative voltage capacity.
- An image sensor includes a plurality of photodiodes that generate charges according to the intensity of incident light for each pixel, a read transistor that reads charges generated by the photodiodes, and the read transistor is turned on.
- a first negative voltage supply unit that supplies a negative voltage to the read transistor if not, and a second negative voltage supply unit that supplies a negative voltage to the read transistor if the read transistor is not turned on, The first negative voltage generator and the second negative voltage generator are switched to supply the negative voltage.
- the negative voltage is supplied by the first negative voltage supply unit, and otherwise, the negative voltage is switched by the second negative voltage supply unit. You can make it.
- a pulse generator for generating a pulse signal can be further included.
- the first negative signal is generated.
- the negative voltage can be supplied from the second negative voltage supply unit by the voltage supply unit.
- the first negative voltage supply unit and the second negative voltage supply unit may have a first negative voltage capacity and a second negative voltage capacity, respectively.
- the first negative voltage capacity and the second negative voltage capacity can be charged by a charge pump circuit.
- the read transistors in the other non-selected rows from the first negative voltage supply unit with respect to the read transistors in the row sharing the floating diffusion with the transistors in the read row On the other hand, the negative voltage can be supplied by switching from the second negative voltage supply unit.
- the negative voltage can be supplied from the first negative voltage supply unit to the predetermined proportion of the non-selected rows at a predetermined interval.
- An image sensor driving method includes: a plurality of photodiodes that generate charges according to the intensity of incident light for each pixel; a read transistor that reads charges generated by the photodiode; and the read transistor A first negative voltage supply unit that supplies a negative voltage to the read transistor, and a second negative voltage supply unit that supplies a negative voltage to the read transistor when the read transistor is not turned on.
- An image pickup device including a first negative voltage generation unit and a second negative voltage generation unit that are switched to supply the negative voltage.
- a program includes a plurality of photodiodes that generate charges according to incident light intensity for each pixel, a read transistor that reads charges generated by the photodiode, and the read transistor is not turned on.
- An imaging device including a first negative voltage supply unit that supplies a negative voltage to the read transistor and a second negative voltage supply unit that supplies a negative voltage to the read transistor when the read transistor is not turned on.
- the computer to be controlled causes the first negative voltage generation unit and the second negative voltage generation unit to perform a process of switching and supplying the negative voltage.
- An electronic device includes a plurality of photodiodes that generate charges according to the intensity of incident light for each pixel, a read transistor that reads charges generated by the photodiodes, and the read transistor is turned on.
- a first negative voltage supply unit that supplies a negative voltage to the read transistor
- a second negative voltage supply unit that supplies a negative voltage to the read transistor when the read transistor is not turned on, The first negative voltage generator and the second negative voltage generator are switched to supply the negative voltage.
- charges corresponding to the intensity of incident light are generated for each pixel by a plurality of photodiodes, and the charges generated by the photodiodes are read by a read transistor, and the first negative
- a negative voltage is supplied to the read transistor.
- a negative voltage is supplied to the read transistor.
- the first negative voltage generator and the second negative voltage generator are switched to supply the negative voltage.
- the imaging device may be an independent device or a block that performs imaging processing.
- FIG. 1 It is a figure which shows the structural example of one Embodiment of the drive circuit of the image pick-up element to which this technique is applied. It is a figure explaining the structure of a general drive circuit. It is a figure explaining operation
- 2 is a timing chart for explaining the operation of the drive circuit in FIG. 1. It is a timing chart explaining the operation
- FIG. 11 is a diagram illustrating a configuration example of a general-purpose personal computer.
- FIG. 1 shows a configuration example of an embodiment of an image sensor driving circuit to which the present technology is applied.
- the drive circuit in FIG. 1 is a drive circuit that drives an image pickup device mounted on an electronic apparatus such as an image pickup apparatus or a mobile phone, and is a circuit that supplies a negative voltage VRL to a read transistor that is turned off.
- the drive circuit of FIG. 1 includes a pulse generation control unit 31, an inverter 32, charge pump circuits 33-1 and 33-2, negative voltage capacitors 34-1 and 34-2, a V scanner 35, and a selection transistor 36. , An amplification transistor 37, a reset transistor 38, a readout transistor 39, and a photodiode 40.
- each of the charge pump circuits 33-1 and 33-2 is a circuit that generates a negative voltage VRL to be supplied to the read transistor 39 that is set to OFF.
- the negative voltage capacitors 34-1 and 34-2 are charged.
- the negative voltages charged in the negative voltage capacitors 34-1 and 34-2 are referred to as negative voltages VRL1 and VRL2.
- the V scanner 35 switches the negative voltages VRL1 and VRL2, which are the charging voltages of the negative voltage capacitors 34-1 and 34-2, and supplies them to the read transistors 39 in the rows that are not in the read state. More specifically, the V scanner 35 includes transistors 51-1 and 51-2.
- the V scanner 35 receives a pulse signal generated by the pulse generation control unit 31 as an input to the gate of the transistor 51-1 and an inverter 32. To the gate of the transistor 51-2. With such a configuration, for example, when the transistors 51-1 and 51-2 are Hi active, when the pulse supplied from the pulse generation control unit 31 is Hi, the transistor 51-1 is controlled to be on, The transistor 51-2 is controlled to be turned off.
- the transistor 51-1 is controlled to be off and the transistor 51-2 is controlled to be on.
- the V scanner 35 switches and outputs the negative voltage VRL1 or VRL2 according to the pulse Hi or Low generated by the pulse generation controller 31.
- the drive circuit shown in FIG. 1 supplies a negative voltage VRL to be supplied to the gate of the read transistor 39 which is set to OFF. Naturally, although not shown, the read transistor 39 is turned on. There is also a configuration for supplying the power supply voltage VDD supplied when the read transistor 39 is turned on, and the read transistor 39 is switched at a timing controlled to be turned on or off.
- the charge pump circuits 33-1 and 33-2 may be combined into 1 and supplied to both the negative voltage capacitors 34-1 and 34-2.
- the read transistor 39 When the read transistor 39 is turned on, the charge generated in the photodiode 40 is transferred to the floating diffusion FD.
- the floating diffusion FD outputs the accumulated charge to the gate of the amplification transistor 37.
- the amplification transistor 37 outputs a pixel signal corresponding to the amount of charge transferred from the floating diffusion FD to the selection transistor 36.
- the selection transistor 36 When the selection transistor 36 is turned on, the selection transistor 36 transfers the pixel signal output from the amplification transistor 37 via the vertical transfer line VSL.
- FIG. 2 is a diagram showing a configuration of a general drive circuit.
- symbol and a name shall be attached
- the configuration that is the difference between the drive circuit of the present technology and the general drive circuit in FIG. 1 is a configuration in which only one charge pump circuit 33 and one negative voltage capacitor 34 are provided.
- the transistors 51-1 and 51-2 and the inverter 32 are not provided.
- the amplification transistors 37-1 to 37-4, the reset transistor 38-1, the read transistors 39-1 to 39-4 and photodiodes 40-1 to 40-4 are respectively configured.
- the selection transistor 36, the amplification transistor 37, the reset transistor 38, the reading transistor 39, and the photodiode 40 are simply referred to, and the other configurations are also referred to similarly.
- the floating diffusion CFDO is commonly used for four pixels.
- Amplifying units 71-1 to 71-4 are provided in each row, and voltages for turning on or off the read transistors 39-1 to 39-4 are supplied to the respective gates via control signal lines TR0 to TR3.
- the amplification unit 71 supplies a power supply voltage VDD (not shown) to the gate of the read transistor 39 when the read transistor 39 is turned on, and reads the negative voltage VRL when the read transistor 39 is turned off. This is supplied to the gate of the transistor 39.
- the vertical transfer line VSL0 in FIG. 3 transfers the charge signal transferred via the floating diffusion FD from any of the photodiodes 40-1 to 40-4 in the 0 column via the amplification transistor 37-1.
- the vertical transfer line VSLN receives a charge signal transferred from a floating diffusion FD (not shown) from an N column photodiode 40-N (not shown), and an amplification transistor 37-N (not shown). ) Through.
- the read transistors 39-1 to 39-3 of the control signal lines TR0 to TR2 in the first to third rows in the vertical direction in FIG. 3 are turned off (non-selected rows), and the control signal line TR3 in the fourth row is turned on.
- the amplifying unit 71-4 supplies the power supply voltage VDD to the gate of the read transistor 39-4.
- the amplifying units 71-1 to 71-3 supply the negative voltage VRL supplied from the V scanner 35 to the reading transistors 39-1 to 39-3.
- the reset operation is performed, and the vertical transfer line voltages VSL0 and VSLN of the vertical transfer line VSL0 are both in the zero state.
- the offset amount in the reset state is counted and read by the counter DAC.
- the displacement ⁇ VRL and the displacement ⁇ VSLN satisfy the following expression (1).
- ⁇ VRL ⁇ VSLN ⁇ CVSL_TRN / (CVRL + CVSL_TRN) ... (1)
- ⁇ VRL is the displacement of the negative voltage VRL in FIG. 4
- ⁇ VSLN is the displacement of the vertical transfer line voltage VSLN in FIG. 4
- CVSL_TRN is the read transistor 39-N in the Nth column with the vertical transfer line VSLN.
- CVRL is the capacity of the negative voltage capacity 34.
- the vertical transfer line voltage VSL0 in the 0th column which should be the black region, drops by the displacement ⁇ VSL0 along with the displacement ⁇ VRL of the negative voltage VRL.
- the displacement ⁇ VSL0 satisfies the relationship satisfying the following equation (2) with the displacement ⁇ VRL.
- the displacement ⁇ VSL0 is the displacement of the vertical transfer line voltage VSL0 in the 0th column of FIG. 4
- ⁇ VFD0 is the displacement of the charging voltage of the floating distortion FD in the 0th row
- ⁇ VRL is the displacement of FIG.
- CFD0_TR0 to CFD0_TR2 are respectively the vertical transfer line VSLN and the output lines of the amplifying units 71-1 to 71-3 to the read transistors 39-1 to 39-3 in the first to third rows.
- This is a coupling capacitance
- CFD0 is the capacitance of the floating diffusion FD.
- streaking is a phenomenon in which only the region Z1 having the same height in the horizontal direction as the region Z0 is recognized as an image that appears to be brightly colored as if it is white, not completely black. Will occur.
- the horizontal axis is the time axis
- the vertical axis indicates the negative voltage VRL
- the dotted line indicates the transfer voltage VSLN of the Nth pixel column in the horizontal direction
- the one-dot chain line indicates The transfer voltage VSL0 of the pixel column at the left end in the horizontal direction is shown.
- the pixel signal is read out from time t2 to t3, and the exposed pixel signal is read out by the counter DAC.
- the displacement ⁇ VRL of the negative voltage VRL can be countered by increasing the negative voltage capacity CVRL to some extent, but the displacement ⁇ VRL cannot be completely suppressed. Further, the coupling capacity and the transfer load are in proportion to the number of pixels, which is disadvantageous for increasing the size of the image sensor.
- streaking may occur in a general driving circuit. Therefore, the streaking is suppressed by the following operation in the driving circuit of FIG.
- the operating conditions are the same as those described above.
- the reset process is performed from time t0 to t21, and the pulse generation control unit 31 does not generate a drive pulse. That is, in this case, the transistor 51-1 is turned on and the transistor 51-2 is turned off. As a result, the negative voltage VRL1 from the negative voltage capacitor 34-1 charged by the charge pump circuit 33-1 is output from the V scanner 35. In this case, the vertical transfer line voltages VSL0 and VSLN remain at 0. Further, during this period, the pixel value to be an offset is read out by the counter DAC.
- the pulse generation control unit 31 At time t21, which is the timing immediately before time t22 when exposure starts, the pulse generation control unit 31 generates a drive pulse. As a result, the transistor 51-1 is turned off and the transistor 51-2 is turned on. As a result, the negative voltage VRL2 from the negative voltage capacitor 34-2 charged by the charge pump circuit 33-2 is output from the V scanner 35.
- the pulse generation control unit 31 stops generating the drive pulse.
- the transistor 51-1 is turned on and the transistor 51-2 is turned off.
- the negative voltage VRL1 from the negative voltage capacitor 34-1 charged by the charge pump circuit 33-1 is output from the V scanner 35.
- the negative voltage VRL1 is not affected by fluctuations in the vertical transfer line voltages VSL0 and VSLN, and the original negative voltage VRL1 is output as it is, so that the displacement ⁇ VSL0 of the vertical transfer line voltage VSL0 becomes 0, 0.
- the pulse generation control unit 31 When the reading is completed at time t24, the pulse generation control unit 31 generates a drive pulse. As a result, the transistor 51-1 is turned off and the transistor 51-2 is turned on. As a result, the negative voltage VRL2 from the negative voltage capacitor 34-2 charged by the charge pump circuit 33-2 is output from the V scanner 35.
- the pixel signal is read out by switching to the negative voltage VRL2 during a predetermined period between the timing when the exposure is started and the timing when the reset is started, that is, the period when the vertical transfer line voltages VSL0 and VSLN fluctuate. During the period, the negative voltage VRL1 was switched.
- the negative voltage VRL1 is not affected by fluctuations due to the vertical transfer line voltages VSL0 and VSLN, and thus maintains a constant state.
- the negative voltage VRL2 fluctuates because it is affected by fluctuations by the vertical transfer line voltages VSL0 and VSLN.
- the negative voltage VRL1 is supplied only during the period in which the pixel signal is read without being affected by fluctuations, there will be no influence as a whole, so that the V scanner output is as shown in the lowermost stage of FIG.
- the vertical transfer line voltage VSL0 can be maintained at 0 in the read period, and as a result, the occurrence of streaking can be suppressed.
- RST reset
- VSL0 vertical transfer line voltages
- VSLN vertical transfer line voltages
- counter DAC drive pulse
- negative potential selection state negative voltage VRL1, VRL2
- negative voltages VRL1, VRL2 negative voltages
- the pixel area includes a pixel area that is an effective area including a pixel area that is used as a pixel signal, and a pixel area that includes a dummy area that is not used for the pixel signal.
- a difference in shutter load at the time of access becomes a difference in negative voltage consumption charge, resulting in a step, which is a so-called shutter step.
- the negative voltage VRL of the pixel in the effective region indicated by the dotted line at the time t0 when the reset pulse falls is The change is larger than the negative voltage VRL of the pixel in the dummy area indicated by the solid line.
- the vertical transfer line voltage VSL can be output as a stable voltage after time t41 when the fluctuation of the negative voltage VRL of the pixel in the dummy region converges.
- the voltage of the vertical transfer line voltage VSL drops according to the fluctuation of the negative voltage VRL.
- the driving circuit of FIG. 1 suppresses the shutter step by operating as shown in FIG.
- the pulse generation control unit 31 generates a drive pulse.
- the transistor 51-1 is turned off and the transistor 51-2 is turned on.
- the negative voltage VRL2 from the negative voltage capacitor 34-2 charged by the charge pump circuit 33-2 is output from the V scanner 35.
- the pixels in the effective area and the dummy area are brought into the shutter-on state.
- the negative voltage VRL2 that is, the output of the V scanner 35
- the negative voltage VRL2 increases as shown by the dotted lines in the lowermost stage and the second stage from the bottom in FIG.
- the negative voltage VRL2 that is, the output of the V scanner 35
- the pulse generation control unit 31 stops generating the drive pulse.
- the transistor 51-1 is turned on and the transistor 51-2 is turned off.
- the negative voltage VRL1 from the negative voltage capacitor 34-1 charged by the charge pump circuit 33-1 is output from the V scanner 35.
- the pulse generation control unit 31 generates a drive pulse at the timing when the global shutter is turned on.
- the transistor 51-1 is turned off and the transistor 51-2 is turned on.
- the negative voltage VRL2 from the negative voltage capacitor 34-2 charged by the charge pump circuit 33-2 is output from the V scanner 35.
- the negative voltage VRL1 is not affected by the fluctuation of the negative voltage VRL2, and thus a constant value is maintained.
- the pulse generation control unit 31 stops generating the drive pulse. As a result, the transistor 51-1 is turned on and the transistor 51-2 is turned off. As a result, the negative voltage VRL1 from the negative voltage capacitor 34-1 charged by the charge pump circuit 33-1 is output from the V scanner 35.
- the pixel signal is read out.
- the drive circuit for the image sensor in FIG. 10 sets the negative voltage VRL separately for the negative voltage VRLT and the negative voltage VRLS, and sets the negative voltage VRLT to the row sharing the floating diffusion of the readout row (selected row). And the negative voltage VRLS is supplied to the other non-selected rows. Furthermore, the drive circuit for the image sensor in FIG. 10 supplies the negative voltage VRLT to a part of the non-selected rows according to the degree of whitening. Thereby, streaking is appropriately suppressed.
- components having the same functions as those described with reference to FIGS. 1 and 3 are given the same reference numerals and names, and description thereof will be omitted as appropriate.
- the image sensor drive circuit of FIG. 10 is provided with charge pump circuits 33-1 and 33-2 and negative voltage capacitors 34-1 and 34-2, respectively, and the negative voltage VRLT,
- the negative voltage VRLS is output to the amplifying units 71-1 to 71-8.
- the selection unit 101 supplies any of the negative voltages VRLT and VRLS from the charge pump circuits 33-1 and 33-2 (negative voltage capacitors 34-1 and 34-2) to the amplification units 71-1 to 71-8. Select.
- the selecting unit 101 when the row corresponding to the amplifying unit 71-4 is a selected row that is a read-out row, the selecting unit 101 is negative to the amplifying units 71-1 to 71-3 in the row sharing the floating diffusion CFD0 with the selected row.
- Supply voltage VRLT An example in which the selection unit 101 supplies the negative voltage VRLS to the amplification units 71-5 to 71-8 corresponding to the non-selected rows that do not share the floating diffusion CFD0 of the selected row will be described.
- the selection unit 101 divides the negative voltage VRLT and the negative voltage VRLS for the shared row that is the non-selected row that shares the floating diffusion CFD0 of the selected row and the other non-selected rows, respectively. Supply. Accordingly, for example, as shown in FIG. 11, when exposure is started at time t151, even if the negative voltage VRLS drops due to the voltage drop of the vertical transfer line voltage VSLN, the negative voltage VRLT is set. Does not affect the vertical transfer line voltage VSL0. As a result, the signal is appropriately read even during the signal reading period from time t152 to t153.
- white floating is caused by the amplitude of the vertical transfer line voltage VSL0.
- a phenomenon called black sink occurs that creates a darker area.
- FIG. 12 shows changes in streaking that occur according to the amplitude of the vertical transfer line voltage VSL0. It has been shown that the white sink (white floating) decreases as the external capacity, which is a negative voltage capacity, increases. FIG. 12 shows changes when the external capacitance is 4.7 ⁇ F, 6.8 ⁇ F, and 10.0 ⁇ F. It is also shown that the black sun increases as the GND impedance increases. FIG. 12 shows changes when the GND impedance is 0.1 ⁇ , 0.2 ⁇ , and 0.3 ⁇ .
- the switching signal generation unit 102 intentionally adjusts the influence of the negative voltage to suppress the occurrence of the phenomenon such as white floating or black sink described above. Specifically, the switching signal generation unit 102 sets a predetermined ratio and a predetermined line interval to the lines allocated as any of the non-selected lines according to the evaluation value for white floating or black sun. A negative voltage VRLT from the charge pump circuit 33-1 is assigned.
- Such an operation makes it possible to adjust the degree of influence due to the fluctuation of the negative voltage and to suppress the occurrence of a phenomenon such as white floating or dark sinking.
- step S31 the selection unit 101 supplies the negative voltage VRLT from the charge pump circuit 33-1 to the amplifying unit 71 of the shared row sharing the floating diffusion of the selected row based on the selected row, and the others A negative voltage VRLS from the charge pump circuit 33-2 is supplied to a non-selected row. Therefore, in the case of FIG. 10, since the selected row is a row corresponding to the amplifying unit 71-4, the negative voltage VRLT from the charge pump circuit 33-1 is supplied to the amplifying units 71-1 to 71-3. The negative voltage VRLS from the charge pump circuit 33-2 is supplied to the amplification units 71-5 to 71-8 corresponding to the other non-selected rows.
- step S32 the degree of white float or dark sink in the image captured by the current image sensor is determined. Since there is an adjustable device for the degree of white floating or black sink in this image, the degree of white floating or black sink may be determined based on this evaluation value.
- step S33 the switching signal generation unit 102 performs charge pumping at a predetermined ratio and a predetermined row interval with respect to the amplifying unit 71 corresponding to the non-selected row according to the degree of white floating or darkening.
- a switching rate for switching to supply the negative voltage VRLS from the circuit 33-2 is set. Thereafter, based on the set switching rate, the negative voltage VRLS from the charge pump circuit 33-2 is supplied to the amplifying unit 71 corresponding to the non-selected row at a predetermined rate and at a predetermined row interval. Is supplied.
- the above-described series of processing can be executed by hardware, but can also be executed by software.
- a program constituting the software may execute various functions by installing a computer incorporated in dedicated hardware or various programs. For example, it is installed from a recording medium in a general-purpose personal computer or the like.
- FIG. 14 shows a configuration example of a general-purpose personal computer.
- This personal computer incorporates a CPU (Central Processing Unit) 1001.
- An input / output interface 1005 is connected to the CPU 1001 via a bus 1004.
- a ROM (Read Only Memory) 1002 and a RAM (Random Access Memory) 1003 are connected to the bus 1004.
- the input / output interface 1005 includes an input unit 1006 including an input device such as a keyboard and a mouse for a user to input an operation command, an output unit 1007 for outputting a processing operation screen and an image of the processing result to a display device, programs, and various types.
- a storage unit 1008 including a hard disk drive for storing data, a LAN (Local Area Network) adapter, and the like are connected to a communication unit 1009 that executes communication processing via a network represented by the Internet.
- magnetic disks including flexible disks
- optical disks including CD-ROM (Compact Disc-Read Only Memory), DVD (Digital Versatile Disc)), magneto-optical disks (including MD (Mini Disc)), or semiconductors
- a drive 1010 for reading / writing data from / to a removable medium 1011 such as a memory is connected.
- the CPU 1001 is read from a program stored in the ROM 1002 or a removable medium 1011 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, installed in the storage unit 1008, and loaded from the storage unit 1008 to the RAM 1003. Various processes are executed according to the program.
- the RAM 1003 also appropriately stores data necessary for the CPU 1001 to execute various processes.
- the CPU 1001 loads the program stored in the storage unit 1008 to the RAM 1003 via the input / output interface 1005 and the bus 1004 and executes the program, for example. Is performed.
- the program executed by the computer (CPU 1001) can be provided by being recorded on the removable medium 1011 as a package medium, for example.
- the program can be provided via a wired or wireless transmission medium such as a local area network, the Internet, or digital satellite broadcasting.
- the program can be installed in the storage unit 1008 via the input / output interface 1005 by attaching the removable medium 1011 to the drive 1010. Further, the program can be received by the communication unit 1009 via a wired or wireless transmission medium and installed in the storage unit 1008. In addition, the program can be installed in advance in the ROM 1002 or the storage unit 1008.
- the program executed by the computer may be a program that is processed in time series in the order described in this specification, or in parallel or at a necessary timing such as when a call is made. It may be a program for processing.
- the system means a set of a plurality of components (devices, modules (parts), etc.), and it does not matter whether all the components are in the same housing. Accordingly, a plurality of devices housed in separate housings and connected via a network and a single device housing a plurality of modules in one housing are all systems. .
- the present technology can take a cloud computing configuration in which one function is shared by a plurality of devices via a network and is jointly processed.
- each step described in the above flowchart can be executed by one device or can be shared by a plurality of devices.
- the plurality of processes included in the one step can be executed by being shared by a plurality of apparatuses in addition to being executed by one apparatus.
- this technique can also take the following structures.
- (1) a plurality of photodiodes that generate charges according to the intensity of incident light for each pixel; A read transistor for reading out the charge generated by the photodiode; A first negative voltage supply unit configured to supply a negative voltage to the read transistor when the read transistor is not turned on; A second negative voltage supply unit for supplying a negative voltage to the read transistor when the read transistor is not turned on; The imaging device in which the first negative voltage generator and the second negative voltage generator are switched to supply the negative voltage. (2) When the exposure of the photodiode is started and reset, the negative voltage is switched by the first negative voltage supply unit and otherwise by the second negative voltage supply unit.
- the imaging device according to (1).
- (3) further includes a pulse generator for generating a pulse signal;
- a pulse generator for generating a pulse signal;
- the imaging device according to (2) wherein the negative voltage is supplied by being switched respectively.
- the first negative voltage supply unit and the second negative voltage supply unit are respectively a first negative voltage capacity and a second negative voltage capacity.
- (1) to (3) The imaging device described.
- the first negative voltage supply unit supplies the read transistors in a row that shares floating diffusion with the transistors in the read row to other non-selected rows.
- a plurality of photodiodes that generate charges according to the intensity of incident light for each pixel;
- a read transistor for reading out the charge generated by the photodiode;
- a first negative voltage supply unit configured to supply a negative voltage to the read transistor when the read transistor is not turned on;
- a second negative voltage supply unit that supplies a negative voltage to the read transistor when the read transistor is not turned on.
- (9) a plurality of photodiodes that generate charges according to the intensity of incident light for each pixel;
- a read transistor for reading out the charge generated by the photodiode;
- a first negative voltage supply unit configured to supply a negative voltage to the read transistor when the read transistor is not turned on;
- a computer for controlling the imaging device including a second negative voltage supply unit that supplies a negative voltage to the readout transistor;
- the program which performs the process by which the said 1st negative voltage generation part and the said 2nd negative voltage generation part are switched, and the said negative voltage is supplied.
- (10) a plurality of photodiodes that generate charges according to the intensity of incident light for each pixel; A read transistor for reading out the charge generated by the photodiode; A first negative voltage supply unit configured to supply a negative voltage to the read transistor when the read transistor is not turned on; A second negative voltage supply unit for supplying a negative voltage to the read transistor when the read transistor is not turned on; An electronic apparatus in which the first negative voltage generator and the second negative voltage generator are switched to supply the negative voltage.
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Abstract
Description
図1は、本技術を適用した撮像素子の駆動回路の一実施の形態の構成例を示している。図1の駆動回路は、撮像装置や携帯電話機等の電子機器に搭載される撮像素子を駆動する駆動回路であり、オフにされている読み出しトランジスタに対して負電圧VRLを供給する回路である。
次に、図1の駆動回路の動作を説明するにあたって、一般的な駆動回路の構成と、その動作について説明する。
次に、図2の一般的な駆動回路の動作を説明する。
・・・(1)
・・・(2)
次に、図1の駆動回路における動作について説明する。
以上においては、ストリーキングを抑制する動作例について説明してきたが、有効領域のシャッタ負荷と、ダミー領域のシャッタ負荷との違いにより生じるシャッタ段差を抑制するように動作させるようにしてもよい。
以上においては、シャッタ段差に対策する例について説明してきたが、同様の技術を応用することにより、グローバルシャッタにおける負電圧VRLの復帰時間による読み出しに対する影響を対策することが可能となる。
以上においては、チャージポンプ回路を2系統設けて、負電圧VRLが変動するタイミングにおいて、一方に切り替え、それ以外のタイミングで他方に切り替えることにより、オフセットおよびデータを読み出すタイミングにおいて、負電圧VRLが変動しないようにする例について説明してきた。しかしながら、読み出し行のフローティングディフュージョンを共有する行と、非選択行とで、予め負電圧を分けて、それぞれ独立した負電圧VRL1,VRL2を供給するようにしてもよい。
次に、図10の撮像素子の駆動回路による調整処理について説明する。
(1) 画素毎に入射光の強度に応じた電荷を発生する複数のフォトダイオードと、
前記フォトダイオードにより発生された電荷を読み出す読み出しトランジスタと、
前記読み出しトランジスタがオンにされない場合、前記読み出しトランジスタに負電圧を供給する第1の負電圧供給部と、
前記読み出しトランジスタがオンにされない場合、前記読み出しトランジスタに負電圧を供給する第2の負電圧供給部とを含み、
前記第1の負電圧発生部と、前記第2の負電圧発生部とが、切り替えられて前記負電圧が供給される
撮像素子。
(2) 前記フォトダイオードの露光を開始するとき、およびリセットするとき、前記第1の負電圧供給部により、それ以外のとき、前記第2の負電圧供給部より、それぞれ切り替えられて前記負電圧が供給される
(1)に記載の撮像素子。
(3) パルス信号を発生するパルス発生部をさらに含み、
前記パルス発生部により発生されるパルスにより、前記フォトダイオードの露光を開始するとき、およびリセットするとき、前記第1の負電圧供給部により、それ以外のとき、前記第2の負電圧供給部より、それぞれ切り替えられて前記負電圧が供給される
(2)に記載の撮像素子。
(4) 前記第1の負電圧供給部、および第2の負電圧供給部は、それぞれ第1の負電圧容量、および第2の負電圧容量である
(1)乃至(3)のいずれかに記載の撮像素子。
(5) 前記第1の負電圧容量、および第2の負電圧容量は、チャージポンプ回路により充電される
(4)に記載の撮像素子。
(6) オンにされていない前記読み出しトランジスタのうち、読み出し行のトランジスタとフローティングディフュージョンを共有する行の前記読み出しトランジスタに対して、前記第1の負電圧供給部より、それ以外の非選択行の前記読み出しトランジスタに対して、前記第2の負電圧供給部より、それぞれ切り替えて前記負電圧が供給される
(1)に記載の撮像素子。
(7) 前記非選択行のうちの、所定の割合の行に、所定の間隔で、前記第1の負電圧供給部より、前記負電圧が供給される
(6)に記載の撮像素子。
(8) 画素毎に入射光の強度に応じた電荷を発生する複数のフォトダイオードと、
前記フォトダイオードにより発生された電荷を読み出す読み出しトランジスタと、
前記読み出しトランジスタがオンにされない場合、前記読み出しトランジスタに負電圧を供給する第1の負電圧供給部と、
前記読み出しトランジスタがオンにされない場合、前記読み出しトランジスタに負電圧を供給する第2の負電圧供給部とを含む撮像素子の駆動方法であり、
前記第1の負電圧発生部と、前記第2の負電圧発生部とが、切り替えられて前記負電圧が供給される
撮像素子の駆動方法。
(9) 画素毎に入射光の強度に応じた電荷を発生する複数のフォトダイオードと、
前記フォトダイオードにより発生された電荷を読み出す読み出しトランジスタと、
前記読み出しトランジスタがオンにされない場合、前記読み出しトランジスタに負電圧を供給する第1の負電圧供給部と、
前記読み出しトランジスタがオンにされない場合、前記読み出しトランジスタに負電圧を供給する第2の負電圧供給部とを含む撮像素子を制御するコンピュータに、
前記第1の負電圧発生部と、前記第2の負電圧発生部とが、切り替えられて前記負電圧が供給される
処理を実行させるプログラム。
(10) 画素毎に入射光の強度に応じた電荷を発生する複数のフォトダイオードと、
前記フォトダイオードにより発生された電荷を読み出す読み出しトランジスタと、
前記読み出しトランジスタがオンにされない場合、前記読み出しトランジスタに負電圧を供給する第1の負電圧供給部と、
前記読み出しトランジスタがオンにされない場合、前記読み出しトランジスタに負電圧を供給する第2の負電圧供給部とを含み、
前記第1の負電圧発生部と、前記第2の負電圧発生部とが、切り替えられて前記負電圧が供給される
電子機器。
Claims (10)
- 画素毎に入射光の強度に応じた電荷を発生する複数のフォトダイオードと、
前記フォトダイオードにより発生された電荷を読み出す読み出しトランジスタと、
前記読み出しトランジスタがオンにされない場合、前記読み出しトランジスタに負電圧を供給する第1の負電圧供給部と、
前記読み出しトランジスタがオンにされない場合、前記読み出しトランジスタに負電圧を供給する第2の負電圧供給部とを含み、
前記第1の負電圧発生部と、前記第2の負電圧発生部とが、切り替えられて前記負電圧が供給される
撮像素子。 - 前記フォトダイオードの露光を開始するとき、およびリセットするとき、前記第1の負電圧供給部により、それ以外のとき、前記第2の負電圧供給部より、それぞれ切り替えられて前記負電圧が供給される
請求項1に記載の撮像素子。 - パルス信号を発生するパルス発生部をさらに含み、
前記パルス発生部により発生されるパルスにより、前記フォトダイオードの露光を開始するとき、およびリセットするとき、前記第1の負電圧供給部により、それ以外のとき、前記第2の負電圧供給部より、それぞれ切り替えられて前記負電圧が供給される
請求項2に記載の撮像素子。 - 前記第1の負電圧供給部、および第2の負電圧供給部は、それぞれ第1の負電圧容量、および第2の負電圧容量である
請求項1に記載の撮像素子。 - 前記第1の負電圧容量、および第2の負電圧容量は、チャージポンプ回路により充電される
請求項4に記載の撮像素子。 - オンにされていない前記読み出しトランジスタのうち、読み出し行のトランジスタとフローティングディフュージョンを共有する行の前記読み出しトランジスタに対して、前記第1の負電圧供給部より、それ以外の非選択行の前記読み出しトランジスタに対して、前記第2の負電圧供給部より、それぞれ切り替えて前記負電圧が供給される
請求項1に記載の撮像素子。 - 前記非選択行のうちの、所定の割合の行に、所定の間隔で、前記第1の負電圧供給部より、前記負電圧が供給される
請求項6に記載の撮像素子。 - 画素毎に入射光の強度に応じた電荷を発生する複数のフォトダイオードと、
前記フォトダイオードにより発生された電荷を読み出す読み出しトランジスタと、
前記読み出しトランジスタがオンにされない場合、前記読み出しトランジスタに負電圧を供給する第1の負電圧供給部と、
前記読み出しトランジスタがオンにされない場合、前記読み出しトランジスタに負電圧を供給する第2の負電圧供給部とを含む撮像素子の駆動方法であり、
前記第1の負電圧発生部と、前記第2の負電圧発生部とが、切り替えられて前記負電圧が供給される
撮像素子の駆動方法。 - 画素毎に入射光の強度に応じた電荷を発生する複数のフォトダイオードと、
前記フォトダイオードにより発生された電荷を読み出す読み出しトランジスタと、
前記読み出しトランジスタがオンにされない場合、前記読み出しトランジスタに負電圧を供給する第1の負電圧供給部と、
前記読み出しトランジスタがオンにされない場合、前記読み出しトランジスタに負電圧を供給する第2の負電圧供給部とを含む撮像素子を制御するコンピュータに、
前記第1の負電圧発生部と、前記第2の負電圧発生部とが、切り替えられて前記負電圧が供給される
処理を実行させるプログラム。 - 画素毎に入射光の強度に応じた電荷を発生する複数のフォトダイオードと、
前記フォトダイオードにより発生された電荷を読み出す読み出しトランジスタと、
前記読み出しトランジスタがオンにされない場合、前記読み出しトランジスタに負電圧を供給する第1の負電圧供給部と、
前記読み出しトランジスタがオンにされない場合、前記読み出しトランジスタに負電圧を供給する第2の負電圧供給部とを含み、
前記第1の負電圧発生部と、前記第2の負電圧発生部とが、切り替えられて前記負電圧が供給される
電子機器。
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003348822A (ja) * | 2002-05-28 | 2003-12-05 | Sony Corp | 電圧変換制御回路及び方法 |
JP2005323331A (ja) * | 2004-02-23 | 2005-11-17 | Sony Corp | Ad変換方法およびad変換装置並びに物理量分布検知の半導体装置および電子機器 |
JP2008042305A (ja) * | 2006-08-02 | 2008-02-21 | Sony Corp | 撮像装置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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JP3951994B2 (ja) * | 2003-09-16 | 2007-08-01 | ソニー株式会社 | 固体撮像装置およびカメラシステム |
US7129883B2 (en) * | 2004-02-23 | 2006-10-31 | Sony Corporation | Method and apparatus for AD conversion, semiconductor device for detecting distribution of physical quantity, and electronic apparatus |
KR100621561B1 (ko) * | 2004-11-05 | 2006-09-19 | 삼성전자주식회사 | Cmos 이미지 센서 및 그 구동 방법 |
JP4848739B2 (ja) * | 2005-11-01 | 2011-12-28 | ソニー株式会社 | 物理量検出装置および撮像装置 |
JP4692262B2 (ja) * | 2005-12-14 | 2011-06-01 | ソニー株式会社 | 固体撮像装置、固体撮像装置の駆動方法および撮像装置 |
JP2008136047A (ja) * | 2006-11-29 | 2008-06-12 | Sony Corp | 固体撮像装置及び撮像装置 |
JP4494492B2 (ja) * | 2008-04-09 | 2010-06-30 | キヤノン株式会社 | 固体撮像装置及び固体撮像装置の駆動方法 |
CN101814912B (zh) * | 2009-02-25 | 2012-01-04 | 北京兆易创新科技有限公司 | 一种负电压电平转换电路 |
US7733126B1 (en) * | 2009-03-31 | 2010-06-08 | Freescale Semiconductor, Inc. | Negative voltage generation |
CN101924324B (zh) * | 2010-09-07 | 2012-05-23 | 凯钰科技股份有限公司 | 用以控制激光二极管的偏压电流的自动功率控制回路 |
CN102595059B (zh) * | 2012-02-27 | 2013-05-22 | 天津大学 | 一种多次曝光方法 |
-
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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JP2005323331A (ja) * | 2004-02-23 | 2005-11-17 | Sony Corp | Ad変換方法およびad変換装置並びに物理量分布検知の半導体装置および電子機器 |
JP2008042305A (ja) * | 2006-08-02 | 2008-02-21 | Sony Corp | 撮像装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113542637A (zh) * | 2016-07-29 | 2021-10-22 | 索尼公司 | 光检测装置 |
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