WO2015176367A1 - 显示器阵列基板的外围测试线路以及液晶显示面板 - Google Patents

显示器阵列基板的外围测试线路以及液晶显示面板 Download PDF

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WO2015176367A1
WO2015176367A1 PCT/CN2014/082101 CN2014082101W WO2015176367A1 WO 2015176367 A1 WO2015176367 A1 WO 2015176367A1 CN 2014082101 W CN2014082101 W CN 2014082101W WO 2015176367 A1 WO2015176367 A1 WO 2015176367A1
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test
test signal
signal line
passivation layer
passivation
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French (fr)
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付延峰
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/383,035 priority Critical patent/US9678372B2/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16504—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed
    • G01R19/16519—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed using FET's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2632—Circuits therefor for testing diodes
    • G01R31/2635—Testing light-emitting diodes, laser diodes or photodiodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing

Definitions

  • the present invention relates to the field of liquid crystal displays, and more particularly to a peripheral test line of a display array substrate and a liquid crystal display panel. Background technique
  • an epitaxial method is used to form millions of thin film transistors on a substrate to serve as a control unit.
  • some of the thin film transistors fail to produce the desired quality, As a result of failing to show its critical control characteristics, defects such as bright spots or dark spots are generated, which greatly reduces the quality of the liquid crystal display. Therefore, the thin film transistor must be effectively tested to maintain the quality of the liquid crystal display.
  • the connection structure between the test signal line and the test pad of the outer region of the TFT array substrate can be specifically referred to FIG.
  • the test signal line M1 in the peripheral region of the substrate passes through the passivation layer via VI connected to the test signal line M, and the passivation layer via hole V2 and the test pad lead connected to the test pad lead M2.
  • the M2 is connected and then connected to the corresponding test pad P.
  • the test pad leads M2 will inevitably span the other test signal lines M1, in the test signal lines M.
  • One of the technical problems to be solved by the present invention is to provide an external test circuit for a display array substrate, which can solve the problem that the test signal line and the test pad lead are easily short-circuited, and reduce the risk of electrostatic discharge.
  • a display array substrate and a liquid crystal display panel are also provided.
  • the present invention provides a test circuit for a display array substrate, comprising: a plurality of sets of test signal lines, each set of test signal lines being separated by a first test signal line and a second test signal Line composition: multiple test pad leads, each test pad lead is disposed at the interval between the first test signal line and the second test signal line of the corresponding group, and each test pad lead and the first test signal line and the second test The signal lines are connected, do not overlap with the first test signal lines and the second test signal lines of the other groups; a plurality of test pads, each of which is disposed on the corresponding test pad leads.
  • each test pad leads through The first passivation layer via and the second passivation via are non-overlapping with the corresponding set of first test signal lines, and each test pad lead passes through the third passivation via and the fourth passivation via Non-overlapping connection with the second test signal line of the corresponding group, wherein the first passivation layer via is a passivation layer via connected to the first test signal line of the ITO layer, and the second passivation layer via is ITO layer and the The passivation layer a hole of the test pad lead connection, the third passivation layer via hole is a passivation layer via hole of another ITO layer and the second test signal line, and the fourth passivation layer via hole is the other a layer of passivation layer vias connected to the test pad leads.
  • the plurality of test pad leads are arranged in parallel with each other.
  • first test signal line and the second test signal line of each group are vertically connected to respective test pad leads.
  • a display array substrate including: a display area; a peripheral test line located around the display area, the outer ring test line includes: a plurality of sets of test signal lines, each set of test signals The line is composed of a first test signal line and a second test signal line which are arranged at intervals; a plurality of test pad leads, each of which is disposed at a spacing between the first test signal line and the second test signal line of the corresponding group Each test pad lead is connected to the first test signal line and the second test signal line, and does not overlap with the first test signal line and the second test signal line of the other group; a plurality of test pads, each test pad is disposed at The corresponding test pad leads.
  • each test pad lead is non-overlappingly connected to the first set of test signal lines through the first passivation layer via and the second passivation via via, and each test pad lead passes the third blunt The via layer and the fourth passivation via are non-overlapping with the second test signal line of the corresponding group, wherein the first passivation via is a passivation layer connected to the first test signal line by the ITO layer
  • the second passivation layer via is a passivation layer via connecting the ITO layer and the test pad lead
  • the third passivation layer via is another: the germanium layer is connected to the second test signal line Passivation layer via, the fourth passivation via is a passivation layer via connected to the test pad lead.
  • the plurality of test pad leads are arranged in parallel with each other.
  • first test signal line and the second test signal line of each group are vertically connected to respective test pad leads.
  • liquid crystal display panel comprising the above-described display array substrate.
  • the peripheral test circuit of the present invention avoids the test pad lead by changing the connection manner of the test signal line and the test pad The occurrence of a crossover phenomenon with the test signal line, and at the junction of the test pad lead and the test signal line, the test pad lead is not crossed to the test signal line through the via.
  • FIG. 1 is a schematic diagram showing a connection structure of test signal lines and test pads in a peripheral region of a TFT array substrate in the prior art
  • FIG. 2 is a schematic diagram of a peripheral test circuit of a display array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a peripheral test circuit of a display array substrate according to an embodiment of the invention.
  • the peripheral test circuit includes: a plurality of sets of test signal lines, each set of test signal lines is composed of a first test signal line M1 and a second test signal line ⁇ arranged at intervals; a plurality of test pad leads M2 Each test pad lead M2 is disposed at an interval between the first test signal line M1 and the second test signal line M1' of the corresponding group, - each test pad lead M2 and the first test signal line M1 and the second test The signal line is connected to the first test signal line M1 and the second test signal line ⁇ ⁇ of the other groups; a plurality of test pads P, each of which is disposed on each of the test pad leads M2.
  • the test pad P can transmit the test signal generated by the signal generator to the corresponding data line or scan line through the test signal lines M l and ⁇ , to test whether the data line or the scan line is broken.
  • each test pad lead M2 is non-overlappingly connected to the first set of test signal lines M1 through the first passivation layer via VI and the second passivation via via V2, and each test The other end of the pad lead M2 is non-overlappingly connected to the second test signal line ⁇ of the corresponding group through the third passivation layer pupil V ' and the fourth passivation layer pupil V2', wherein the first purification layer via VI a passivation layer via hole connecting the ITO layer and the first test signal line M1, and a second passivation layer via hole V2 is a passivation layer via hole connected to one end of the test pad lead M2, the passivation layer The via VT is a passivation layer via connected to the second test signal line ⁇ , and the fourth passivation layer via V2' is connected to the other end of the test pad lead M2.
  • test pad leads Preferably, a plurality of test pad leads
  • the M2s are arranged in parallel with each other, and the first test signal line M1 and the second test signal line ⁇ of each group are vertically connected to the corresponding test pad leads M2, respectively, as shown in FIG.
  • the peripheral test circuit of the embodiment of the present invention improves the test pad bow in the existing external ID test circuit!
  • the line and the test signal line have overlapping overlaps, which are liable to cause electrostatic discharge, which causes the test pad leads to be shorted to the test signal line. It can reduce the risk of injury from electrostatic discharge, improve product test accuracy, and improve product yield.
  • the present invention also provides a display array substrate comprising a display area and a peripheral test line located around the display area, wherein the peripheral test line is a peripheral test line of the above structure.
  • the present invention also provides a liquid crystal display panel comprising the above-described display array substrate.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种显示器阵列基板的外围测试线路以及液晶显示面板。该显示器阵列基板的外围测试线路包括：多组测试信号线，每组测试信号线由隔开间隔设置的第一测试信号线（M1）和第二测试信号线（M1'）组成；多条测试垫引线（M2），每条测试垫引线（M2）设置在相应组的第一测试信号线（M1）和第二测试信号线（M1'）的间隔处，且每条测试垫引线（M2）与第一测试信号线（M1）和第二测试信号线（M1'）连接、不与其他组的第一测试信号线（M1）和第二测试信号线（M1'）重叠；多个测试垫（P），每个测试垫（P）设置在相应的测试垫引线（M2）上。该外围测试电路改善了现有外围测试电路中测试垫引线与测试信号线具有重叠跨接、容易造成静电释放而导致测试垫引线与测试信号线短接的问题，能够降低静电释放的击伤风险。

Description

显示器阵列基板的外围测试线路以及液晶显示面板 本申请要求享有 2014年 5月 21日提交的名称为 "显示器阵列基板的外围测试线路以 及液晶显示面板" 的中国专利申请 CN201410216387.4的优先权， 其全部内容通过引用并 入本文中。 技术领域
本发明涉及液晶显示器领域，尤其涉及一种显示器阵列基板的外围测试线路以及液晶 显示面板。 背景技术
一般，在制作液晶显示器的前段过程中，使用外延的方法在基板上形成数百万颗的薄 膜晶体管以作为控刺单元， 然而， 若有部分的薄膜晶体管在制作^质量达不到预期效果， 导致无法表现出其幵关控制特性，则会产生如亮点或暗点的缺陷，大幅地降低液晶显示器 的质量。 因此， 必须对薄膜晶体管进行有效地测试， 以维持液晶显示器的质量。
在现有的对液晶显示器的薄膜晶体管进行测试的方案中， TFT 阵列基板外圑区域的 测试信号线与测试垫的连接结构具体可参考图 1。 如图 1所示， 基板外围区域的测试信号 线 M l通过 ΠΌ与测试信号线 M 连接的钝化层过孔 VI、 以及 ΠΌ与测试垫引线 M2连 接的钝化层过孔 V2与测试垫引线 M2连接， 进而连接到相应的测试垫 P上。 从图中可以 看出， 在不同的测试信号线 Ml通过测试垫引线 M2连接到相应的测试垫 P的过程中， 测 试垫引线 M2必然会横跨其他的测试信号线 Ml , 在测试信号线 M l与测试垫引线 M2交 界跨接的 ϋ程中容易造成静电施放而使测试信号线 Ml和测试垫引线 M2短接，导致测试 信号线短路而无法检测， 因而降低产品的合格率。
因此， 需要一种解决方案来改善现有技术中测试信号线和测试垫引线容易短接的问 题， 降低静电施放的击伤风险， 提升产品测试准确率， 进而提高产品合格率。 发明内容
本发明所要解决的技术问题之一是需要提供一种显示器阵列基板的外圏测试线路，该 外围测试线路能够解决测试信号线和测试垫引线容易短接的问题，降低静电施放的击伤风 险。 另外， 还提供了一种显示器阵列基板和液晶显示面板。 为了解决上述技术问题， 本发明提供了一种显示器阵列基板的外圏测试线路， 包括： 多组测试信号线,每组测试信号线由隔开间隔设置的第一测试信号线和第二测试信号线组 成：多条测试垫引线，每条测试垫引线设置在相应组的第一测试信号线和第二测试信号线 的间隔处，且每条测试垫引线与第一测试信号线和第二测试信号线连接、不与其他组的第 一测试信号线和第二测试信号线重叠； 多个测试垫，每个测试垫设置在相应的测试垫引线 在一个实施例中， 每条测试垫引线通过第一钝化层过孔和第二钝化层过孔与相应组 的第一测试信号线非重叠连接，且每条测试垫引线通过第三钝化层过孔和第四钝化层过孔 与相应组的第二测试信号线非重叠连接， 其中， 第一钝化层过孔为 ITO层与该第一测试 信号线连接的钝化层过孔， 第二钝化层过孔为所述 ITO层与该测试垫引线连接的钝化层 a孔， 第:三钝化层过孔为另一 ITO层与该第二测试信号线连接的钝化层过孔， 第四钝化 层过孔为所述另一 ΠΧ)层与该测试垫引线连接的钝化层过孔。
在一个实施例中， 多条测试垫引线以相互平行错位的方式排列。
在一个实施例中， 每组的第一测试信号线和第二测试信号线分别与相应的测试垫引 线垂直连接。
根据本发明的另一方面， 还提供了一种显示器阵列基板， 包括： 显示区； 位于所述显 示区周围的外围测试线路， 该外圈测试线路包括： 多组测试信号线， 每组测试信号线由隔 开间隔设置的第一测试信号线和第二测试信号线组成； 多条测试垫引线，每条测试垫引线 设置在相应组的第一测试信号线和第二测试信号线的间隔处，旦每条测试垫引线与第一测 试信号线和第二测试信号线连接、 不与其他组的第一测试信号线和第二测试信号线重叠； 多个测试垫， 每个测试垫设置在相应的测试垫引线上。
在一个实施例中， 每条测试垫引线通过第一钝化层过孔和第二钝化层过孔与相应组 的第一测试信号线非重叠连接，且每条测试垫引线通过第三钝化层过孔和第四钝化层过孔 与相应组的第二测试信号线非重叠连接， 其中， 第一钝化层过孔为 ITO层与该第一测试 信号线连接的钝化层过孔， 第二钝化层过孔为所述 ITO层与该测试垫引线连接的钝化层 过孔， 第：三钝化层过孔为另一： ΠΌ层与该第二测试信号线连接的钝化层过孔， 第四钝化 层过孔为所述另一 ΠΧ)层与该测试垫引线连接的钝化层过孔。
在一个实施例中， 多条测试垫引线以相互平行错位的方式排列。
在一个实施例中， 每组的第一测试信号线和第二测试信号线分别与相应的测试垫引 线垂直连接。
根据本发明的另一方面， 还提供了一种液晶显示面板， 包括上述的显示器阵列基板。 与现有技术相比， 本发明的一个或多个实施例 以具有如下优点：
本发明的外围测试线路，通过改变测试信号线与测试垫的连接方式，避免测试垫引线 与测试信号线跨界现象的出现， 且在测试垫引线与测试信号线连接处，通过过孔使测试垫 引线不跨界到测试信号线。 降低静电释放的击伤风险， 提升产品测试准确率， 提高产品良 本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显 而易见， 或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要 求书以及 f†图中所特别指出的结构来实现和获得。
階图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例 共同用于解释本发明， 并不构成对本发明的限制。 在附图中：
图 1是现有技术中 TFT阵列基板外围区域的测试信号线与测试垫的连接结构示意图； 图 2是根据本发明实施例的显示器阵列基板的外围测试线路示意图。 具体实施方式
为使本发明的目的、技术方案和优点更加清楚， 以下结合 图对本发明作进一步地详 细说明。
图 2是根据本发明实施例的显示器阵列基板的外围测试线路示意图。
如图 2所示， 该外围测试线路包括： 多组测试信号线， 每组测试信号线由隔开间隔设 置的第一测试信号线 Ml和第二测试信号线 ΜΓ组成； 多条测试垫引线 M2， 每条测试垫 引线 M2设置在相应组的第一测试信号线 M l和第二测试信号线 Ml '的间隔处， — 每条测 试垫引线 M2与第一测试信号线 M l和第二测试信号线 ΜΓ连接、 旦不与其他组的第一测 试信号线 Ml和第二测试信号线 Μ Γ重叠； 多个测试垫 P, 每个测试垫 P设置在每条测试 垫引线 M2上。测试垫 P可将信号发生器产生的测试信号通过测试信号线 M l和 Μ Γ传输 到相应的数据线或扫描线， 以测试数据线或扫描线是否断路。
在一个实施例中，每条测试垫引线 M2的一端通过第一钝化层过孔 VI和第二钝化层 过孔 V2与相应组的第一测试信号线 Ml非重叠连接， 且每条测试垫引线 M2的另一端通 过第:三钝化层 ϋ孔 V '和第四钝化层 ϋ孔 V2'与相应组的第二测试信号线 ΜΓ非重叠连接， 其中， 第一纯化层过孔 VI为 ITO层与该第一测试信号线 Ml连接的钝化层过孔， 第二钝 化层过孔 V2为 ΠΌ层与该测试垫引线 M2的一端连接的钝化层过孔， 第 钝化层过孔 VT为另一 ΠΌ层与该第二测试信号线 ΜΓ连接的钝化层过孔， 第四钝化层过孔 V2'为该 另一 ΠΌ层与该测试垫引线 M2的另一端连接的钝化层过孔。 优选地， 多条测试垫引线 M2以相互平行错位的方式排列， 而且每组的第一测试信号线 Ml和第二测试信号线 ΜΓ 分别与相应的测试垫引线 M2垂直连接， 具体如图 2所示。
本发明实施例的外围测试电路改善了现有外 ID测试电路中测试垫弓！线与测试信号线 具有重叠跨接、容易造成静电释放而导致测试垫引线与测试信号线短接的问题。能够降低 静电释放的击伤风险， 提升产品测试准确率， 提高产品的合格率。
本发明还提供了一种显示器阵列基板，该显示器阵列基板包括显示区和位于该显示区 周围的外围测试线路， 其中， 该外围测试线路为上述结构的外围测试线路。 另外， 本发明 还提供了一种液晶显示面板， 该液晶显示面板包括上述的显示器阵列基板。
以上所述， 仅为本发明的具体实施案例， 本发明的保护范围并不局限于此， 任何熟悉 本技术的技术人员在本发明所述的技术规范内，对本发明的修改或替换，都应在本发明的 保护范围之内。

Claims

权利要求书
1、 一种显示器阵列基板的外围测试线路， 其中， 包括：
多组测试信号线， 每组测试信号线由隔幵间隔设置的第一测试信号线和第二测试信 号线组成；
多条测试垫引线， 每条测试垫引线设置在相应组的第一测试信号线和第二测试信号 线的间隔处， 且每条测试垫引线与第一测试信号线和第二测试信号线连接、不与其他组的 第一测试信号线和第二测试信号线重叠- 多个测试垫， 每个测试垫设置在相应的测试垫引线上。
2、 根据权利要求 1所述的外围测试线路， 其中， 每条测试垫引线通过第一钝化层过 孔和第二钝化层过孔与相应组的第一测试信号线非重叠连接， ϋ每条测试垫引线通过第三 钝化层过孔和第四钝化层过孔与相应组的第二测试信号线非重叠连接， 其中，
第一钝化层过孔为 ΙΤΟ层与该第一测试信号线连接的钝化层过孔， 第二钝化层过孔 为所述 ΙΤΟ层与该测试垫引线连接的钝化层过孔， 第三.钝化层过孔为另一 ΙΤΟ层与该第 二测试信号线连接的钝化层过孔， 第四钝化层过孔为所述另一 ΙΤΟ层与该测试垫引线连 接的钝化层过孔。
3、 根据权利要求 2所述的外围测试线路， 其中，
多条测试垫引线以相互平行错位的方式排列。
4、 根据权利要求 3所述的外围测试线路， 其中，
每组的第一测试信号线和第二测试信号线分别与相应的测试垫引线垂直连接。
5、 一种显示器阵列基板， 其中， 包括： 位于所述显示区周 的外围测试线路， 该外围测试线路包括- 多组测试信号线， 每组测试信号线由隔开间隔设置的第一测试信号线和第二测 试信号线组成；
多条测试垫 ^线， 每条测试垫 ^线设置在相应组的第一测试信号线和第二测试 信号线的间隔处， 且每条测试垫引线与第一测试信号线和第二测试信号线连接、 不 与其他组的第一测试信号线和第二测试信号线重叠；
多个测试垫， 每个测试垫设置在相应的测试垫引线上。
6、 根据权利要求 5所述的显示器阵列基板， 其中， 每条测试垫引线通过第一钝化层 过孔和第二钝化层过孔与相应组的第一测试信号线非重叠连接，且每条测试垫引线通过第 —三钝化层过孔和第四钝化层过孔与相应组的第二测试信号线非重叠连接， 其中，
第一钝化层过孔为 ΠΌ层与该第一测试信号线连接的钝化层过孔， 第二钝化层过孔 为所述 ΠΌ层与该测试垫引线连接的钝化层过孔， 第 钝化层过孔为另一： ΠΌ层与该第 二测试信号线连接的钝化层过孔， 第四钝化层过孔为所述另一 ΠΌ层与该测试垫引线连 接的钝化层过孔。
7、 根据权利要求 4所述的显示器阵列基板， 其中，
多条测试垫引线以相互平行错位的方式排列。
8、 根据权利要求 7所述的显示器阵列基板， 其中，
每组的第一测试信号线和第二测试信号线分别与相应的测试垫引线垂直连接。
9、 一种液晶显示靣板， 其中， 包括显示器阵列基板，
该显示器阵列基板包括；
显示区：
位于所述显示区周圑的外围测试线路， 该外围测试线路包括- 多组测试信号线， 每组测试信号线由隔开间隔设置的第一测试信号线和第二测 试信号线组成；
多条测试垫引线， 每条测试垫引线设置在相应组的第一测试信号线和第二测试 信号线的间隔处， 且每条测试垫引线与第一测试信号线和第二测试信号线连接、 不 与其他组的第一测试信号线和第二测试信号线重叠；
多个测试垫， 每个测试垫设置在相应的测试垫引线上。
10、 根据权利要求 9所述的液晶显示面板， 其中， 每条测试垫引线通过第一钝化层 过孔和第二钝化层过孔与相应组的第一测试信号线非重叠连接，且每条测试垫引线通过第 三钝化层过孔和第四钝化层过孔与相应组的第二测试信号线非重叠连接， 其中，
第一钝化层过孔为 ITO层与该第一测试信号线连接的钝化层过孔， 第二钝化层过孔 为所述 ITO层与该测试垫引线连接的钝化层过孔， 第三钝化层过孔为另一 ITO层与该第 二测试信号线连接的钝化层过孔， 第四钝化层过孔为所述另一 ΠΌ层与该测试垫引线连 接的钝化层过孔。
11、 根据权利要求 9所述的液晶显示面板， 其中，
多条测试垫引线以相互平行错位的方式排列。
12、 根据权利要求 11所述的液晶显示面板， 其中，
每组的第一测试信号线和第二测试信号线分别与相应的测试垫引线垂直连接
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160252756A1 (en) * 2014-05-21 2016-09-01 Shenzhen China Star Optoelectronics Technology Co., Ltd. Peripheral test circuit of display array substrate and liquid crystal display panel
TWI706191B (zh) * 2018-12-26 2020-10-01 大陸商友達光電（昆山）有限公司 顯示面板

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104750343A (zh) * 2015-02-05 2015-07-01 深圳市华星光电技术有限公司 电容式感应元件、触摸屏及电子设备
CN104867924B (zh) * 2015-05-06 2018-10-23 深圳市华星光电技术有限公司 Tft显示器件及其制作方法
CN104880877A (zh) * 2015-06-18 2015-09-02 京东方科技集团股份有限公司 一种阵列基板及其制作方法、测试方法
CN106169482B (zh) 2016-08-01 2019-04-09 京东方科技集团股份有限公司 一种基板及其制作方法、电子器件
CN107785350A (zh) * 2016-08-24 2018-03-09 中华映管股份有限公司 静电防护电路及静电防护方法
US11054709B2 (en) * 2017-01-24 2021-07-06 Sakai Display Products Corporation Display panel and display device
CN107123384B (zh) * 2017-06-01 2020-09-04 深圳市华星光电技术有限公司 一种显示基板的测试方法及应用于显示设备的基板
CN107093391B (zh) * 2017-06-30 2020-09-08 深圳市华星光电技术有限公司 液晶显示面板的检测电路结构与液晶显示面板
CN207517281U (zh) * 2017-11-16 2018-06-19 京东方科技集团股份有限公司 一种阵列基板及显示装置
CN108427230A (zh) * 2018-05-24 2018-08-21 京东方科技集团股份有限公司 显示基板、显示面板和显示装置
CN108983520B (zh) * 2018-09-29 2021-04-02 武汉华星光电技术有限公司 抗静电放电的显示面板
CN208969376U (zh) * 2018-11-12 2019-06-11 惠科股份有限公司 测试走线结构、测试装置及测试系统
CN110824799B (zh) * 2019-11-19 2022-04-15 合肥维信诺科技有限公司 阵列基板线路检测结构及其检测方法、阵列基板
KR102780550B1 (ko) * 2019-11-20 2025-03-12 삼성디스플레이 주식회사 표시 장치 및 이의 검사 방법
KR102744149B1 (ko) * 2020-05-04 2024-12-20 삼성디스플레이 주식회사 게이트 검사부 및 이를 포함하는 표시 장치
CN113593407B (zh) * 2021-07-06 2023-05-30 Tcl华星光电技术有限公司 显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002303845A (ja) * 2000-12-30 2002-10-18 Hyundai Display Technology Inc パネル内配線の欠陥をテストするための液晶表示装置
CN1503040A (zh) * 2002-11-19 2004-06-09 三星电子株式会社 液晶显示器及其测试方法
US20080137021A1 (en) * 2006-12-12 2008-06-12 Jin Young Choi Preventing wiring corrosion in LCDs
CN101604103A (zh) * 2008-06-13 2009-12-16 乐金显示有限公司 液晶显示器设备的阵列基板
US20110096449A1 (en) * 2009-10-26 2011-04-28 Mi-Sun Lee Substrate for a Display Device and Method of Manufacturing the Same
CN102789076A (zh) * 2012-08-01 2012-11-21 深圳市华星光电技术有限公司 一种检测线路及液晶显示面板的制作方法
CN103713434A (zh) * 2012-09-28 2014-04-09 株式会社日本显示器 显示装置

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5546013A (en) * 1993-03-05 1996-08-13 International Business Machines Corporation Array tester for determining contact quality and line integrity in a TFT/LCD
KR100242437B1 (ko) * 1996-08-07 2000-02-01 윤종용 액정 모듈 및 그 제조 방법
TW440736B (en) * 1997-10-14 2001-06-16 Samsung Electronics Co Ltd Liquid crystal displays and manufacturing methods thereof
US6150833A (en) * 1999-02-03 2000-11-21 Industrial Technology Research Institute LCD panel power-up test fixture and method of using
KR100724745B1 (ko) * 2000-09-30 2007-06-04 엘지.필립스 엘시디 주식회사 액정표시소자 및 그 검사방법
KR100831280B1 (ko) * 2001-12-26 2008-05-22 엘지디스플레이 주식회사 액정표시장치
KR100798320B1 (ko) * 2002-03-06 2008-01-28 엘지.필립스 엘시디 주식회사 액정 패널의 검사 장치 및 그 방법
KR100900537B1 (ko) * 2002-08-23 2009-06-02 삼성전자주식회사 액정 표시 장치, 그 검사 방법 및 제조 방법
KR100864501B1 (ko) * 2002-11-19 2008-10-20 삼성전자주식회사 액정 표시 장치
KR100640208B1 (ko) * 2002-12-28 2006-10-31 엘지.필립스 엘시디 주식회사 액정표시패널의 검사용 범프 구조
TW589484B (en) * 2003-10-16 2004-06-01 Au Optronics Corp Liquid crystal display module
KR101100883B1 (ko) * 2004-11-08 2012-01-02 삼성전자주식회사 박막 트랜지스터 표시판
KR101129438B1 (ko) * 2005-06-10 2012-03-27 삼성전자주식회사 표시 기판, 이를 구비한 표시 패널의 검사 장치 및 방법
KR101137863B1 (ko) * 2005-08-30 2012-04-23 엘지디스플레이 주식회사 박막트랜지스터 어레이 기판
KR101148206B1 (ko) * 2005-11-29 2012-05-24 삼성전자주식회사 표시 기판과, 이의 검사 방법
KR20070077282A (ko) * 2006-01-23 2007-07-26 삼성전자주식회사 표시 장치, 액정 표시판 조립체, 및 표시 장치의 검사 방법
KR101142993B1 (ko) * 2006-02-20 2012-05-08 삼성전자주식회사 표시 장치 및 그의 감지부 검사 방법
KR101232157B1 (ko) * 2006-06-09 2013-02-12 엘지디스플레이 주식회사 Ｌｃｄ 검사 장비
KR100926429B1 (ko) * 2007-12-21 2009-11-12 엘지디스플레이 주식회사 액정표시장치 및 그 제조방법
TWI368779B (en) * 2008-02-15 2012-07-21 Chunghwa Picture Tubes Ltd Peripheral circuit
TW200937069A (en) * 2008-02-25 2009-09-01 Chunghwa Picture Tubes Ltd Active device array substrate and liquid crystal display panel
KR100950514B1 (ko) * 2008-04-30 2010-03-30 엘지디스플레이 주식회사 액정표시장치
TWI370310B (en) * 2008-07-16 2012-08-11 Au Optronics Corp Array substrate and display panel thereof
CN100562789C (zh) 2008-07-21 2009-11-25 友达光电股份有限公司 间隙子结构及显示面板
TWI380255B (en) * 2008-10-17 2012-12-21 Prime View Int Co Ltd Flat display panel and active device array substrate and light-on testing method thereof
KR101579853B1 (ko) * 2009-03-23 2015-12-24 삼성디스플레이 주식회사 정전기 방지 패턴을 가지는 표시 패널
CN102236179B (zh) * 2010-05-07 2014-03-19 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN102768421A (zh) * 2012-07-24 2012-11-07 深圳市华星光电技术有限公司 液晶面板及其制作方法
US9000797B2 (en) * 2012-09-12 2015-04-07 Shenzhen China Star Optoelectronics Technology Co., Ltd. TFT-LCD array substrate having a connecting device for testing twice and test method for the same
US9177497B2 (en) * 2012-11-22 2015-11-03 Shenzhen China Star Optoelectronics Technology Co., Ltd Method for testing LCD panel
CN103246092B (zh) * 2013-04-28 2015-08-19 京东方科技集团股份有限公司 阵列基板及显示装置
CN103353693B (zh) 2013-06-14 2018-07-06 昆山龙腾光电有限公司 液晶显示装置及其制造方法
CN103513454B (zh) * 2013-08-29 2015-06-10 京东方科技集团股份有限公司 阵列基板及其检测方法和制备方法
CN103969890B (zh) * 2013-09-04 2016-08-24 上海天马微电子有限公司 一种tft阵列基板及显示面板、显示装置
KR102105369B1 (ko) * 2013-09-25 2020-04-29 삼성디스플레이 주식회사 표시 기판용 모기판, 이의 어레이 검사 방법 및 표시 기판
CN103676255B (zh) * 2013-12-26 2016-02-24 深圳市华星光电技术有限公司 阵列基板的防静电结构
CN103728763A (zh) 2013-12-31 2014-04-16 深圳市华星光电技术有限公司 液晶面板及其制作方法
KR102272789B1 (ko) * 2014-01-15 2021-07-05 삼성디스플레이 주식회사 표시 패널 및 이를 포함하는 표시 장치
US20150301419A1 (en) * 2014-04-16 2015-10-22 Shenzhen China Star Optoelectronics Technology Co., Ltd. Array plate and liquid crystal display panel having the same
CN104035217B (zh) * 2014-05-21 2016-08-24 深圳市华星光电技术有限公司 显示器阵列基板的外围测试线路以及液晶显示面板
US9618810B2 (en) * 2015-02-11 2017-04-11 Shenzhen China Star Optoelectronics Technology Co., Ltd. Array substrate and liquid crystal display panel

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002303845A (ja) * 2000-12-30 2002-10-18 Hyundai Display Technology Inc パネル内配線の欠陥をテストするための液晶表示装置
CN1503040A (zh) * 2002-11-19 2004-06-09 三星电子株式会社 液晶显示器及其测试方法
US20080137021A1 (en) * 2006-12-12 2008-06-12 Jin Young Choi Preventing wiring corrosion in LCDs
CN101604103A (zh) * 2008-06-13 2009-12-16 乐金显示有限公司 液晶显示器设备的阵列基板
US20110096449A1 (en) * 2009-10-26 2011-04-28 Mi-Sun Lee Substrate for a Display Device and Method of Manufacturing the Same
CN102789076A (zh) * 2012-08-01 2012-11-21 深圳市华星光电技术有限公司 一种检测线路及液晶显示面板的制作方法
CN103713434A (zh) * 2012-09-28 2014-04-09 株式会社日本显示器 显示装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160252756A1 (en) * 2014-05-21 2016-09-01 Shenzhen China Star Optoelectronics Technology Co., Ltd. Peripheral test circuit of display array substrate and liquid crystal display panel
US9678372B2 (en) * 2014-05-21 2017-06-13 Shenzhen China Star Optoelectronics Technology, Co., Ltd. Peripheral test circuit of display array substrate and liquid crystal display panel
TWI706191B (zh) * 2018-12-26 2020-10-01 大陸商友達光電（昆山）有限公司 顯示面板

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