WO2016090718A1 - 测试垫的形成方法及利用该测试垫进行阵列测试的方法 - Google Patents

测试垫的形成方法及利用该测试垫进行阵列测试的方法 Download PDF

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WO2016090718A1
WO2016090718A1 PCT/CN2015/070204 CN2015070204W WO2016090718A1 WO 2016090718 A1 WO2016090718 A1 WO 2016090718A1 CN 2015070204 W CN2015070204 W CN 2015070204W WO 2016090718 A1 WO2016090718 A1 WO 2016090718A1
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transistor
transistor region
region
test
test pads
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PCT/CN2015/070204
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English (en)
French (fr)
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胡宇彤
杜鹏
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深圳市华星光电技术有限公司
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Priority to US14/423,113 priority Critical patent/US9658284B2/en
Publication of WO2016090718A1 publication Critical patent/WO2016090718A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for forming a test pad between adjacent transistor regions and a method for performing array test on adjacent transistor regions by using a test pad formed by the method for forming a test pad.
  • LTPS Low Temperature Poly-Silicon
  • each piece of glass All of the transistor regions formed on the substrate are arranged in the same direction, that is, a set of test pads is disposed on one edge region of each transistor region, and the occupied area is relatively large, which is disadvantageous for the display to realize a narrow bezel.
  • an object of the present invention is to provide a method for forming a test pad between adjacent transistor regions, comprising: forming a plurality of sets of transistor regions arranged in an array on a glass substrate; wherein each group The transistor region includes a first transistor region and a second transistor region disposed opposite each other; a plurality of test pads are formed between the first transistor region and the second transistor region.
  • a plurality of field effects are formed in adjacent edge regions of the first transistor region before performing "forming a plurality of test pads between the first transistor region and the second transistor region" a transistor, and a plurality of field effect transistors are formed in adjacent edge regions of the second transistor region.
  • the gates of the plurality of field effect transistors formed in the adjacent edge regions of the first transistor region are electrically connected to one of the plurality of test pads; and the plurality of fields formed in the adjacent edge regions of the second transistor region The effect transistor gates are each electrically connected to the other of the plurality of test pads.
  • the number of field effect transistors is equal to the number of data lines of the first transistor region or the second transistor region.
  • an external lead connection region is formed in an edge region of the first transistor region away from the second transistor region, and an external lead connection is formed in an edge region of the second transistor region away from the first transistor region region.
  • the number of test pads is at least two more than the number of data lines of the first transistor region or the second transistor region.
  • first transistor region and the second transistor region each include a plurality of field effect transistors arranged in an array.
  • the field effect transistor is a thin film transistor.
  • Another object of the present invention is to provide a method for performing array test on adjacent transistor regions by using the test pad formed by the above method, comprising the steps of: providing a high level signal to one of a plurality of test pads, and providing a low level Signaling to another of the plurality of test pads to perform an array test on the first transistor region; providing a low level signal to one of the plurality of test pads, and providing a high level signal to the other of the plurality of test pads to The second transistor region is subjected to an array test.
  • Still another object of the present invention is to provide a method for performing array test on adjacent transistor regions by using the test pad formed by the above method, comprising the steps of: providing a low level signal to one of a plurality of test pads, and providing a high level Signaling to another of the plurality of test pads to perform an array test on the second transistor region; providing a high level signal to one of the plurality of test pads, and providing a low level signal to the other of the plurality of test pads to The first transistor region is described for array testing.
  • the invention utilizes a common test pad formed between adjacent transistor regions of each group of transistor regions, and can perform array test on adjacent transistor regions by using the shared test pad, and can reduce each The size of the adjacent edge region of a transistor region facilitates the display to achieve a narrow frame.
  • FIG. 1 is a flow chart of a method of forming a test pad between adjacent transistor regions in accordance with an embodiment of the present invention
  • FIG. 2 is a top plan view of forming a plurality of sets of transistor regions arranged in an array on a glass substrate and forming test pads between adjacent transistor regions, in accordance with an embodiment of the present invention
  • FIG. 3 is a top plan view of a set of transistor regions in accordance with an embodiment of the present invention.
  • FIG. 4 is a flow diagram of a method of array testing adjacent transistor regions using a test pad formed using the method illustrated in FIG. 1 in accordance with an embodiment of the present invention.
  • 1 is a flow chart of a method of forming a test pad between adjacent transistor regions in accordance with an embodiment of the present invention.
  • 2 is a top plan view of forming a plurality of sets of transistor regions arranged in an array on a glass substrate and forming test pads between adjacent transistor regions, in accordance with an embodiment of the present invention.
  • 3 is a top plan view of a set of transistor regions in accordance with an embodiment of the present invention.
  • a method of forming a test pad between adjacent transistor regions in accordance with an embodiment of the present invention includes:
  • Step S10 forming a plurality of sets of transistor regions 20 arranged in an array on the glass substrate 10; wherein each set of transistor regions 20 includes a first transistor region 21 and a second transistor region 22 disposed opposite each other.
  • step S10 the area of the glass substrate 10 is much larger than the area of the first transistor region 21 or the second transistor region 22.
  • the glass substrate 10 needs to be cut. After being diced, the first transistor region 21 and the glass substrate carrying the same, or the second transistor region 22 and the glass substrate carrying the same are referred to as an array substrate.
  • first transistor region 21 and the second transistor region 22 each include a plurality of field effect transistors 40 arranged in an array.
  • the field effect transistor 40 is a thin film transistor.
  • Step S11 A plurality of test pads 30 are formed between the first transistor region 21 and the second transistor region 22.
  • the intermediate portion of each test pad 30 is on the cutting line.
  • the number of test pads 30 is at least two more than the number of data lines of the first transistor region 21 or the second transistor region 22.
  • a plurality of field effect transistors 40 are formed in the adjacent edge regions 211 of the first transistor region 21, and a plurality of field effect transistors 40 are formed in the adjacent edge regions 221 of the second transistor regions 22.
  • the adjacent edge region 211 of the first transistor region 21 refers to the region of the first transistor region 21 adjacent to the second transistor region 22, and the abutting edge region 221 of the second transistor region 22 refers to the second transistor region 22 An area adjacent to the first transistor region 21.
  • the number of field effect transistors 40 in the adjacent edge region 211 of the first transistor region 21 is equal to the number of data lines of the first transistor region 21 or the second transistor region 22; and in the adjacent edge region 221 of the second transistor region 22 The number of field effect transistors 40 is equal to the number of data lines of the first transistor region 21 or the second transistor region 22.
  • the gates of the plurality of field effect transistors 40 formed by the adjacent edge regions 211 of the first transistor region 21 are electrically connected to one of the plurality of test pads 30; the plurality of fields formed in the adjacent edge regions 221 of the second transistor region 22 The gates of the effect transistor 40 are each electrically coupled to the other of the plurality of test pads 30.
  • an outer lead connection (OLB) region 212 is formed in an edge region of the first transistor region 21 away from the second transistor region 22, and an edge region of the second transistor region 22 away from the first transistor region 21
  • An external lead connection region 222 is formed.
  • FIG. 4 is a test pad formed by the method shown in FIG. 1 for adjacent crystals in accordance with an embodiment of the present invention. Flowchart of a method of performing array testing on a body tube region.
  • a method for performing array test on adjacent transistor regions using a test pad formed by the method illustrated in FIG. 1 according to an embodiment of the present invention includes:
  • step S41 a high level signal is supplied to one of the plurality of test pads 30, and a low level signal is supplied to the other of the plurality of test pads 30 to perform array test on the first transistor region 21.
  • step S42 a low level signal is supplied to one of the plurality of test pads 30, and a high level signal is supplied to the other of the plurality of test pads 30 to perform array test on the second transistor region 22.
  • step 42 may be performed first, and then step 41 is performed.
  • a shared test pad formed between adjacent transistor regions of each group of transistor regions can be used to reduce the array of adjacent transistor regions by using the shared test pad.
  • the size of the adjacent edge region of each transistor region facilitates the display to achieve a narrow frame.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种相邻晶体管区域（20）之间形成测试垫（30）的方法，包括：在玻璃基板上形成阵列排布的多组晶体管区域（20）；其中，每组晶体管区域（20）包括相对设置的第一晶体管区域（21）及第二晶体管区域（22）；在所述第一晶体管区域（21）与所述第二晶体管区域（22）之间形成多个测试垫（30）。还提供一种利用上述方法形成的测试垫（30）对相邻晶体管区域（20）进行阵列测试的方法。该方法利用在每组晶体管区域（20）的相邻晶体管区域（20）之间形成的共用的测试垫（30），利用该共用的测试垫（30）对相邻晶体管区域（20）进行阵列测试的同时，能够减小每一晶体管区域（20）的邻接边缘区域的尺寸，从而利于显示器实现窄边框化。

Description

测试垫的形成方法及利用该测试垫进行阵列测试的方法 技术领域
本发明属于显示技术领域，具体地讲，涉及一种相邻晶体管区域之间形成测试垫的方法及利用该形成测试垫的方法形成的测试垫对相邻晶体管区域进行阵列测试的方法。
背景技术
众所周知，在小尺寸高分辨率的显示器中，LTPS(Low Temperature Poly-Silicon，低温多晶硅)技术由于高迁移率、稳定的性能已经得到了广泛的应用。但是，LTPS显示器良率低一直困扰诸多面板企业，为此，阵列检测(Array Test)是能够监测各道制程的一个必须且快捷的方式。
伴随着手机市场的飞速发展，对手机的各项参数要求越来越高，其中，高图像分辨率和窄边框一直是手机厂商标榜的两大特征。为了能够更清晰高效的查找问题，阵列检测更是细化到可以检测每一个像素(Pixel)，为了应对高图像分辨率的显示器的阵列检测，生产厂商通常采用解复用器(De-Mux)来提高效率，然而，由于制程及机台精准度等问题，解复用器和测试垫(Test Pad)所需高度成为阻碍显示器的窄边框的因素，例如，在现有技术中，每一块玻璃基板上形成的所有晶体管区域同向排列，即，每一晶体管区域的一侧边缘区域设置一组测试垫，其所占面积相对较大，不利于显示器实现窄边框。
发明内容
为了解决上述现有技术存在的问题，本发明的目的在于提供一种相邻晶体管区域之间形成测试垫的方法，包括：在玻璃基板上形成阵列排布的多组晶体管区域；其中，每组晶体管区域包括相对设置的第一晶体管区域及第二晶体管区域；在所述第一晶体管区域与所述第二晶体管区域之间形成多个测试垫。
进一步地，在执行“在所述第一晶体管区域与所述第二晶体管区域之间形成多个测试垫”之前，在所述第一晶体管区域的邻接边缘区域形成多个场效应 晶体管，且在所述第二晶体管区域的邻接边缘区域形成多个场效应晶体管。
进一步地，在所述第一晶体管区域的邻接边缘区域形成的多个场效应晶体管的栅极均电连接至多个测试垫之一；在所述第二晶体管区域的邻接边缘区域形成的多个场效应晶体管栅极均电连接至多个测试垫之另一。
进一步地，所述场效应晶体管的数量与所述第一晶体管区域或所述第二晶体管区域的数据线的数量相等。
进一步地，在所述第一晶体管区域的远离所述第二晶体管区域的边缘区域形成外部引线连接区域，且在所述第二晶体管区域的远离所述第一晶体管区域的边缘区域形成外部引线连接区域。
进一步地，所述测试垫的数量比所述第一晶体管区域或所述第二晶体管区域的数据线的数量至少多两个。
进一步地，所述第一晶体管区域和所述第二晶体管区域均包括阵列排布的多个场效应晶体管。
进一步地，所述场效应晶体管为薄膜晶体管。
本发明的另一目的还在于提供一种利用上述的方法形成的测试垫对相邻晶体管区域进行阵列测试的方法，包括步骤：提供高电平信号至多个测试垫之一，且提供低电平信号至多个测试垫之另一，以对所述第一晶体管区域进行阵列测试；提供低电平信号至多个测试垫之一，且提供高电平信号至多个测试垫之另一，以对所述第二晶体管区域进行阵列测试。
本发明的又一目的又在于提供一种利用上述的方法形成的测试垫对相邻晶体管区域进行阵列测试的方法，包括步骤：提供低电平信号至多个测试垫之一，且提供高电平信号至多个测试垫之另一，以对所述第二晶体管区域进行阵列测试；提供高电平信号至多个测试垫之一，且提供低电平信号至多个测试垫之另一，以对所述第一晶体管区域进行阵列测试。
本发明利用在每组晶体管区域的相邻晶体管区域之间形成的共用的测试垫，利用该共用的测试垫对相邻晶体管区域进行阵列测试的同时，能够减小每 一晶体管区域的邻接边缘区域的尺寸，从而利于显示器实现窄边框化。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的实施例的相邻晶体管区域之间形成测试垫的方法的流程图；
图2是根据本发明的实施例的在玻璃基板上形成阵列排布的多组晶体管区域及在相邻晶体管区域之间形成测试垫的俯视图；
图3是根据本发明的实施例的一组晶体管区域的俯视图；
图4是根据本发明的实施例的利用图1所示的方法形成的测试垫对相邻晶体管区域进行阵列测试的方法的流程图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
图1是根据本发明的实施例的相邻晶体管区域之间形成测试垫的方法的流程图。图2是根据本发明的实施例的在玻璃基板上形成阵列排布的多组晶体管区域及在相邻晶体管区域之间形成测试垫的俯视图。图3是根据本发明的实施例的一组晶体管区域的俯视图。
参照图1、图2和图3，根据本发明的实施例的相邻晶体管区域之间形成测试垫的方法包括：
步骤S10：在玻璃基板10上形成阵列排布的多组晶体管区域20；其中，每组晶体管区域20包括相对设置的第一晶体管区域21及第二晶体管区域22。
在步骤S10中，玻璃基板10的面积远大于第一晶体管区域21或第二晶体管区域22的面积，在后续制程中，需对玻璃基板10进行切割。经切割后，第一晶体管区域21及承载其的玻璃基板，或者第二晶体管区域22及承载其的玻璃基板被称为阵列基板。
此外，第一晶体管区域21和第二晶体管区域22均包括阵列排布的多个场效应晶体管40。在本实施例中，优选的，场效应晶体管40为薄膜晶体管。
步骤S11：在第一晶体管区域21与第二晶体管区域22之间形成多个测试垫30。优选的，在步骤S11中，每个测试垫30的中间部分处于切割线上。此外，测试垫30数量比第一晶体管区域21或第二晶体管区域22的数据线的数量至少多两个。
此外，在执行步骤S11之前，在第一晶体管区域21的邻接边缘区域211形成多个场效应晶体管40，且在第二晶体管区域22的邻接边缘区域221形成多个场效应晶体管40。这里，第一晶体管区域21的邻接边缘区域211指的是第一晶体管区域21的邻接第二晶体管区域22的区域，而第二晶体管区域22的邻接边缘区域221指的是第二晶体管区域22的邻接第一晶体管区域21的区域。
第一晶体管区域21的邻接边缘区域211中的场效应晶体管40的数量与第一晶体管区域21或第二晶体管区域22的数据线的数量相等；且第二晶体管区域22的邻接边缘区域221中的场效应晶体管40的数量与第一晶体管区域21或第二晶体管区域22的数据线的数量相等。
此外，第一晶体管区域21的邻接边缘区域211形成的多个场效应晶体管40的栅极均电连接至多个测试垫30之一；在第二晶体管区域22的邻接边缘区域221形成的多个场效应晶体管40的栅极均电连接至多个测试垫30之另一。
另外，在第一晶体管区域21的远离第二晶体管区域22的边缘区域形成外部引线连接(Outer Lead Bonding，简称OLB)区域212，且在第二晶体管区域22的远离第一晶体管区域21的边缘区域形成外部引线连接区域222。
图4是根据本发明的实施例的利用图1所示的方法形成的测试垫对相邻晶 体管区域进行阵列测试的方法的流程图。
参照图4，根据本发明的实施例的利用图1所示的方法形成的测试垫对相邻晶体管区域进行阵列测试的方法包括：
步骤S41，提供高电平信号至多个测试垫30之一，且提供低电平信号至多个测试垫30之另一，以对第一晶体管区域21进行阵列测试。
步骤S42，提供低电平信号至多个测试垫30之一，且提供高电平信号至多个测试垫30之另一，以对第二晶体管区域22进行阵列测试。
此外，由于对第一晶体管区域21或对第二晶体管区域22进行阵列测试为本领域技术人员所熟知的技术，在此不再赘述。
另外，作为本发明的另一实施方式，可先执行步骤42，再执行步骤41。
综上，根据本发明的实施例，利用在每组晶体管区域的相邻晶体管区域之间形成的共用的测试垫，利用该共用的测试垫对相邻晶体管区域进行阵列测试的同时，能够减小每一晶体管区域的邻接边缘区域的尺寸，从而利于显示器实现窄边框化。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (13)

  1. 一种相邻晶体管区域之间形成测试垫的方法，其中，包括：
    在玻璃基板上形成阵列排布的多组晶体管区域；其中，每组晶体管区域包括相对设置的第一晶体管区域及第二晶体管区域；
    在所述第一晶体管区域与所述第二晶体管区域之间形成多个测试垫。
  2. 根据权利要求1所述的方法，其中，在执行“在所述第一晶体管区域与所述第二晶体管区域之间形成多个测试垫”之前，在所述第一晶体管区域的邻接边缘区域形成多个场效应晶体管，且在所述第二晶体管区域的邻接边缘区域形成多个场效应晶体管。
  3. 根据权利要求2所述的方法，其中，在所述第一晶体管区域的邻接边缘区域形成的多个场效应晶体管的栅极均电连接至多个测试垫之一；在所述第二晶体管区域的邻接边缘区域形成的多个场效应晶体管的栅极均电连接至多个测试垫之另一。
  4. 根据权利要求2所述的方法，其中，所述场效应晶体管的数量与所述第一晶体管区域或所述第二晶体管区域的数据线的数量相等。
  5. 根据权利要求1所述的方法，其中，在所述第一晶体管区域的远离所述第二晶体管区域的边缘区域形成外部引线连接区域，且在所述第二晶体管区域的远离所述第一晶体管区域的边缘区域形成外部引线连接区域。
  6. 根据权利要求2所述的方法，其中，在所述第一晶体管区域的远离所述第二晶体管区域的边缘区域形成外部引线连接区域，且在所述第二晶体管区域的远离所述第一晶体管区域的边缘区域形成外部引线连接区域。
  7. 根据权利要求1所述的方法，其中，所述测试垫的数量比所述第一晶体管区域或所述第二晶体管区域的数据线的数量至少多两个。
  8. 根据权利要求2所述的方法，其中，所述测试垫的数量比所述第一晶体管区域或所述第二晶体管区域的数据线的数量至少多两个。
  9. 根据权利要求1所述的方法，其中，所述第一晶体管区域和所述第二晶体管区域均包括阵列排布的多个场效应晶体管。
  10. 根据权利要求2所述的方法，其中，所述场效应晶体管为薄膜晶体管。
  11. 根据权利要求9所述的方法，其中，所述场效应晶体管为薄膜晶体管。
  12. 一种利用权利要求1所述的方法形成的测试垫对相邻晶体管区域进行阵列测试的方法，其中，包括步骤：
    提供高电平信号至多个测试垫之一，且提供低电平信号至多个测试垫之另一，以对所述第一晶体管区域进行阵列测试；
    提供低电平信号至多个测试垫之一，且提供高电平信号至多个测试垫之另一，以对所述第二晶体管区域进行阵列测试。
  13. 一种利用权利要求1所述的方法形成的测试垫对相邻晶体管区域进行阵列测试的方法，其中，包括步骤：
    提供低电平信号至多个测试垫之一，且提供高电平信号至多个测试垫之另一，以对所述第二晶体管区域进行阵列测试；
    提供高电平信号至多个测试垫之一，且提供低电平信号至多个测试垫之另一，以对所述第一晶体管区域进行阵列测试。
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