WO2015169069A1 - 薄膜晶体管及其制作方法、显示基板和显示装置 - Google Patents

薄膜晶体管及其制作方法、显示基板和显示装置 Download PDF

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WO2015169069A1
WO2015169069A1 PCT/CN2014/089900 CN2014089900W WO2015169069A1 WO 2015169069 A1 WO2015169069 A1 WO 2015169069A1 CN 2014089900 W CN2014089900 W CN 2014089900W WO 2015169069 A1 WO2015169069 A1 WO 2015169069A1
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Prior art keywords
zinc oxide
thin film
film transistor
indium gallium
gallium zinc
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PCT/CN2014/089900
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English (en)
French (fr)
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陈江博
王东方
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京东方科技集团股份有限公司
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Priority to US14/651,376 priority Critical patent/US9773917B2/en
Publication of WO2015169069A1 publication Critical patent/WO2015169069A1/zh

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    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, a display substrate, and a display device.
  • Oxide transistors have received wide attention due to their high mobility and compatibility with a-Si production lines.
  • an oxide transistor having an etch barrier layer (ESL) structure develops a back channel etch type (BCE) oxide (such as indium gallium zinc) due to the disadvantage of a complicated process and insufficient competitiveness with respect to a-Si. Oxide) thin film transistors have become the focus of development.
  • ESL etch barrier layer
  • BCE back channel etch type oxide
  • Embodiments of the present invention provide a thin film transistor, a method of fabricating the same, a display substrate, and a display device.
  • a method of fabricating a thin film transistor comprising the steps of: fabricating an active having C-axis crystal orientation characteristics using indium gallium zinc oxide InGaO 3 (ZnO) m on a substrate. Layer, where m ⁇ 2.
  • the active layer is formed by depositing an indium gallium zinc oxide layer on the substrate at least twice.
  • an active layer having C-axis crystal orientation characteristics using indium gallium zinc oxide InGaO 3 (ZnO) m deposited by physical vapor deposition at a first power and a first rate a C-axis oriented first indium gallium zinc oxide layer; depositing a second indium gallium zinc oxide layer at a second power and a second rate by physical vapor deposition on the formed first layer of indium gallium zinc oxide layer
  • the first indium gallium zinc oxide layer and the second indium gallium zinc oxide layer form an active layer, wherein the first power is less than the second power, and the first rate is less than the second rate.
  • the temperature condition for forming the first indium gallium zinc oxide layer and the temperature condition for the second indium gallium zinc oxide layer are both 200 ° C to 400 ° C.
  • the active layer is deposited by vacuum deposition using a Nd:YAG laser, and the laser has an output wavelength of 193 to 1064 nm, a repetition frequency of greater than 1 Hz, and a small pulse width. At 10ns.
  • the active layer is deposited using a Nd:YAG laser under vacuum conditions, and the laser has an output wavelength of 1064 nm, a repetition rate of 10 Hz, and a pulse width of 10 ns.
  • the first power is a laser power of 0.2 to 0.4 W before focusing.
  • the first power is a laser power of 0.3 W before focusing.
  • the first indium gallium zinc oxide layer is deposited for a period of 10 to 30 s, and the first indium gallium zinc oxide layer is formed to have a thickness of 0 ⁇ d ⁇ 10 nm.
  • the second power is 0.5 to 1.0 W before the laser is focused.
  • the second power is 0.5W before focusing.
  • the first indium gallium zinc oxide layer and the second indium gallium zinc oxide layer are formed by sputtering under vacuum conditions.
  • the first indium gallium zinc oxide layer is formed by one scan at a condition of the first power of 2 to 3 KW and an O 2 flow rate of 25 standard milliliters per minute;
  • the second layer of indium gallium zinc oxide layer is formed by one scan at a condition of the second power of 4 to 6 KW and an O 2 flow rate of 25 standard milliliters per minute.
  • the first indium gallium zinc oxide layer is formed by one scan under the condition that the first power is 3 KW and the O 2 flow rate is 25 standard milliliters per minute; the second layer of indium gallium zinc The oxide layer was formed by one scan under the conditions of the second power of 4.5 KW and the O 2 flow rate of 25 standard milliliters per minute.
  • the indium zinc oxide InGaO 3 (ZnO) m comprises: any one of InGaZn 2 O 5 , InGaZn 3 O 6 , InGaZn 4 O 7 , InGaZn 5 O 8 or InGaZn 6 O 9 .
  • the active layer is deposited in three layers on the substrate, wherein the indium gallium zinc oxide InGaO 3 (ZnO) m growth rate of each layer increases in a gradually increasing manner.
  • At least one embodiment of the present invention also provides a thin film transistor including an active layer disposed on a substrate, wherein the active layer includes indium zinc oxide having C-axis crystal orientation characteristics,
  • the indium zinc oxide is InGaO 3 (ZnO) m , where m ⁇ 2.
  • the indium zinc oxide InGaO 3 (ZnO) m includes any one of InGaZn 2 O 5 , InGaZn 3 O 6 , InGaZn 4 O 7 , InGaZn 5 O 8 or InGaZn 6 O 9 .
  • At least one embodiment of the present invention also provides a display substrate including a substrate And the thin film transistor disposed on the substrate.
  • At least one embodiment of the present invention also provides a display device including the above display substrate.
  • FIG. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present invention.
  • FIGS. 2a-2d are flowcharts showing the fabrication of a thin film transistor structure according to an embodiment of the present invention.
  • the indium gallium zinc oxide has a high crystallization temperature, such as a commonly used indium gallium zinc oxide semiconductor thin film transistor device and a target component used in the preparation of the back sheet.
  • InGaZnO 4 therefore, the sample deposited by the target target is not easily crystallized, and even when the substrate is heated to 500 degrees, the film cannot be crystallized.
  • This method has high process requirements, thereby affecting the production efficiency and stability of the thin film transistor.
  • embodiments of the present invention provide a thin film transistor, a method of fabricating the same, a display substrate, and a display device.
  • the method changes the zinc content of the existing target by using an active layer formed by indium gallium zinc oxide InGaO 3 (ZnO) m having C-axis crystal orientation characteristics. The crystallization temperature of the indium gallium zinc oxide is lowered, and the stability of the bias voltage test of the thin film transistor is improved.
  • the etch rate of the indium gallium zinc oxide sample after crystallization in the source and drain etching liquid is slow. Several times, precise control of the etching can be achieved.
  • the material characteristics enable the thin film transistor to adopt a back channel etch type structure, which reduces the fabrication process of the etch barrier layer.
  • the active layer made of InGaO 3 (ZnO) m has a good electron migration effect, improves the quality of the active layer produced, and further improves the quality of the display device.
  • Embodiments of the present invention provide a method of fabricating a thin film transistor, the method comprising the following steps:
  • An active layer having C-axis crystal orientation characteristics is formed on the substrate using indium gallium zinc oxide InGaO 3 (ZnO) m , where m ⁇ 2.
  • the C-axis crystal orientation is such that the X-axis is oriented horizontally, the Y-axis is perpendicular to the X-axis, the Z-axis is perpendicular to the plane formed by the XY-axis, and the circular motion along the Z-axis is the C-axis orientation.
  • the method by using an active layer having C-axis crystal orientation characteristics formed by indium gallium zinc oxide InGaO 3 (ZnO) m, the method changes the zinc content in the existing target and reduces the oxidation of indium gallium zinc.
  • the crystallization temperature of the material improves the stability of the bias test of the thin film transistor.
  • the etch rate of the indium gallium zinc oxide sample after crystallization in the source and drain etching liquid is slow. Several times, precise control of the etching can be achieved.
  • the material characteristics enable the thin film transistor to adopt a back channel etch type structure, which reduces the fabrication process of the etch barrier layer.
  • the active layer made of InGaO 3 (ZnO) m has a good electron transfer effect and improves the quality of the active layer produced.
  • the indium zinc oxide InGaO 3 (ZnO) m may be, for example, any one of InGaZn 2 O 5 , InGaZn 3 O 6 , InGaZn 4 O 7 , InGaZn 5 O 8 or InGaZn 6 O 9 .
  • the active layer is formed by using such an indium gallium zinc oxide, and since it has a low crystallization temperature, it can be crystallized at 200 to 400 ° C, thereby effectively reducing the crystallization temperature of the indium gallium zinc oxide.
  • a first indium gallium zinc oxide layer having a C-axis orientation is deposited by physical vapor deposition at a first power and a first rate.
  • a second indium gallium zinc oxide layer is deposited at a second rate.
  • the first indium gallium zinc oxide layer and the second indium gallium zinc oxide layer form an active layer.
  • the first power is less than the second power, and the first rate is less than the second rate.
  • the first indium gallium zinc oxide layer is formed by slow deposition, and the first indium gallium zinc oxide layer can obtain a better crystallization effect due to the slow deposition rate.
  • the first indium zinc oxide layer can be used as a crystal nucleus when the second indium gallium zinc oxide layer is crystallized, thereby improving the second indium gallium zinc oxide.
  • the crystallization rate of the layer further increases the fabrication efficiency of the active layer while allowing the resulting active layer to have C-axis crystal orientation characteristics.
  • both the first indium gallium zinc oxide layer and the second indium gallium zinc oxide layer are formed at a temperature of 200 ° C to 400 ° C. Therefore, the temperature at which the indium gallium zinc oxide crystallizes is lowered as compared with the general technique.
  • the active layer is formed by physical deposition, different processes can be employed.
  • a first indium gallium zinc oxide layer having a C-axis crystal orientation characteristic may be deposited at a first power and a first rate by a laser pulse method; on the formed first indium gallium zinc oxide layer A second indium gallium zinc oxide layer is deposited at the second power and the second rate, and the first indium gallium zinc oxide layer and the second indium gallium zinc oxide layer form an active layer.
  • an active layer is formed using a Nd:YAG pulsed laser.
  • the output wavelength of the laser is 193-1064 nm, for example 1064 nm, the repetition frequency is greater than 1 Hz, for example 10 Hz, and the pulse width is less than or equal to 10 ns.
  • the mechanical pump of the vacuum system is turned on, and the vacuum chamber is evacuated.
  • the degree of vacuum reaches 0 to 5 Pa
  • the molecular pump is turned on and the vacuuming operation is continued.
  • the molecular pump When the degree of vacuum reached 2.5 ⁇ 10 -4 Pa, the molecular pump was turned off, the mechanical pump was turned on, and oxygen was simultaneously introduced into the vacuum chamber to maintain the oxygen partial pressure at 10.0 Pa.
  • the laser before focusing uses a first power of 0.2-0.4W, for example, 0.3W, a temperature of 200-400 degrees when depositing an indium gallium zinc oxide layer, a deposition time of 10-30s, and a first rate.
  • a first indium gallium zinc oxide layer having a thickness between 0 ⁇ d ⁇ 10 nm.
  • the oxygen flow rate is reduced, the vacuum chamber pressure is maintained at 5.0 Pa, and the laser is used to have a second power of 0.5-1.0 W, for example 0.5 W, before focusing, and a second deposition rate is formed on the first indium gallium zinc oxide layer.
  • the active layer may be formed by sputtering.
  • the degree of vacuum reaches 2.5 ⁇ 10 ⁇ 4 Pa
  • the deposition temperature is kept at 200 to 400 degrees
  • oxygen and Ar gas are introduced into the vacuum chamber.
  • O: Ar 1:4.
  • the power during deposition is 2-3 KW of the first power, for example, 3 KW, the flow rate of O 2 is 25 ML/min, and the number of scans is 1 time, so that the indium gallium zinc oxide forms the first indium gallium zinc oxide at the first rate. Layer of matter.
  • the deposition power is increased to a second power of 4-6 KW, for example, 4.5 KW, and the O 2 flow rate is 25
  • the ML/min, the number of scans was 1 and deposited to the desired film thickness to form the active layer.
  • two layers of indium gallium zinc oxide layers are formed by different process conditions: a first indium gallium zinc oxide layer is formed by slow deposition, and the first indium gallium zinc oxide layer is formed due to a slow deposition rate. A better crystallization effect can be obtained. And, in the subsequent rapid deposition to form the second indium gallium zinc oxide layer, the first indium zinc oxide layer can serve as a crystal nucleus when the second indium gallium zinc oxide layer is crystallized, thereby improving the second indium gallium zinc oxide. The crystallization rate of the layer further increases the fabrication efficiency of the active layer, and at the same time, the resulting active layer has C-axis crystal orientation characteristics.
  • the etch rate of the thus-crystallized InGaO 3 (ZnO) m sample in the source and drain etching solutions is slower than that of the uncrystallized indium zinc oxide sample in the source and drain etching solutions.
  • precise control of the etching can be achieved.
  • the back channel etch type structure thin film transistor requires the etching solution to have different etching selectivity ratios to the active layer and the source and drain layers, otherwise the channel may be greatly damaged during the source and drain layer pattern process. The channel is etched away.
  • the in-crystalized InGaO 3 (ZnO) m is less affected by the source and drain etching liquids than the amorphous indium zinc oxide, and the physical properties enable the back channel to be engraved.
  • Etched oxide thin film transistor structure Compared with the etch barrier type thin film transistor structure, the etch stop layer can be saved in a separate patterning process, which can simplify the fabrication process of the oxide thin film transistor and save the manufacturing cost.
  • FIG. 2 is a flow chart showing a structure of a thin film transistor according to an embodiment of the present invention. A method for fabricating a thin film transistor according to an embodiment of the present invention will be described in detail below with reference to FIGS. 2a to 2d.
  • Step 1 The transparent substrate 1 is cleaned by a standard method.
  • Step 2 As shown in FIG. 2a, a gate electrode 2 is formed on the transparent substrate 1.
  • a gate metal layer of 50 to 400 nm is deposited by sputtering or evaporation to form a gate electrode 2 by patterning.
  • Step 3 As shown in FIG. 2b, a gate insulating layer 3 is formed on the gate 2.
  • a gate insulating layer 3 of SiNx or SiO x having a thickness of 100 to 500 nm is prepared by plasma enhanced chemical vapor deposition, wherein x is a natural number.
  • Step 4 As shown in FIG. 2c, an active layer 4 having C-axis crystal orientation characteristics, wherein m ⁇ 2, is formed using indium gallium zinc oxide InGaO 3 (ZnO) m .
  • a first indium gallium zinc oxide layer having a C-axis orientation is deposited by physical vapor deposition at a first power and a first rate.
  • the physical vapor deposition method can be a sputtering or laser pulse method.
  • the laser system used is a Nd:YAG pulsed laser having an output wavelength of 193-1064 nm, for example, 1064 nm, a repetition frequency greater than 1 Hz, for example, 10 Hz, and a pulse width of 10 ns or less.
  • Embodiments of the invention employ the third harmonic of the laser (wavelength 355 nm).
  • the mechanical pump of the vacuum system is turned on to evacuate the vacuum chamber. When the degree of vacuum reaches 0 to 5 Pa, the molecular pump is turned on and the vacuuming operation is continued. When the degree of vacuum reached 2.5 ⁇ 10 -4 Pa, the molecular pump was turned off, the mechanical pump was turned on, and oxygen was simultaneously introduced into the vacuum chamber to maintain the oxygen partial pressure at 10.0 Pa.
  • the average power of the laser before focusing is 0.2-0.4 W, for example, 0.3 W.
  • the temperature of depositing the indium gallium zinc oxide layer is 200-400 degrees, and the deposition time is 10-30 s, forming a layer of 0-10 nm indium gallium zinc oxide layer, that is, the first indium gallium zinc oxide layer.
  • the first indium gallium zinc oxide layer acts as a seed crystal to improve crystallization properties.
  • the oxygen flow rate is decreased, the vacuum chamber pressure is 5.0 Pa, and the average laser power before focusing is 0.5-1.0 W, for example, 0.5 W, and deposition is continued on the first indium gallium zinc oxide layer to form a second indium gallium zinc oxide layer.
  • the desired thickness to form an active layer.
  • the power during deposition is 2-3 KW of the first power, for example 3 KW, the flow rate of O 2 is 25 ML/min, and the number of scans is 1 time, so that the indium gallium zinc oxide forms the first indium gallium zinc oxide at the first rate.
  • Floor 2-3 KW of the first power, for example 3 KW, the flow rate of O 2 is 25 ML/min, and the number of scans is 1 time, so that the indium gallium zinc oxide forms the first indium gallium zinc oxide at the first rate.
  • a second layer of indium gallium zinc oxide layer is deposited on the deposited first layer of indium gallium zinc oxide layer.
  • the deposition power is increased to a second power of 4-6 KW, for example, 4.5 KW, an O 2 flow rate of 25 cc/min, a number of scans, and deposition to a desired film thickness to form an active layer.
  • the active layer pattern 4 is finally formed by a patterning process.
  • Step 5 as shown in Figure 2d, forming source 5 and drain 6;
  • a source 5 and a drain 6 having a thickness of 50 to 400 nm are prepared by sputtering using a material such as molybdenum, aluminum, an aluminum-niobium alloy, or copper, and photolithography and etching are performed according to a desired pattern.
  • the method provided by the embodiment of the present invention reduces the formation of the active layer 4 having C-axis crystal orientation characteristics by using indium gallium zinc oxide InGaO 3 (ZnO) m , m ⁇ 2 .
  • the crystallization temperature of the indium gallium zinc oxide improves the stability of the formed active layer 4, and the active layer 4 made of InGaO 3 (ZnO) m has a good electron transporting effect.
  • the display substrate In the production of the display substrate, in addition to the above-described steps of fabricating the thin film transistor, as needed, other structures, such as pixel electrodes, pixel defining layers, anodes, etc., which are provided for display in the display substrate, are not required, and the present invention is not specific to the display substrate.
  • the structure is limited.
  • the display substrate provided by the embodiment of the present invention may include a pixel electrode 7 connected to the drain electrode 6 through a via hole.
  • the active layer to be formed may be divided into three or more layers, wherein the growth rate of the indium gallium zinc oxide InGaO 3 (ZnO) m of each layer may be gradually increased.
  • the manner of the increase is increased, and the power of the corresponding deposition laser or sputtering apparatus or the like is also gradually changed to obtain the desired active layer.
  • the method for fabricating the thin film transistor of the embodiment of the present invention changes the zinc content of the existing target component by using an active layer formed by indium gallium zinc oxide InGaO 3 (ZnO) m having C-axis crystal orientation characteristics.
  • the crystallization temperature of the indium gallium zinc oxide is lowered, and the stability of the bias test of the thin film transistor is improved.
  • the etch rate of the indium gallium zinc oxide sample after crystallization in the source and drain etching liquid is slow. Several times, precise control of the etching can be achieved.
  • the characteristics of the active layer material enable the thin film transistor to adopt a back channel etch type structure, which reduces the fabrication process of the etch barrier layer separately, can simplify the fabrication process of the oxide thin film transistor, and save the manufacturing cost.
  • the active layer made of InGaO 3 (ZnO) m has a good electron migration effect and improves the quality of the produced active layer.
  • an embodiment of the present invention provides a thin film transistor including an active layer 4 disposed on a substrate 1, wherein the active layer 4 is indium gallium zinc oxide InGaO 3 (ZnO) m A film layer having C-axis crystal orientation characteristics, wherein m ⁇ 2 is formed.
  • the indium gallium zinc oxide of the embodiment of the present invention is InGaO 3 (ZnO) m , m ⁇ 2, and therefore, the indium gallium zinc oxide forming the active layer 4 can be made of materials of different compositions; for example, the above InGaO 3 (ZnO) m may be any of InGaZn 2 O 5 , InGaZn 3 O 6 , InGaZn 4 O 7 , InGaZn 5 O 8 or InGaZn 6 O 9 . These materials have a change in the content of zinc in the composition of the target in the general art, and finally lower the crystallization temperature of the oxide active layer.
  • the active layer 4 made of InGaO 3 (ZnO) m has a good electron transporting effect and improves the quality of the active layer 4.
  • the etched InGaO 3 (ZnO) m sample is etched in the source and drain etchants.
  • the etch rate is several times slower and precise control of the etch can be achieved.
  • the indium gallium zinc oxide provided by the embodiment of the present invention is not limited to the ones listed in the above specific examples, and any indium gallium zinc oxide satisfying InGaO 3 (ZnO) m and m ⁇ 2 can be applied to the present invention. In the examples.
  • the structure of the thin film transistor provided by the embodiment of the present invention further includes a gate electrode 2, and a gate insulating layer 3 disposed between the gate electrode 2 and the active layer 4.
  • the structure of the thin film transistor provided in this embodiment is: a gate electrode 2, a gate insulating layer 3 disposed above the gate electrode 2, and an active layer 4 disposed above the gate insulating layer 3, respectively, and the active layer 4
  • the source 5 and the drain 6 are connected, wherein the source 5, the drain 6, and the active layer 4 form a back channel etch type structure.
  • the back channel etch type structure omits the arrangement of the etch barrier layer on the active layer, and the thin film transistor has a simple structure and a simple manufacturing process, low fabrication cost, and high production efficiency.
  • the active layer 4 formed of indium gallium zinc oxide InGaO 3 (ZnO) m by using the active layer 4 formed of indium gallium zinc oxide InGaO 3 (ZnO) m , the content of zinc in the existing target is changed, and the crystallization temperature of the indium gallium zinc oxide is lowered, thereby improving The stability of the formed active layer 4 is achieved. And the active layer 4 made of InGaO 3 (ZnO) m has a good electron migration effect and improves the quality of the active layer 4.
  • the etched InGaO 3 (ZnO) m sample is etched in the source and drain etchants. The etch rate is several times slower and precise control of the etch can be achieved.
  • the back channel etch type structure thin film transistor requires the etching solution to have different etching selectivity ratios to the active layer and the source and drain layers, otherwise the channel may be greatly damaged during the patterning of the source and drain layers. Even the channel is etched away.
  • the in-crystalized InGaO 3 (ZnO) m is less affected by the source and drain etching liquids than the amorphous indium zinc oxide, and the physical properties enable the back channel to be engraved.
  • Etched oxide thin film transistor structure Compared with the etch barrier type thin film transistor structure, the etch stop layer can be saved in a separate patterning process, which can simplify the fabrication process of the oxide thin film transistor and save the manufacturing cost.
  • the embodiment of the invention further provides a display substrate comprising a substrate 1 and the thin film transistor of any one of the substrates 1 disposed on the substrate 1.
  • the display substrate may further include other structures, such as a pixel electrode, a pixel defining layer, an anode, and the like, which are provided for display, and the present invention does not limit the specific structure of the display substrate.
  • the display substrate provided by the embodiment of the present invention may include a pixel electrode 7, and the pixel electrode 7 passes through a via and a drain. The pole 6 is connected.
  • the display substrate in the embodiment of the present invention has a thin film transistor which changes the content of zinc in the existing target by using an active layer formed by indium gallium zinc oxide InGaO 3 (ZnO) m and having C-axis crystal orientation characteristics.
  • the crystallization temperature of the indium gallium zinc oxide is lowered, and the stability of the bias voltage test of the thin film transistor is improved.
  • the etch rate of the indium gallium zinc oxide sample after crystallization in the source and drain etching liquid is slow. Several times to achieve precise control of the etch.
  • the characteristics of the material enable the thin film transistor to adopt a back channel etch type structure, which reduces the fabrication process of the etch barrier layer.
  • the active layer made of InGaO 3 (ZnO) m has a good electron migration effect, improves the quality of the active layer produced, and further improves the quality of the display device.
  • Embodiments of the present invention also provide a display device including the display substrate.
  • the active layer 4 having C-axis crystal orientation characteristics formed by indium gallium zinc oxide InGaO 3 (ZnO) m , the crystallization temperature of the indium gallium zinc oxide is lowered, thereby improving the formation.
  • the active layer 4 made of InGaO 3 (ZnO) m has a good electron migration effect, improves the quality of the active layer 4 produced, and further improves the quality of the display device.

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Abstract

一种薄膜晶体管及其制作方法、显示基板和显示装置，该薄膜晶体管的制作方法包括：在衬底（1）上采用铟镓锌氧化物InGaO3(ZnO)m形成具有C轴结晶取向特性的有源层（4），其中m≥2。采用InGaO3(ZnO)m制作的有源层具有良好的电子迁移效果，提高了制作的有源层的质量。

Description

薄膜晶体管及其制作方法、显示基板和显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管及其制作方法、显示基板和显示装置。
背景技术
氧化物晶体管由于具有较高的迁移率及与a-Si生产线兼容性好而受到广泛的关注。然而，具有刻蚀阻挡层(ESL)结构的氧化物晶体管由于存在工艺复杂的缺点，相对于a-Si竞争力不足，因此开发背沟道刻蚀型(BCE)的氧化物(如铟镓锌氧化物)薄膜晶体管成为开发重点。
发明内容
本发明的实施例提供了一种薄膜晶体管及其制作方法、显示基板和显示装置。
根据本发明的至少一个实施例，提供一种薄膜晶体管的制作方法，该方法包括以下步骤：在衬底上采用铟镓锌氧化物InGaO3(ZnO)m制作具有C轴结晶取向特性的有源层，其中m≥2。
在一个示例中，所述有源层通过在所述衬底上至少两次沉积铟镓锌氧化物层而形成。
在一个示例中，在所述采用铟镓锌氧化物InGaO3(ZnO)m制作具有C轴结晶取向特性的有源层的过程中，通过物理气相沉积方式以第一功率和第一速率沉积具有C轴取向的第一铟镓锌氧化物层；在形成的第一层铟镓锌氧化物层上通过物理气相沉积方式以第二功率和第二速率沉积第二铟镓锌氧化物层，所述第一铟镓锌氧化物层和第二铟镓锌氧化物层形成有源层，其中所述第一功率小于所述第二功率，所述第一速率小于所述第二速率。
在一个示例中，所述形成第一铟镓锌氧化物层的温度条件和第二铟镓锌氧化物层的温度条件均为200℃～400℃。
在一个示例中，采用Nd:YAG激光器在真空条件下沉积形成所述有源层，以及所述激光器的输出波长为193～1064nm，重复频率为大于1Hz，脉宽小 于10ns。
在一个示例中，采用Nd:YAG激光器在真空条件下沉积形成所述有源层，以及所述激光器的输出波长为1064nm，重复频率为10Hz，脉宽为10ns。
在一个示例中，所述第一功率为激光器聚焦前功率为0.2～0.4W。
在一个示例中，所述第一功率为激光器聚焦前功率为0.3W。
在一个示例中，沉积所述第一铟镓锌氧化物层的时间为10～30s，形成的所述第一铟镓锌氧化物层的厚度：0<d≤10nm。
在一个示例中，所述第二功率为激光器聚焦前功率为0.5～1.0W。
在一个示例中，所述第二功率为聚焦前功率为0.5W。
在一个示例中，所述第一铟镓锌氧化物层和所述第二铟镓锌氧化物层在真空条件下以溅射方式形成。
在一个示例中，在真空条件下进行溅射时，向真空室通入氧气和Ar气，其比例O:Ar＝1:4。
在一个示例中，所述第一铟镓锌氧化物层以2～3KW的所述第一功率，O2流量为25标况毫升/分的条件，一次扫描形成；以及
所述第二层铟镓锌氧化物层以4～6KW的所述第二功率，O2流量为25标况毫升/分的条件，一次扫描形成。
在一个示例中，所述第一铟镓锌氧化物层在所述第一功率3KW，O2流量为25标况毫升/分的条件下，通过一次扫描形成；所述第二层铟镓锌氧化物层以所述第二功率4.5KW，O2流量为25标况毫升/分的条件下，通过一次扫描形成。
在一个示例中，所述铟稼锌氧化物InGaO3(ZnO)m包含：InGaZn2O5、InGaZn3O6、InGaZn4O7、InGaZn5O8或InGaZn6O9中的任一种。
在一个示例中，所述有源层分成三层在所述衬底上沉积形成，其中每一层的铟镓锌氧化物InGaO3(ZnO)m生长速度以逐渐递增的方式增大。
本发明的至少一个实施例还提供了一种薄膜晶体管，该薄膜晶体管包括设置于衬底上的有源层，其中所述有源层包括具有C轴结晶取向特性的铟稼锌氧化物，所述铟稼锌氧化物为InGaO3(ZnO)m，其中m≥2。
在一个示例中，所述铟稼锌氧化物InGaO3(ZnO)m包含InGaZn2O5、InGaZn3O6、InGaZn4O7、InGaZn5O8或InGaZn6O9中的任一种。
本发明的至少一个实施例还提供了一种显示基板，该显示基板包括衬底 以及设置于所述衬底上的所述薄膜晶体管。
本发明的至少一个实施例还提供了一种显示装置，该显示装置包括上述显示基板。
附图说明
以下将结合附图对本发明的实施例进行更详细的说明，以使本领域普通技术人员更加清楚地理解本发明，其中：
图1为本发明实施例提供的显示基板的结构示意图；
图2a～图2d为本发明实施例提供的具有薄膜晶体管结构的制作流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在不需做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，本文使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“上”、“下”、等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
发明人注意到，在薄膜氧化物晶体管的制作过程中，由于铟镓锌氧化物的晶化温度高，而如常用的铟镓锌氧化物半导体薄膜晶体管器件及背板制备时采用的靶材成分InGaZnO4，因此利用该成分靶材进行沉积的样品不易晶化，甚至基底加热至500度时仍不能结晶，该方法对工艺要求较高，从而影响到薄膜晶体管的生产效率以及其稳定性。
为了提高薄膜晶体管的制作效率以及薄膜晶体管的稳定性，本发明实施例提供了一种薄膜晶体管及其制作方法、显示基板和显示装置。在本发明至 少一个实施例的技术方案中，通过采用铟镓锌氧化物InGaO3(ZnO)m形成的具有C轴结晶取向特性的有源层，该方法改变了现有靶材中锌的含量，降低了铟镓锌氧化物的结晶温度，提高了薄膜晶体管的偏压测试的稳定性。与未结晶的铟镓锌氧化物样品在源、漏极刻蚀液中的刻蚀速率相比，结晶后的铟镓锌氧化物样品在源、漏极的刻蚀液中的刻蚀速率慢数倍，可以实现刻蚀的精确控制。该材料特性可使薄膜晶体管可采用背沟道刻蚀型结构，减少了刻蚀阻挡层的制作工艺。并且，采用InGaO3(ZnO)m制作的有源层具有良好的电子迁移效果，提高了制作的有源层的质量，进而提高了显示装置的质量。
本发明的实施例提供了一种薄膜晶体管的制作方法，该方法包括以下步骤：
在衬底上采用铟镓锌氧化物InGaO3(ZnO)m形成具有C轴结晶取向特性的有源层，其中m≥2。
C轴结晶取向为：X轴沿水平取向，Y轴垂直于X轴，Z轴垂直于XY轴所构成的平面，沿Z轴作圆周运动就是C轴取向。在上述方法中，通过采用铟镓锌氧化物InGaO3(ZnO)m形成的具有C轴结晶取向特性的有源层，该方法改变了现有靶材中锌的含量，降低了铟镓锌氧化物的结晶温度，提高了薄膜晶体管的偏压测试的稳定性。与未结晶的铟镓锌氧化物样品在源、漏极刻蚀液中的刻蚀速率相比，结晶后的铟镓锌氧化物样品在源、漏极的刻蚀液中的刻蚀速率慢数倍，可以实现刻蚀的精确控制。该材料特性可使薄膜晶体管可采用背沟道刻蚀型结构，减少了刻蚀阻挡层的制作工艺。并且，采用InGaO3(ZnO)m制作的有源层具有良好的电子迁移效果，提高了制作的有源层的质量。
铟稼锌氧化物InGaO3(ZnO)m例如可为：InGaZn2O5、InGaZn3O6、InGaZn4O7、InGaZn5O8或InGaZn6O9中的任一种。采用此种铟镓锌氧化物制作有源层，由于其具有较低的结晶温度，在200～400℃的条件下即可结晶，因此，有效地降低了铟镓锌氧化物的结晶温度。
在一个示例中，在所述采用铟镓锌氧化物InGaO3(ZnO)m制作具有C轴结晶取向特性的有源层的过程中，
通过物理气相沉积方式以第一功率和第一速率沉积具有C轴取向的第一铟镓锌氧化物层。
在形成的第一层铟镓锌氧化物层上通过物理气相沉积方式以第二功率和 第二速率沉积第二铟镓锌氧化物层。所述第一铟镓锌氧化物层和第二铟镓锌氧化物层形成有源层。所述第一功率小于所述第二功率，所述第一速率小于所述第二速率。
通过慢速沉积形成第一铟镓锌氧化物层，由于沉积速率慢，第一铟镓锌氧化物层可获得较好的结晶效果。而在后续快速沉积形成第二铟镓锌氧化物层时，第一铟稼锌氧化物层可作为第二铟镓锌氧化物层结晶时的晶核，因此，可以提高第二铟镓锌氧化物层结晶速率，进而提高有源层的制作效率，同时使生成的有源层具有C轴结晶取向特性。
例如，第一铟镓锌氧化物层和第二铟镓锌氧化物层均在200℃～400℃的温度条件下形成。因此，与一般技术相比，降低了铟镓锌氧化物结晶时的温度。
在采用物理沉积方式形成有源层时，可以采用不同的工艺方法。
可选择的，例如可以采用激光脉冲方式，以第一功率和第一速率沉积具有C轴结晶取向特性的第一铟镓锌氧化物层；在形成的第一层铟镓锌氧化物层上以第二功率和第二速率沉积第二铟镓锌氧化物层，所述第一铟镓锌氧化物层和第二铟镓锌氧化物层形成有源层。
例如，采用Nd:YAG脉冲激光器形成有源层。所述激光器的输出波长为193-1064nm，例如为1064nm，重复频率大于1Hz，例如为10Hz，脉宽小于等于10ns。
在制作过程中，首先，打开真空系统的机械泵，对真空室抽真空。当真空度达到0～5Pa时，打开分子泵，继续进行抽真空操作。
当真空度达到2.5×10-4Pa时，关闭分子泵，打开机械泵，并同时向真空室通入氧气，使氧分压保持在10.0Pa。
沉积时，聚焦前激光采用第一功率为0.2-0.4W，例如为0.3W，沉积铟镓锌氧化物层时的温度为200～400度，沉积时间为10～30s，并以第一速率形成一层厚度在0<d≤10nm之间的第一铟镓锌氧化物层。
然后，降低氧气流量，保持真空腔压强为5.0Pa，聚焦前激光采用第二功率为0.5-1.0W，例如为0.5W，在第一铟镓锌氧化物层上以第二沉积速率形成第二铟镓锌氧化物层，以形成所述有源层。
或者，还可以采用溅射方式形成有源层。
在该方式的一个示例中，当真空度达到2.5×10-4Pa时，开始进行铟镓锌氧化物薄膜沉积，沉积温度保持200～400度不变，向真空室通入氧气和Ar 气，O:Ar＝1：4。
沉积时的功率采用第一功率2-3KW，例如为3KW，O2流量为25标况毫升/分，扫描次数为1次，使铟镓锌氧化物以第一速率形成第一铟镓锌氧化物层。
在沉积的第一层铟镓锌氧化物层上沉积第二层铟镓锌氧化物层，在沉积时，沉积功率提高至第二功率4-6KW，例如为4.5KW，O2流量为25标况毫升/分，扫描次数为1次，沉积至所需薄膜厚度，以形成所述有源层。
在本发明的实施例中，通过不同的工艺条件形成两层铟镓锌氧化物层：通过慢速沉积形成第一铟镓锌氧化物层，由于沉积速率慢，第一铟镓锌氧化物层可获得较好的结晶效果。并且，在后续快速沉积形成第二铟镓锌氧化物层时，第一铟稼锌氧化物层可作为第二铟镓锌氧化物层结晶时的晶核，从而提高第二铟镓锌氧化物层结晶速率，进而提高有源层的制作效率，同时可以使生成的有源层具有C轴结晶取向特性。这样结晶后的InGaO3(ZnO)m样品在源、漏极的刻蚀液中的刻蚀速率，比未结晶的铟稼锌氧化物样品在源、漏极刻蚀液中的刻蚀速率慢数倍，可以实现刻蚀的精确控制。背沟道刻蚀型结构薄膜晶体管，要求刻蚀液对有源层和源、漏极层有不同的刻蚀选择比，否则在源、漏极层图案过程中会较大地损伤沟道甚至把沟道刻蚀掉。本发明实施例中结晶后的InGaO3(ZnO)m相对于非晶的铟稼锌氧化物，其受源、漏极刻蚀液影响更小，这样的物理性质使其可采用背沟道刻蚀型氧化物薄膜晶体管结构。相对于刻蚀阻挡层型的薄膜晶体管结构，其可节省刻蚀阻挡层单独的构图工艺，可简化氧化物薄膜晶体管的制作流程，节省制作成本。
附图2a～图2d为本发明的一个实施例提供的薄膜晶体管结构的生产流程图，下面结合其中的图2a～图2d对本发明实施例提供的薄膜晶体管的制作方法进行详细说明。
步骤一、对透明衬底1采用标准方法进行清洗。
步骤二、如图2a所示，在透明衬底1上形成栅极2。
例如，用溅射或蒸镀法沉积50～400nm的栅极金属层，进行图形化形成栅极2。
步骤三、如图2b所示，在栅极2上形成栅极绝缘层3。
例如，利用等离子体增强化学气相沉积法制备厚度为100～500nm的SiNx或SiOx的栅极绝缘层3，其中x为自然数。
步骤四、如图2c所示，采用铟镓锌氧化物InGaO3(ZnO)m制作具有C轴结晶取向特性的有源层4，其中m≥2。
例如，通过物理气相沉积方式以第一功率和第一速率沉积具有C轴取向的第一铟镓锌氧化物层。
在形成的第一层铟镓锌氧化物层上通过物理气相沉积方式以第二功率和第二速率沉积第二铟镓锌氧化物层，第一铟镓锌氧化物层和第二铟镓锌氧化物层形成有源层4，其中第一功率小于第二功率，第一速率小于第二速率。
物理气相沉积方法可以为溅射或激光脉冲的方式。
1)激光脉冲方式：所使用的激光系统为Nd:YAG脉冲激光器，其输出波长为193-1064nm，例如为1064nm，重复频率大于1Hz，例如为10Hz，脉宽小于等于10ns。本发明的实施例采用该激光器的三次谐波(波长为355nm)。首先，打开真空系统的机械泵，对真空室抽真空。当真空度达到0～5Pa时，打开分子泵，继续进行抽真空操作。当真空度达到2.5×10-4Pa时，关闭分子泵，打开机械泵，并同时向真空室通入氧气，使氧分压保持在10.0Pa。沉积时，聚焦前激光平均功率为0.2-0.4W，例如为0.3W。沉积铟镓锌氧化物层时的温度为200～400度，沉积时间为10～30s，形成一层0-10nm的铟镓锌氧化物层，即第一铟镓锌氧化物层。第一铟镓锌氧化物层作为籽晶可提高结晶性能。然后降低氧气流量，保持真空腔压强为5.0Pa，聚焦前激光平均功率为0.5-1.0W，例如为0.5W，在第一铟镓锌氧化物层上继续沉积形成第二铟镓锌氧化物层至所需厚度，以形成有源层。
2)溅射方式：当真空度达到2.5×10-4Pa时，开始进行铟镓锌氧化物薄膜沉积，沉积温度保持200～400度不变，并向真空室通入氧气和Ar气，O:Ar＝1:4。
沉积时的功率采用第一功率2-3KW，例如3KW，O2流量为25标况毫升/分，扫描次数为1次，使铟镓锌氧化物以第一速率形成第一铟镓锌氧化物层；
在沉积的第一层铟镓锌氧化物层上沉积第二层铟镓锌氧化物层。在沉积时，沉积功率提高至第二功率4-6KW，例如4.5KW，O2流量为25标况毫升/分，扫描次数为1次，沉积至所需薄膜厚度，以形成有源层。
在沉积形成铟镓锌氧化物有源层后，通过构图工艺最终形成有源层图形4。
步骤五、如图2d所示，形成源极5和漏极6；
例如，采用钼、铝、铝钕合金，铜等材料，通过溅射的方式制备厚度为50～400nm的源极5和漏极6，并根据所需图形进行光刻和刻蚀。
通过上述具体实施例描述可以看出，本发明实施例提供的方法，通过采用铟镓锌氧化物InGaO3(ZnO)m，m≥2形成具有C轴结晶取向特性的有源层4，降低了铟镓锌氧化物的结晶温度，提高了形成的有源层4的稳定性，并且采用InGaO3(ZnO)m制作的有源层4具有良好的电子迁移效果。
在制作显示基板时，根据需要，除上述制作薄膜晶体管的步骤外还包括制作显示基板中为实现显示而设置的其他结构，如像素电极、像素界定层、阳极等，本发明不对显示基板的具体结构做限定。如图1所示，本发明实施例提供的显示基板可以包括像素电极7，像素电极7通过过孔与漏极6相连。
在本发明的其它实施例中，可以通过将要形成的有源层分成三层或更多层的方式实施，其中每一层的铟镓锌氧化物InGaO3(ZnO)m生长速度可以以逐渐递增的方式增大，并且对应的沉积用的激光器或溅射设备等的功率也相应的逐渐变化，从而获得需要的有源层。
本发明实施例的薄膜晶体管的制作方法，通过采用铟镓锌氧化物InGaO3(ZnO)m形成的具有C轴结晶取向特性的有源层，改变了现有靶材组分中锌的含量，降低了铟镓锌氧化物的结晶温度，提高了薄膜晶体管的偏压测试的稳定性。与未结晶的铟镓锌氧化物样品在源、漏极刻蚀液中的刻蚀速率相比，结晶后的铟镓锌氧化物样品在源、漏极的刻蚀液中的刻蚀速率慢数倍，可以实现刻蚀的精确控制。即有源层材料的特性使薄膜晶体管可采用背沟道刻蚀型结构，减少了刻蚀阻挡层单独形成的制作工艺，可简化氧化物薄膜晶体管的制作流程，节省制作成本。并且采用InGaO3(ZnO)m制作的有源层具有良好的电子迁移效果，提高了制作的有源层的质量。
如图2d所示，本发明实施例提供了一种薄膜晶体管，该薄膜晶体管包括设置于衬底1上的有源层4，其中有源层4为铟镓锌氧化物InGaO3(ZnO)m形成的具有C轴结晶取向特性的薄膜层，其中m≥2。
本发明实施例的铟镓锌氧化物为InGaO3(ZnO)m，m≥2，因此，制作有源层4的铟镓锌氧化物可以为不同组分的材料制作而成；例如，上述InGaO3(ZnO)m可以为：InGaZn2O5、InGaZn3O6、InGaZn4O7、InGaZn5O8或InGaZn6O9中的任一种。这些材料相对于一般技术中的靶材，其组成中锌的含量发生了改变，最终降低了氧化物有源层的结晶温度。并且采用InGaO3(ZnO)m制作 的有源层4具有良好的电子迁移效果，提高了有源层4的质量。此外，与未结晶的铟稼锌氧化物样品在源、漏极刻蚀液中的刻蚀速率相比，结晶后的InGaO3(ZnO)m样品在源、漏极的刻蚀液中的刻蚀速率慢数倍，可以实现刻蚀的精确控制。应当理解的是，本发明实施例提供的铟镓锌氧化物不限于上述具体实施例列举的几种，任何满足InGaO3(ZnO)m，m≥2的铟镓锌氧化物均可应用于本实施例中。
继续参考图2d，本发明实施例提供的薄膜晶体管的结构还包括栅极2、设置于栅极2和有源层4之间的栅极绝缘层3。本实施例提供的薄膜晶体管的结构为：栅极2、设置在栅极2上方的栅极绝缘层3、设置在栅极绝缘层3上方的有源层4，分别与有源层4两端连接的源极5和漏极6，其中源极5、漏极6以及有源层4形成背沟道刻蚀型结构。背沟道刻蚀型结构在有源层上省略了刻蚀阻挡层的设置，该薄膜晶体管结构和制作工艺简单、制作成本低、生产效率高。
在上述实施例中，通过采用铟镓锌氧化物InGaO3(ZnO)m形成的有源层4，改变了现有靶材中锌的含量，降低了铟镓锌氧化物的结晶温度，从而提高了形成的有源层4的稳定性。并且采用InGaO3(ZnO)m制作的有源层4具有良好的电子迁移效果，提高了有源层4的质量。此外，与未结晶的铟稼锌氧化物样品在源、漏极刻蚀液中的刻蚀速率相比，结晶后的InGaO3(ZnO)m样品在源、漏极的刻蚀液中的刻蚀速率慢数倍，可以实现刻蚀的精确控制。而背沟道刻蚀型结构薄膜晶体管，要求刻蚀液对有源层和源、漏极层有不同的刻蚀选择比，否则在源、漏极层图案化过程中会较大地损伤沟道甚至把沟道刻蚀掉。本发明实施例中结晶后的InGaO3(ZnO)m相对于非晶的铟稼锌氧化物，其受源、漏极刻蚀液影响更小，这样的物理性质使其可采用背沟道刻蚀型氧化物薄膜晶体管结构。相对于刻蚀阻挡层型的薄膜晶体管结构，其可节省刻蚀阻挡层单独的构图工艺，可简化氧化物薄膜晶体管的制作流程，节省制作成本。
本发明实施例还提供了一种显示基板，该显示基板包括衬底1以及设置于衬底1上的所述任一项的薄膜晶体管。该显示基板除上述薄膜晶体管外，根据需要，该显示基板还可以包括实现显示而设置的其他结构，如像素电极、像素界定层、阳极等，本发明不对显示基板的具体结构做限定。如图1所示，本发明实施例提供的显示基板可以包括像素电极7，像素电极7通过过孔与漏 极6相连。
本发明实施例中的显示基板，其具有的薄膜晶体管通过采用铟镓锌氧化物InGaO3(ZnO)m形成的具有C轴结晶取向特性的有源层，改变了现有靶材中锌的含量，降低了铟镓锌氧化物的结晶温度，提高了薄膜晶体管的偏压测试的稳定性。与未结晶的铟镓锌氧化物样品在源、漏极刻蚀液中的刻蚀速率相比，结晶后的铟镓锌氧化物样品在源、漏极的刻蚀液中的刻蚀速率慢数倍，从而实现刻蚀的精确控制。也就是材料的特性使薄膜晶体管可采用背沟道刻蚀型结构，减少了刻蚀阻挡层的制作工艺。并且采用InGaO3(ZnO)m制作的有源层具有良好的电子迁移效果，提高了制作的有源层的质量，进而提高了显示装置的质量。
本发明实施例还提供了一种显示装置，该显示装置包括所述显示基板。
在上述实施例中，通过采用铟镓锌氧化物InGaO3(ZnO)m形成的具有C轴结晶取向特性的有源层4，降低了铟镓锌氧化物的结晶温度，从而提高了形成的有源层4的稳定性。并且采用InGaO3(ZnO)m制作的有源层4具有良好的电子迁移效果，提高了制作的有源层4的质量，进而提高了显示装置的质量。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有这样的变化和变形以及等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。
本申请要求于2014年05月07日提交的名称为“薄膜晶体管及其制作方法、显示基板和显示装置”的中国专利申请No.201410190720.9的优先权，其全文以引用方式合并于本文。

Claims (22)

  1. 一种薄膜晶体管的制作方法，包括：
    在衬底上采用铟镓锌氧化物InGaO3(ZnO)m形成具有C轴结晶取向特性的有源层，其中m≥2。
  2. 如权利要求1所述的薄膜晶体管的制作方法，其中所述有源层通过在所述衬底上至少两次沉积铟镓锌氧化物层而形成。
  3. 如权利要求1或2所述的薄膜晶体管的制作方法，其中，
    在采用铟镓锌氧化物InGaO3(ZnO)m形成具有C轴结晶取向特性的有源层过程中，
    通过物理气相沉积方式以第一功率和第一速率沉积具有C轴结晶取向特性的第一铟镓锌氧化物层；以及
    在形成的第一层铟镓锌氧化物层上通过物理气相沉积方式以第二功率和第二速率沉积第二铟镓锌氧化物层，所述第一铟镓锌氧化物层和第二铟镓锌氧化物层形成所述有源层；
    所述第一功率小于所述第二功率，所述第一速率小于所述第二速率。
  4. 如权利要求1-3任一项所述的薄膜晶体管的制作方法，其中所述形成第一铟镓锌氧化物层的温度条件和第二铟镓锌氧化物层的温度条件均为200℃～400℃。
  5. 如权利要求1-4任一项所述的薄膜晶体管的制作方法，其中采用Nd:YAG激光器在真空条件下沉积形成所述有源层，以及
    所述激光器的输出波长为193～1064nm，重复频率为大于1Hz，脉宽小于10ns。
  6. 如权利要求1-4任一项所述的薄膜晶体管的制作方法，其中采用Nd:YAG激光器在真空条件下沉积形成所述有源层，以及
    所述激光器的输出波长为1064nm，重复频率为10Hz，脉宽为10ns。
  7. 如权利要求5或6所述的薄膜晶体管的制作方法，其中，所述第一功率为激光器聚焦前功率为0.2～0.4W。
  8. 如权利要求5或6所述的薄膜晶体管的制作方法，其中，所述第一功率为激光器聚焦前功率为0.3W。
  9. 如权利要求3-8任一项所述的薄膜晶体管的制作方法，其中沉积所述第一铟镓锌氧化物层的时间为10～30s，形成的所述第一铟镓锌氧化物层的厚度大于0，小于等于10nm。
  10. 如权利要求9所述的薄膜晶体管的制作方法，其中所述第二功率为激光器聚焦前功率为0.5～1.0W。
  11. 如权利要求9所述的薄膜晶体管的制作方法，其中所述第二功率为激光器聚焦前功率为0.5W。
  12. 如权利要求3或4所述的薄膜晶体管的制作方法，其中所述第一铟镓锌氧化物层和所述第二铟镓锌氧化物层在真空条件下以溅射方式形成。
  13. 如权利要求12所述的薄膜晶体管的制作方法，其中，在真空条件下进行溅射时，向真空室通入氧气和氩气混合气。
  14. 如权利要求13所述的薄膜晶体管的制作方法，其中所述氧气和氩气比例为O:Ar＝1:4。
  15. 如权利要求14所述的薄膜晶体管的制作方法，其中，所述第一铟镓锌氧化物层以2～3KW的所述第一功率，O2流量为25标况毫升/分的条件，一次扫描形成；以及
    所述第二层铟镓锌氧化物层以4～6KW的所述第二功率，O2流量为25标 况毫升/分的条件，一次扫描形成。
  16. 如权利要求14所述的薄膜晶体管的制作方法，其中，所述第一铟镓锌氧化物层以3KW的所述第一功率，O2流量为25标况毫升/分的条件，一次扫描形成；以及
    所述第二层铟镓锌氧化物层以4.5KW的所述第二功率，O2流量为25标况毫升/分的条件，一次扫描形成。
  17. 如权利要求1-16任一项所述的薄膜晶体管的制作方法，其中所述铟稼锌氧化物InGaO3(ZnO)m包含：InGaZn2O5、InGaZn3O6、InGaZn4O7、InGaZn5O8或InGaZn6O9中的任一种。
  18. 如权利要求2所述的薄膜晶体管的制作方法，其中所述有源层分成三层在所述衬底上沉积形成，其中每一层的铟镓锌氧化物InGaO3(ZnO)m生长速度以逐渐递增的方式增大。
  19. 一种薄膜晶体管，包括设置于衬底上的有源层，其中所述有源层包括具有C轴结晶取向特性的铟稼锌氧化物，所述铟稼锌氧化物为InGaO3(ZnO)m，其中m≥2。
  20. 如权利要求19所述的薄膜晶体管，其中所述铟稼锌氧化物InGaO3(ZnO)m包含：InGaZn2O5、InGaZn3O6、InGaZn4O7、InGaZn5O8或InGaZn6O9中的任一种。
  21. 一种显示基板，包括衬底以及设置在所述衬底上的如权利要求19或20所述的薄膜晶体管。
  22. 一种显示装置，包括如权利要求21所述的显示基板。
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