WO2015168961A1 - 薄膜晶体管阵列基板制造方法及薄膜晶体管阵列基板 - Google Patents

薄膜晶体管阵列基板制造方法及薄膜晶体管阵列基板 Download PDF

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WO2015168961A1
WO2015168961A1 PCT/CN2014/077626 CN2014077626W WO2015168961A1 WO 2015168961 A1 WO2015168961 A1 WO 2015168961A1 CN 2014077626 W CN2014077626 W CN 2014077626W WO 2015168961 A1 WO2015168961 A1 WO 2015168961A1
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layer
gate
thin film
film transistor
drain
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French (fr)
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戴天明
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
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    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
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    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
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    • H10D86/01—Manufacture or treatment
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    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present invention relates to an array substrate manufacturing method and an array substrate, and more particularly to a method for fabricating a low temperature polysilicon thin film transistor array substrate and a thin film transistor array substrate.
  • Liquid crystal display (Liquid Crystal Display, LCD) has a large number of applications in various electronic products due to its small size, light weight, and low power consumption.
  • low temperature polysilicon Low Temperature Poly Silicon, LTPS
  • LTPS Low Temperature Poly Silicon
  • low-temperature polysilicon has the following problems.
  • the structure of the existing standard low-temperature polysilicon thin film transistor (LTPS-TFT) will contain two n-type doping regions for the source and the drain on the polysilicon layer, due to the two n-types.
  • the doping concentration of the doped region is high, and the spacing between the gate electrode and the gate electrode is very small, resulting in an electric field near the drain being too strong, thus generating a hot carrier effect (hot Carrier effect), causing leakage current of the polysilicon thin film transistor in the off state (leakage The problem of current) arises.
  • hot Carrier effect hot Carrier effect
  • lightly doped drain structure lightly doped drain, LDD
  • LDD lightly doped drain
  • FIG. 1 in the process of a general low-temperature polysilicon thin film transistor, self-aligning is formed.
  • the flow of the lightly doped drain structure thin film transistor array substrate is as follows: 1. A buffer layer 11 and an amorphous silicon layer are deposited on the substrate 10, and are crystallized into a polysilicon layer 12 by a laser tempering (ELA) process. The mask defines a polysilicon region. 2.
  • An n-type doped block is defined by a photomask and ions are implanted by an ion implantation process to form an n-type doped region 13.
  • the gate insulating layer 14 is deposited by low temperature chemical vapor deposition (PECVD).
  • PECVD low temperature chemical vapor deposition
  • a gate 15 is deposited over the gate insulating layer 14, a gate region is defined by a mask, and metal in other regions is etched away by dry etching. 5.
  • the ion implantation process (at the arrow in the figure) is performed with the gate 15 as a mask to form a lightly doped drain region 16.
  • the gate metal is etched by dry etching, a certain etching of the gate insulating layer causes a loss of the gate insulating layer, and subsequent ion implantation is performed to form a lightly doped drain region.
  • the dose of the ions will be uneven, which will eventually cause differences in the electrical properties of the various places on the channel, resulting in uneven brightness or various traces of the display.
  • the object of the present invention is to provide a thin film transistor array substrate manufacturing method and a thin film transistor array substrate, which avoids the loss of the gate insulating layer when the gate electrode is dry etched, improves the uniformity of the thickness of the gate insulating layer, and enables implantation.
  • the ion dose of the lightly doped drain region remains the same.
  • the present invention provides a method for fabricating a thin film transistor array substrate, comprising the following steps:
  • the step of forming a buffer layer may be further included before the formation of the polysilicon layer on the substrate.
  • the drain doping region and the source doping region are formed by implanting phosphorus ions into the polysilicon layer.
  • the gate metal layer is etched by using a dry etching process to etch away a gate metal layer other than the first mask to form the gate, and the metal oxide layer is performed.
  • Etching is to etch away a metal oxide layer other than the second mask by using a wet etching process and using the gate as a second mask.
  • the gate insulating layer is a silicon oxide (SiO2) layer and a silicon nitride (SiNX). Layer or layered structure.
  • the metal oxide layer is made of indium tin oxide (ITO).
  • the dimensional deviation between the metal oxide layer and the gate is less than 0.3 um.
  • the thin film transistor array substrate is suitable for an organic light emitting diode (Organic) Light-Emitting Diode, OLED) display.
  • Organic light emitting diode Organic Light-Emitting Diode
  • the present invention provides a method for manufacturing a thin film transistor array substrate, comprising the following steps:
  • the step of forming a buffer layer may be further included before the formation of the polysilicon layer on the substrate.
  • the drain doping region and the source doping region are formed by implanting phosphorus ions into the polysilicon layer.
  • the gate metal layer is etched by using a dry etching process to etch away a gate metal layer other than the first mask to form the gate, and the metal oxide layer is performed.
  • Etching is to etch away a metal oxide layer other than the second mask by using a wet etching process and using the gate as a second mask.
  • the gate insulating layer is a silicon oxide (SiO2) layer and a silicon nitride (SiNX). Layer or layered structure.
  • the metal oxide layer is made of indium tin oxide (ITO).
  • the dimensional deviation between the metal oxide layer and the gate is less than 0.3 um.
  • the thin film transistor array substrate is suitable for an organic light emitting diode (Organic) Light-Emitting Diode, OLED) display.
  • Organic light emitting diode Organic Light-Emitting Diode
  • the present invention provides a thin film transistor array substrate, including:
  • Forming a via hole over the drain doped region depositing a metal layer on the insulating layer, the metal layer having a source and a drain, wherein the source and the drain pass through the a hole is connected to the source doped region and the drain doped region, wherein a metal oxide layer is interposed between the gate and the gate insulating layer, and the gate and the metal oxide layer are covered
  • the range is the same and does not cover the lightly doped drain region.
  • the buffer layer may be further included between the substrate and the polysilicon layer.
  • the metal oxide layer is made of indium tin oxide (ITO).
  • the dimensional deviation between the metal oxide layer and the gate is less than 0.3 um.
  • the invention discloses a method for manufacturing a thin film transistor array substrate, comprising forming a polysilicon layer and a gate insulating layer on the substrate, forming a metal oxide layer on the gate insulating layer, and forming a gate on the metal oxide layer a metal layer, etching the gate metal layer to define a gate, using the gate as a second mask to etch away a metal oxide layer outside the second mask, to the gate and the remaining metal oxide
  • the layer is ion implanted as a third mask to form a lightly doped drain region on each side of the polysilicon layer, forming an insulating layer on the gate and the gate insulating layer, and forming a metal on the insulating layer a layer, and defining a source and a drain connected to the source doping region and the drain doping region, respectively
  • the dose of the ion implantation is kept uniform, and the brightness of the display is further maintained.
  • the invention also discloses a thin film transistor array substrate prepared by the above manufacturing method.
  • FIG. 1 is a schematic view showing the process and structure of a conventional low temperature polysilicon thin film transistor
  • FIG. 2 is a flow chart showing a method of fabricating a thin film transistor array substrate in accordance with a preferred embodiment of the present invention
  • 3 to 9 are schematic diagrams showing the process and structure of a thin film transistor array substrate in accordance with a preferred embodiment of the present invention.
  • a method of fabricating a thin film transistor array substrate includes the steps of: providing a substrate, which may be made of glass, quartz, or the like.
  • a polysilicon layer on the substrate, wherein the polysilicon layer is formed on the substrate by an amorphous silicon layer, and the amorphous silicon layer is subjected to a laser tempering (ELA) process to convert the amorphous silicon into polysilicon.
  • ELA laser tempering
  • At least one polysilicon region (not shown) is subsequently defined by the mask processing and the etching process.
  • the step of forming a buffer layer may be further included before the formation of the polysilicon layer on the substrate.
  • a photoresist is coated on the polysilicon layer, and a back exposure process is applied to the substrate to define a photoresist pattern on the polysilicon layer, and then the photoresist pattern is used as a mask, and the substrate is ion implanted to n.
  • a five-valent impurity ion such as phosphorus or arsenic is selected for ion implantation (ion In the case of a p-type thin film transistor, a trivalent impurity ion such as boron or gallium is selected for ion implantation, thereby forming a drain doping region and a source doping region in the polysilicon layer.
  • phosphorus ions are implanted in the polysilicon region of the polysilicon layer to form the drain doping region and the source doping region, the drain doping region and the source. Doped regions are formed on both sides of the polysilicon layer, respectively.
  • a gate insulating layer is deposited on the polysilicon layer by low temperature chemical vapor deposition (PECVD).
  • the gate insulating layer is silicon monoxide (SiO2).
  • a metal oxide layer is formed on the gate insulating layer.
  • the metal oxide layer is made of indium tin oxide (ITO), but not limited thereto.
  • the gate metal layer is etched to use a dry etching process to etch away the gate metal layer outside the first mask to form the gate.
  • the dry etching process is mainly Because of the high critical pulse size (ppi), the critical size of the dry etch process (Critical Dimension, CD) errors are less than the error of the wet etch process.
  • the metal oxide layer outside the range of the second mask is etched away by using the gate as a second mask.
  • the metal oxide layer is etched to adopt a wet etching process. And etching the metal oxide layer outside the second mask with the gate as a second mask.
  • the ion implantation is performed by using the gate and the remaining metal oxide layer as a third mask, and therefore, the range covered by the gate and the remaining metal oxide layer does not
  • the lightly doped drain regions overlap, and the lightly doped drain regions are outside the remaining metal oxide layer and the gate coverage, and the lightly doped drain regions are respectively
  • the drain doping region and the source doping region are adjacent. This also achieves a self-aligning effect and can control the shift of the gate and the remaining metal oxide layer as a third mask. Less than 0.3um, avoiding the critical dimension (Critical Dimension, CD) error, and will not affect the gate line width.
  • the drain has a via, Defining a source doped region and a drain doped region of the polysilicon layer respectively corresponding to the via, the source and the drain respectively passing through the via and the source doped region and The drain doped regions are connected.
  • the present invention provides a thin film transistor array substrate comprising: a substrate 20 having a polysilicon layer 22 thereon; and the polysilicon layer 22 has a gate insulating layer 23 thereon.
  • the gate insulating layer 23 has a gate 24, the polysilicon layer 22 has a drain doping region 221 and a source doping region 222, and each of the polysilicon layers 22 has a light doping layer a drain region 30, the lightly doped drain region 30 is adjacent to the drain doping region 221 and the source doping region 222, respectively, and the gate electrode 24 and the gate insulating layer 23 are
  • the insulating layer 25 is respectively provided with a via hole 27 corresponding to the source doped region 222 and the drain doped region 221 of the polysilicon layer 22, and a metal layer 28 is formed on the insulating layer 25, and
  • the metal layer 28 has a source 281 and a drain 282 connected to the source doping region 222 and the drain doping region 221 of the poly
  • the thin film transistor array substrate of the present embodiment uses the gate electrode 24 and the metal oxide layer 26 as a photomask to ion implant the lightly doped drain region 30 (shown by an arrow in FIG. 7).
  • the gate 24 is aligned with the metal oxide layer 26 and the lightly doped drain region 30, and the gate 24 and metal oxide layer 26 are not covered by the lightly doped drain region 30. There is an intersection.
  • the metal oxide layer 26 is made of indium tin oxide (ITO). And the size deviation between the metal oxide layer 26 and the gate electrode 24 is less than 0.3 um, and the thin film transistor array substrate is suitable for an organic light emitting diode (Organic Light-Emitting) Diode, OLED) display.
  • ITO indium tin oxide
  • OLED Organic Light-Emitting Diode
  • the buffer layer 21 may be further included between the substrate 20 and the polysilicon layer 22.
  • the present invention provides a thin film transistor array substrate manufacturing method and a thin film transistor array substrate.
  • the metal oxide layer is used to resist the dry etching process of the gate by providing a metal oxide layer under the gate.
  • the etching of the gate insulating layer is caused, thereby improving the uniformity of the gate insulating layer, and the dimensional deviation between the gate and the metal oxide layer can be controlled to be less than 0.3 um, avoiding the gate
  • the gate insulating layer is lost, so that the depth and the dose of the ion implantation are well uniform when the lightly doped drain region is formed, and the lightly doped drain after implantation is ensured.
  • the dose in the zone is consistent. This will avoid unevenness in the energy and dose of the ions implanted in the lightly doped drain region, and eventually cause electrical differences in various places on the channel, resulting in uneven brightness of the display or loss of various traces.

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  • Optics & Photonics (AREA)

Abstract

一种薄膜晶体管阵列基板及其制造方法。制造方法包括在基板（20）上形成多晶硅层（22）与栅极绝缘层（23），栅极绝缘层（23）上形成金属氧化物层（26），金属氧化物层（26）上形成栅极金属层，刻蚀栅极金属层定义栅极（24），以栅极（24）作为第二光罩刻蚀掉第二光罩范围以外的金属氧化物层（26），以栅极（24）与剩余的金属氧化物层（26）作为第三光罩进行离子植入以分别形成轻掺杂漏极区（30）于所述多晶硅层（22）两侧，于栅极（24）与栅极绝缘层（23）上形成绝缘层（25），于绝缘层（25）上形成金属层(28)，并定义源极（281）及漏极（282）分别与源极掺杂区（222）和漏极掺杂区（221）相连，使得离子植入的剂量保持均匀性，进一步维持显示器亮度一致。

Description

薄膜晶体管阵列基板制造方法及薄膜晶体管阵列基板 技术领域
本发明涉及阵列基板制造方法及阵列基板，特别是涉及一种低温多晶硅薄膜晶体管阵列基板的制造方法及薄膜晶体管阵列基板。
 背景技术
液晶显示器(Liquid Crystal Display, LCD)由于具有体积小、重量轻、消耗功率低等优点，而大量的应用于各式电子产品中。为了实现高精细度的组件与像素排列，低温多晶硅(Low Temperature Poly Silicon, LTPS)薄膜晶体管液晶显示器成为研发的主流。
然而低温多晶硅具有下述问题，现有标准低温多晶硅薄膜晶体管(LTPS-TFT)的结构在多晶硅层上会包含两个作为源极与漏极之用的n型掺杂区，由于两个n型掺杂区的掺杂浓度较高，且与栅电极导体间的间距甚小，导致漏极附近的电场太强，因而产生热载流子效应(hot carrier effect),使多晶硅薄膜晶体管在关闭状态下会有漏电流(leakage current)的问题产生。为解决这个问题，现有技术多采用轻掺杂漏极结构(lightly doped drain, LDD)，用来降低漏极接触处的电场进而减少漏电流。如图1所示，一般低温多晶硅薄膜晶体管的制程中，在形成自对准(self-align) 轻掺杂漏极结构薄膜晶体管阵列基板的流程如下：1.在基板10上沉积缓冲层11和非晶硅层，并通过雷射回火(ELA)程序使之结晶化为多晶硅层12，通过光罩定义出多晶硅区。2.通过光罩定义出n型掺杂区块并通过离子植入程序植入离子，形成n型掺杂区13。3.借着低温化学气相沉积法(PECVD)沉积栅极绝缘层14。4.在栅极绝缘层14上沉积栅极15，通过光罩定义栅极区，并采用干式蚀刻法蚀刻掉其他区域的金属。5.以栅极15为光罩进行离子植入程序(图中箭头处)，形成轻掺杂漏极区16。
由于采用干式刻蚀法蚀刻栅极金属的同时会对栅极绝缘层产生一定的刻蚀导致栅极绝缘层流失，后续在进行离子植入程序以形成轻掺杂漏极区的时候，植入离子的剂量上会产生不均匀，最终会使得通道上各个地方的电性产生差异，导致显示器亮度不均或造成各种痕迹。
 技术问题
本发明目的在于提供一种薄膜晶体管阵列基板制造方法及薄膜晶体管阵列基板，避免在进行干刻蚀栅极的时候导致栅极绝缘层流失，改进了栅极绝缘层厚度的均匀性，使得植入的轻掺杂漏极区的离子剂量保持一致。
 技术解决方案
为达上述技术目的，本发明提供一种薄膜晶体管阵列基板制造方法，包括以下步骤：
提供一基板；
在所述基板上形成一多晶硅层；
于所述多晶硅层中形成一漏极掺杂区及一源极掺杂区；
于所述多晶硅层上沉积一栅极绝缘层；
于所述栅极绝缘层上形成一金属氧化物层；
于所述金属氧化物层上形成一栅极金属层；
使用一第一光罩对所述栅极金属层进行蚀刻以定义一栅极；
以所述栅极作为一第二光罩蚀刻掉第二光罩范围以外的所述金属氧化物层；
以所述栅极与剩余的所述金属氧化物层作为一第三光罩进行一离子植入以分别形成轻掺杂漏极区于所述多晶硅层两侧，所述轻掺杂漏极区分别与所述漏极掺杂区及所述源极掺杂区邻接；
于所述栅极与所述栅极绝缘层上形成一绝缘层，分别定义所述多晶硅层的源极掺杂区和漏极掺杂区上方的一过孔；
于所述绝缘层上沉积一金属层，并定义一源极及一漏极，所述源极及所述漏极分别通过所述过孔与所述源极掺杂区和所述漏极掺杂区相连。
依据本发明制法，在所述基板上形成所述多晶硅层之前更可包括形成一缓冲层的步骤。
依据本发明制法，形成所述漏极掺杂区及所述源极掺杂区为以磷离子植入于所述多晶硅层。
依据本发明制法，对所述栅极金属层进行蚀刻为采用一干蚀刻程序以蚀刻掉所述第一光罩以外的栅极金属层以形成所述栅极，对所述金属氧化物层进行蚀刻为采用一湿蚀刻程序并以所述栅极作为第二光罩蚀刻掉所述第二光罩以外的金属氧化物层。
依据本发明制法，所述栅极绝缘层为一氧化硅(SiO2 )层、一氮化硅(SiNX )层或为两者层迭结构。
依据本发明制法，所述金属氧化物层的材质为氧化铟锡(ITO)。
依据本发明制法，所述金属氧化物层与所述栅极间的尺寸偏差小于0.3um。
依据本发明制法，所述薄膜晶体管阵列基板适用于有机发光二极管 (Organic Light-Emitting Diode, OLED) 显示器。
其次，为达上述技术目的，本发明提供一种薄膜晶体管阵列基板制造方法，包括以下步骤：
提供一基板；
在所述基板上形成一多晶硅层；
于所述多晶硅层中形成一漏极掺杂区及一源极掺杂区；
于所述多晶硅层上沉积一栅极绝缘层；
于所述栅极绝缘层上形成一金属氧化物层；
于所述金属氧化物层上形成一栅极金属层；
使用一第一光罩对所述栅极金属层进行蚀刻以定义一栅极；
以所述栅极作为一第二光罩蚀刻掉第二光罩范围以外的所述金属氧化物层；
以所述栅极与剩余的所述金属氧化物层作为一第三光罩进行一离子植入以分别形成轻掺杂漏极区于所述多晶硅层两侧；
于所述栅极与所述栅极绝缘层上形成一绝缘层，分别定义所述多晶硅层的源极掺杂区和漏极掺杂区上方的一过孔；
于所述绝缘层上沉积一金属层，并定义一源极及一漏极，所述源极及所述漏极分别通过所述过孔与所述源极掺杂区和所述漏极掺杂区相连。
依据本发明制法，在所述基板上形成所述多晶硅层之前更可包括形成一缓冲层的步骤。
依据本发明制法，形成所述漏极掺杂区及所述源极掺杂区为以磷离子植入于所述多晶硅层。
依据本发明制法，对所述栅极金属层进行蚀刻为采用一干蚀刻程序以蚀刻掉所述第一光罩以外的栅极金属层以形成所述栅极，对所述金属氧化物层进行蚀刻为采用一湿蚀刻程序并以所述栅极作为第二光罩蚀刻掉所述第二光罩以外的金属氧化物层。
依据本发明制法，所述栅极绝缘层为一氧化硅(SiO2 )层、一氮化硅(SiNX )层或为两者层迭结构。
依据本发明制法，所述金属氧化物层的材质为氧化铟锡(ITO)。
依据本发明制法，所述金属氧化物层与所述栅极间的尺寸偏差小于0.3um。
依据本发明制法，所述薄膜晶体管阵列基板适用于有机发光二极管 (Organic Light-Emitting Diode, OLED) 显示器。
另一方面，为达上述技术目的，本发明提供一种薄膜晶体管阵列基板，包括：
一基板，所述基板上具有一多晶硅层，所述多晶硅层上具有一栅极绝缘层，所述栅极绝缘层上具有一栅极，所述多晶硅层具一漏极掺杂区及一源极掺杂区，所述多晶硅层两侧各具有一轻掺杂漏极区，所述栅极与所述栅极绝缘层上具一绝缘层，分别于所述多晶硅层的源极掺杂区和漏极掺杂区上方形成一过孔，于所述绝缘层上沉积一金属层，所述金属层具一源极及一漏极，所述源极及所述漏极分别通过所述过孔与所述源极掺杂区和所述漏极掺杂区相连，其中，所述栅极与栅极绝缘层间具一金属氧化物层，所述栅极与所述金属氧化物层覆盖范围相同且并未覆盖所述轻掺杂漏极区。
依据本发明薄膜晶体管阵列基板，所述基板与所述多晶硅层间更可包括一缓冲层。
依据本发明薄膜晶体管阵列基板，所述金属氧化物层的材质为氧化铟锡(ITO)。
依据本发明薄膜晶体管阵列基板，所述金属氧化物层与所述栅极间的尺寸偏差小于0.3um。
 有益效果
本发明公开了一种薄膜晶体管阵列基板制造方法，包括在所述基板上形成多晶硅层与栅极绝缘层，所述栅极绝缘层上形成金属氧化物层，所述金属氧化物层上形成栅极金属层，蚀刻所述栅极金属层定义栅极，以所述栅极作为第二光罩蚀刻掉第二光罩范围以外的金属氧化物层，以所述栅极与剩余的金属氧化物层作为第三光罩进行离子植入以分别形成轻掺杂漏极区于所述多晶硅层两侧，于所述栅极与所述栅极绝缘层上形成绝缘层，于绝缘层上形成金属层，并定义源极及漏极分别与所述源极掺杂区和所述漏极掺杂区相连, 使得离子植入的剂量保持均匀性，进一步维持显示器亮度一致。本发明还公开了一种具有上述制造方法制备而成的薄膜晶体管阵列基板。
 附图说明
图1为现有低温多晶硅薄膜晶体管的制程与结构示意图；
图2为依据本发明的一优选实施例的薄膜晶体管阵列基板制造方法的流程示意图；以及
图3至图9为依据本发明的一优选实施例的薄膜晶体管阵列基板的制程与结构示意图。
 本发明的最佳实施方式
有关本发明的技术内容及详细说明，现配合附图说明如下：
请参阅图2，为一种依据本发明的优选实施例的薄膜晶体管阵列基板制造方法，包括以下步骤：提供一基板，所述基板可以使用玻璃、石英、或者类似的透明绝缘材质。
在所述基板上形成一多晶硅层，其中所述多晶硅层由一非晶硅层形成于基板上，并对非晶硅层进行雷射回火(ELA)程序，使得非晶硅转为多晶硅，以做为薄膜晶体管之通道区域使用， 后续通过光罩处理与蚀刻处理定义出至少一多晶硅区(未图示)。于本发明不同实施例中，在所述基板上形成所述多晶硅层之前更可包括形成一缓冲层的步骤。
接着涂布光阻于所述多晶硅层上，并对基板施以背面曝光程序，以定义一光阻图案于多晶硅层上，再以光阻图案为光罩，对基板采用离子植入，以n型薄膜晶体管而言，选择如磷、砷等五价的杂质离子进行离子植入(ion implantation)；以p型薄膜晶体管而言，选择如硼、镓等三价的杂质离子进行离子植入，藉此于所述多晶硅层中形成一漏极掺杂区及一源极掺杂区。于本实施例中，于所述多晶硅层的多晶硅区植入磷离子，用以形成所述漏极掺杂区及所述源极掺杂区，所述漏极掺杂区及所述源极掺杂区分别形成于所述多晶硅层两侧。
后藉由低温化学气相沉积法(PECVD)于所述多晶硅层上沉积一栅极绝缘层，于本实施例中，所述栅极绝缘层为一氧化硅(SiO2 )层、一氮化硅(SiNX )层或为两者层迭结构，但不以此为限。
后于所述栅极绝缘层上形成一金属氧化物层，优选地，所述金属氧化物层的材质为氧化铟锡(ITO)，但不以此为限。
紧接于所述金属氧化物层上形成一栅极金属层，使用一第一光罩定义出一栅极区(未图示)，对所述栅极金属层进行一蚀刻程序以定义一栅极，于本实施例中，对所述栅极金属层进行蚀刻为采用一干蚀刻程序以蚀刻掉所述第一光罩以外的栅极金属层以形成所述栅极，采用干蚀刻程序主要是因为在每英吋脉冲数(ppi)高的情况下，干蚀刻程序的关键尺寸(Critical Dimension, CD)误差会比湿蚀刻程序的误差为小。
接着，以所述栅极作为一第二光罩蚀刻掉第二光罩范围以外的所述金属氧化物层，于本实施例中，对所述金属氧化物层进行蚀刻为采用一湿蚀刻程序，并以所述栅极作为第二光罩蚀刻掉所述第二光罩以外的金属氧化物层。
后以所述栅极与剩余的所述金属氧化物层作为一第三光罩进行一离子植入以分别形成轻掺杂漏极区于所述多晶硅层两侧，剩余的所述金属氧化物层位于所述栅极与所述栅极绝缘层间，并且，剩余的所述金属氧化物层与所述栅极具有相同覆盖范围。即所述离子植入是以所述栅极与剩余的所述金属氧化物层作为第三光罩，因此，所述栅极与剩余的所述金属氧化物层覆盖的范围并不会与所述轻掺杂漏极区有所重迭，且所述轻掺杂漏极区在剩余的所述金属氧化物层及所述栅极覆盖范围之外，所述轻掺杂漏极区分别与所述漏极掺杂区及所述源极掺杂区邻接。如此还可达到自对准(self-align)的效果，并可控制以所述栅极与剩余的所述金属氧化物层为第三光罩发生的偏移(shift) 小于0.3um，避免造成关键尺寸(Critical Dimension, CD)的误差，亦不会影响到栅极的线宽。
后于所述栅极与所述栅极绝缘层上形成绝缘层，在绝缘层上形成一金属层且所述金属层具一源极及一漏极,绝缘层通过光罩分别在源极与漏极开有过孔, 分别定义所述多晶硅层的源极掺杂区和漏极掺杂区与所述过孔对应，所述源极及所述漏极分别通过所述过孔与所述源极掺杂区和所述漏极掺杂区相连。
此外，请参阅图3至图9，本发明提供一种薄膜晶体管阵列基板，包括：一基板20，所述基板20上具有一多晶硅层22，所述多晶硅层22上具有一栅极绝缘层23，所述栅极绝缘层23上具有一栅极24，所述多晶硅层22具一漏极掺杂区221及一源极掺杂区222，所述多晶硅层22两侧各具有一轻掺杂漏极区30，所述轻掺杂漏极区30分别邻接于所述漏极掺杂区221与所述源极掺杂区222，所述栅极24与所述栅极绝缘层23上具绝缘层25，所述绝缘层25分别对应所述多晶硅层22的源极掺杂区222和漏极掺杂区221上方设有过孔27,在绝缘层25上形成一金属层28，且所述金属层28具一源极281及一漏极282,其分别通过过孔27与多晶硅层22的源极掺杂区222和漏极掺杂区221相连，其中，所述栅极24与栅极绝缘层23间具一金属氧化物层26，所述栅极24与所述金属氧化物层25覆盖范围相同且并未覆盖所述轻掺杂漏极区23。
优选地，本实施例的薄膜晶体管阵列基板采用栅极24与金属氧化物层26共同作为光罩以对轻掺杂漏极区30进行离子植入(图7箭头所示)，故如图7所示， 由垂直方向观察，栅极24与金属氧化物层26和轻掺杂漏极区30是切齐对齐的，栅极24与金属氧化物层26覆盖范围并不会与轻掺杂漏极区30有所交集。
优选地，所述金属氧化物层26的材质为氧化铟锡(ITO) ，且所述金属氧化物层26与所述栅极24间的尺寸偏差小于0.3um，且所述薄膜晶体管阵列基板适用于有机发光二极管 (Organic Light-Emitting Diode, OLED) 显示器。
于本发明不同实施例中，所述基板20与所述多晶硅层22间更可包括一缓冲层21。
综上所述，本发明提供一种薄膜晶体管阵列基板制造方法及薄膜晶体管阵列基板，通过在栅极下方设置金属氧化物层的方式，通过金属氧化物层来抵挡对栅极进行干式蚀刻程序过程中造成对于栅极绝缘层的刻蚀，进而提高的栅极绝缘层的均匀性，且所述栅极与所述金属氧化物层间的尺寸偏差可控制在小于0.3um，避免在对栅极进行干式蚀刻程序的时候产生栅极绝缘层流失，使得形成所述轻掺杂漏极区时离子植入的深度和剂量保持很好的均匀性，确保植入后的轻掺杂漏极区的剂量保持一致。如此将可避免植入轻掺杂漏极区的离子的能量和剂量上会产生不均匀，最终会使得通道上各个地方的电性产生差异，导致显示器亮度不均或造成各种痕迹的缺失。
虽然本发明已以优选实施例公开如上，但上述优选实施例并非用以限定本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
序列表自由内容

Claims (20)

  1. 一种薄膜晶体管阵列基板制造方法，包括以下步骤：
    提供一基板；
    于所述基板上形成一多晶硅层；
    于所述多晶硅层中形成一漏极掺杂区及一源极掺杂区；
    于所述多晶硅层上沉积一栅极绝缘层；
    于所述栅极绝缘层上形成一金属氧化物层；
    于所述金属氧化物层上形成一栅极金属层；
    使用一第一光罩对所述栅极金属层进行蚀刻以定义一栅极；
    以所述栅极作为一第二光罩蚀刻掉所述第二光罩范围以外的所述金属氧化物层；
    以所述栅极与剩余的所述金属氧化物层作为一第三光罩进行一离子植入以分别形成轻掺杂漏极区于所述多晶硅层两侧，所述轻掺杂漏极区分别与所述漏极掺杂区及所述源极掺杂区邻接；
    于所述栅极与所述栅极绝缘层上形成绝缘层，分别定义所述多晶硅层的源极掺杂区和漏极掺杂区上方的一过孔；
    于所述绝缘层上沉积一金属层，并定义一源极及一漏极，所述源极及所述漏极分别通过所述过孔与所述源极掺杂区和所述漏极掺杂区相连。
  2. 根据权利要求1所述的薄膜晶体管阵列基板制造方法，其中，在所述基板上形成所述多晶硅层之前更可包括形成一缓冲层的步骤。
  3. 根据权利要求1所述的薄膜晶体管阵列基板制造方法，其中，形成所述漏极掺杂区及所述源极掺杂区为以磷离子植入于所述多晶硅层形成。
  4. 根据权利要求1所述的薄膜晶体管阵列基板制造方法，其中，对所述栅极金属层进行蚀刻为采用一干蚀刻程序以蚀刻掉所述第一光罩以外的栅极金属层以形成所述栅极，对所述金属氧化物层进行蚀刻为采用一湿蚀刻程序并以所述栅极作为第二光罩蚀刻掉所述第二光罩以外的金属氧化物层。
  5. 根据权利要求1所述的薄膜晶体管阵列基板制造方法，其中，所述栅极绝缘层为一氧化硅层、一氮化硅层或为两者层迭结构。
  6. 根据权利要求1所述的薄膜晶体管阵列基板制造方法，其中，所述金属氧化物层的材质为氧化铟锡。
  7. 根据权利要求1所述的薄膜晶体管阵列基板制造方法，其中，所述金属氧化物层与所述栅极间的尺寸偏差小于0.3um。
  8. 根据权利要求1所述的薄膜晶体管阵列基板制造方法，其中，所述薄膜晶体管阵列基板适用于有机发光二极管显示器。
  9. 一种薄膜晶体管阵列基板制造方法，包括以下步骤：
    提供一基板；
    于所述基板上形成一多晶硅层；
    于所述多晶硅层中形成一漏极掺杂区及一源极掺杂区；
    于所述多晶硅层上沉积一栅极绝缘层；
    于所述栅极绝缘层上形成一金属氧化物层；
    于所述金属氧化物层上形成一栅极金属层；
    使用一第一光罩对所述栅极金属层进行蚀刻以定义一栅极；
    以所述栅极作为一第二光罩蚀刻掉所述第二光罩范围以外的所述金属氧化物层；
    以所述栅极与剩余的所述金属氧化物层作为一第三光罩进行一离子植入以分别形成轻掺杂漏极区于所述多晶硅层两侧；
    于所述栅极与所述栅极绝缘层上形成绝缘层，分别定义所述多晶硅层的源极掺杂区和漏极掺杂区上方的一过孔；
    于所述绝缘层上沉积一金属层，并定义一源极及一漏极，所述源极及所述漏极分别通过所述过孔与所述源极掺杂区和所述漏极掺杂区相连。
  10. 根据权利要求9所述的薄膜晶体管阵列基板制造方法，其中，在所述基板上形成所述多晶硅层之前更可包括形成一缓冲层的步骤。
  11. 根据权利要求9所述的薄膜晶体管阵列基板制造方法，其中，形成所述漏极掺杂区及所述源极掺杂区为以磷离子植入于所述多晶硅层形成。
  12. 根据权利要求9所述的薄膜晶体管阵列基板制造方法，其中，对所述栅极金属层进行蚀刻为采用一干蚀刻程序以蚀刻掉所述第一光罩以外的栅极金属层以形成所述栅极，对所述金属氧化物层进行蚀刻为采用一湿蚀刻程序并以所述栅极作为第二光罩蚀刻掉所述第二光罩以外的金属氧化物层。
  13. 根据权利要求9所述的薄膜晶体管阵列基板制造方法，其中，所述栅极绝缘层为一氧化硅层、一氮化硅层或为两者层迭结构。
  14. 根据权利要求9所述的薄膜晶体管阵列基板制造方法，其中，所述金属氧化物层的材质为氧化铟锡。
  15. 根据权利要求9所述的薄膜晶体管阵列基板制造方法，其中，所述金属氧化物层与所述栅极间的尺寸偏差小于0.3um。
  16. 根据权利要求9所述的薄膜晶体管阵列基板制造方法，其中，所述薄膜晶体管阵列基板适用于有机发光二极管显示器。
  17. 一种薄膜晶体管阵列基板，包括：
    一基板，所述基板上具有一多晶硅层，所述多晶硅层上具有一栅极绝缘层，所述栅极绝缘层上具有一栅极，所述多晶硅层具一漏极掺杂区及一源极掺杂区，所述多晶硅层两侧各具有一轻掺杂漏极区，所述栅极与所述栅极绝缘层上具一绝缘层，分别于所述多晶硅层的源极掺杂区和漏极掺杂区上方形成一过孔，于所述绝缘层上沉积一金属层，所述金属层具一源极及一漏极，所述源极及所述漏极分别通过所述过孔与所述源极掺杂区和所述漏极掺杂区相连，其中，所述栅极与栅极绝缘层间具一金属氧化物层，所述栅极与所述金属氧化物层覆盖范围相同且并未覆盖所述轻掺杂漏极区。
  18. 根据权利要求17所述的薄膜晶体管阵列基板，其中，所述基板与所述多晶硅层间更可包括一缓冲层。
  19. 根据权利要求17所述的薄膜晶体管阵列基板，其中，所述金属氧化物层的材质为氧化铟锡。
  20. 根据权利要求17所述的薄膜晶体管阵列基板，其中，所述金属氧化物层与所述栅极间的尺寸偏差小于0.3um。
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