WO2015165421A1 - 基于氮氧化硅抗反射层的化学机械平坦化工艺 - Google Patents

基于氮氧化硅抗反射层的化学机械平坦化工艺 Download PDF

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WO2015165421A1
WO2015165421A1 PCT/CN2015/078121 CN2015078121W WO2015165421A1 WO 2015165421 A1 WO2015165421 A1 WO 2015165421A1 CN 2015078121 W CN2015078121 W CN 2015078121W WO 2015165421 A1 WO2015165421 A1 WO 2015165421A1
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layer
mechanical planarization
planarization process
silicon
silicon dioxide
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PCT/CN2015/078121
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English (en)
French (fr)
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华强
周耀辉
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无锡华润上华科技有限公司
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Priority to US15/120,323 priority Critical patent/US9754795B2/en
Publication of WO2015165421A1 publication Critical patent/WO2015165421A1/zh

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    • H01L21/3105—After-treatment
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Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a chemical mechanical planarization process based on an anti-reflective layer of silicon oxynitride.
  • STI shallow channel isolation
  • CMP chemical mechanical polishing
  • Reverse CMP reverse chemical mechanical planarization
  • Direct CMP direct chemical mechanical planarization
  • SiON silicon oxynitride
  • H 3 PO 4 phosphoric acid
  • FIG. 1A-1D is a schematic diagram of a process flow of direct shallow trench isolation planarization (Direct CMP STI) commonly used in the industry.
  • step (a) first, an oxide layer S120 (Pad-Ox) is formed on the silicon substrate S110, a silicon nitride layer S130 is formed on the surface of the oxide layer S120, and a silicon nitride layer S130 is formed.
  • an oxide layer S120 (Pad-Ox) is formed on the silicon substrate S110
  • a silicon nitride layer S130 is formed on the surface of the oxide layer S120
  • a silicon nitride layer S130 is formed.
  • a silicon oxynitride layer S140 (anti-reflection layer) is formed on the surface; step (b): STI etching (STI-ETCH) is performed, STI depth is etched, and STI etching is performed by high-density plasma deposition (high density) Plasma chemical vapor deposition (HDP-CVD) deposited silicon dioxide layer (SiO 2 ) S150; step (c): grinding the silicon dioxide layer S150 on the surface of the anti-reflective layer S140 to the anti-reflective layer S140 by direct CMP method; (d): The silicon nitride layer is removed by reacting phosphoric acid (H 3 PO 4 ) with the silicon nitride layer S130 to form an active region and an isolation region.
  • STI-ETCH STI etching
  • HDP-CVD Plasma chemical vapor deposition
  • the Direct CMP method will no longer be applicable because, during Direct CMP, the slurry is silica/silicon oxynitride (SiO 2 ). /SiON) The higher the selection ratio (greater than 10:1), the CMP will eventually stay on the silicon oxynitride surface.
  • the slurry will react with the surface of the silicon oxynitride to form a denser complex A (see step (d).
  • the blocking phosphoric acid reacts with the silicon nitride, resulting in the inability to remove the silicon nitride.
  • FIG. 2A and FIG. 2B are schematic diagrams of the morphology of silicon oxynitride as an anti-reflective layer after being removed by silicon nitride, respectively.
  • FIGS. 2A and 2B due to the blocking of the surface complex of silicon oxynitride, Most of the silicon nitride (B and C in the figure) cannot be removed.
  • Organic bottom anti-reflective coating on the shallow trench insulation layer (STI layer) replaces silicon oxynitride as an antireflection layer.
  • STI layer shallow trench insulation layer
  • Organic Barc Organic bottom anti-reflective coating on the shallow trench insulation layer
  • a chemical mechanical planarization process based on an anti-reflective layer of silicon oxynitride comprising: providing a semiconductor wafer, the semiconductor wafer comprising a substrate, an oxide layer formed on the substrate, and being formed on the oxide layer a silicon nitride layer, an anti-reflective layer formed on the silicon nitride layer, a trench extending through the anti-reflective layer and extending into the substrate, and being filled in the trench and covering the a first silicon dioxide layer on the anti-reflective layer;
  • the silicon nitride layer is removed.
  • the process of the present invention is in normal Direct After CMP, the surface of the wafer is plasma treated, a certain amount of fluorocarbon is combined with a gas with strong ion bombardment ability, and the surface of the silicon oxynitride is bombarded to open the bond of the surface complex, fluorocarbon and nitrogen oxide.
  • the silicon reacts and eventually oxidizes the silicon oxynitride. Since the silicon dioxide inside the trench is also etched away, the difference between the silicon nitride and the silicon dioxide will become larger, and then a silicon dioxide layer of about 2 um is re-deposited for secondary CMP, and the CMP will eventually stay.
  • the difference in height between silicon nitride and silicon dioxide is also improved, after which the silicon phosphate is removed by silicon nitride to remove the silicon nitride to form an active region and an isolation region.
  • the process of the present invention does not require the addition of an additional reverse shallow trench isolation cover (Reverse STI Mask) and corresponding exposure, etching, cleaning, and simplification of the process; and the present invention uses a general-purpose silicon oxynitride as an anti-reflection layer, and CD control is relatively simple.
  • Reverse STI Mask reverse shallow trench isolation cover
  • 1A-1D are schematic illustrations of a conventional direct shallow trench isolation planarization (Direct CMP STI) process flow
  • 2A-2B are schematic views showing the morphology of silicon oxynitride as an antireflection layer after being removed by silicon nitride;
  • FIG. 3 is a flow chart of a chemical mechanical planarization process based on an anti-reflective layer of silicon oxynitride according to an embodiment
  • 4A-4F are schematic diagrams showing the structure of a chemical mechanical planarization process based on a silicon oxynitride antireflection layer according to an embodiment
  • Fig. 5 is a view showing the effect of silicon nitride removal in the planarization process of an embodiment.
  • FIG. 3 is a flow chart of a chemical mechanical planarization process based on a silicon oxynitride anti-reflection layer according to an embodiment.
  • FIGS. 4A-4F are schematic structural diagrams of a chemical mechanical planarization process based on an oxynitride anti-reflection layer according to an embodiment.
  • Step S1 providing a semiconductor wafer.
  • the semiconductor wafer includes a substrate S310, an oxide layer S320 formed on the substrate, and a silicon nitride layer S330 formed on the oxide layer S320.
  • the anti-reflective layer S340 is a silicon oxynitride layer.
  • the anti-reflective layer S340 can also be other kinds of materials.
  • the first silicon dioxide layer S350 is formed by a high-density plasma chemical vapor deposition (HDP-CVD) method, and the high-density plasma is a mixture of SiH 4 , O 2 and Ar, and the deposition temperature is 380-400 ° C, pressure is 450 Torr, time is 220 s.
  • the ratio of the components in the mixture of SiH 4 , O 2 and Ar in the high-density plasma is not limited and may be determined according to the actual conditions of production.
  • the deposition temperature is 390 °C. In other embodiments, the deposition pressure and time can be optimized based on actual production conditions.
  • Step S2 grinding the first silicon dioxide layer S350 up to the anti-reflection layer S340.
  • the ground polishing liquid is subjected to chemical mechanical planarization (CMP) grinding to the first silicon dioxide layer S350 by using a polishing liquid having a main component of SiO 2 until the anti-reflection layer. S340, wherein the grinding time is 30-50 s.
  • the step is carried out at normal temperature and normal pressure.
  • the slurry is a mixture of at least two, wherein the SiO 2 has a greater proportion in the mixture than the other components. In other embodiments, the slurry may also be composed of only SiO 2 .
  • the slurry will react with the surface of the antireflective layer S340 to form a relatively dense complex A (see Figure 4B).
  • Step S3 dry etching removes the anti-reflection layer S340.
  • the surface of the anti-reflective layer S340 is bombarded with a mixture of argon gas, fluorocarbon and oxygen gas at a temperature of 60 ° C, a pressure of 15 mTorr, and a time of 10 s to open the surface of the anti-reflection layer S340.
  • the bond of the complex, the fluorocarbon and the anti-reflective layer S340 react, and finally the anti-reflective layer S340 is etched away.
  • the surface of the wafer is subjected to plasma treatment using a gas having a strong ion bombardment capability, argon gas, and oxygen combined with a certain amount of fluorocarbon.
  • the fluorocarbon is carbon tetrafluoride (CF4)
  • the mixed gas is argon, carbon tetrafluoride, and oxygen in a volume ratio of 3:1:1.
  • the dry etching surface treatment of the silicon oxynitride layer S340 after the step (b) is performed once using a mixed gas of argon, carbon tetrafluoride and oxygen.
  • the nitrogen is applied.
  • the number of dry etching of the silicon oxide layer S340 is not limited, so that it is preferable to completely etch the silicon oxynitride layer S340.
  • Step S4 forming a second silicon dioxide layer S360 on the surface of the semiconductor wafer from which the anti-reflection layer S340 is removed.
  • the second silicon dioxide layer S360 is formed by high-density plasma chemical vapor deposition.
  • the high density plasma is a mixture of silane (SiH 4 ), O 2 and Ar, a deposition temperature of 380-400 ° C, a pressure of 450 Torr, and a time of 100 s.
  • the deposition The temperature is 390 °C.
  • the thickness of the second silicon dioxide layer S360 deposited in this step is 2 um.
  • Step S5 grinding the second silicon dioxide layer S360 formed in the step (d) up to the silicon nitride layer S330.
  • the ground slurry is subjected to direct chemical mechanical planarization (CMP) of the second silicon dioxide layer S360 deposited in the step (d) by using a slurry having a main component of silicon dioxide.
  • CMP chemical mechanical planarization
  • the end of the CMP will eventually stay on the surface of the silicon nitride layer S330, so that the difference between the silicon nitride layer S330 and the second silicon dioxide S360 is also improved.
  • the step is the same as the step (b), and is also carried out at normal temperature and normal pressure, and the grinding time is 30 to 50 s.
  • the slurry is a mixture of at least two, wherein the SiO 2 has a greater proportion in the mixture than the other components.
  • the slurry may also be composed of only silica.
  • the process conditions of step (e) and step (b) may also be different, and may be specifically set according to actual production conditions and the degree of planarization of the silicon oxynitride layer.
  • Step S6 removing the silicon nitride layer S330.
  • the silicon nitride layer S330 is completely exposed.
  • the silicon nitride layer S330 is removed by using an acid solution and a silicon nitride layer S330 to form a silicon nitride layer S330.
  • Source area and isolation area In this embodiment, the acid solution is phosphoric acid, the reaction temperature is 150 ° C, and the reaction time is 1800 s. In other embodiments, the acid solution is not limited to phosphoric acid, and the reaction temperature and time may be determined on a case-by-case basis.
  • the substrate is a silicon substrate, and the oxide layer formed on the surface of the substrate is silicon dioxide, the silicon dioxide has a thickness of 110 angstroms, and the silicon nitride layer has a thickness of 1500.
  • the antireflection layer has a thickness of 300 angstroms.
  • the substrate may also be a substrate of other materials.
  • FIG. 5 is an effect diagram of silicon nitride after planarization process of an embodiment. As shown in FIG. 5, the planarization process of one embodiment completely removes silicon nitride.
  • the method of the present invention does not require the addition of an additional reverse shallow trench isolation cover (Reverse STI) Mask) and the corresponding exposure, etching and cleaning simplifies the process; the present invention uses silicon oxynitride silicon as an anti-reflection layer, CD control is relatively simple, and silicon nitride can be effectively stripped.
  • Reverse STI reverse shallow trench isolation cover

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Abstract

一种基于氮氧化硅抗反射层（S340）的化学机械平坦化工艺，其包括：（S1）提供一半导体晶圆，所述半导体晶圆包括衬底（S310）、形成于衬底（S310）上的氧化层（S320）、形成于所述氧化层（S320）上的氮化硅层（S330）、形成于所述氮化硅层（S330）上的抗反射层（S340）、贯穿所述抗反射层（S340）并延伸入所述衬底（S310）中的沟槽、以及填充于所述沟槽内并覆盖于所述抗反射层（S340）上的第一二氧化硅层（S350）；（S2）研磨所述第一二氧化硅层（S350）直至所述抗反射层（S340）；（S3）干法刻蚀去除所述抗反射层（S340）；（S4）在去除所述抗反射层（S340）的半导体晶圆表面形成第二二氧化硅层（S360）；（S5）研磨所述第二二氧化硅层（S360）直至所述氮化硅层（S330）；（S6）去除所述氮化硅层（S330）。

Description

基于氮氧化硅抗反射层的化学机械平坦化工艺
【技术领域】
本发明涉及半导体技术领域，尤其涉及一种基于氮氧化硅抗反射层的化学机械平坦化工艺。
【背景技术】
在半导体浅沟道隔离（Shallow Trench Isolation，简称STI）工艺生产过程中，浅沟道隔离（STI）化学机械平坦化（Chemical Mechanical Polishing，简称CMP）存在两种主流方式：反向化学机械平坦化（Reverse CMP）以及直接化学机械平坦化（Direct CMP），一般情况下浅沟绝缘层（STI layer）用氮氧化硅（SiON）作为抗反射层的工艺不会采用Direct CMP方式，这主要是因为氮化硅（SiN）表面剩余氮氧化硅在STI CMP后并不能被磷酸（H3PO4）去除，进而导致氮化硅无法被湿法剥掉。
目前为了线宽（CD）精确管控，大部分采用氮氧化硅作为抗反射层。请参阅图1A-1D，其为业内目前常用的直接浅沟道隔离平坦化 (Direct CMP STI)的工艺流程示意图。如图1A-1D所示，步骤（a）：首先在硅衬底S110上形成氧化层S120（Pad-Ox）、在氧化层S120的表面形成氮化硅层S130、在氮化硅层S130的表面形成一层氮氧化硅层S140（抗反射层）；步骤（b）：进行STI刻蚀（STI-ETCH），刻蚀出STI深度， STI蚀刻后，采用高密度等离子体沉积法(high density plasma chemical vapor deposition，简称HDP-CVD)沉积二氧化硅层（SiO2）S150；步骤（c）：通过direct CMP方式，研磨抗反射层S140表面的二氧化硅层S150直至抗反射层S140；步骤（d）：通过磷酸（H3PO4）与氮化硅层S130反应将氮化硅层去除，形成有源(Active)区域及隔离(Isolation)区域。
请继续参阅图1A-1D。当STI layer（STI层次）表面以氮氧化硅作为抗反射层S140时，Direct CMP方式将不再适用，其原因是：在Direct CMP时，由于研磨液对二氧化硅/氮氧化硅（SiO2/SiON）较高的选择比（大于10:1），CMP最终会停留在氮氧化硅表面。研磨液将会与氮氧化硅表面发生反应，形成一层较为致密的络合物A（参见步骤（d），在后续磷酸处理时，阻挡磷酸与氮化硅反应，导致氮化硅无法去除。
请参阅图2A和2B，其分别为以氮氧化硅作为抗反射层在经过氮化硅清除之后的形貌示意图，由图2A和2B可以看出，由于氮氧化硅表面络合物的阻挡，大部分区域氮化硅（图中B和C指代区域）都无法清除。
为了避免发生此种问题，目前FAB常用的规避方式有两种：
a、用反向浅沟道隔离平坦化（Reverse STI CMP）方式代替Direct CMP方式，用不一样的研磨液进行研磨。该方法的缺陷为：需要增加一层反罩幕（reverse Mask），进行曝光、蚀刻、清洗，工艺流程相对复杂，产品单位产出低；
b、在浅沟绝缘层（STI layer）采用有机底部抗反射涂层 (Organic Barc)代替氮氧化硅作为抗反射层。该方法的缺陷为：采用Organic barc将会增加STI蚀刻CD控制的困难度，增加量产的制程管控难度。
【发明内容】
有鉴于此，有必要提供一种基于氮氧化硅抗反射层的化学机械平坦化工艺，该工艺方法简单，CD管控简单，可以有效解决氮化硅无法剥掉的问题。
一种基于氮氧化硅抗反射层的化学机械平坦化工艺，包括：提供一半导体晶圆，所述半导体晶圆包括衬底、形成于衬底上的氧化层、形成于所述氧化层上的氮化硅层、形成于所述氮化硅层上的抗反射层、贯穿所述抗反射层并延伸入所述衬底中的沟槽、以及填充于所述沟槽内并覆盖于所述抗反射层上的第一二氧化硅层；
研磨所述第一二氧化硅层直至所述抗反射层；
干法刻蚀去除所述抗反射层；
在去除所述抗反射层的半导体晶圆表面形成第二二氧化硅层；
研磨所述第二二氧化硅层直至所述氮化硅层；以及
去除所述氮化硅层。
有益效果：本发明的工艺是在正常的Direct CMP之后，对晶片表面进行电浆处理，用离子轰击能力较强的气体结合一定量的碳氟化合物，对氮氧化硅表面进行轰击，打开表面络合物的键结，碳氟化合物和氮氧化硅发生反应，最终将氮氧化硅蚀刻掉。由于沟槽内部的二氧化硅亦被蚀刻掉，氮化硅和二氧化硅的高低落差将会变大，之后再重新沉积2um左右的二氧化硅层，进行二次CMP，CMP结束最终会停留在氮化硅表面，氮化硅和二氧化硅的高低落差也得到改善，之后磷酸进行氮化硅清除将氮化硅去除干净形成有源区域及隔离区域。本发明的工艺无需增加额外的反向浅沟道隔离罩（Reverse STI Mask）及相对应的曝光、蚀刻，清洗，简化了工艺；并且本发明采用通用氮氧化硅作为抗反射层，CD管控相对简单。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1A-1D为传统的直接浅沟道隔离平坦化 (Direct CMP STI)的工艺流程示意;
图2A-2B为以氮氧化硅作为抗反射层在经过氮化硅清除之后的形貌示意图；
图3 为一实施例的基于氮氧化硅抗反射层的化学机械平坦化工艺流程图；
图4A-4F为一实施例的基于氮氧化硅抗反射层的化学机械平坦化工艺流程结构示意图；以及
图5为一实施例的平坦化工艺中氮化硅清除后的效果图。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
请参阅图3，其为一实施例的基于氮氧化硅抗反射层的化学机械平坦化工艺流程图。请参阅图4A-4F，其为一实施例的基于氮氧化硅抗反射层的化学机械平坦化工艺流程结构示意图。一实施例的一种基于氮氧化硅抗反射层的化学机械平坦化工艺，其包括如下步骤：
步骤S1：提供一半导体晶圆，请参阅图4A，所述半导体晶圆包括衬底S310、形成于衬底上的氧化层S320、形成于所述氧化层S320上的氮化硅层S330、形成于所述氮化硅层S330上的抗反射层S340、贯穿所述抗反射层S340并延伸入所述衬底中的沟槽、以及填充于所述沟槽内并覆盖于所述抗反射层S340上的第一二氧化硅层S350。在该实施例中，所述抗反射层S340为氮氧化硅层。在其他实施例中，所述抗反射层S340还可以为其他种类的材料。本步骤中，所述第一二氧化硅层S350的形成是采用高密度等离子体化学气相沉积（HDP-CVD）法，所述高密度等离子体为SiH4、O2和Ar混合物，沉积温度为380-400℃，压强为450Torr，时间为220s。一实施例中，对高密度等离子体为SiH4、O2和Ar混合物中各成分的比例不做限制，可以根据生产的实际情况而定。在一实施例中，所述沉积温度为390℃。在其他实施例中，可根据实际生产情况来优化沉积压强和时间。
步骤S2：研磨所述第一二氧化硅层S350直至所述抗反射层S340。请参阅图4B，本步骤中，所述研磨的研磨液采用主成分为SiO2的研磨液对所述第一二氧化硅层S350进行化学机械平坦化（CMP）法研磨直至所述抗反射层S340，其中，研磨时间为30-50s。在该实施例中，该步骤是在常温、常压下进行的。一实施例中，所述研磨液为混合物，该混合物至少为两种，其中所述SiO2在混合物中的所占比重大于另外其他成分。在其他实施例中，所述研磨液也可以有仅有SiO2组成。经该步骤研磨时，研磨液将会与抗反射层S340表面发生反应，形成一层较为致密的络合物A（见图4B）。
步骤S3：干法刻蚀去除所述抗反射层S340。请参阅图4C，本步骤中，采用氩气、碳氟化合物和氧气混合气体、在温度60℃、压强15mTorr、时间10s条件下对所述抗反射层S340表面进行轰击，打开抗反射层S340表面络合物的键结，碳氟化合物和抗反射层S340发生反应，最终将抗反射层S340刻蚀掉。由于本步骤中沟槽内部的第一二氧化硅S350也被部分刻蚀掉，氮化硅层S330和第一二氧化硅S350的高低落差将会变大。本步骤中，对晶圆表面进行电浆处理，采用的是离子轰击能力较强的气体氩气、氧气结合一定量的碳氟化合物。在该实施例中，所述碳氟化合物为四氟化碳（CF4），所述混合气体为氩气、四氟化碳和氧气的体积比为3:1:1，在其他实施例中，还可以是其他碳氟化合物，所述混合气体为氩气、四氟化碳和氧气的体积比可根据实际情况而定。在该实施例中，采用混合气体氩气、四氟化碳和氧气对步骤（b）后的氮氧化硅层S340进行干蚀刻表面处理的次数为一次，在其他实施例中，对所述氮氧化硅层S340干法刻蚀的次数不做限制，以能够保证将氮氧化硅层S340完全刻蚀掉为宜。
步骤S4：在去除所述抗反射层S340的半导体晶圆表面形成第二二氧化硅层S360。请参阅图4D，该步骤中，所述第二二氧化硅层S360的形成是采用高密度等离子体化学气相沉积法。在该实施例中，所述高密度等离子体为硅烷（SiH4）、O2和Ar混合物，沉积温度为380-400℃，压强为450Torr下，时间100s，在一实施例中，所述沉积温度为390℃。在该实施例中，本步骤沉积的第二二氧化硅层S360的厚度为2um。
步骤S5：研磨步骤（d）所形成的第二二氧化硅层S360直至所述氮化硅层S330。请参阅图4E，在该步骤中，所述研磨的研磨液采用主成分为二氧化硅的研磨液对步骤（d）沉积的第二二氧化硅层S360进行直接化学机械平坦化（CMP），CMP结束最终会停留在氮化硅层S330表面，使得氮化硅层S330和第二二氧化硅S360高低落差也得到改善。在该实施例中，该步骤与所述步骤（b）相同，也是在常温、常压下进行的，研磨时间为30-50s。在该实施例中，所述研磨液为混合物，该混合物至少为两种，其中所述SiO2在混合物中的所占比重大于另外其他成分。在其他实施例中，所述研磨液也可以有仅有二氧化硅组成。一实施例中，步骤（e）和步骤（b）的工艺条件还可以不相同，可以根据实际生产情况及氮氧化硅层的平坦化程度而具体设定。
步骤S6：去除所述氮化硅层S330。请参阅图4F，经步骤（e）研磨后，所述氮化硅层S330完全裸露，本步骤通过采用酸液与氮化硅层S330进行反应将氮化硅层S330移除干净，以形成有源区域和隔离区域。在该实施例中，所述酸液为磷酸，反应温度为150℃，反应时间为1800s。在其他实施例中，所述酸液不仅限于磷酸，反应温度和时间可根据具体情况而定。
在该实施例中，所述衬底为硅衬底，所述衬底表面上形成的氧化层为二氧化硅，该二氧化硅的厚度为110埃，所述氮化硅层的厚度为1500埃，所述抗反射层的厚度为300埃。在其他实施例中，所述衬底还可以为其他材质的衬底。
需要说明的是，一实施例中，可根据具体的生产情况而选择不同的工艺参数。
请参阅图5，其为一实施例的平坦化工艺氮化硅清除后的效果图。如图5所示，一实施例的平坦化工艺完全清除了氮化硅。
本发明的方法无需增加额外的反向浅沟道隔离罩（Reverse STI Mask）及相对应的曝光、蚀刻及清洗，简化了工艺；本发明采用氮氧化硅硅作为抗反射层，CD管控相对简单，并且能够有效的剥掉氮化硅。
上述说明已经充分揭露了本发明的具体实施方式。需要指出的是，熟悉该领域的技术人员对本发明的具体实施方式所做的任何改动均不脱离本发明的权利要求书的范围。相应地，本发明的权利要求的范围也并不仅仅局限于前述具体实施方式。

Claims (10)

  1. 一种基于氮氧化硅抗反射层的化学机械平坦化工艺，其特征在于：
    提供一半导体晶圆，所述半导体晶圆包括衬底、形成于衬底上的氧化层、形成于所述氧化层上的氮化硅层、形成于所述氮化硅层上的抗反射层、贯穿所述抗反射层并延伸入所述衬底中的沟槽、以及填充于所述沟槽内并覆盖于所述抗反射层上的第一二氧化硅层；
    研磨所述第一二氧化硅层直至所述抗反射层；
    干法刻蚀去除所述抗反射层；
    在去除所述抗反射层的半导体晶圆表面形成第二二氧化硅层；
    研磨所述第二二氧化硅层直至所述氮化硅层；以及
    去除所述氮化硅层。
  2. 根据权利要求1所述的化学机械平坦化工艺，其特征在于：所述抗反射层为氮氧化硅层。
  3. 根据权利要求1所述的化学机械平坦化工艺，其特征在于：所述第一二氧化硅层的形成是采用高密度等离子体化学气相沉积法，所述高密度等离子体为SiH4、O2和Ar混合物，沉积温度为380-400℃，压强为450Torr，时间为220s。
  4. 根据权利要求1所述的化学机械平坦化工艺，其特征在于：所述研磨所述第一二氧化硅层直至所述抗反射层步骤中，所述研磨的研磨液采用主成分为SiO2的研磨液，研磨时间为30-50s。
  5. 根据权利要求1所述的化学机械平坦化工艺，其特征在于：所述干法刻蚀去除所述抗反射层步骤中采用氩气、碳氟化合物和氧气混合气体、在温度60℃、压强15mTorr、时间10s条件下干法刻蚀。
  6. 根据权利要求1所述的化学机械平坦化工艺，其特征在于：所述第二二氧化硅层的形成是采用高密度等离子体化学气相沉积法沉积法，其中所述高密度等离子体为SiH4、O2和Ar混合物，沉积温度为380-400℃，压强为450Torr下，时间100s。
  7. 根据权利要求1所述的化学机械平坦化工艺，其特征在于：所述研磨所述第一二氧化硅层直至所述抗反射层步骤中，所述研磨的研磨液采用主成分为SiO2的研磨液，研磨时间为30-50s。
  8. 根据权利要求1所述的化学机械平坦化工艺，其特征在于：采用磷酸在温度150℃、时间1800s条件下去除所述氮化硅层。
  9. 根据权利要求5所述的化学机械平坦化工艺，其特征在于：所述氩气、碳氟化合物和氧气混合气体的体积比为3:1:1。
  10. 根据权利要求1所述的化学机械平坦化工艺，其特征在于：所述衬底为硅衬底，所述衬底表面上形成的氧化层为二氧化硅，该二氧化硅的厚度为110埃，所述氮化硅层的厚度为1500埃，所述抗反射层的厚度为300埃。
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