CN105097491B - 一种基于氮氧化硅抗反射层的化学机械平坦化工艺 - Google Patents

一种基于氮氧化硅抗反射层的化学机械平坦化工艺 Download PDF

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CN105097491B
CN105097491B CN201410180862.7A CN201410180862A CN105097491B CN 105097491 B CN105097491 B CN 105097491B CN 201410180862 A CN201410180862 A CN 201410180862A CN 105097491 B CN105097491 B CN 105097491B
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reflecting layer
silicon
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silicon nitride
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CN105097491A (zh
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华强
周耀辉
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CSMC Technologies Corp
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Abstract

本发明提供了一种基于氮氧化硅抗反射层的化学机械平坦化工艺，包括：提供一半导体晶圆，所述半导体晶圆包括衬底、形成于衬底上的氧化层、形成于所述氧化层上的氮化硅层、形成于所述氮化硅层上的抗反射层、贯穿所述抗反射层并延伸入所述衬底中的沟槽、以及填充于所述沟槽内并覆盖于所述抗反射层上的第一二氧化硅层；研磨所述第一二氧化硅层直至所述抗反射层；干法刻蚀去除所述抗反射层；在去除所述抗反射层的半导体晶圆表面形成第二二氧化硅层；研磨所述第二二氧化硅层直至所述氮化硅层；去除所述氮化硅层。本发明工艺简单，采用氮氧化硅作为抗反射层，CD管控相对简单。

Description

一种基于氮氧化硅抗反射层的化学机械平坦化工艺
技术领域
本发明涉及半导体技术领域，尤其涉及一种基于氮氧化硅抗反射层的化学机械平坦化工艺。
背景技术
在半导体浅沟道隔离(Shallow Trench Isolation，简称STI)工艺生产过程中，浅沟道隔离(STI)化学机械平坦化(Chemical Mechanical Polishing，简称CMP)存在两种主流方式：反向化学机械平坦化(Reverse CMP)以及直接化学机械平坦化(Direct CMP)，一般情况下浅沟绝缘层(STI layer)用氮氧化硅(SiON)作为抗反射层的工艺不会采用DirectCMP方式，这主要是因为氮化硅(SiN)表面剩余氮氧化硅在STI CMP后并不能被磷酸(H3PO4)去除，进而导致氮化硅无法被湿法剥掉。
目前为了线宽(CD)精确管控，大部分采用氮氧化硅作为抗反射层。请参阅图1(a)—(d)，其为业内目前常用的直接浅沟道隔离平坦化(Direct CMP STI)的工艺流程示意图。如图1所述，步骤(a)：首先在硅衬底S110上形成氧化层S120(Pad-Ox)、在氧化层S120的表面形成氮化硅层S130、在氮化硅层S130的表面形成一层氮氧化硅层S140(抗反射层)；步骤(b)：进行STI刻蚀(STI-ETCH)，刻蚀出STI深度,STI蚀刻后，采用高密度等离子体沉积法(high density plasma chemical vapor deposition，简称HDP-CVD)沉积二氧化硅层(SiO2)S150；步骤(c)：通过direct CMP方式，研磨抗反射层S140表面的二氧化硅层S150直至抗反射层S140；步骤(d)：通过磷酸(H3PO4)与氮化硅层S130反应将氮化硅层去除，形成有源(Active)区域及隔离(Isolation)区域。
请继续参阅图1(a)—(d)。当STI layer(STI层次)表面以氮氧化硅作为抗反射层S140时，Direct CMP方式将不再适用。其原因是：在Direct CMP时，由于研磨液对二氧化硅/氮氧化硅(SiO2/SiON)较高的选择比(大于10:1)，CMP最终会停留在氮氧化硅表面。研磨液将会与氮氧化硅表面发生反应，形成一层较为致密的络合物A(参见步骤(d)，在后续磷酸处理时，阻挡磷酸与氮化硅反应，导致氮化硅无法去除(参见步骤S150)。
请参阅图2(a)和(b)，其分别为以氮氧化硅作为抗反射层在经过氮化硅清除之后的形貌示意图，由图2(a)和(b)可以看出，由于氮氧化硅表面络合物的阻挡，大部分区域氮化硅(图中B和C指代区域)都无法清除。
为了避免发生此种问题，目前FAB常用的规避方式有两种：
a、用反向浅沟道隔离平坦化(Reverse STI CMP)方式代替Direct CMP方式，用不一样的研磨液进行研磨。该方法的缺陷为：需要增加一层反罩幕(reverse Mask)，进行曝光、蚀刻、清洗，工艺流程相对复杂，产品单位产出低；
b、在浅沟绝缘层(STI layer)采用有机底部抗反射涂层(Organic Barc)代替氮氧化硅作为抗反射层。该方法的缺陷为：采用Organic barc将会增加STI蚀刻CD控制的困难度,增加量产的制程管控难度。
发明内容
本发明的目的在于克服上述现有技术的缺陷提供一种基于氮氧化硅抗反射层的化学机械平坦化工艺，本发明的工艺方法简单，CD管控简单，可以有效解决氮化硅无法剥掉的问题。
为达成前述目的，本发明一种基于氮氧化硅抗反射层的化学机械平坦化工艺，其包括：提供一半导体晶圆，所述半导体晶圆包括衬底、形成于衬底上的氧化层、形成于所述氧化层上的氮化硅层、形成于所述氮化硅层上的抗反射层、贯穿所述抗反射层并延伸入所述衬底中的沟槽、以及填充于所述沟槽内并覆盖于所述抗反射层上的第一二氧化硅层；
研磨所述第一二氧化硅层直至所述抗反射层；
干法刻蚀去除所述抗反射层；
在去除所述抗反射层的半导体晶圆表面形成第二二氧化硅层；
研磨所述第二二氧化硅层直至所述氮化硅层；
去除所述氮化硅层。
作为本发明一个优选的实施例，所述抗反射层为氮氧化硅层。
作为本发明一个优选的实施例，所述第一二氧化硅层的形成是采用高密度等离子体化学气相沉积法，所述高密度等离子体为SiH4、O2和Ar混合物，沉积温度为380-400℃，压强为450Torr，时间为220s。
作为本发明一个优选的实施例，所述研磨所述第一二氧化硅层直至所述抗反射层步骤中，所述研磨的研磨液采用主成分为SiO2的研磨液，研磨时间为30-50s。
作为本发明一个优选的实施例，所述干法刻蚀去除所述抗反射层步骤中采用氩气、碳氟化合物和氧气混合气体、在温度60℃、压强15mTorr、时间10s条件下干法刻蚀。
作为本发明一个优选的实施例，所述第二二氧化硅层的形成是采用高密度等离子体化学气相沉积法沉积法，其中所述高密度等离子体为SiH4、O2和Ar混合物，沉积温度为380-400℃，压强为450Torr下，时间100s。
作为本发明一个优选的实施例，所述研磨所述第一二氧化硅层直至所述抗反射层步骤中，所述研磨的研磨液采用主成分为SiO2的研磨液，研磨时间为30-50s。
作为本发明一个优选的实施例，采用磷酸在温度150℃、时间1800s条件下去除所述氮化硅层。
作为本发明一个优选的实施例，所述氩气、碳氟化合物和氧气混合气体的体积比为3:1:1。
作为本发明一个优选的实施例，所述衬底为硅衬底，所述衬底表面上形成的氧化层为二氧化硅，该二氧化硅的厚度为110埃，所述氮化硅层的厚度为1500埃，所述抗反射层的厚度为300埃。
有益效果：本发明的工艺是在正常的Direct CMP之后，对晶片表面进行电浆处理，用离子轰击能力较强的气体结合一定量的碳氟化合物，对氮氧化硅表面进行轰击，打开表面络合物的键结，碳氟化合物和氮氧化硅发生反应，最终将氮氧化硅蚀刻掉。由于沟槽内部的二氧化硅亦被蚀刻掉，氮化硅和二氧化硅的高低落差将会变大，之后再重新沉积2um左右的二氧化硅层，进行二次CMP，CMP结束最终会停留在氮化硅表面，氮化硅和二氧化硅的高低落差也得到改善，之后磷酸进行氮化硅清除将氮化硅去除干净形成有源区域及隔离区域。
本发明的工艺无需增加额外的反向浅沟道隔离罩(Reverse STI Mask)及相对应的曝光、蚀刻，清洗，简化了工艺；并且本发明采用通用氮氧化硅作为抗反射层，CD管控相对简单。
附图说明
图1(a)—(d)是业内目前常用的直接浅沟道隔离平坦化(Direct CMP STI)的工艺流程示意；
图2(a)和(b)是以氮氧化硅作为抗反射层在经过氮化硅清除之后的形貌示意图；
图3是本发明基于氮氧化硅抗反射层的化学机械平坦化工艺流程图；
图4(a)—(f)是本发明的基于氮氧化硅抗反射层的化学机械平坦化工艺流程结构示意图。
图5是本发明的平坦化工艺氮化硅清除后的效果图。
具体实施方式
下面结合附图对本发明作进一步详细说明。
此处所称的“一个实施例”或“实施例”是指可包含于本发明至少一个实现方式中的特定特征、结构或特性。在本说明书中不同地方出现的“在一个实施例中”并非均指同一个实施例，也不是单独的或选择性的与其他实施例互相排斥的实施例。
请参阅图3，其为本发明基于氮氧化硅抗反射层的化学机械平坦化工艺流程图。请参阅图4(a)—(f)，其为本发明的基于氮氧化硅抗反射层的化学机械平坦化工艺流程结构示意图。本发明一种基于氮氧化硅抗反射层的化学机械平坦化工艺,其包括如下步骤：
步骤S1：提供一半导体晶圆，请参阅图,4(a)，所述半导体晶圆包括衬底S310、形成于衬底上的氧化层S320、形成于所述氧化层S320上的氮化硅层S330、形成于所述氮化硅层S330上的抗反射层S340、贯穿所述抗反射层S340并延伸入所述衬底中的沟槽、以及填充于所述沟槽内并覆盖于所述抗反射层S340上的第一二氧化硅层S350。在该实施例中，所述抗反射层S340为氮氧化硅层。在其他实施例中，所述抗反射层S340还可以为其他种类的材料。本步骤中，所述第一二氧化硅层S350的形成是采用高密度等离子体化学气相沉积(HDP-CVD)法，所述高密度等离子体为SiH4、O2和Ar混合物，沉积温度为380-400℃，压强为450Torr，时间为220s。本发明中，对高密度等离子体为SiH4、O2和Ar混合物中各成分的比例不做限制，可以根据生产的实际情况而定。在一个优选的实施例中，所述沉积温度为390℃。在其他实施例中，可根据实际生产情况来优化沉积压强和时间。
步骤S2：研磨所述第一二氧化硅层S350直至所述抗反射层S340。请参阅图4(b)，本步骤中，所述研磨的研磨液采用主成分为SiO2的研磨液对所述第一二氧化硅层S350进行化学机械平坦化(CMP)法研磨直至所述抗反射层S340，其中，研磨时间为30-50s。在该实施例中，该步骤是在常温、常压下进行的。本发明中，所述研磨液为混合物，该混合物至少为两种，其中所述SiO2在混合物中的所占比重大于另外其他成分。在其他实施例中，所述研磨液也可以有仅有SiO2组成。经该步骤研磨时，研磨液将会与抗反射层S340表面发生反应，形成一层较为致密的络合物A(见图4(b))。
步骤S3：干法刻蚀去除所述抗反射层S340。请参阅图4(c)，本步骤中，采用氩气、碳氟化合物和氧气混合气体、在温度60℃、压强15mTorr、时间10s条件下对所述抗反射层S340表面进行轰击，打开抗反射层S340表面络合物的键结，碳氟化合物和抗反射层S340发生反应，最终将抗反射层S340刻蚀掉。由于本步骤中沟槽内部的第一二氧化硅S350也被部分刻蚀掉，氮化硅层S330和第一二氧化硅S350的高低落差将会变大。本步骤中，对晶圆表面进行电浆处理，采用的是离子轰击能力较强的气体氩气、氧气结合一定量的碳氟化合物。在该实施例中，所述碳氟化合物为四氟化碳(CF4)，所述混合气体为氩气、四氟化碳和氧气的体积比为3:1:1，在其他实施例中，还可以是其他碳氟化合物，所述混合气体为氩气、四氟化碳和氧气的体积比可根据实际情况而定。在该实施例中，采用混合气体氩气、四氟化碳和氧气对步骤(b)后的氮氧化硅层S340进行干蚀刻表面处理的次数为一次，在其他实施例中，对所述氮氧化硅层S340干法刻蚀的次数不做限制，以能够保证将氮氧化硅层S340完全刻蚀掉为宜。
步骤S4：在去除所述抗反射层S340的半导体晶圆表面形成第二二氧化硅层S360。请参阅图4(d)，该步骤中，所述第二二氧化硅层S360的形成是采用高密度等离子体化学气相沉积法。在该实施例中，所述高密度等离子体为硅烷(SiH4)、O2和Ar混合物，沉积温度为380-400℃，压强为450Torr下，时间100s，在一个优选的实施例中，所述沉积温度为390℃。在该实施例中，本步骤沉积的第二二氧化硅层S360的厚度为2um。
步骤S5：研磨步骤(d)所形成的第二二氧化硅层S360直至所述氮化硅层S330。请参阅图4(e)，在该步骤中，所述研磨的研磨液采用主成分为二氧化硅的研磨液对步骤(d)沉积的第二二氧化硅层S360进行直接化学机械平坦化(CMP)，CMP结束最终会停留在氮化硅层S330表面，使得氮化硅层S330和第二二氧化硅S360高低落差也得到改善。在该实施例中，该步骤与所述步骤(b)相同，也是在常温、常压下进行的，研磨时间为30-50s。在该实施例中，所述研磨液为混合物，该混合物至少为两种，其中所述SiO2在混合物中的所占比重大于另外其他成分。在其他实施例中，所述研磨液也可以有仅有二氧化硅组成。本发明中，步骤(e)和步骤(b)的工艺条件还可以不相同，可以根据实际生产情况及氮氧化硅层的平坦化程度而具体设定。
步骤S6：去除所述氮化硅层S330。请参阅图4(f)，经步骤(e)研磨后，所述氮化硅层S330完全裸露，本步骤通过采用酸液与氮化硅层S330进行反应将氮化硅层S330移除干净，以形成有源区域和隔离区域。在该实施例中，所述酸液为磷酸，反应温度为150℃，反应时间为1800s。在其他实施例中，所述酸液不仅限于磷酸，反应温度和时间可根据具体情况而定。
在该实施例中，所述衬底为硅衬底，所述衬底表面上形成的氧化层为二氧化硅，该二氧化硅的厚度为110埃，所述氮化硅层的厚度为1500埃，所述抗反射层的厚度为300埃。在其他实施例中，所述衬底还可以为其他材质的衬底。
需要说明的是，本发明中，可根据具体的生产情况而选择不同的工艺参数。请参阅图5，其为本发明的平坦化工艺氮化硅清除后的效果图。如图5所示，本发明的平坦化工艺完全清除了氮化硅。
本发明的方法无需增加额外的反向浅沟道隔离罩(Reverse STI Mask)及相对应的曝光、蚀刻及清洗，简化了工艺；本发明采用氮氧化硅硅作为抗反射层，CD管控相对简单，并且能够有效的剥掉氮化硅。
上述说明已经充分揭露了本发明的具体实施方式。需要指出的是，熟悉该领域的技术人员对本发明的具体实施方式所做的任何改动均不脱离本发明的权利要求书的范围。相应地，本发明的权利要求的范围也并不仅仅局限于前述具体实施方式。

Claims (10)

1.一种基于氮氧化硅抗反射层的化学机械平坦化工艺,其特征在于：
提供一半导体晶圆，所述半导体晶圆包括衬底、形成于衬底上的氧化层、形成于所述氧化层上的氮化硅层、形成于所述氮化硅层上的抗反射层、贯穿所述抗反射层并延伸入所述衬底中的沟槽、以及填充于所述沟槽内并覆盖于所述抗反射层上的第一二氧化硅层；
研磨所述第一二氧化硅层直至所述抗反射层；
干法刻蚀去除所述抗反射层，其中，采用氩气、碳氟化合物和氧气混合气体对抗反射层表面进行轰击，打开抗反射层表面络合物的键结，通过碳氟化合物和抗反射层发生反应，最终将抗反射层刻蚀掉；
在去除所述抗反射层的半导体晶圆表面形成第二二氧化硅层；
研磨所述第二二氧化硅层直至所述氮化硅层；
去除所述氮化硅层。
2.根据权利要求1所述的化学机械平坦化工艺，其特征在于：所述抗反射层为氮氧化硅层。
3.根据权利要求1所述的化学机械平坦化工艺，其特征在于：所述第一二氧化硅层的形成是采用高密度等离子体化学气相沉积法，所述高密度等离子体为SiH4、O2和Ar混合物，沉积温度为380-400℃，压强为450Torr，时间为220s。
4.根据权利要求1所述的化学机械平坦化工艺，其特征在于：所述研磨所述第一二氧化硅层直至所述抗反射层步骤中，所述研磨的研磨液采用主成分为SiO2的研磨液，研磨时间为30-50s。
5.根据权利要求1所述的化学机械平坦化工艺，其特征在于：所述干法刻蚀去除所述抗反射层步骤中采用氩气、碳氟化合物和氧气混合气体、在温度60℃、压强15mTorr、时间10s条件下干法刻蚀。
6.根据权利要求1所述的化学机械平坦化工艺，其特征在于：所述第二二氧化硅层的形成是采用高密度等离子体化学气相沉积法，其中所述高密度等离子体为SiH4、O2和Ar混合物，沉积温度为380-400℃，压强为450Torr下，时间100s。
7.根据权利要求1所述的化学机械平坦化工艺，其特征在于：所述研磨所述第一二氧化硅层直至所述抗反射层步骤中，所述研磨的研磨液采用主成分为SiO2的研磨液，研磨时间为30-50s。
8.根据权利要求1所述的化学机械平坦化工艺，其特征在于：采用磷酸在温度150℃、时间1800s条件下去除所述氮化硅层。
9.根据权利要求5所述的化学机械平坦化工艺,其特征在于：所述氩气、碳氟化合物和氧气混合气体的体积比为3:1:1。
10.根据权利要求1所述的化学机械平坦化工艺，其特征在于：所述衬底为硅衬底，所述衬底表面上形成的氧化层为二氧化硅，该二氧化硅的厚度为110埃，所述氮化硅层的厚度为1500埃，所述抗反射层的厚度为300埃。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1391265A (zh) * 2002-07-19 2003-01-15 上海华虹（集团）有限公司 一种无机抗反射层去除方法
CN101281866A (zh) * 2007-04-03 2008-10-08 中芯国际集成电路制造(上海)有限公司 浅沟槽形成方法及浅沟槽结构

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6048765A (en) 1998-06-03 2000-04-11 Texas Instruments - Acer Incorporated Method of forming high density buried bit line flash EEPROM memory cell with a shallow trench floating gate
TW396520B (en) * 1998-10-30 2000-07-01 United Microelectronics Corp Process for shallow trench isolation
US6777336B2 (en) * 2002-04-29 2004-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a shallow trench isolation structure
US6849518B2 (en) * 2002-05-07 2005-02-01 Intel Corporation Dual trench isolation using single critical lithographic patterning
US6864150B2 (en) * 2003-03-06 2005-03-08 Silicon Integrated Systems Corp. Manufacturing method of shallow trench isolation
US7098116B2 (en) * 2004-01-08 2006-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Shallow trench isolation method for reducing oxide thickness variations at different pattern densities
JP4825402B2 (ja) * 2004-01-14 2011-11-30 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7176138B2 (en) * 2004-10-21 2007-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Selective nitride liner formation for shallow trench isolation
CN101330037A (zh) * 2007-06-21 2008-12-24 中芯国际集成电路制造(上海)有限公司 浅沟槽隔离的制造方法
CN101359596B (zh) * 2007-07-31 2010-06-23 中芯国际集成电路制造(上海)有限公司 沟槽的填充方法及浅沟槽隔离的制造方法
US8035165B2 (en) * 2008-08-26 2011-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating a first contact structure in a gate last process
US8367515B2 (en) * 2008-10-06 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid shallow trench isolation for high-k metal gate device improvement
US8461015B2 (en) * 2009-07-08 2013-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. STI structure and method of forming bottom void in same
CN102569161B (zh) * 2010-12-22 2014-06-04 无锡华润上华半导体有限公司 半导体器件制造方法
CN103227143B (zh) * 2013-04-08 2016-08-24 上海华力微电子有限公司 浅沟槽隔离工艺

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1391265A (zh) * 2002-07-19 2003-01-15 上海华虹（集团）有限公司 一种无机抗反射层去除方法
CN101281866A (zh) * 2007-04-03 2008-10-08 中芯国际集成电路制造(上海)有限公司 浅沟槽形成方法及浅沟槽结构

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