CN106653675B - 浅沟槽隔离结构的形成方法 - Google Patents
浅沟槽隔离结构的形成方法 Download PDFInfo
- Publication number
- CN106653675B CN106653675B CN201510543291.3A CN201510543291A CN106653675B CN 106653675 B CN106653675 B CN 106653675B CN 201510543291 A CN201510543291 A CN 201510543291A CN 106653675 B CN106653675 B CN 106653675B
- Authority
- CN
- China
- Prior art keywords
- insulating layer
- shallow trench
- flow rate
- forming
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 68
- 238000002955 isolation Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 37
- 238000009832 plasma treatment Methods 0.000 claims abstract description 24
- 238000004140 cleaning Methods 0.000 claims abstract description 9
- 230000008569 process Effects 0.000 claims description 48
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 18
- 238000005137 deposition process Methods 0.000 claims description 14
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 7
- 239000002243 precursor Substances 0.000 claims description 6
- 238000012545 processing Methods 0.000 claims description 6
- 239000008367 deionised water Substances 0.000 claims description 3
- 229910021641 deionized water Inorganic materials 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical group O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 239000007789 gas Substances 0.000 description 32
- 239000006227 byproduct Substances 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 239000000126 substance Substances 0.000 description 7
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 6
- 229910052731 fluorine Inorganic materials 0.000 description 6
- 239000011737 fluorine Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229910008284 Si—F Inorganic materials 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Plasma & Fusion (AREA)
- Element Separation (AREA)
Abstract
一种浅沟槽隔离结构的形成方法,包括:提供半导体衬底,所述半导体衬底内形成有浅沟槽;在半导体衬底表面及所述浅沟槽内形成第一绝缘层,位于浅沟槽内的第一绝缘层中具有开口;刻蚀第一绝缘层以增大开口的宽度;对刻蚀后的第一绝缘层的表面进行等离子体处理;清洗等离子体处理后的所述第一绝缘层的表面;清洗所述第一绝缘层的表面后,向浅沟槽内填充满第二绝缘层。所述浅沟槽隔离结构的形成方法提高了浅沟槽隔离结构的性能。
Description
技术领域
本发明涉及半导体制造领域,尤其涉及一种浅沟槽隔离结构的形成方法。
背景技术
浅沟槽隔离结构(STI)是一种重要的隔离结构,在目前的半导体器件制造中用于器件隔离。所述浅沟槽隔离结构的形成步骤为:提供半导体衬底;在半导体衬底中形成浅沟槽;在所述半导体衬底表面和浅沟槽内形成填充满浅沟槽的绝缘层;采用化学机械研磨工艺去除半导体衬底表面的绝缘层,在浅沟槽中形成浅沟槽隔离结构。
随着半导体技术的发展,器件尺寸持续缩小,导致浅沟槽隔离结构的宽度尺寸也相应的减小,则用于形成浅沟槽隔离结构的浅沟槽的深宽比(aspect ratio)不断增大,在形成所述绝缘层的过程中,绝缘材料容易堆积在靠近浅沟槽顶部的侧壁表面,导致形成于浅沟槽顶部侧壁的绝缘层厚度较厚,浅沟槽底部的绝缘膜厚度较薄,继续沉积绝缘层,位于浅沟槽顶部的绝缘膜首先闭合,从而导致所形成的浅沟槽隔离结构内产生空隙。
为了避免在具有高深宽比的浅沟槽内填充绝缘层时产生空隙的现象,现有技术中采用高深宽比沉积工艺(HARP,High Ratio Process)形成绝缘层,以满足高深宽比浅沟槽的填充需求。具体的,以正硅酸乙酯(TEOS)与臭氧(O3)为反应气体,对高深宽比的浅沟槽进行填充。
然而,随着所述浅沟槽的深宽比继续增加时,现有技术中形成的浅沟槽隔离结构的性能较差。
发明内容
本发明解决的问题是提供一种浅沟槽隔离结构的形成方法,以提高浅沟槽隔离结构的性能。
为解决上述问题,本发明提供一种浅沟槽隔离结构的形成方法,包括:提供半导体衬底,所述半导体衬底内形成有浅沟槽;在半导体衬底表面及所述浅沟槽内形成第一绝缘层,位于浅沟槽内的第一绝缘层中具有开口;刻蚀第一绝缘层以增大开口的宽度;对刻蚀后的第一绝缘层的表面进行等离子体处理;清洗等离子体处理后的所述第一绝缘层的表面;清洗所述第一绝缘层的表面后,向浅沟槽内填充满第二绝缘层。
可选的,所述等离子体处理采用的气体为Ar、He或He和Ar的混合气体。
可选的,所述等离子体处理的工艺参数为:所述气体的总流量为1000sccm~3000sccm,高频射频功率为100瓦~500瓦,低频射频功率为50瓦~150瓦,腔室压强为5torr~15torr,温度为350摄氏度~450摄氏度,处理时间为30秒~90秒。
可选的,清洗所述第一绝缘层表面采用的溶液为去离子水。
可选的,所述第一绝缘层的材料为氧化硅。
可选的,形成第一绝缘层的工艺为高深宽比沉积工艺,具体参数为:采用的前驱体为正硅酸乙酯与臭氧,正硅酸乙酯的流量为500毫克每分钟~2500毫克每分钟,臭氧的流量为15000sccm~25000sccm,腔室压强为550torr~650torr,温度为450摄氏度~600摄氏度。
可选的,刻蚀第一绝缘层的工艺为干刻工艺,具体的参数为:采用的气体为NH3、NF3、He和Ar,NH3的流量为50sccm~200sccm,NF3的流量为50sccm~200sccm,He的流量为500sccm~2000sccm,Ar的流量为300sccm~600sccm,射频功率为50瓦~150瓦,刻蚀腔室压强为3torr~8torr。
可选的,所述第二绝缘层的材料为氧化硅。
可选的,形成第二绝缘层的工艺为高深宽比沉积工艺,具体的参数为:采用的前驱体为正硅酸乙酯与臭氧,正硅酸乙酯的流量为500毫克每分钟~2500毫克每分钟,臭氧的流量为15000sccm~25000sccm,腔室压强为550torr~650torr,温度为450摄氏度~600摄氏度。
可选的,还包括,在形成第一绝缘层之前,在浅沟槽侧壁和底部形成绝缘衬垫层。
与现有技术相比,本发明的技术方案具有以下优点:
本发明提供的浅沟槽隔离结构的形成方法中,由于对刻蚀后的第一绝缘层的表面进行了等离子体处理,将在刻蚀第一绝缘过程中刻蚀气体与第一绝缘层反应后形成的化学键打断,在第一绝缘层表面形成游离的残余物;然后清洗第一绝缘层的表面,将所述残余物去除,同时去除刻蚀气体与第一绝缘层反应后形成的副产物;清洗第一绝缘层的表面后,向浅沟槽内填充满第二绝缘层。使得第二绝缘层的均一性提高,从而提高了浅沟槽隔离结构的性能。
附图说明
图1至图4是本发明一实施例中浅沟槽隔离结构形成过程的示意图;
图5至图12本发明另一实施例中浅沟槽隔离结构形成过程的示意图。
具体实施方式
正如背景技术所述,现有技术中形成的浅沟槽隔离结构的性能较差。
图1至图4是本发明一实施例中浅沟槽隔离结构形成过程的示意图。
参考图1,提供半导体衬底100,所述半导体衬底100内形成有浅沟槽110。
所述半导体衬底100顶部表面具有掩膜层101。
参考图2,在半导体衬底100表面和浅沟槽110(参考图1)内形成第一绝缘层120,位于浅沟槽110内的第一绝缘层120中具有开口111。
所述第一绝缘层120的材料为氧化硅。
参考图3,刻蚀第一绝缘层120以增大开口111的宽度。
刻蚀第一绝缘层120采用的气体为NF3、NH3、He和Ar。
参考图4,刻蚀第一绝缘层120后,向浅沟槽110填充满第二绝缘层121。
研究发现,上述方法形成的浅沟槽隔离结构依然存在性能较差的原因在于:
在刻蚀第一绝缘层以增大开口宽度的过程中,刻蚀气体采用含氟的气体,一方面,刻蚀气体与第一绝缘层反应在部分第一绝缘层表面形成Si-F键,Si-F键在第一绝缘层表面分布不均匀,导致在第一绝缘层表面形成的第二绝缘层均一性变差;另一方面,刻蚀气体与第一绝缘层反应在部分第一绝缘层表面形成含氟的副产物,所述含氟的副产物聚集在开口中,会阻挡第二绝缘层的填充而形成孔隙,导致第二绝缘层的均一性较差。从而降低了浅沟槽隔离结构的性能。
在此基础上,本发明另一实施例提供一种浅沟槽隔离结构的形成方法,包括:提供具有浅沟槽的半导体衬底;在半导体衬底表面及所述浅沟槽内形成第一绝缘层,位于浅沟槽内的第一绝缘层中具有开口;然后刻蚀第一绝缘层以增大开口的宽度;通过对刻蚀后的第一绝缘层的表面进行等离子体处理,将在刻蚀第一绝缘层过程中刻蚀气体与第一绝缘层反应后形成的化学键打断,在第一绝缘层表面形成残余物;之后,清洗等离子体处理后的所述第一绝缘层的表面,将所述残余物去除,同时去除刻蚀气体与第一绝缘层反应后形成的副产物;清洗所述第一绝缘层的表面后,向浅沟槽内填充满第二绝缘层。使得第二绝缘层的均一性提高,从而提高了浅沟槽隔离结构的性能。
为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。
参考图5,提供半导体衬底200。
所述半导体衬底200为后续形成浅沟槽隔离结构提供工艺平台。
所述半导体衬底200可以是单晶硅,多晶硅或非晶硅;所述半导体衬底200也可以是硅、锗、锗化硅、砷化镓等半导体材料。本实施例中,所述半导体衬底200的材料为硅。
本实施例中,所述半导体衬底200表面还具有掩膜层201,所述掩膜层201包括位于半导体衬底200表面的氧化层202和位于所述氧化层202表面的刻蚀阻挡层203。
所述氧化层202的材料为氧化硅;所述氧化层202的厚度为20埃~100埃;所述氧化层202采用湿法氧化或干法氧化工艺形成;所述氧化层202作为后续形成的刻蚀阻挡层203的缓冲层,具体的说,氧化层202形成在半导体衬底200和所述刻蚀阻挡层203之间,避免了直接在半导体衬底200上形成所述刻蚀阻挡层203对半导体衬底200产生较大的应力,并且在后续去掉所述刻蚀阻挡层203的过程中所述氧化层202还可以作为隔离层保护有源区免受化学污沾。
所述刻蚀阻挡层203的材料为氮化硅;所述刻蚀阻挡层203的厚度为500埃~700埃;所述刻蚀阻挡层203的形成工艺为沉积工艺;所述刻蚀阻挡层203作为后续化学机械研磨工艺的停止层,保护有源区。
参考图6,在所述半导体衬底200内形成浅沟槽210。
所述浅沟槽210为后续填充第一绝缘层和第二绝缘层提供空间。
所述浅沟槽210的形成步骤为:形成覆盖半导体衬底200表面的掩膜层201(参考图5);在所述掩膜层201表面形成图形化的光刻胶,所述图形化的光刻胶定义浅沟槽210的位置;以所述图形化的光刻胶为掩膜,采用各向异性干刻工艺刻蚀掩膜层201和半导体衬底200,在半导体衬底200中形成浅沟槽210。
随着半导体器件的特征尺寸的持续缩小,导致用于形成浅沟槽隔离结构的浅沟槽210的深宽比不断增大,本实施例中,所述浅沟槽210的深宽比为5:1~10:1。
所述浅沟槽210的剖面形状为V型或U型。为了利于后续在浅沟槽210中填充第一绝缘层,优选的,所述浅沟槽210的剖面形状为V型。
本实施例中,还包括:在浅沟槽210侧壁和底部形成绝缘衬垫层(未图示)。本实施例中,所述绝缘衬垫层的材料为氧化硅,所述绝缘衬垫层的厚度为30埃~200埃。所述绝缘衬垫层的形成工艺为沉积工艺,如原子层沉积工艺、等离子体化学气相沉积工艺或热氧化工艺。
所述绝缘衬垫层作为半导体衬底200和后续形成的第一绝缘层之间的过渡层,使得后续形成的第一绝缘层与半导体衬底200之间的结合质量更好,减小第一绝缘层与半导体衬底200接触面之间的缺陷。
由于所述浅沟槽210的深宽比较大,后续在浅沟槽210中填充绝缘层的难度高,用于填充浅沟槽210的绝缘层难以充分进入浅沟槽210的底部,容易在浅沟槽210的顶部被绝缘层闭合的情况下,所述浅沟槽210内仍具有未被填充的孔隙。因此,本实施例中,后续在浅沟槽210中先填充第一绝缘层,位于浅沟槽210内的第一绝缘层中具有开口,使得浅沟槽210顶部未闭合。
参考图7,在半导体衬底200表面及浅沟槽210(参考图6)内形成第一绝缘层220,位于浅沟槽210内的第一绝缘层220中具有开口211。
第一绝缘层220的作用为:在浅沟槽210侧壁和底部填充第一绝缘层220,使得浅沟槽210顶部未闭合。
本实施例中,第一绝缘层220的材料为氧化硅。
形成第一绝缘层220的方法为沉积工艺,如等离子体化学气相沉积工艺、高浓度等离子体化学气相沉积工艺、次常压化学气相沉积工艺或高深宽比沉积工艺。本实施例中,形成第一绝缘层220的工艺为高深宽比沉积工艺(HARP,High Ratio Process)。
在一个具体的实施例中,形成第一绝缘层220采用的所述高深宽比沉积工艺是在次常压化学气相沉积(SACVD)机台中进行的,具体的工艺参数为:采用的前驱体为正硅酸乙酯(TEOS)与臭氧(O3),正硅酸乙酯(TEOS)的流量为500毫克每分钟~2500毫克每分钟,臭氧(O3)的流量为15000sccm~25000sccm,腔室压强为550torr~650torr,温度为450摄氏度~600摄氏度。
在浅沟槽210中填充第一绝缘层220,位于浅沟槽210内的第一绝缘层220中具有开口211,使得浅沟槽210的顶部未闭合。所述开口211的深宽比大于浅沟槽210的深宽比,具体的,开口211的深宽比为15:1~25:1。若继续填充第一绝缘层220,会使得浅沟槽210的顶部闭合而在第一绝缘层220中形成孔隙。因此,后续刻蚀第一绝缘层220,以增加开口211的宽度,利于后续在浅沟槽210中填充第二绝缘层。
参考图8,刻蚀第一绝缘层220以增大开口211的宽度。
刻蚀所述第一绝缘层220的工艺为干刻工艺或湿刻工艺。本实施例中,刻蚀第一绝缘层220的工艺为干刻工艺。
在一个具体的实施例中,所述干刻工艺的参数为:采用的气体为NH3、NF3、He和Ar,NH3的流量为50sccm~200sccm,NF3的流量为50sccm~200sccm,He的流量为500sccm~2000sccm,Ar的流量为300sccm~600sccm,射频功率为50瓦~150瓦,刻蚀腔室压强为3torr~8torr。
由于将开口211的宽度增大,使得开口211的深宽比减小,利于后续在浅沟槽210中填充第二绝缘层。本实施例中,刻蚀第一绝缘层220后,开口211的深宽比为10:1~15:1。
需要说明的是,在刻蚀第一绝缘层220以增大开口211的宽度的过程中,刻蚀气体采用含氟的气体,一方面,刻蚀气体与第一绝缘层220反应在部分第一绝缘层220表面形成Si-F键,所述Si-F键影响后续第二绝缘层在第一绝缘层220表面沉积的选择比;另一方面,刻蚀气体与第一绝缘层220反应在部分第一绝缘层220表面形成含氟的副产物,所述含氟的副产物聚集在开口211中,阻挡后续第二绝缘层的填充,故后续对刻蚀后的第一绝缘层220的表面进行等离子体处理,然后清洗所述第一绝缘层220的表面,以提高后续形成的第二绝缘层的均一性。
参考图9,对刻蚀后的第一绝缘层220的表面进行等离子体处理;清洗等离子体处理后的第一绝缘层220的表面。
对刻蚀后的第一绝缘层220的表面进行等离子体处理,打断刻蚀气体与第一绝缘层220反应在部分第一绝缘层220表面形成Si-F键,在第一绝缘层220表面形成游离的残余物,然后清洗第一绝缘层220表面,将所述残余物去除;另外,清洗所述第一绝缘层220的表面的过程中,将刻蚀气体与第一绝缘层220反应后形成于第一绝缘层220表面的副产物去除。利于后续在浅沟槽210中填充第二绝缘层,使得形成于第一绝缘层220表面的第二绝缘层具有良好的均一性。
所述等离子体处理采用的气体为He、Ar或者He和Ar的混合气体。
若等离子体处理采用的气体的总流量较小,会降低形成的等离子体的密度,从而降低对第一绝缘层220表面等离子体处理的效率;若等离子体处理采用的气体的总流量较大,会增加工艺成本。故本实施例中,等离子体处理采用的气体的总流量为1000sccm~3000sccm。
等离子体处理的高频射频功率使得所述气体等离子体化,若高频射频功率过低,所述气体不能被等离子体化,若高频射频功率过高,会增加制作成本且受到工艺条件的限制。故本实施例中,等离子体处理采用的高频射频功率为100瓦~500瓦。
低频射频功率产生偏置电压,使得所述等离子体具有一定速率且向第一绝缘层表面运动,若低频射频功率过低,所述等离子体具有的运动能量过低,不能打断第一绝缘层220表面的Si-F键,若低频射频功率过高,所述等离子体具有的运动能量过高,使得第一绝缘层220表面受到损伤。故本实施例中,低频射频功率为50瓦~150瓦。
若等离子体处理的时间过短,没有足够的时间完全打断第一绝缘层220表面的Si-F键,若等离子体处理的时间过长,会造成对第一绝缘层220表面严重的损伤。故本实施例中,等离子体处理的时间为30秒~90秒。
所述等离子体处理的腔室压强为5torr~15torr,温度为350摄氏度~450摄氏度。
本实施例中,采用去离子水清洗所述第一绝缘层220的表面。
参考图10,清洗所述第一绝缘层220的表面后,向浅沟槽210内填充满第二绝缘层221。
本实施例中,第二绝缘层221的材料为氧化硅。
形成第二绝缘层221的方法为沉积工艺,如等离子体化学气相沉积工艺、高浓度等离子体化学气相沉积工艺、次常压化学气相沉积工艺或高深宽比沉积工艺。本实施例中,形成第二绝缘层221的工艺为高深宽比沉积工艺。
在一个具体的实施例中,形成第二绝缘层221采用的高深宽比沉积工艺是在次常压化学气相沉积(SACVD)机台中进行的,具体的工艺参数为:采用的前驱体为正硅酸乙酯(TEOS)与臭氧(O3),正硅酸乙酯(TEOS)的流量为500毫克每分钟~2500毫克每分钟,臭氧(O3)的流量为15000sccm~25000sccm,腔室压强为550torr~650torr,温度为450摄氏度~600摄氏度。
由于刻蚀第一绝缘层220后的开口211的深宽比减小,避免在填充第二绝缘层221的过程中形成空隙。另外,由于去除了等离子体刻蚀后在第一绝缘层220表面的残余物,及去除了刻蚀气体与第一绝缘层220反应后形成于第一绝缘层220表面的副产物,向浅沟槽210填充第二绝缘层221的过程中,使得第二绝缘层221的均一性提高。
参考图11,平坦化第一绝缘层220和第二绝缘层221,直至暴露出所述掩膜层201的表面。
平坦化第一绝缘层220和第二绝缘层221的方法为化学机械研磨工艺(CMP)。
所述刻蚀阻挡层203作为平坦化第一绝缘层220和第二绝缘层221过程中的停止层,避免化学机械研磨工艺对所述氧化层202和半导体衬底200造成损伤。
参考图12,采用湿刻工艺去除掩膜层201(参考图11),形成浅沟槽隔离结构。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (8)
1.一种浅沟槽隔离结构的形成方法,其特征在于,包括:
提供半导体衬底,所述半导体衬底内形成有浅沟槽;
在半导体衬底表面及所述浅沟槽内形成第一绝缘层,位于浅沟槽内的第一绝缘层中具有开口;
刻蚀第一绝缘层以增大开口的宽度,刻蚀第一绝缘层的工艺为干刻工艺,采用的气体包括NF3;
对刻蚀后的第一绝缘层的表面进行等离子体处理,所述等离子体处理采用的气体为Ar、He或He和Ar的混合气体,所述等离子体处理的工艺参数为:所述气体的总流量为1000sccm~3000sccm,高频射频功率为100瓦~500瓦,低频射频功率为50瓦~150瓦,腔室压强为5torr~15torr,温度为350摄氏度~450摄氏度,处理时间为30秒~90秒;
清洗等离子体处理后的所述第一绝缘层的表面;
清洗所述第一绝缘层的表面后,向浅沟槽内填充满第二绝缘层。
2.根据权利要求1所述的浅沟槽隔离结构的形成方法,其特征在于,清洗所述第一绝缘层表面采用的溶液为去离子水。
3.根据权利要求1所述的浅沟槽隔离结构的形成方法,其特征在于,所述第一绝缘层的材料为氧化硅。
4.根据权利要求3所述的浅沟槽隔离结构的形成方法,其特征在于,形成第一绝缘层的工艺为高深宽比沉积工艺,具体参数为:采用的前驱体为正硅酸乙酯与臭氧,正硅酸乙酯的流量为500毫克每分钟~2500毫克每分钟,臭氧的流量为15000sccm~25000sccm,腔室压强为550torr~650torr,温度为450摄氏度~600摄氏度。
5.根据权利要求1所述的浅沟槽隔离结构的形成方法,其特征在于,所述干刻工艺的具体的参数为:采用的气体为NH3、NF3、He和Ar,NH3的流量为50sccm~200sccm,NF3的流量为50sccm~200sccm,He的流量为500sccm~2000sccm,Ar的流量为300sccm~600sccm,射频功率为50瓦~150瓦,刻蚀腔室压强为3torr~8torr。
6.根据权利要求1所述的浅沟槽隔离结构的形成方法,其特征在于,所述第二绝缘层的材料为氧化硅。
7.根据权利要求6所述的浅沟槽隔离结构的形成方法,其特征在于,形成第二绝缘层的工艺为高深宽比沉积工艺,具体的参数为:采用的前驱体为正硅酸乙酯与臭氧,正硅酸乙酯的流量为500毫克每分钟~2500毫克每分钟,臭氧的流量为15000sccm~25000sccm,腔室压强为550torr~650torr,温度为450摄氏度~600摄氏度。
8.根据权利要求1所述的浅沟槽隔离结构的形成方法,其特征在于,还包括,在形成第一绝缘层之前,在浅沟槽侧壁和底部形成绝缘衬垫层。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510543291.3A CN106653675B (zh) | 2015-08-28 | 2015-08-28 | 浅沟槽隔离结构的形成方法 |
US15/249,205 US10134625B2 (en) | 2015-08-28 | 2016-08-26 | Shallow trench isolation structure and fabricating method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510543291.3A CN106653675B (zh) | 2015-08-28 | 2015-08-28 | 浅沟槽隔离结构的形成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106653675A CN106653675A (zh) | 2017-05-10 |
CN106653675B true CN106653675B (zh) | 2020-07-10 |
Family
ID=58104253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510543291.3A Active CN106653675B (zh) | 2015-08-28 | 2015-08-28 | 浅沟槽隔离结构的形成方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10134625B2 (zh) |
CN (1) | CN106653675B (zh) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10276677B2 (en) * | 2016-11-28 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
CN108630605B (zh) * | 2017-03-22 | 2020-12-18 | 中芯国际集成电路制造(上海)有限公司 | 半导体装置及其制造方法 |
CN107799460B (zh) * | 2017-10-20 | 2020-02-21 | 上海华力微电子有限公司 | 浅沟槽隔离结构的形成方法 |
CN110911344B (zh) * | 2018-09-14 | 2023-09-05 | 长鑫存储技术有限公司 | 半导体衬底浅沟槽制作方法及半导体衬底浅沟槽结构 |
CN109712916B (zh) * | 2018-12-29 | 2021-12-14 | 上海华力微电子有限公司 | Sti的填充方法 |
US11615966B2 (en) * | 2020-07-19 | 2023-03-28 | Applied Materials, Inc. | Flowable film formation and treatments |
US11699571B2 (en) | 2020-09-08 | 2023-07-11 | Applied Materials, Inc. | Semiconductor processing chambers for deposition and etch |
US11887811B2 (en) | 2020-09-08 | 2024-01-30 | Applied Materials, Inc. | Semiconductor processing chambers for deposition and etch |
CN115662941A (zh) * | 2021-07-08 | 2023-01-31 | 长鑫存储技术有限公司 | 浅沟槽隔离结构及其制备方法 |
CN113611661B (zh) * | 2021-08-02 | 2023-06-13 | 长鑫存储技术有限公司 | 半导体结构的制备方法及半导体结构 |
US11862458B2 (en) * | 2021-09-08 | 2024-01-02 | Applied Materials, Inc. | Directional selective deposition |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5904154A (en) * | 1997-07-24 | 1999-05-18 | Vanguard International Semiconductor Corporation | Method for removing fluorinated photoresist layers from semiconductor substrates |
CN101819930A (zh) * | 2009-02-26 | 2010-09-01 | 中芯国际集成电路制造(上海)有限公司 | 降低沟槽内残留物的方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6165375A (en) * | 1997-09-23 | 2000-12-26 | Cypress Semiconductor Corporation | Plasma etching method |
US6902987B1 (en) * | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
JP4001498B2 (ja) * | 2002-03-29 | 2007-10-31 | 東京エレクトロン株式会社 | 絶縁膜の形成方法及び絶縁膜の形成システム |
US6908862B2 (en) * | 2002-05-03 | 2005-06-21 | Applied Materials, Inc. | HDP-CVD dep/etch/dep process for improved deposition into high aspect ratio features |
KR101062293B1 (ko) * | 2008-11-14 | 2011-09-05 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조방법 |
US20120009796A1 (en) * | 2010-07-09 | 2012-01-12 | Applied Materials, Inc. | Post-ash sidewall healing |
-
2015
- 2015-08-28 CN CN201510543291.3A patent/CN106653675B/zh active Active
-
2016
- 2016-08-26 US US15/249,205 patent/US10134625B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5904154A (en) * | 1997-07-24 | 1999-05-18 | Vanguard International Semiconductor Corporation | Method for removing fluorinated photoresist layers from semiconductor substrates |
CN101819930A (zh) * | 2009-02-26 | 2010-09-01 | 中芯国际集成电路制造(上海)有限公司 | 降低沟槽内残留物的方法 |
Also Published As
Publication number | Publication date |
---|---|
US10134625B2 (en) | 2018-11-20 |
CN106653675A (zh) | 2017-05-10 |
US20170062266A1 (en) | 2017-03-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106653675B (zh) | 浅沟槽隔离结构的形成方法 | |
US8975155B2 (en) | Method of forming a shallow trench isolation structure | |
TWI511234B (zh) | 半導體結構及用於在鰭狀場效電晶體裝置之鰭狀結構間形成隔離的方法 | |
US9960074B2 (en) | Integrated bi-layer STI deposition | |
US20140361353A1 (en) | Semiconductor device and method for manufacturing the same | |
US8404561B2 (en) | Method for fabricating an isolation structure | |
US20060148197A1 (en) | Method for forming shallow trench isolation with rounded corners by using a clean process | |
CN109390235B (zh) | 半导体结构及其形成方法 | |
CN108305850B (zh) | 半导体结构及其形成方法 | |
US20080305609A1 (en) | Method for forming a seamless shallow trench isolation | |
US8163625B2 (en) | Method for fabricating an isolation structure | |
CN109872953B (zh) | 半导体器件及其形成方法 | |
CN108573862B (zh) | 半导体结构及其形成方法 | |
CN108807377B (zh) | 半导体器件及其形成方法 | |
CN106856189B (zh) | 浅沟槽隔离结构及其形成方法 | |
US6784075B2 (en) | Method of forming shallow trench isolation with silicon oxynitride barrier film | |
TWI508223B (zh) | 用於製造具有均勻梯狀高度之隔離區的半導體裝置的方法 | |
CN112117192B (zh) | 半导体结构的形成方法 | |
CN105702724B (zh) | 半导体器件及其形成方法 | |
US6720235B2 (en) | Method of forming shallow trench isolation in a semiconductor substrate | |
CN109300844B (zh) | 鳍式晶体管及其形成方法 | |
KR100912988B1 (ko) | 반도체 소자의 제조 방법 | |
CN108962971A (zh) | 一种半导体结构及其形成方法 | |
KR100691016B1 (ko) | 반도체 소자의 소자분리막 형성방법 | |
US10490451B2 (en) | Process for fabricating a transistor structure including a plugging step |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |