WO2015145913A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2015145913A1 WO2015145913A1 PCT/JP2014/084600 JP2014084600W WO2015145913A1 WO 2015145913 A1 WO2015145913 A1 WO 2015145913A1 JP 2014084600 W JP2014084600 W JP 2014084600W WO 2015145913 A1 WO2015145913 A1 WO 2015145913A1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/7722—Field effect transistors using static field induced regions, e.g. SIT, PBT
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Definitions
- the present invention relates to a semiconductor device such as an electrostatic induction transistor or an electrostatic induction thyristor.
- a MOSFET having a superjunction structure in a drift layer of a vertical power MOSFET is conventionally known.
- a depletion layer spreads from both of a plurality of parallel pn junctions between a p-type column and an n-type column to both sides of the p-type column and the n-type column.
- the depletion layer is depleted with low electric field strength. This leads to higher breakdown voltage.
- a MOSFET having a superjunction structure has an effect that an on-resistance having a trade-off relationship with a withstand voltage is reduced (see JP 2012-004173 A).
- JP 2012-004173 A an electrostatic induction transistor of silicon carbide.
- Japanese Patent No. 3284120 since the surface structure is complicated, it is difficult to miniaturize the superjunction. It is.
- a power semiconductor device having a superjunction static induction transistor capable of improving the characteristics of the reverse mode operation of the transistor has been disclosed (Japanese Patent Laid-Open No. 2010-045218).
- a p-type gate / drift layer is formed in a columnar shape extending in the vertical direction, and a super-junction structure is configured by the p-type gate / drift layer and the n-type drift layer.
- the p-type gate / drift layer also serves as the gate region, there is a possibility that the on-resistance is high and the withstand voltage when off is low.
- An object of the present invention is to provide a semiconductor device capable of improving the on-characteristic and off-characteristic by utilizing the advantages of the superjunction structure.
- the on characteristic indicates a conduction characteristic
- the off characteristic indicates a breakdown voltage characteristic.
- a semiconductor device is formed on a first conductivity type semiconductor region, a first conductivity type source region formed on one surface of the semiconductor region, and on the other surface of the semiconductor region.
- a superjunction structure is configured by a plurality of first conductivity type first regions extending toward the drain region and a first conductivity type second region existing between the first regions, and the first region is It is p-type, the second region is n-type, the buried gate region is p-type, and the buried gate region is connected to the upper portion of the first region.
- the width of the buried gate region is larger than the width of the first region, both sides of the buried gate region protrude laterally from the first region, and the adjacent buried gate regions
- the length of the channel region is equal to or less than the thickness of the buried gate region
- the impurity concentration of the source region is 10 17 cm ⁇ 3 or more and less than 10 21 cm ⁇ 3
- the impurity concentration of the buried gate region is 10 18 cm ⁇ . It may be 3 or more and less than 10 21 cm ⁇ 3
- the impurity concentration of the first region may be 10 15 cm ⁇ 3 or more and less than 10 18 cm ⁇ 3 .
- the upper end of the buried gate region may be in contact with the lower end of the source region.
- the low concentration n-type region having an impurity concentration of 10 16 cm ⁇ 3 or less from the upper end of the buried gate region to a depth of more than 1 ⁇ 2 of the thickness of the buried gate region and 5/6 or less.
- an intrinsic semiconductor region or an active high-resistance semiconductor layer is preferably formed.
- the buried gate region may extend in one direction and be arranged in another direction orthogonal to the one direction.
- a region between the adjacent buried gate regions constitutes a channel region, and the channel region extends along the one direction and extends along the other direction. May be arranged.
- the source region may extend over the adjacent channel region.
- At least the extending direction of the source region and the extending direction of the bonding surface of the super-junction structure may be parallel.
- At least the extension direction of the source region and the extension direction of the bonding surface of the super-junction structure may be perpendicular.
- the source region may be separated, and the source region may extend in the one direction and be arranged in the other direction on the channel region.
- the source region may be further separated in an island shape, and the island-like source region may be arranged in the one direction and the other direction.
- the ratio of the length of the channel region to the thickness of the semiconductor region may be 8/100 or less.
- the ratio of the length of the channel region to the thickness of the semiconductor region is preferably 1/300 or more and 6/100 or less.
- the width of the first region and the width of the second region may be substantially the same.
- the total amount of impurities in the first region and the total amount of impurities in the second region are preferably substantially the same.
- the on characteristic and the off characteristic can be improved by utilizing the advantages of the superjunction structure.
- FIG. 2A is a cross-sectional view taken along line IIA-IIA in FIG. 1
- FIG. 2B is a cross-sectional view taken along line IIB-IIB in FIG. 2A.
- It is a graph which shows the ON characteristic of a 1st semiconductor device.
- It is a graph which shows the OFF characteristic of a 1st semiconductor device.
- It is a graph which shows the change of the breakdown voltage with respect to the dispersion
- FIG. 7A is a cross-sectional view taken along line VIIA-VIIA in FIG. 6, and FIG. 7B is a cross-sectional view taken along line VIIB-VIIB in FIG. 7A.
- FIG. 9A is a cross-sectional view taken along line IXA-IXA in FIG. 8, and FIG. 9B is a cross-sectional view taken along line IXB-IXB in FIG. 9A.
- FIG. 13A is a cross-sectional view showing the main part of the semiconductor device (fifth semiconductor device) according to the fifth embodiment
- FIG. 13B is a sectional view of the fifth semiconductor device at the gate extraction region as in FIG. 2B. It is sectional drawing which shows the principal part.
- FIG. 15A is a diagram illustrating the on-state and off-state potentials of the fifth semiconductor device
- FIG. 15B is a diagram illustrating the on-state and off-state potentials of the conventional semiconductor device. “Potential” in the figure indicates potential energy.
- FIG. 16A is a characteristic diagram showing temporal changes in drain-source voltage and output current at turn-on in the fifth semiconductor device
- FIG. 16B shows drain-source voltage and output current at turn-on in the conventional semiconductor device. It is a characteristic view which shows the time change of.
- FIG. 16A is a diagram illustrating the on-state and off-state potentials of the fifth semiconductor device
- FIG. 16B shows drain-source voltage and output current at turn-on in the conventional semiconductor device. It is a characteristic view which shows the time change of.
- FIG. 16A is a diagram illustrating the on-state and off-state potentials of the fifth semiconductor device
- FIG. 16B shows drain-source voltage and output current at turn-on in the conventional semiconductor device. It is a
- FIG. 17A is a cross-sectional view schematically showing the periphery of a channel region and a gate region of an FET (field effect transistor), and FIG. 17B is a diagram showing a potential between the source and drain of the FET before pinching off and when pinching off. It is. “Potential” in the figure indicates potential energy.
- FIG. 18A is a cross-sectional view schematically showing the periphery of the channel region and gate region of SIT (electrostatic induction transistor), and FIG. 18B is a diagram showing the potential between the source and drain of SIT before pinching off and when pinching off. It is. “Potential” in the figure indicates potential energy. It is sectional drawing which shows the principal part of the semiconductor device (6th semiconductor device) which concerns on 6th this Embodiment. It is sectional drawing which shows the principal part of the semiconductor device (7th semiconductor device) which concerns on 7th this Embodiment.
- ⁇ indicating a numerical range is used as a meaning including numerical values described before and after the numerical value as a lower limit value and an upper limit value.
- a semiconductor device includes an n-type semiconductor region 12 (which may be a semiconductor substrate) and a semiconductor region 12 as shown in FIG. N-type high impurity concentration source region 14 formed on one surface side of the semiconductor region 12, n-type drain region 16 formed on the other surface side of the semiconductor region 12, and the source region 14 among the semiconductor regions 12. And a plurality of p-type buried gate regions 18 formed at positions closer to each other. In FIG. 1, the plurality of buried gate regions 18 are electrically connected to a gate electrode (indicated by symbol “G”).
- G gate electrode
- the first semiconductor device 10 ⁇ / b> A is electrically insulated from the source electrode 20 formed at a position corresponding to the source region 14, a drain electrode 22 formed at a position corresponding to the drain region 16, and the source electrode 20.
- a plurality of gate electrodes 24 (see FIG. 2B) for controlling conduction of current flowing between the source electrode 20 and the drain electrode 22.
- the gate electrodes 24 are electrically connected together around the source region 14, for example.
- An n-type high concentration region 25 is formed between the drain region 16 and the drain electrode 22.
- a plurality of p-type gate extraction regions 28 that electrically connect each gate electrode 24 and the buried gate region 18 are formed between each gate electrode 24 and the buried gate region 18. ing. Of the semiconductor region 12, a region between adjacent buried gate regions 18 forms a channel region 30.
- the plurality of buried gate regions 18 are formed so as to extend in the first direction (y direction) and be arranged along a second direction (x direction) orthogonal to the first direction. ing.
- the width Wg of the buried gate region 18 is larger than the width Wp of the first region 36p (which constitutes a superjunction structure 38 described later) and protrudes toward the buried gate region 18 adjacent to each other. It has a shape. That is, the buried gate region 18 has a configuration connected to the upper portion of the first region 36p.
- FIG. 1 shows an example in which the cross-sectional shape of the buried gate region 18 is a flat track shape.
- FIG. 2A shows a cross section taken along line IIA-IIA in FIG. 1
- FIG. 2B shows a cross section taken along line IIB-IIB in FIG. 2A.
- the plurality of buried gate regions 18 are electrically connected to the gate electrode (indicated by symbol “G”) via the gate extraction region 28, and the source region 14 is indicated by the source electrode (indicated by symbol “S”). ) Is electrically connected.
- the channel region 30 extends in the first direction (y direction) and extends in the second direction (x direction) perpendicular to the first direction, like the buried gate region 18 described above. Are arranged along.
- the length Lc of the channel region 30 (length in the third direction (z direction): referred to as channel length Lc) is preferably short.
- the width Wg of the buried gate region 18 is larger than the width Wp of the first region 36p, and both sides of the buried gate region 18 protrude laterally from the first region 36p.
- the channel length Lc is substantially regulated by the thickness tg of the buried gate region 18 and is equal to or shorter than the thickness tg.
- the ratio of the channel length Lc to the thickness La of the semiconductor region 12, that is, (channel length Lc / thickness La of the semiconductor region 12) is 8/100 or less, preferably 1/300 or more and 6/100 or less. It is.
- the source region 14 described above is a single region that extends over the entire surface of one of the semiconductor regions 12 except for the gate extraction region 28 that penetrates the source region 14, as shown in FIGS. 1, 2A, and 2B. Is configured. That is, the source region 14 extends over the adjacent channel region 30.
- a first insulating film 32 such as SiO 2 is interposed between the gate electrode 24 and the source region 14. Further, a source electrode 20 is formed on the entire surface including each gate electrode 24, and second insulation is formed between each gate electrode 24 and the source electrode 20 by, for example, TEOS (Tetra Ethoxy Silane: Si (OC 2 H 5 ) 4 ). A membrane 34 is interposed.
- TEOS Tetra Ethoxy Silane: Si (OC 2 H 5 ) 4
- the first semiconductor device 10A has a superjunction structure 38.
- the superjunction structure 38 includes a plurality of p-type first regions 36p extending from the respective buried gate regions 18 toward the drain region 16, and an n-type second region 36n existing between the first regions 36p.
- preferable impurity concentrations of the source region 14, the drain region 16, the buried gate region 18, and the first region 36p (second region 36n) are as follows.
- the source region 14 is 10 17 cm ⁇ 3 or more and less than 10 21 cm ⁇ 3
- the drain region 16 is 10 17 cm ⁇ 3 or more and less than 10 21 cm ⁇ 3
- the buried gate region 18 is 10 16 cm ⁇ 3 or more and 10 18 cm 3 or more. less than -3
- a first region 36p (second region 36n) is less than 10 15 cm -3 or more 10 18 cm -3.
- the total impurity amount of the first region 36p and the total impurity amount of the second region 36n constituting the superjunction structure 38 are substantially the same.
- the width Wp of the first region 36p constituting the superjunction structure 38 and the width Wn of the second region 36n are equal, the impurity concentration of the first region 36p and the impurity concentration of the second region 36n constituting the superjunction structure 38 are substantially equal.
- “Substantially the same” means that the impurity concentration of the first region 36p is NA, and the impurity concentration of the second region 36n is ND.
- the width Wp of the first region 36p and the width Wn of the second region 36n are substantially the same. “Substantially the same” indicates
- the total amount of impurities in the first region 36p and the total amount of impurities in the second region 36n can be made substantially the same.
- the superjunction structure 38 has a larger aspect ratio.
- the on-resistance for a specific breakdown voltage can be lowered.
- the aspect ratio of the superjunction structure 38 indicates ⁇ length Lsj in the vertical direction (z direction) / (width Wp / 2 + of the first region 36p + width Wn / 2 of the second region 36n) ⁇ .
- the length Lsj in the vertical direction indicates the length from the center position in the thickness direction of the buried gate region 18 to the lower end of the superjunction structure 38.
- the aspect ratio of the super junction structure 38 is 16.5, the widths Wp and Wn of the first region 36p and the second region 36n are 2 ⁇ m, respectively, and the ratio of the channel length Lc to the thickness La of the semiconductor region 12 is 1 /. 300.
- impurity concentration n pil the impurity concentration of the first region 36p and the second region 36n.
- the breakdown voltage is at a high voltage level.
- the impurity concentration n pil is 2 ⁇ 10 16 cm ⁇ 3
- the breakdown voltage is slightly decreased
- the impurity concentration n pil is 3 ⁇ 10 16 cm ⁇ 3 , the breakdown voltage is rapidly decreased.
- the impurity concentration is preferably 6 ⁇ 10 15 cm ⁇ 3 or more and less than 3 ⁇ 10 16 cm ⁇ 3 in order to improve both the on-characteristic and off-characteristic.
- This preferable range is merely an example, and it is obvious that the preferable range of the impurity concentration of the first region 36p also varies if, for example, the required specification of the breakdown voltage is different.
- FIG. 5 shows that the breakdown voltage decreases as the variation in impurity concentration increases.
- the impurity concentration n pil is high, the degree of the decrease is large.
- the decrease in breakdown voltage is less than 50 V, a significant decrease in off characteristics can be avoided. Therefore, the variation in impurity concentration between the first region 36p and the second region 36n
- / ND is 5%
- the following range is preferable.
- “substantially the same” in “the impurity concentration in the first region and the impurity concentration in the second region are substantially the same” indicates that
- the first semiconductor device 10A can improve the on-characteristic and off-characteristic.
- a semiconductor device according to the second embodiment (hereinafter referred to as a second semiconductor device 10B) will be described with reference to FIGS. 6, 7A, and 7B.
- the second semiconductor device 10B has substantially the same configuration as the first semiconductor device 10A described above, but differs in the following points. That is, as shown in FIGS. 6, 7A and 7B, the source region 14 is separated on the buried gate region 18, and each source region 14 is striped on the channel region 30 along the first direction (y direction). It is the form formed in. In other words, at least the extending direction of the source region 14 and the extending direction of the bonding surface (the bonding surface between the first region 36p and the second region 36n) of the superjunction structure 38 are parallel to each other.
- “parallel” includes variations of about 1 ° to 3 °.
- a width substantially the same as the width Wp of the first region 36p for example, (width Wp ⁇ 0.1 ⁇ m) or more (width Wp + 0.1 ⁇ m) or less can be selected.
- the width Ws of the source region 14 it is possible to select substantially the same width as the width Wn of the second region 36n, for example, (width Wn ⁇ 0.1 ⁇ m) or more (width Wn + 0.1 ⁇ m) or less.
- a semiconductor device according to the third embodiment (hereinafter referred to as a third semiconductor device 10C) will be described with reference to FIGS. 8, 9A, and 9B.
- the third semiconductor device 10C has substantially the same configuration as the second semiconductor device 10B described above, but the source region 14 is further separated in an island shape as shown in FIGS. 8, 9A, and 9B. It is different in point.
- FIG. 9A shows an example in which a plurality of island-shaped source regions 14 are arranged in a matrix in the first direction (y direction) and the second direction (x direction).
- the arrangement of the source regions 14 may be a matrix or a staggered arrangement.
- a semiconductor device according to the fourth embodiment (hereinafter referred to as a fourth semiconductor device 10D) will be described with reference to FIG.
- a trench groove 40 reaching the buried gate region 18 is formed on the buried gate region 18 except for the gate extraction region 28. Insulator 42 is filled.
- the source region 14 can be formed in a stripe shape or an island shape by appropriately changing the planar shape of the trench groove 40.
- the gate-source voltage V GS was set to 0.7V.
- the change in the energization current density J D with respect to the drain-source voltage V DS has substantially the same characteristics in the first semiconductor device 10A, the second semiconductor device 10B, and the third semiconductor device 10C. I understand.
- the energization current density J D changes almost linearly, so that the first semiconductor device 10A, the second semiconductor device 10B, and the third semiconductor device 10C have substantially resistance. Can be considered.
- the gate current density J G is increased.
- the planar shape of the source region 14 is a stripe shape, the opposed area between the buried gate region 18 and the source region 14 is smaller than that of the first semiconductor device 10A.
- the effective distance between the buried gate region 18 and the source region 14 is long. As a result, it is considered that the gate current density J G is lower than that of the first semiconductor device 10A.
- the planar shape of the source region 14 is an island shape, and the opposing area between the buried gate region 18 and the source region 14 is narrower than that of the second semiconductor device 10B. It is considered that the gate current density J G is lower than that.
- the gate current continues to flow until the supply of the gate current is stopped.
- the first semiconductor device 10A to the third semiconductor device 10C can be regarded as resistors. Therefore, the amount of heat generated by the gate current (Joule heat) H is I GS , the parasitic resistance component between the gate electrode 24 and the source electrode 20 of the first semiconductor device 10A to the third semiconductor device 10C, and the outside of the gate electrode 24.
- H I GS 2 ⁇ R ⁇ t It becomes. That is, the heat generation amount H is seen to increase in proportion to the square of the gate current I GS.
- the second semiconductor device 10B or the third semiconductor device having a lower gate current density than the first semiconductor device 10A or the third semiconductor device. It can be seen that the semiconductor device 10C is preferably used, and the third semiconductor device 10C is more preferably used.
- the extending direction of the source region 14 and the extending direction of the bonding surface of the superjunction structure 38 are parallel, but they may be perpendicular.
- the vertical includes a variation of about 1 ° to 3 °. In the vertical case, a portion where the source region 14 does not exist on the channel region 30 is generated, so that the channel utilization efficiency is reduced as compared with the parallel case, but there is an advantage that it is advantageous for miniaturization.
- a semiconductor device according to a fifth embodiment (hereinafter referred to as a fifth semiconductor device 10E) will be described with reference to FIGS. 13A and 13B.
- the fifth semiconductor device 10E has substantially the same configuration as the first semiconductor device 10A described above, but differs in that at least the impurity concentration of the buried gate region 18 is high.
- a preferable range of the impurity concentration of the buried gate region 18 is 10 18 cm ⁇ 3 or more and less than 10 21 cm ⁇ 3 .
- the impurity concentration of the source region 14 is a medium level or high level concentration in the above-described preferable range (10 17 cm ⁇ 3 or more and less than 10 21 cm ⁇ 3 ).
- the impurity concentration of the drain region 16 is also a medium level or high level concentration in the above-described preferred range (10 17 cm ⁇ 3 or more and less than 10 21 cm ⁇ 3 ).
- the semiconductor region 12 is n
- the source region 14 is n + (n ++ )
- the drain region 16 is n + (n ++ )
- the buried gate region 18 is p ++
- the gate is extracted.
- the region 28 is denoted by p ++
- the first region 36p constituting the superjunction structure 38 is denoted by p.
- the semiconductor device 100 As shown in FIG. 14, the semiconductor device 100 according to the conventional structure is formed in a columnar shape in which a p-type gate / drift layer 102 is elongated in the vertical direction, and the p-type gate / drift layer 102, the n-type drift layer 104, Thus, the super-junction structure 106 is configured. Further, in this semiconductor device 100, the p-type gate / drift layer 102 also serves as the gate region 108 (see FIG. 3 of JP 2010-045218 A). An n-type source region 110 is formed on the surface of the n-type drift layer 104, and a source electrode 112 is formed in contact with the source region 110.
- n-type drain region 114 is formed on the back surface of the n-type drift layer 104, and a drain electrode 116 is formed in contact with the drain region 114.
- the semiconductor device 100 is characterized in that the length of the channel region 118 (channel length Lc) is increased because the p-type gate / drift layer 102 also serves as the gate region 108.
- the potential barrier 50 formed by the depletion layer is formed in the portion corresponding to the channel region 30.
- the fifth semiconductor device 10E has a channel length Lc shorter than that of the semiconductor device 100, a potential barrier 50 is formed in a narrow range as shown by a solid line L1a in FIG. 15A. (Built-in potential Vbi) increases. As a result, the withstand voltage at the time of OFF becomes high.
- the super junction structure 38 can be formed long in the vertical direction, the effect of the super junction structure 38 can be sufficiently exhibited.
- the potential barrier 50 is lowered and is kept slightly high as shown by the broken line L1b in FIG. 15A.
- the channel length Lc is short, even if the lowered potential barrier 50 is somewhat convex, it is not narrow enough to block the flow of charges. That is, the on-resistance Ron can be lowered.
- FIG. 16A is a characteristic diagram showing temporal changes in the drain-source voltage V DS (see the solid line L1v) and the output current I DS (see the broken line L1i) when the fifth semiconductor device 10E is turned on.
- the current amplification factor hfe can be increased to about 400.
- the channel region 30 causes conductivity modulation. .
- the resistance component of the channel portion is reduced, and the on-resistance is further reduced.
- minority carriers are hardly injected into the super junction structure 38, the turn-off speed does not decrease.
- the fifth semiconductor device 10E can achieve a high breakdown voltage at the time of off and can reduce the on-resistance Ron at the time of on. Further, the switching speed can be increased, and the loss due to switching can be reduced.
- FIG. 16B is a characteristic diagram showing temporal changes in drain-source voltage V DS (see solid line L2v) and output current I DS (see broken line L2i) at turn-on in semiconductor device 100 according to the conventional structure.
- the semiconductor device 100 according to the conventional structure may have a disadvantage that the on-resistance is high at the time of on-state, and the switching speed cannot be increased and the loss due to switching increases. May occur.
- the difference in effect between the above-described fifth semiconductor device 10E and the conventional semiconductor device 100 can also be derived from the difference between an FET (Field Effect Transistor) and an SIT (Static Induction Transistor) (Patent 2050668). Issue (see Japanese Patent Publication No. 28-6077).
- FIG. 17A and 18A are cross-sectional views schematically showing the periphery of the channel region 200 and the gate region 202 of the FET and SIT.
- FIG. 17B and FIG. 18B are diagrams showing the potential between the source and drain of the FET and SIT before pinching off and when pinching off.
- the boundary of the depletion layer 204 before pinching off is indicated by a one-dot chain line
- the boundary of the depletion layer 204 when pinching off is indicated by a two-dot chain line.
- the curve LFa and the curve LFb of FIG. 17B show the potential before the pinch-off and when the pinch-off is performed in the FET
- the curve LSa and the curve LSb of FIG. Indicates potential.
- the potential level Vpb when pinched off is higher than the level Vp before pinching off, and the portion corresponding to the true gate 206 (see FIG. 18A) peaks.
- a potential barrier 208 is formed. Therefore, as compared with the FET, the electrical resistance rs of the channel region 200 can be reduced, the channel length can be shortened, and the on-resistance can be lowered. As a result, the electrostatic induction effect becomes easy to work.
- the comparison between FET and SIT is as described above.
- at least the impurity concentration of the channel region 30 and the buried gate region 18 is increased. Therefore, the electrical resistance of the channel region 30 is further reduced, and the decrease in on-resistance can be further promoted.
- the impurity concentration of the buried gate region 18 is increased in combination with the increase of the impurity concentration of the channel region 30, the gate resistance can be lowered and the gate impedance can be lowered.
- the channel region 30 can be operated evenly (gate low impedance effect).
- the on-resistance is low when conducting, there is an effect that the on-off operation can be performed at high speed.
- a semiconductor device according to a sixth embodiment (hereinafter referred to as a sixth semiconductor device 10F) will be described with reference to FIG.
- the sixth semiconductor device 10F has substantially the same configuration as the fifth semiconductor device 10E described above, but the distance between the upper end of the buried gate region 18 and the lower end of the source region 14 is infinitely 0 mm. It differs in the point close to.
- FIG. 19 shows a state in which the upper end of the buried gate region 18 and the lower end of the source region 14 are in contact with each other.
- the on-resistance can be reduced as the distance between the upper end of the buried gate region 18 and the lower end of the source region 14 becomes as close as possible to 0 mm.
- the sixth semiconductor device 10F has the high-concentration buried gate region 18, a high breakdown voltage at the time of off can be realized and the responsiveness can be improved as in the fifth semiconductor device 10E. .
- the semiconductor device according to the seventh embodiment (hereinafter referred to as the seventh semiconductor device 10G) has substantially the same configuration as the sixth semiconductor device 10F as shown in FIG. The difference is that a low-concentration n-type region or intrinsic semiconductor region 52 is formed from the upper end of 18 to a depth greater than 1/2 of the thickness tg of the buried gate region 18 and 5/6 or less.
- FIG. 20 shows an example in which a low concentration n-type region or intrinsic semiconductor region 52 is formed from the upper end of the buried gate region 18 to a depth of 3/4 of the thickness tg of the buried gate region 18.
- the low-concentration n-type region or intrinsic semiconductor region 52 preferably has an impurity concentration of 10 16 cm ⁇ 3 or less because of the relationship between the impurity concentration of the buried gate region 18 and the source region 14. Further, the low-concentration n-type region or the intrinsic semiconductor region 52 may be an active high-resistance semiconductor layer.
- the depletion layer easily spreads at the time of OFF. Therefore, the breakdown voltage can be further improved and the on-resistance can be reduced. This also leads to faster switching and lower loss.
- the semiconductor device according to the present invention is not limited to the above-described embodiment, and various configurations can be adopted without departing from the gist of the present invention.
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Abstract
Description
|NA-ND|/ND≦5(%)
をいう。これについては後述する。
H=IGS 2・R・t
となる。すなわち、発熱量Hは、ゲート電流IGSの2乗に比例して大きくなることがわかる。
Claims (15)
- 第1導電型の半導体領域(12)と、
前記半導体領域(12)の一方の表面に形成された第1導電型のソース領域(14)と、
前記半導体領域(12)の他方の表面に形成された第1導電型のドレイン領域(16)と、
前記半導体領域(12)のうち、前記ソース領域(14)寄りの位置に形成された第2導電型の複数の埋め込みゲート領域(18)とを有する半導体装置において、
各前記埋め込みゲート領域(18)からそれぞれ前記ドレイン領域(16)に向けて延在する第2導電型の複数の第1領域(36p)と、前記第1領域(36p)間に存する第1導電型の第2領域(36n)とで超接合構造(38)が構成され、
前記第1領域(36P)がp型、前記第2領域(36n)がn型、前記埋め込みゲート領域(18)がp型であり、
前記埋め込みゲート領域(18)は、前記第1領域(36p)の上部に接続された構成を有することを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記埋め込みゲート領域(18)の幅(Wg)が前記第1領域(36p)の幅(Wp)よりも大きく、前記埋め込みゲート領域(18)の両側が前記第1領域(36p)よりも横方向に張り出し、隣接する前記埋め込みゲート領域(18)間のチャネル領域(30)の長さ(Lc)が前記埋め込みゲート領域(18)の厚み(tg)以下であり、
前記ソース領域(14)の不純物濃度が1017cm-3以上1021cm-3未満であり、
前記埋め込みゲート領域(18)の不純物濃度が1018cm-3以上1021cm-3未満であり、前記第1領域(36p)の不純物濃度が1015cm-3以上1018cm-3未満であることを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記埋め込みゲート領域(18)の上端と前記ソース領域(14)の下端とが接触していることを特徴とする半導体装置。 - 請求項3記載の半導体装置において、
前記埋め込みゲート領域(18)の上端から前記埋め込みゲート領域(18)の厚み(tg)の1/2よりも大きく5/6以下の深さにわたって、不純物濃度が1016cm-3以下の低濃度のn型領域、又は真性半導体領域(52)、又は能動的高抵抗半導体層が形成されていることを特徴とする半導体装置。 - 請求項1~4のいずれか1項に記載の半導体装置において、
前記埋め込みゲート領域(18)は、一方向に延在し、且つ、前記一方向と直交する他方向に配列していることを特徴とする半導体装置。 - 請求項5記載の半導体装置において、
前記半導体領域(12)のうち、隣接する前記埋め込みゲート領域(18)間の領域がチャネル領域(30)を構成し、
前記チャネル領域(30)は、前記一方向に沿って延在し、且つ、前記他方向に沿って配列していることを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
前記ソース領域(14)は、隣接する前記チャネル領域(30)にわたって延在していることを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
少なくとも前記ソース領域(14)の延在方向と、前記超接合構造(38)の接合面の延在方向とが平行であることを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
少なくとも前記ソース領域(14)の延在方向と、前記超接合構造(38)の接合面の延在方向とが垂直であることを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
前記ソース領域(14)が分離され、
前記ソース領域(14)は、前記チャネル領域(30)上において、前記一方向に延在し、且つ、前記他方向に配列していることを特徴とする半導体装置。 - 請求項10記載の半導体装置において、
さらに、前記ソース領域(14)は、島状に分離され、
前記島状のソース領域(14)は、前記一方向と前記他方向に配列されていることを特徴とする半導体装置。 - 請求項6~11のいずれか1項に記載の半導体装置において、
前記半導体領域(12)の厚み(La)に対する前記チャネル領域(30)の長さ(Lc)の比が8/100以下であることを特徴とする半導体装置。 - 請求項12記載の半導体装置において、
前記半導体領域(12)の厚み(La)に対する前記チャネル領域(30)の長さ(Lc)の比が1/300以上6/100以下であることを特徴とする半導体装置。 - 請求項1~13のいずれか1項に記載の半導体装置において、
前記第1領域(36p)の幅(Wp)と前記第2領域(36n)の幅(Wn)はほぼ同じであることを特徴とする半導体装置。 - 請求項1~14のいずれか1項に記載の半導体装置において、
前記第1領域(36p)の不純物総量と前記第2領域(36n)の不純物総量はほぼ同じであることを特徴とする半導体装置。
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001196605A (ja) * | 2000-01-12 | 2001-07-19 | Hitachi Ltd | 炭化珪素半導体装置およびそれを用いた電力変換器 |
JP3284120B2 (ja) | 2000-01-12 | 2002-05-20 | 株式会社日立製作所 | 静電誘導トランジスタ |
JP2005005385A (ja) * | 2003-06-10 | 2005-01-06 | Toshiba Corp | 半導体装置 |
JP2010045218A (ja) | 2008-08-13 | 2010-02-25 | Toshiba Discrete Technology Kk | 電力用半導体装置 |
WO2011108768A1 (ja) * | 2010-03-04 | 2011-09-09 | 独立行政法人産業技術総合研究所 | 埋め込みゲート型炭化珪素静電誘導トランジスタおよびその製造方法 |
JP4832723B2 (ja) | 2004-03-29 | 2011-12-07 | 日本碍子株式会社 | 能動的高抵抗半導体層を有する半導体装置 |
JP2012004173A (ja) | 2010-06-14 | 2012-01-05 | Fuji Electric Co Ltd | 超接合半導体装置の製造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4127987B2 (ja) * | 2001-08-23 | 2008-07-30 | 株式会社日立製作所 | 半導体装置 |
JP4085604B2 (ja) * | 2001-08-29 | 2008-05-14 | 株式会社デンソー | 炭化珪素半導体装置の製造方法 |
JP4192469B2 (ja) * | 2001-12-27 | 2008-12-10 | 住友電気工業株式会社 | 接合型電界効果トランジスタ、及び接合型電界効果トランジスタの製造方法 |
DE10317383B4 (de) * | 2003-04-15 | 2008-10-16 | Infineon Technologies Ag | Sperrschicht-Feldeffekttransistor (JFET) mit Kompensationsgebiet und Feldplatte |
JP5196513B2 (ja) * | 2005-03-09 | 2013-05-15 | 独立行政法人産業技術総合研究所 | 炭化珪素トランジスタ装置 |
JP2012204410A (ja) * | 2011-03-23 | 2012-10-22 | Toshiba Corp | 半導体装置およびその製造方法 |
-
2014
- 2014-03-26 WO PCT/JP2014/058677 patent/WO2015145641A1/ja active Application Filing
- 2014-12-26 EP EP14863060.1A patent/EP2963678A4/en not_active Withdrawn
- 2014-12-26 WO PCT/JP2014/084600 patent/WO2015145913A1/ja active Application Filing
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001196605A (ja) * | 2000-01-12 | 2001-07-19 | Hitachi Ltd | 炭化珪素半導体装置およびそれを用いた電力変換器 |
JP3284120B2 (ja) | 2000-01-12 | 2002-05-20 | 株式会社日立製作所 | 静電誘導トランジスタ |
JP2005005385A (ja) * | 2003-06-10 | 2005-01-06 | Toshiba Corp | 半導体装置 |
JP4832723B2 (ja) | 2004-03-29 | 2011-12-07 | 日本碍子株式会社 | 能動的高抵抗半導体層を有する半導体装置 |
JP2010045218A (ja) | 2008-08-13 | 2010-02-25 | Toshiba Discrete Technology Kk | 電力用半導体装置 |
WO2011108768A1 (ja) * | 2010-03-04 | 2011-09-09 | 独立行政法人産業技術総合研究所 | 埋め込みゲート型炭化珪素静電誘導トランジスタおよびその製造方法 |
JP2012004173A (ja) | 2010-06-14 | 2012-01-05 | Fuji Electric Co Ltd | 超接合半導体装置の製造方法 |
Non-Patent Citations (1)
Title |
---|
See also references of EP2963678A4 * |
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