WO2015074432A1 - 具有浮结结构的igbt - Google Patents

具有浮结结构的igbt Download PDF

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Publication number
WO2015074432A1
WO2015074432A1 PCT/CN2014/082808 CN2014082808W WO2015074432A1 WO 2015074432 A1 WO2015074432 A1 WO 2015074432A1 CN 2014082808 W CN2014082808 W CN 2014082808W WO 2015074432 A1 WO2015074432 A1 WO 2015074432A1
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drift region
igbt
floating junction
floating
region
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PCT/CN2014/082808
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English (en)
French (fr)
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曹琳
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西安永电电气有限责任公司
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Publication of WO2015074432A1 publication Critical patent/WO2015074432A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

Definitions

  • the present invention relates to the field of power electronics, and in particular to an IGBT having a floating junction structure. Background technique
  • Insulated Gate Bipolar Transistor is a Darlington structure formed by a combination of a field effect transistor (MOSFET) and a bipolar power transistor (BJT). It has the advantages of high input impedance of MOSFET, simple driving, high switching speed, and BJT current. The advantages of high density, reduced saturation voltage, and strong current handling capability are ideal fully-controlled devices.
  • the new generation of trench gate field termination IGBTs combines the advantages of previous generations of products, using the latest power semiconductor manufacturing process, and its module capacity should have reached 400A-2400A/1200V-6500V, meeting the application requirements of power electronics and power transmission. And is expanding to the application areas of higher power requirements.
  • Japan's Toshiba Corporation Ichiro Omura and others filed a patent in the United States, proposing a prototype of a floating structure.
  • Professor Chen Xingyu of the University of Electronic Science and Technology of China first proposed the introduction of an opposite-doped island structure in the pressure-resistant layer of power devices to solve the relationship between the on-resistance of the power device and the breakdown voltage.
  • Japanese scientist Watam Saitoh et al. prepared Si BL-SBD (p-buried layer) by ion implantation. For the same on-state specific resistance of 29m ⁇ cm2, the breakdown voltage was increased from 230V to 350V in the conventional structure.
  • applying the floating junction structure to the IGBT can meet the high withstand voltage requirements while further reducing the on-state specific resistance and reducing the forward conduction power consumption of the device.
  • the pressure-resistant layer of power semiconductor devices usually adopts a super junction structure, such as a commercial CoolMOSTM.
  • the superjunction structure is a pressure-resistant layer composed of n regions and p regions which alternately exist.
  • the structure is applied with a large reverse bias, the n-column and the p-column are all depleted, and the donor and acceptor ionizations generate positive and negative charges. Since the n-column and the p-column are alternately arranged, the positive electric charge generated by the positive electric charge in the n-column is negatively charged in the p-column, and the positive and negative electric charges are compensated.
  • the equivalent charge density of the drift region is much lower.
  • the positive and negative charges in the withstand voltage layer are completely compensated, similar to the intrinsic. Therefore, even if the doping concentration of the n-column and the p-column is high, a high breakdown voltage can be obtained, and the breakdown voltage is independent of the doping concentration. In the forward conduction, although the current path becomes half, the doping concentration of the drift region (n-column or p-column) is much improved, and the on-resistance is greatly reduced.
  • the prior art super junction structure IGBT has the following disadvantages: (1) The super junction structure is based on the charge compensation principle and requires charge balance, otherwise the device performance is greatly reduced.
  • the column area in the pressure-resistant layer has a large aspect ratio.
  • the high-voltage IGBT chip has a thick withstand voltage layer. Therefore, regardless of the etching epitaxy or the multiple epitaxial implantation process, it is difficult to satisfy the charge balance and the preparation cost is high in the case where the length and the width are relatively large.
  • the PiN diode is parasitic in the super junction structure, which acts as an anti-parallel freewheeling diode during operation.
  • the super-junction structure has a high reverse charge recovery.
  • the n-column and p-column in the super-junction structure are usually very narrow.
  • the lateral pn junction allows the carriers to be quickly discharged, and the reverse recovery is hard.
  • the reverse recovery has a high current peak and a large electromagnetic interference (EMI) noise. And higher power consumption.
  • EMI electromagnetic interference
  • the reverse recovery current is too high to cause a high electromotive force in the circuit inductance. This superimposition of the electromotive force on the power supply not only increases the voltage requirements and cost of the diode and the switching element, but also threatens the diode and the switching device.
  • the present invention provides an IGBT having a floating junction structure, and a floating junction structure designed based on the charge compensation principle is applied to the IGBT to satisfy the high withstand voltage while further reducing the on-state specific resistance and reducing the device positive
  • the guide passes power consumption.
  • An IGBT having a floating junction structure including a drift region, a p-type region and an n-type region above the drift region, a buffer layer under the drift region, and under the buffer layer
  • the injection layer is characterized in that a plurality of floating junctions are formed in the drift region.
  • the floating junction is formed by a method of ion implantation in the drift region.
  • the drift region is n-doped and the floating junction is a p-type floating junction.
  • the plurality of floating junctions are arranged horizontally in the drift region.
  • the buffer layer is an n-type region, and the injection layer is a p-type region.
  • the injection layer is p+ doped.
  • the drift region is n-doped and the floating junction is p+ floating junction.
  • an emitter and a gate are respectively disposed at two ends of the n-type region above the drift region, and a collector is disposed under the injection layer.
  • p+ buried layer is formed by ion implantation to form a floating junction IGBT structure, and the floating junction structure designed by the charge compensation principle is applied in the IGBT drift region, which can ensure the same withstand voltage and improve drift region doping. Concentration, reducing on-resistance and forward voltage drop, reducing power consumption.
  • FIG. 1 is a schematic structural view and an electric field distribution curve of an electric field cut-off type FS-IGBT in the prior art
  • FIG. 2 is a schematic structural view and an electric field distribution curve diagram of a floating junction structure FJ-IGBT according to an embodiment of the present invention
  • FIG. 3 is a schematic view of a strip-like and point-like floating structure according to an embodiment of the present invention.
  • the prior art electric field cut-off type FS-IGBT includes a drift region 3, a p-type region 2 and an n-type region 1 located above the drift region 3, a buffer layer 4 located below the drift region, and a buffer layer.
  • the implant layer 5 under the punch layer 4 further includes an emitter 6 above the n-type region 1, a gate electrode 7, and a collector electrode 8 under the implant layer 5.
  • the drift region 3 is n-doped.
  • the electric field slope in the electric field cut-off type FS-IGBT is inversely proportional to the doping concentration of the n-drift region.
  • the relationship between the breakdown voltage and the on-state specific resistance, the doping concentration of the drift region should not be too large, and the on-state specific resistance is high.
  • the floating junction structure is designed according to the charge compensation principle.
  • the drift region is divided into upper and lower portions. Due to the embedded p-type floating junction, when the collector voltage increases, the depletion region expands from the P-base region to the floating junction.
  • the upper half drift region is completely depleted, it is similar to the junction termination protection ring, and the floating junction and the upper pn junction pass through. , the voltage only increases in the lower half drift region. As the voltage rises further, the depletion region expands from the p+ float junction to the collector until the lower half drift region is also completely depleted.
  • the upper and lower portions of the floating structure drift region respectively form two triangular electric fields, as shown in FIG. 2, effectively reducing the pn junction.
  • the electric field strength Through this method, the voltage withstand capability of the device is greatly improved. If the distribution of the electric field is continuous and the embedded floating junction does not affect the forward current flow. Compared with the conventional structure, the withstand voltage capability will increase by M (the number of drift zones).
  • M the number of drift zones.
  • the relationship between the on-state specific resistance and the withstand voltage also evolves from the original square relationship to the one-way relationship. Under the same pressure layer thickness, the doping concentration can be increased to lower the on-state specific resistance while maintaining the withstand voltage.
  • the electric field is thought to be formed by superposition of electric fields generated by different types of electric charges.
  • the electric field is a vector, and the non-movable negative charge in the floating junction produces an electric field in the upper pn junction opposite to the applied voltage and the pn junction electric field, and the electric field strength at the n junction decreases.
  • ⁇ is the charged plane charge density and srsO is the dielectric constant.
  • the magnitude of the electric field strength at the pn junction is mainly determined by the charge amount of the floating junction layer. Therefore, increasing the doping concentration and width of the floating junction can reduce the electric field strength at the pn junction and improve the withstand voltage capability of the device. Of course, in order to avoid the pinch-off of the conductive channel during the forward conduction, it is necessary to optimize the design and concentration of the floating junction doping.
  • IGBT modules meet most of the requirements of power electronic devices.
  • the turn-on voltage drop is usually large and the power consumption is large.
  • the present invention has the following beneficial effects:
  • p+ buried layer is formed by ion implantation to form a floating junction IGBT structure, and the floating junction structure designed by the charge compensation principle is applied in the IGBT drift region, which can ensure the same withstand voltage and improve drift region doping. Concentration, reducing on-resistance and forward voltage drop, reducing power consumption.

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Abstract

一种具有浮结结构的IGBT，所述IGBT包括漂移区（3）、位于所述漂移区（3）上方的p型区（2）及n型区（1）、位于所述漂移区（3）下方的缓冲层（4）、以及位于所述缓冲层（4）下方的注入层（5），所述漂移区（3）内形成有若干浮结（31）。将电荷补偿原理设计的浮结结构应用在IGBT漂移区中，能保证相同耐压的同时提高漂移区掺杂浓度，降低导通电阻及正向压降，降低功耗。

Description

具有浮结结构的 IGBT
技术领域
本发明涉及电力电子技术领域， 特别是涉及一种具有浮结结构的 IGBT。 背景技术
绝缘栅双极晶体管 （IGBT )是场效应晶体管 （MOSFET )和双极功率晶 体管（BJT )结合形成的达林顿结构， 具有 MOSFET输入阻抗高、 驱动简单、 开关速度高的优点， 又具有 BJT电流密度大、 饱和压降低、 电流处理能力强 的优点， 是比较理想的全控型器件。 新一代沟槽栅场终止型 IGBT综合了前 几代产品的优点， 釆用最新功率半导体制造工艺， 其模块容量应已经达到 400A-2400A/1200V-6500V , 满足电力电子与电力传动领域应用要求， 并正在 向更高功率要求的应用领域拓展。
1996年， 日本东芝公司 Ichiro Omura等人在美国申请专利， 提出了浮结 结构的原型。 2000年， 我国电子科技大学陈星弼教授最先提出在功率器件耐 压层中引入反型岛 （opposite-doped island )结构来解决功率器件导通电阻与 击穿电压之间的关系。 2002年， 日本科学家 Watam Saitoh等人通过离子注入 制备了 Si BL-SBD ( p-buried layer )， 对于同样的通态比电阻 29m Ω .cm2， 击 穿电压由传统结构的 230V提高到 350V。
因此， 将浮结结构应用在 IGBT 中可以满足高耐压要求的同时进一步减 小通态比电阻， 降低器件正向导通功耗。
目前功率半导体器件耐压层通常釆用超结结构， 如商品化 CoolMOSTM。 超结结构（ superjunction )是由交替存在的 n区和 p区所构成的耐压层。 该结 构外加较大反向偏压时， n柱及 p柱将全部耗尽， 施主和受主电离产生出正 电荷及负电荷。 由于 n柱及 p柱交替排列， n柱中正电荷产生的电力线沿横 向大部分终止于 p柱中的负电荷， 正负电荷补偿。 这样整体看来， 漂移区等 效电荷密度降低很多， 理想情况下耐压层中正负电荷完全补偿， 类似于本征。 所以， 即使 n柱及 p柱掺杂浓度很高， 也能得到很高的击穿电压， 击穿电压 与掺杂浓度无关。 正向导通时， 虽然电流通路变为原来一半， 但漂移区 (n柱 或 p柱)掺杂浓度提高很多， 导通电阻大大降低。
现有技术中超结结构 IGBT具有以下缺点： (1) 超结结构基于电荷补偿原理，要求电荷平衡，否则器件性能大大降低。
(2)设计中为了满足高耐压和低通态电阻的要求，要求耐压层中柱区长宽 比很大。 高压 IGBT芯片耐压层很厚， 因此无论釆用刻蚀外延还是多次外延 注入工艺， 在长宽比较大的情况下很难满足电荷平衡且制备成本很高。
(3) 超结结构中寄生着 PiN二极管， 工作中起到反并联续流二极管作用。 正向导通时， 大量过剩载流子储存在 n柱中， 使得超结结构反向恢复电荷很 高。 同时，超结结构中 n柱及 p柱通常很窄，横向 pn结使得载流子迅速排出， 反向恢复较硬， 反向恢复具有较高的电流峰值， 较大的电磁干扰（EMI )噪 声和较高的功耗。 反向恢复电流下降速度过大使得其在电路电感中产生较高 的电动势， 这个电动势叠加到电源上不仅提高了二极管及开关元件对电压的 要求和成本， 同时也对二极管和开关器件产生威胁。
针对这些问题， 目前已经提出了如掺金、 铂或通过辐照来控制载流子寿 命， 减小反向恢复电荷等方法。 但掺杂会破坏电荷平衡， 辐照对器件使用寿 命有较大的影响。 因此， 有人提出在超结 MOSFET中使用肖特基接触来改善 开关特性。 第三代 COOLMOSTM C3系列则通过在内部集成一个 SiC二极管 来改善其反向恢复特性， 取得了较好的效果但增加了制造难度及成本。
因此， 针对上述技术问题， 有必要提供一种具有浮结结构的 IGBT。
发明内容
有鉴于此， 本发明提供了一种具有浮结结构的 IGBT， 将同样基于电荷补 偿原理设计的浮结结构应用在 IGBT 中， 满足高耐压的同时进一步减小通态 比电阻， 降低器件正向导通功耗。
为了实现上述目的， 本发明实施例提供的技术方案如下：
一种具有浮结结构的 IGBT， 所述 IGBT包括漂移区、 位于所述漂移区上 方的 p型区及 n型区、 位于所述漂移区下方的緩冲层、 以及位于所述緩冲层 下方的注入层， 其特征在于， 所述漂移区内形成有若干浮结。
作为本发明的进一步改进，所述浮结在漂移区通过离子注入的方法形成。 作为本发明的进一步改进， 所述漂移区为 n掺杂， 浮结为 p型浮结。 作为本发明的进一步改进， 所述若干浮结水平排列设置于漂移区内。 作为本发明的进一步改进， 所述緩冲层为 n型区， 所述注入层为 p型区。 作为本发明的进一步改进， 所述注入层为 p+掺杂。
作为本发明的进一步改进， 所述漂移区为 n-掺杂， 浮结为 p+浮结。
作为本发明的进一步改进， 所述漂移区上方 n型区两端分别设有发射极 和栅极， 所述注入层的下方设有集电极。
本发明具有以下有益效果：
在 n型 IGBT耐压层中通过离子注入形成 p+埋层，形成浮结 IGBT结构， 将电荷补偿原理设计的浮结结构应用在 IGBT漂移区中， 能保证相同耐压的 同时提高漂移区掺杂浓度， 降低导通电阻及正向压降， 降低功耗。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面 描述中的附图仅仅是本发明中记载的一些实施例， 对于本领域普通技术人员 来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附图。
图 1 为现有技术中电场截止型 FS-IGBT 的结构示意图及电场分布曲线 图；
图 2为本发明一实施方式中浮结结构 FJ-IGBT的结构示意图及电场分布 曲线图；
图 3为本发明一实施方式中条状及点状浮结结构的示意图。
具体实施方式
为了使本技术领域的人员更好地理解本发明中的技术方案， 下面将结合 本发明实施例中的附图， 对本发明实施例中的技术方案进行清楚、 完整地描 述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施 例。 基于本发明中的实施例， 本领域普通技术人员在没有做出创造性劳动前 提下所获得的所有其他实施例， 都应当属于本发明保护的范围。
参图 1所示， 现有技术中电场截止型 FS-IGBT包括漂移区 3、 位于漂移 区 3上方的 p型区 2及 n型区 1、位于漂移区下方的緩冲层 4、 以及位于緩冲 层 4下方的注入层 5， 还包括位于 n型区 1上方的发射极 6、栅极 7和位于注 入层 5下方的集电极 8。 其中， 漂移区 3为 n-掺杂。
电场截止型 FS-IGBT中电场斜率与 n-漂移区掺杂浓度成反比， 综合考虑 击穿电压与通态比电阻之间的关系， 漂移区掺杂浓度不能太大， 通态比电阻 较高。
参图 2所示， 浮结结构按照电荷补偿原理设计， 通过在 n型 IGBT漂移 区 3中嵌入 p型浮结 （埋层） 31， 将漂移区划分成上下两个部分。 由于嵌入 了 p型浮结， 集电极电压增加时， 耗尽区由 P-基区向浮结扩展， 上半漂移区 完全耗尽时， 类似于结终端保护环， 浮结与上部 pn结穿通， 电压只在下半漂 移区增加。 随着电压进一步上升， 耗尽区由 p+浮结向集电极扩展， 直到下半 漂移区也完全耗尽。
与电场截止型 IGBT漂移区形成一个三角形电场相比， 如图 1所示， 浮 结结构漂移区的上下两部分分别形成了两个三角形的电场， 如图 2所示， 有 效的降低了 pn结处电场强度。 通过这个方法， 器件耐压能力大大提高。 如果 电场的分布是连续的且嵌入的浮结不会影响正向电流流通。与传统结构相比， 耐压能力将有 M (漂移区个数）倍提高。 通态比电阻与耐压的关系也由原来 的平方关系演变为一次方关系。 同样的耐压层厚度下， 可以增加掺杂浓度来 降低通态比电阻而保持耐压不变。
反向电压增加时， 漂移区及埋层中电子和空穴分别被发射极和集电极抽 走， 留下不可移动的正电荷与负电荷。 这里认为电场是由不同类型电荷产生 电场叠加而形成的。 电场是矢量， 浮结中不可移动负电荷在上部 pn结产生电 场方向与外加电压及 pn结电场方向相反， n结处电场强度降低。
通常有两种类型的浮结， 条状和点状， 其浮结结构示意图参图 3所示。 通过高斯定律可以计算出点状浮结及条状浮结电场分布， 然而， 由于所 有浮结都对空间中电场有贡献， 很难对其进行准确的计算。 为了计算简单， 从宏观上看， 这里将浮结层看做一个电荷均匀分布的带电平面， 电场与平面 垂直， 强度与距离无关， 其大小可以计算为：
Figure imgf000005_0001
其中 σ为带电平面电荷密度， srsO为介电常数。
可以看出， pn结处电场强度减弱大小主要取决于浮结层带电量。 因此， 提高浮结掺杂浓度及宽度可以降低 pn结处电场强度， 提高器件耐压能力。 然 而， 设计中为了避免正向导通时导电沟道被夹断， 需要对浮结掺杂浓度及宽 度进行优化设计。
目前， IGBT模块满足电力电子装置的绝大部分要求。然而对于高压 IGBT 模块， 导通压降通常较大， 功耗大。
由以上技术方案可以看出， 本发明具有以下有益效果：
在 n型 IGBT耐压层中通过离子注入形成 p+埋层，形成浮结 IGBT结构， 将电荷补偿原理设计的浮结结构应用在 IGBT漂移区中， 能保证相同耐压的 同时提高漂移区掺杂浓度， 降低导通电阻及正向压降， 降低功耗。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节， 而且在不背离本发明的精神或基本特征的情况下， 能够以其他的具体形式实 现本发明。 因此， 无论从哪一点来看， 均应将实施例看作是示范性的， 而且 是非限制性的， 本发明的范围由所附权利要求而不是上述说明限定， 因此旨 在将落在权利要求的等同要件的含义和范围内的所有变化嚢括在本发明内。 不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
此外， 应当理解， 虽然本说明书按照实施方式加以描述， 但并非每个实 施方式仅包含一个独立的技术方案， 说明书的这种叙述方式仅仅是为清楚起 见， 本领域技术人员应当将说明书作为一个整体， 各实施例中的技术方案也 可以经适当组合， 形成本领域技术人员可以理解的其他实施方式。

Claims

权 利 要 求
1、 一种具有浮结结构的 IGBT， 所述 IGBT包括漂移区、 位于所述漂移 区上方的 p型区及 n型区、 位于所述漂移区下方的緩冲层、 以及位于所述緩 冲层下方的注入层， 其特征在于， 所述漂移区内形成有若干浮结。
2、 根据权利要求 1所述的具有半超结结构的 IGBT， 其特征在于， 所述 浮结在漂移区通过离子注入的方法形成。
3、 根据权利要求 1所述的具有半超结结构的 IGBT， 其特征在于， 所述 漂移区为 n掺杂， 浮结为 p型浮结。
4、 根据权利要求 1所述的具有半超结结构的 IGBT， 其特征在于， 所述 若干浮结水平排列设置于漂移区内。
5、 根据权利要求 1所述的具有半超结结构的高压 IGBT， 其特征在于， 所述緩冲层为 n型区， 所述注入层为 p型区。
6、 根据权利要求 5所述的具有半超结结构的高压 IGBT， 其特征在于， 所述注入层为 p+掺杂。
7、 根据权利要求 3所述的具有半超结结构的高压 IGBT， 其特征在于， 所述漂移区为 n-掺杂， 浮结为 p+浮结。
8、 根据权利要求 1所述的具有半超结结构的高压 IGBT， 其特征在于， 所述漂移区上方 n型区两端分别设有发射极和栅极， 所述注入层的下方设有 集电极。
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