WO2015139311A1 - 一种功率放大电路及发射机 - Google Patents

一种功率放大电路及发射机 Download PDF

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Publication number
WO2015139311A1
WO2015139311A1 PCT/CN2014/073883 CN2014073883W WO2015139311A1 WO 2015139311 A1 WO2015139311 A1 WO 2015139311A1 CN 2014073883 W CN2014073883 W CN 2014073883W WO 2015139311 A1 WO2015139311 A1 WO 2015139311A1
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WIPO (PCT)
Prior art keywords
oxide semiconductor
metal oxide
power amplifier
capacitor
semiconductor capacitor
Prior art date
Application number
PCT/CN2014/073883
Other languages
English (en)
French (fr)
Inventor
张小敏
黄安
焦留彦
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201480000696.6A priority Critical patent/CN105308858B/zh
Priority to EP14886265.9A priority patent/EP3113360A4/en
Priority to JP2017500109A priority patent/JP6478253B2/ja
Priority to PCT/CN2014/073883 priority patent/WO2015139311A1/zh
Publication of WO2015139311A1 publication Critical patent/WO2015139311A1/zh
Priority to US15/270,954 priority patent/US9866181B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
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    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
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    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
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    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H03F2200/222—A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
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    • H03F2200/387—A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
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    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a power amplifying circuit and a transmitter. Background technique
  • the power amplifier circuit is an important component of the transmitter in the communication system.
  • the power amplifier circuit mainly includes an input matching network, a power amplifier tube and an output matching network.
  • An existing power amplifier tube is shown in FIG. 2, and the power amplifier tube is connected to the input matching network and the output matching network through the package pins.
  • the internal structure is shown in Figure 3. It consists of a power amplifier die die (usually an active device, the core part of power amplification) and a metal oxide semiconductor capacitor Moscap.
  • LB0, LB1 and LB2 are bonding wires for connecting separate components, which refer to metal bonding wires connecting two separate components, usually gold wire or aluminum wire, which are often used inside the device.
  • bonding line LB0 is specifically used to connect the gate of the power amplifier die die and the input pin of the power amplifier tube
  • bonding line LB1 is specifically used to connect the drain of the power die die die and Metal oxide semiconductor capacitor Moscap
  • bonding wire LB2 is specifically used to connect the drain of the power amplifier die die and the output pin of the power amplifier tube.
  • Ropt is the output impedance of the power amplifier die die
  • Cds is the parasitic between the drain and the source of the power die die die. capacitance.
  • the low-frequency resonant circuit at the output end is composed of a power amplifier tube, an output matching network, and a grounded back-end network connected to the output of the output matching network. The inductance and capacitance in the low-frequency resonant circuit at the output determine the low-frequency resonant frequency. If the inductance is large, Causes the low frequency resonant frequency to be low.
  • the low frequency resonant frequency of the power amplifying circuit of the transmitter is not desirable for the low frequency resonant frequency of the power amplifying circuit of the transmitter to be low.
  • the signals are modulated wideband signal, the modulated signal into a radio frequency signal through the transmission
  • the power amplifier circuit in the machine is transmitted.
  • the RF power amplification link DPD (Digital Pre-Distortion) correction is required.
  • the impedance of the envelope signal of the radio frequency signal at the output end of the power amplifying circuit changes greatly, and the characteristic of the power amplifying circuit changes greatly at different times, based on the DPD.
  • Embodiments of the present invention provide a power amplifying circuit and a transmitter for improving a low frequency resonant frequency of a power amplifying circuit.
  • a power amplifying circuit including a power amplifier die, a first metal oxide semiconductor capacitor, a DC decoupling capacitor, and an output matching network, wherein:
  • a drain of the power amplifier die is connected to a first end of the first metal oxide semiconductor capacitor through a bonding wire, and a second end of the first metal oxide semiconductor capacitor is grounded;
  • the drain of the power amplifier die is directly connected to the output matching network through a bonding wire; the source of the power amplifier die is grounded;
  • the first end of the first metal oxide semiconductor capacitor is connected to one end of the DC decoupling capacitor through a bonding wire;
  • the other end of the DC decoupling capacitor is grounded.
  • the first end of the first metal oxide semiconductor capacitor is specifically connected to the microstrip line on the printed circuit board where the power amplifier circuit is located through a bonding wire.
  • the microstrip line connects one end of the DC decoupling capacitor.
  • the first end of the first metal oxide semiconductor capacitor is specifically connected to the power through a bonding wire A microstrip line between the first metal oxide semiconductor capacitor and the output matching network on a printed circuit board on which the amplifying circuit is located.
  • the first end of the first metal oxide semiconductor capacitor is specifically connected to the power through a bonding wire A microstrip line on a side of the first metal oxide semiconductor capacitor on the printed circuit board on which the amplifying circuit is located.
  • the first end of the first metal oxide semiconductor capacitor is specifically connected to the power through a bonding wire
  • the output on the printed circuit board on which the amplifier circuit is located matches the microstrip line on the side of the network.
  • the input matching network is further included, and the gate of the power amplifier die is directly connected to the input matching network through a bonding line.
  • the first possible implementation of the first aspect, the second possible implementation of the first aspect, the third possible implementation of the first aspect, the fourth possible The implementation manner is the fifth possible implementation manner of the first aspect, or the sixth possible implementation manner of the first aspect.
  • the DC decoupling capacitor is specifically a nano-level capacitor. Or micro-level capacitors.
  • a transmitter including any of the power amplifying circuits described above.
  • the inductance in the low frequency resonant circuit at the output end of the power amplifying circuit is reduced by increasing the DC decoupling capacitance, and thus the solution provided by the embodiment of the present invention is used.
  • Able to increase the low frequency resonance frequency of the power amplifying circuit and Compared to the prior art, packaging the power amplifier die and the first metal oxide semiconductor capacitor can make the circuit design more flexible.
  • FIG. 1 is a schematic diagram of a power amplifying circuit in the prior art
  • FIG. 2 is a schematic view showing the appearance of a power amplifier tube in the prior art
  • FIG. 3 is a schematic view showing the internal structure of a power amplifier tube in the prior art
  • FIG. 4 is an equivalent circuit diagram of an output end of a power amplifying circuit in the prior art
  • FIG. 5 is a schematic diagram of a power amplifying circuit according to Embodiment 1 of the present invention.
  • FIG. 6 is a schematic diagram of an equivalent circuit of an output end of a power amplifying circuit according to Embodiment 1 of the present invention
  • FIG. 7 is a schematic diagram of a printed circuit board in which a power amplifying circuit according to Embodiment 1 of the present invention is located
  • FIG. 8 is an embodiment of the present invention.
  • 1 is a schematic diagram of a printed circuit board in which a power amplifying circuit is provided.
  • FIG. 9 is a schematic diagram of a printed circuit board in which a power amplifying circuit according to Embodiment 1 of the present invention is located.
  • FIG. 10 is a power amplifying circuit according to Embodiment 1 of the present invention. The fourth of the printed circuit board is located;
  • FIG. 11 is a schematic diagram of a power amplifying circuit according to Embodiment 2 of the present invention.
  • Figure 12 is a schematic diagram of a power amplifying circuit according to Embodiment 3 of the present invention. detailed description
  • the embodiment of the present invention provides a power amplifying circuit and a transmitter.
  • a preferred embodiment of the present invention will be described with reference to the accompanying drawings. It is understood that the preferred embodiments described herein are only The invention is illustrated and described, and is not intended to limit the invention. And in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.
  • Embodiment 1 of the present invention provides a power amplifying circuit, as shown in FIG. 5, including a power amplifier die die, a first metal oxide semiconductor capacitor Moscap 1, a DC decoupling capacitor CLF, and an output matching network, wherein:
  • the drain of the power die die die is connected to the first end of the first metal oxide semiconductor capacitor Moscap 1 through the bonding line LB1, and the second end of the first metal oxide semiconductor capacitor Moscap 1 is grounded; the drain of the power die die die passes The bonding line LB2 is directly connected to the output matching network; the source of the power amplifier die is grounded;
  • the first metal oxide semiconductor capacitor has a first end of the Moscapl connected to one end of the DC decoupling capacitor CLF through a bonding line LB3;
  • the other end of the DC decoupling capacitor CLF is grounded.
  • the DC decoupling capacitor CLF may be a nano-level capacitor, preferably a micro-level capacitor. In practical applications, the DC decoupling capacitor CLF has a larger value. The specific value can be selected according to the bandwidth lower limit value of the envelope signal of the radio frequency signal. The lower the bandwidth lower limit value of the envelope signal of the radio frequency signal, the DC decoupling The capacitance CLF needs to be larger.
  • the power amplifying circuit may further comprise an input matching network, and the gate of the power amplifier die die is directly connected to the input matching network through the bonding line LB4.
  • Ropt is the output impedance of the power amplifier die die
  • Cds is the parasitic capacitance between the drain and the source of the power die die.
  • the output matching network is directly connected through the bonding die through the bonding die. That is, in the power amplifying circuit provided by the embodiment 1 of the present invention, the devices are not packaged, and the specific components of each device may be performed according to the field requirements of the actual application scenario. Select to make the circuit design more flexible. Also, the circuit cost is reduced.
  • the power amplifying circuit provided in Embodiment 1 of the present invention is applied to a 3G network and a 4G network, Increasing the low-frequency resonant frequency can make the impedance change of the envelope signal smaller, that is, the memory effect is small, thereby improving the DPD correction effect and expanding the signal bandwidth of the power amplifying circuit.
  • the first end of the first metal oxide semiconductor capacitor Moscap1 in the power amplifying circuit provided by Embodiment 1 of the present invention may be specifically connected to the microstrip line on the printed circuit board where the power amplifying circuit is located through the bonding line LB3.
  • the microstrip line is connected to one end of the DC decoupling capacitor CLF.
  • 701 is a power die die die
  • 702 is a first metal oxide semiconductor capacitor Moscapl
  • 703 is a bonding wire (the first bonding wire, the second bonding wire, and the third are not distinguished here).
  • 704 is the DC decoupling capacitor CLF
  • 705 is the output matching network.
  • the first end of the first metal oxide semiconductor capacitor Moscapl 702 is specifically connected to the power amplifying circuit through a bonding wire.
  • the first end of the first metal oxide semiconductor capacitor Moscapl 702 is specifically connected to the side of the first metal oxide semiconductor capacitor Moscapl 702 on the printed circuit board where the power amplifier circuit is located through a bonding wire.
  • the microstrip line 800 has a microstrip line 800 on the side of the first metal oxide semiconductor capacitor Moscapl 702 connected to one end of the DC decoupling capacitor CLF 704.
  • the first metal oxide semiconductor capacitor Moscapl 702 is connected above the first metal oxide semiconductor capacitor Moscapl 702 through a bonding wire. In other examples, the first metal oxide semiconductor capacitor Moscapl 702 passes The microstrip line connected to the bonding wire may also be located under the first metal oxide semiconductor capacitor Moscapl 702, or other side.
  • the first end of the first metal oxide semiconductor capacitor Moscapl 702 is specifically connected to the side of the output matching network 705 on the printed circuit board where the power amplifying circuit is located through a bonding wire.
  • the line i.e., the microstrip line 900 in FIG. 9, the microstrip line 1000 in FIG. 10
  • the microstrip line on the side of the output matching network 705 is connected to one end of the DC decoupling capacitor CLF 704.
  • the first metal oxide semiconductor capacitor Moscapl 702 is connected to the microstrip through a bonding wire.
  • the lines are all above the output matching network 705.
  • the microstrip lines of the first metal oxide semiconductor capacitor Moscapl 702 connected by bonding wires may also be located below the output matching network 705, or other sides.
  • the schemes of Figures 7-10 are merely examples and are not intended to limit the invention.
  • the first end of the first metal oxide semiconductor capacitor Moscapl 702 can also be specifically connected to the microstrip line at other positions on the printed circuit board where the power amplifying circuit is located through the bonding line, and connected to the DC through the microstrip line at other positions.
  • the power amplifying circuit provided in the above embodiment 1 can also be modified, and is within the scope of the present invention, such as the following embodiment 2.
  • Embodiment 2 of the present invention further provides a power amplifying circuit.
  • the power amplifying circuit provided in Embodiment 1 further includes a second metal oxide semiconductor capacitor Moscap2, and the power amplifier die die The drain is directly connected to the output matching network through two bonding wires LB2 and LB5, and the terminal between the two bonding wires LB2 and LB5 is connected to the first end of the second metal oxide semiconductor capacitor Moscap2, and the second metal oxide semiconductor capacitor Moscap2 The second end is grounded.
  • the drain of the power die die die is connected to the first end of the second metal oxide semiconductor capacitor Moscap2 through the bonding line LB2, and the first end of the second metal oxide semiconductor capacitor Moscap2 is connected to the output matching network through the bonding line LB2.
  • the power amplifying circuit provided in Embodiment 2 of the present invention adds a primary metal oxide semiconductor capacitor to the power amplifying circuit provided in the above Embodiment 1 to change the matching impedance of the output terminal.
  • a multi-level metal oxide semiconductor capacitor can also be added.
  • Embodiment 3 of the present invention further provides a power amplifying circuit, wherein the power amplifying circuit is in the above Embodiment 1 or Embodiment 2 may further include a drain bias circuit connected to the output matching network.
  • the low frequency resonant circuit is composed of a power amplifier die, a metal oxide semiconductor capacitor, a DC decoupling capacitor, an output matching network, and a grounded back-end network connected to the output of the output matching network.
  • the low-frequency resonant circuit has a long line; when the output matching network is connected to the drain bias circuit, the low-frequency resonant circuit is composed of a power amplifier die, a metal oxide semiconductor capacitor, a DC decoupling capacitor, an output matching network, and a drain bias circuit, that is, Through the drain bias circuit, the length of the low-frequency resonant circuit line is shortened, that is, the inductance in the low-frequency resonant circuit is further reduced, the low-frequency resonant frequency is improved, and the performance index of the output end of the power amplifying circuit can be improved.
  • the power amplifying circuit provided in Embodiment 3 of the present invention may further include a gate bias circuit connected to the input matching network, which can improve the performance index of the input end of the power amplifying circuit.
  • the power amplifying circuit shown in FIG. 12 is a specific example of the power amplifying circuit provided in Embodiment 3 of the present invention.
  • CLF is a DC decoupling capacitor
  • CRF is a radio frequency bypass capacitor.
  • Embodiment 4 of the present invention provides a transmitter comprising the power amplifying circuit shown in any of the above embodiments.
  • the scheme provided by the embodiment of the present invention can improve the low frequency resonance frequency of the power amplifying circuit, and the circuit design is flexible and the cost is low.

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Abstract

一种能够提高低频谐振频率、设计更加灵活的功率放大电路，该功率放大电路包括功放管芯（die）、第一金属氧化物半导体电容（Moscap1）、直流去耦电容（CLF）和输出匹配网络，其中：该功放管芯（die）的漏极通过邦定线（LB1）连接第一金属氧化物半导体电容（Moscap1）的第一端，该第一金属氧化物半导体电容（Moscap1）的第二端接地；该功放管芯（die）的漏极通过邦定线（LB2）直接连接输出匹配网络；该功放管芯（die）的源极接地；该第一金属氧化物半导体电容（Moscap1）的第一端通过邦定线（LB3）连接该直流去耦电容（CLF）的一端；该直流去耦电容（CLF）的另一端接地。

Description

一种功率放大电路及发射机
技术领域
本发明涉及通信技术领域， 特别涉及一种功率放大电路及发射机。 背景技术
功率放大电路是通信系统中发射机的一个重要组成部分， 如图 1 所示， 功率放大电路主要包括输入匹配网络、 功放管和输出匹配网络三部分。 现有 的一种功放管如图 2所示， 功放管通过封装管脚来连接输入匹配网络和输出 匹配网络。 其内部具体结构如图 3所示， 包括封装在一起的功放管芯 die (通 常为有源器件， 功率放大的核心部分）和金属氧化物半导体电容 Moscap。 图 3中 LB0、 LBl和 LB2为用于连接分离部件的邦定线 (bonding wire, 指的是连 接两个分离的部件的金属键合线， 通常为金丝或者铝丝， 在器件内部经常用 到， 在 10G以下表现为电感特性）， 其中邦定线 LB0具体用于连接功放管芯 die的栅极和功放管输入管脚， 邦定线 LB1具体用于连接功放管芯 die的漏极 和金属氧化物半导体电容 Moscap, 邦定线 LB2具体用于连接功放管芯 die的 漏极和功放管输出管脚。
图 4为釆用图 3所示功放管的功率放大电路的输出端的等效电路， Ropt 为功放管芯 die工作时的输出阻抗， Cds为功放管芯 die的漏极和源极之间的 寄生电容。 输出端的低频谐振回路由功放管、 输出匹配网络以及输出匹配网 络输出端连接的接地的后端网络构成， 输出端的低频谐振回路中的电感和电 容决定了低频谐振频率， 若电感较大， 则会导致低频谐振频率较低。
而在目前的很多通信网络中， 不希望发射机的功率放大电路的低频谐振 频率较低。 例如在 3G(3M generation , 第三代移动通信技术）网络和 4G(4th generation, 第四代移动通信技术)网络中， 调制信号均为宽带信号， 该调制信 号转换为射频信号后通过发射机中的功率放大电路发射出去。 为保证网络中 的邻道干扰 ( adjacent channel interference )符合协议要求， 射频功率放大链路 需要进行 DPD ( Digital Pre-Distortion, 数字预失真）校正。 若功率放大电路 的低频谐振频率较低， 则会导致射频信号的包络信号在功率放大电路输出端 的阻抗变化较大，进而导致功率放大电路在不同时刻特性变化较大，基于 DPD
影响了功率放大电路的可支持信号带宽。
因此， 如何提高功率放大电路的低频谐振频率越来越成为现代技术研究 的热点。 发明内容
本发明实施例提供一种功率放大电路及发射机， 用以提高功率放大电路 的低频谐振频率。
第一方面， 提供一种功率放大电路， 包括功放管芯、 第一金属氧化物半 导体电容、 直流去耦电容和输出匹配网络， 其中：
所述功放管芯的漏极通过邦定线连接所述第一金属氧化物半导体电容的 第一端， 所述第一金属氧化物半导体电容的第二端接地；
所述功放管芯的漏极通过邦定线直接连接所述输出匹配网络； 所述功放 管芯的源极接地；
所述第一金属氧化物半导体电容的第一端通过邦定线连接所述直流去耦 电容的一端；
所述直流去耦电容的另一端接地。
结合第一方面， 在第一种可能的实现方式中， 所述第一金属氧化物半导 体电容的第一端， 具体通过邦定线连接至功率放大电路所在的印刷电路板上 的微带线， 所述微带线连接所述直流去耦电容的一端。
结合第一方面， 或者第一方面的第一种可能的实现方式， 在第二种可能 的实现方式中， 所述第一金属氧化物半导体电容的第一端， 具体通过邦定线 连接至功率放大电路所在的印刷电路板上所述第一金属氧化物半导体电容和 所述输出匹配网络之间的微带线。 结合第一方面， 或者第一方面的第一种可能的实现方式， 在第三种可能 的实现方式中， 所述第一金属氧化物半导体电容的第一端， 具体通过邦定线 连接至功率放大电路所在的印刷电路板上所述第一金属氧化物半导体电容侧 面的微带线。
结合第一方面， 或者第一方面的第一种可能的实现方式， 在第四种可能 的实现方式中， 所述第一金属氧化物半导体电容的第一端， 具体通过邦定线 连接至功率放大电路所在的印刷电路板上所述输出匹配网络侧面的微带线。
结合第一方面， 第一方面的第一种可能的实现方式， 第一方面的第二种 可能的实现方式， 第一方面的第三种可能的实现方式， 或者第一方面的第四 种可能的实现方式， 在第五种可能的实现方式中， 还包括输入匹配网络， 所 述功放管芯的栅极通过邦定线直接连接所述输入匹配网络。
结合第一方面， 第一方面的第一种可能的实现方式， 第一方面的第二种 可能的实现方式， 第一方面的第三种可能的实现方式， 第一方面的第四种可 能的实现方式， 或者第一方面的第五种可能的实现方式， 在第六种可能的实 现方式中， 还包括至少一个第二金属氧化物半导体电容， 所述功放管芯的漏 极具体通过两段邦定线直接连接所述输出匹配网络， 所述两段邦定线之间的 接线端连接所述第二金属氧化物半导体电容的第一端， 所述第二金属氧化物 半导体电容的第二端接地。
结合第一方面， 第一方面的第一种可能的实现方式， 第一方面的第二种 可能的实现方式， 第一方面的第三种可能的实现方式， 第一方面的第四种可 能的实现方式， 第一方面的第五种可能的实现方式， 或者第一方面的第六种 可能的实现方式， 在第七种可能的实现方式中， 所述直流去耦电容具体为纳 法级电容或微法级电容。
第二方面， 提供一种发射机， 包括上述任一功率放大电路。
根据第一方面提供的功率放大电路或第二方面提供的发射机， 通过增加 直流去耦电容， 减小了功率放大电路输出端的低频谐振回路中的电感， 因此 釆用本发明实施例提供的方案能够提高功率放大电路的低频谐振频率， 并且， 相比于现有技术， 不对功放管芯和第一金属氧化物半导体电容进行封装， 能 够使电路设计更加灵活。 附图说明
附图用来提供对本发明的进一步理解， 并且构成说明书的一部分， 与本 发明实施例一起用于解释本发明， 并不构成对本发明的限制。 在附图中： 图 1为现有技术中的功率放大电路的示意图；
图 2为现有技术中的功放管的外观示意图；
图 3为现有技术中的功放管的内部结构示意图；
图 4为现有技术中的功率放大电路的输出端的等效电路示意图； 图 5为本发明实施例 1提供的功率放大电路的示意图；
图 6为本发明实施例 1提供的功率放大电路的输出端的等效电路示意图； 图 7为本发明实施例 1提供的功率放大电路所在的印制电路板的示意之 图 8为本发明实施例 1提供的功率放大电路所在的印制电路板的示意之 图 9为本发明实施例 1提供的功率放大电路所在的印制电路板的示意之 图 10为本发明实施例 1提供的功率放大电路所在的印制电路板的示意之 四；
图 11为本发明实施例 2提供的功率放大电路的示意图；
图 12为本发明实施例 3提供的功率放大电路的示意图。 具体实施方式
为了给出能够提高低频谐振频率、 设计更加灵活的功率放大电路的实现 方案， 本发明实施例提供了一种功率放大电路及发射机， 以下结合说明书附 图对本发明的优选实施例进行说明， 应当理解， 此处所描述的优选实施例仅 用于说明和解释本发明， 并不用于限定本发明。 并且在不冲突的情况下， 本 申请中的实施例及实施例中的特征可以相互组合。
实施例 1 :
本发明实施例 1提供了一种功率放大电路， 如图 5所示， 包括功放管芯 die、 第一金属氧化物半导体电容 Moscap 1、 直流去耦电容 CLF和输出匹配网 络， 其中：
功放管芯 die 的漏极通过邦定线 LB1 连接第一金属氧化物半导体电容 Moscap 1的第一端， 第一金属氧化物半导体电容 Moscap 1的第二端接地； 功放管芯 die的漏极通过邦定线 LB2直接连接输出匹配网络； 功放管芯 die的源极接地；
第一金属氧化物半导体电容 Moscapl的第一端通过邦定线 LB3连接直流 去耦电容 CLF的一端；
直流去耦电容 CLF的另一端接地。
上述直流去耦电容 CLF可以为纳法级电容，较佳的，可以为微法级电容。 实际应用中， 直流去耦电容 CLF容值越大越好， 具体可以根据射频信号的包 络信号的带宽下限值来进行选择， 射频信号的包络信号的带宽下限值越小， 直流去耦电容 CLF容值需要越大。
进一步的， 该功率放大电路还可以包括输入匹配网络， 功放管芯 die的栅 极通过邦定线 LB4直接连接该输入匹配网络。
图 6为图 5所示的功率放大电路的输出端的等效电路， Ropt为功放管芯 die工作时的输出阻抗， Cds为功放管芯 die的漏极和源极之间的寄生电容。
可见相比于现有技术， 通过增加直流去耦电容 CLF, 能够减小输出端的 低频谐振回路中的电感， 因此能够提高功率放大电路的低频谐振频率。 并且， 通过功放管芯 die通过邦定线直接连接输出匹配网络，即本发明实施例 1提供 的功率放大电路中， 不对各器件进行封装， 可以根据实际应用场景的现场需 求来进行各器件的具体选择， 使电路设计更加灵活。 并且， 降低了电路成本。
本发明实施例 1提供的功率放大电路应用在 3G网络和 4G网络中， 通过 提高低频谐振频率， 能够使包络信号的阻抗变化较小， 即记忆效应较小， 进 而提高 DPD校正效果， 扩展了功率放大电路的信号带宽。
具体实施时， 本发明实施例 1 提供的功率放大电路中第一金属氧化物半 导体电容 Moscapl的第一端， 具体可以通过邦定线 LB3连接至功率放大电路 所在的印刷电路板上的微带线， 该微带线连接直流去耦电容 CLF的一端。 从 而实现了第一金属氧化物半导体电容 Moscapl和直流去耦电容 CLF的连接。
具体可以如图 7所示， 701为功放管芯 die, 702为第一金属氧化物半导 体电容 Moscapl , 703为邦定线（此处不区分第一绑定线、 第二绑定线和第三 绑定线， 均称为邦定线）， 704为直流去耦电容 CLF, 705为输出匹配网络， 第一金属氧化物半导体电容 Moscapl 702的第一端， 具体通过邦定线连接至 功率放大电路所在的印刷电路板上第一金属氧化物半导体电容 Moscapl 702 和输出匹配网络 705 之间的微带线 700 , 该第一金属氧化物半导体电容 Moscapl 702和输出匹配网络 705之间的微带线 700连接直流去耦电容 CLF 704的一端。
具体也可以如图 8所示， 第一金属氧化物半导体电容 Moscapl 702的第 一端， 具体通过邦定线连接至功率放大电路所在的印刷电路板上第一金属氧 化物半导体电容 Moscapl 702侧面的微带线 800,该第一金属氧化物半导体电 容 Moscapl 702侧面的微带线 800连接直流去耦电容 CLF 704的一端。在图 8 中， 第一金属氧化物半导体电容 Moscapl 702通过邦定线连接的微带线位于 第一金属氧化物半导体电容 Moscapl 702上方， 在其它示例中， 第一金属氧 化物半导体电容 Moscapl 702通过邦定线连接的微带线也可以位于第一金属 氧化物半导体电容 Moscapl 702下方， 或者其它侧面。
具体也可以如图 9或图 10所示，第一金属氧化物半导体电容 Moscapl 702 的第一端， 具体通过邦定线连接至功率放大电路所在的印刷电路板上输出匹 配网络 705侧面的微带线（即图 9中的微带线 900、 图 10中的微带线 1000 ), 该输出匹配网络 705侧面的微带线连接直流去耦电容 CLF 704的一端。在图 9 或图 10中， 第一金属氧化物半导体电容 Moscapl 702通过邦定线连接的微带 线均位于输出匹配网络 705上方， 在其它示例中， 第一金属氧化物半导体电 容 Moscapl 702通过邦定线连接的微带线也可以位于输出匹配网络 705下方， 或者其它侧面。
图 7-图 10方案仅为示例， 并不用于限定本发明。 第一金属氧化物半导体 电容 Moscapl 702的第一端， 也可以通过邦定线具体连接至功率放大电路所 在的印刷电路板上其它位置的微带线， 通过其它位置的微带线实现连接直流 去耦电容 CLF 704。 即实施时， 可以从布局方面考虑， 根据实际情况选择较佳 的布局方案， 确定第一金属氧化物半导体电容 Moscapl 702与直流去耦电容 CLF 704之间具体的连接方案。 通常来讲， 布局走线不宜过长。
在本发明的其它实施例中， 还可以对上述实施例 1 提供的功率放大电路 进行变型， 均在本发明的保护范围之内， 例如下述实施例 2。
实施例 2:
本发明实施例 2还提供了一种功率放大电路， 如图 11所示， 相比于上述 实施例 1 提供的功率放大电路， 还包括一个第二金属氧化物半导体电容 Moscap2, 功放管芯 die的漏极具体通过两段邦定线 LB2和 LB5直接连接输 出匹配网络， 两段邦定线 LB2和 LB5之间的接线端连接第二金属氧化物半导 体电容 Moscap2的第一端， 第二金属氧化物半导体电容 Moscap2的第二端接 地。
即功放管芯 die的漏极通过邦定线 LB2连接第二金属氧化物半导体电容 Moscap2的第一端， 第二金属氧化物半导体电容 Moscap2的第一端再通过邦 定线 LB2连接输出匹配网络。
其它具体内容参见上述实施例 1 , 在此不再详述。
可见， 本发明实施例 2提供的功率放大电路， 相比于上述实施例 1提供 的功率放大电路增加了一级金属氧化物半导体电容， 以改变输出端匹配阻抗。 在本发明的另一实施例中， 还可以增加多级金属氧化物半导体电容。
实施例 3:
本发明实施例 3还提供了一种功率放大电路， 该功率放大电路在上述实 施例 1或实施例 2的基础上还可以包括连接输出匹配网络的漏极偏置电路。 在输出匹配网络未连接漏极偏置电路时， 低频谐振回路由功放管芯、 金属氧 化物半导体电容、 直流去耦电容、 输出匹配网络以及输出匹配网络输出端连 接的接地的后端网络构成， 低频谐振回路线路较长； 在输出匹配网络连接漏 极偏置电路时， 低频谐振回路由功放管芯、 金属氧化物半导体电容、 直流去 耦电容、 输出匹配网络以及漏极偏置电路构成， 即通过漏极偏置电路， 缩短 了低频谐振回路线路长度， 即进一步减小了低频谐振回路中的电感， 提高了 低频谐振频率， 能够改善功率放大电路的输出端的性能指标。
本发明实施例 3提供的功率放大电路还可以包括连接输入匹配网络的栅 极偏置电路， 能够改善功率放大电路的输入端的性能指标。
图 12所示的功率放大电路即为本发明实施例 3提供的功率放大电路的一 个具体示例， 两个偏置电路中 CLF为直流去耦电容， CRF为射频旁路电容。
实施例 4:
本发明实施例 4提供了一种发射机， 包括上述实施例中任一所示的功率 放大电路。
综上所述， 釆用本发明实施例提供的方案能够提高功率放大电路的低频 谐振频率， 并且电路设计灵活， 成本较低。
本领域内的技术人员应明白， 尽管已描述了本发明的优选实施例， 但本 领域内的技术人员一旦得知了基本创造性概念， 则可对这些实施例作出另外 的变更和修改。 所以， 所附权利要求意欲解释为包括优选实施例以及落入本 发明范围的所有变更和修改。 脱离本发明实施例的精神和范围。 这样， 倘若本发明实施例的这些修改和变 型属于本发明权利要求及其等同技术的范围之内， 则本发明也意图包含这些 改动和变型在内。

Claims

权 利 要 求
1、 一种功率放大电路， 其特征在于， 包括功放管芯、 第一金属氧化物半 导体电容、 直流去耦电容和输出匹配网络， 其中：
所述功放管芯的漏极通过邦定线连接所述第一金属氧化物半导体电容的 第一端， 所述第一金属氧化物半导体电容的第二端接地；
所述功放管芯的漏极通过邦定线直接连接所述输出匹配网络； 所述功放 管芯的源极接地；
所述第一金属氧化物半导体电容的第一端通过邦定线连接所述直流去耦 电容的一端；
所述直流去耦电容的另一端接地。
2、 如权利要求 1所述的功率放大电路， 其特征在于， 所述第一金属氧化 物半导体电容的第一端， 具体通过邦定线连接至功率放大电路所在的印刷电 路板上的微带线， 所述微带线连接所述直流去耦电容的一端。
3、 如权利要求 1或 2所述的功率放大电路， 其特征在于， 所述第一金属 氧化物半导体电容的第一端， 具体通过邦定线连接至功率放大电路所在的印 刷电路板上所述第一金属氧化物半导体电容和所述输出匹配网络之间的微带 线。
4、 如权利要求 1或 2所述的功率放大电路， 其特征在于， 所述第一金属 氧化物半导体电容的第一端， 具体通过邦定线连接至功率放大电路所在的印 刷电路板上所述第一金属氧化物半导体电容侧面的微带线。
5、 如权利要求 1或 2所述的功率放大电路， 其特征在于， 所述第一金属 氧化物半导体电容的第一端， 具体通过邦定线连接至功率放大电路所在的印 刷电路板上所述输出匹配网络侧面的 带线。
6、 如权利要求 1-5任一所述的功率放大电路， 其特征在于， 还包括输入 匹配网络， 所述功放管芯的栅极通过邦定线直接连接所述输入匹配网络。
7、 如权利要求 1-6任一所述的功率放大电路， 其特征在于， 还包括第二 金属氧化物半导体电容， 所述功放管芯的漏极具体通过两段邦定线直接连接 所述输出匹配网络， 所述两段邦定线之间的接线端连接所述第二金属氧化物 半导体电容的第一端， 所述第二金属氧化物半导体电容的第二端接地。
8、 如权利要求 1-7任一所述的功率放大电路， 其特征在于， 所述直流去 耦电容具体为纳法级电容或微法级电容。
9、 一种发射机， 其特征在于， 包括权利要求 1-8任一所述的功率放大电 路。
PCT/CN2014/073883 2014-03-21 2014-03-21 一种功率放大电路及发射机 WO2015139311A1 (zh)

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EP14886265.9A EP3113360A4 (en) 2014-03-21 2014-03-21 Power amplification circuit and transmitter
JP2017500109A JP6478253B2 (ja) 2014-03-21 2014-03-21 電力増幅回路およびトランスミッタ
PCT/CN2014/073883 WO2015139311A1 (zh) 2014-03-21 2014-03-21 一种功率放大电路及发射机
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