WO2015127713A1 - 一种非易失性存储器的擦除方法和装置 - Google Patents

一种非易失性存储器的擦除方法和装置 Download PDF

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Publication number
WO2015127713A1
WO2015127713A1 PCT/CN2014/076147 CN2014076147W WO2015127713A1 WO 2015127713 A1 WO2015127713 A1 WO 2015127713A1 CN 2014076147 W CN2014076147 W CN 2014076147W WO 2015127713 A1 WO2015127713 A1 WO 2015127713A1
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Prior art keywords
verification
erasure
target
erase
area
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PCT/CN2014/076147
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English (en)
French (fr)
Inventor
胡洪
王林凯
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北京兆易创新科技股份有限公司
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Priority to US14/897,646 priority Critical patent/US9490026B2/en
Publication of WO2015127713A1 publication Critical patent/WO2015127713A1/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3477—Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/107—Programming all cells in an array, sector or block to the same state prior to flash erasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure

Definitions

  • the present application relates to the field of semiconductor memory technologies, and in particular, to a method and apparatus for erasing a nonvolatile memory. Background technique
  • Non-volatile memory refers to a type of memory that retains data even after power is turned off, that is, data stored after power-off is not lost.
  • EEPROM Electrically Erasable Programmable Read-Only Memory
  • Flash Memory Flash Memory
  • the non-volatile memory includes a plurality of memory cells, and the information is stored by changing the number of electrons in the floating gate of the memory cell: during the programming process, after the electrons are injected into the floating gate of the memory cell, the threshold voltage of the memory cell increases, At this time, the memory cell is in the programmed state; during the erasing process, after the electrons trapped in the floating gate are removed, the threshold voltage of the memory cell is lowered, and the memory cell is in the erased state. After the programming or erasing is completed, the data is stored in the non-volatile memory. At this time, the memory cells of the non-volatile memory generally have both a programming unit (Pgm cell ) and an Erase cell. Have different threshold voltages.
  • Pgm cell programming unit
  • the erase operation for the non-volatile memory is performed in blocks, i.e., each memory cell in a target erase area is erased at a time.
  • each memory cell in a target erase area is erased at a time.
  • the erase operation is performed. It is difficult to ensure convergence of the threshold voltage of the memory cells in the target erase region after completion.
  • the current general practice is to increase the pre-programming process before performing the erase operation: first, program the Erase cell in the target erase region, and program it as After the operation is completed, an erase operation is performed on the target erase area.
  • the threshold voltage distribution of the memory cells in the target erase region after the erase operation can be made to have good convergence.
  • the above process increases the execution time of the entire erase operation; in particular, if the target erase region is in the full erase state before the erase operation (ie, the memory cells in the target erase region are all Erase cells), then The pre-programming process still programs all Erase cells in the target erase area into Pgm cells, and then performs the erase operation, which causes unnecessary time overhead and the process is complicated. Summary of the invention
  • the present application provides a method and apparatus for erasing a non-volatile memory to solve the problem that the current erasing operation causes unnecessary time overhead and the process is complicated.
  • the present application discloses a method for erasing a nonvolatile memory, which is characterized in that it comprises:
  • the step of performing pre-read verification on the target erasure area corresponding to the erasure instruction comprises: performing a pre-reading check on the target erasure area according to a pre-read verification reference voltage set in advance;
  • the step of performing pre-programming verification on the target erase region includes: performing pre-programming verification on the target erase region according to a preset pre-programmed verify reference voltage;
  • the pre-read verify reference voltage is less than or equal to the pre-programmed verify reference voltage.
  • the target erase area includes a plurality of storage units,
  • the step of performing pre-read verification on the target erasure area according to the preset pre-read verification reference voltage includes: Pre-reading calibration reference voltage;
  • the step of being less than the pre-read verification reference voltage includes:
  • a pre-read verify voltage set in advance is applied to the gate of the memory cell, and a drain current of the memory cell is detected;
  • the drain current of the memory cell is greater than a pre-read verify reference current set in advance, it is determined that the threshold voltage of the memory cell is less than the pre-read verify reference voltage.
  • the method before performing the erasing operation on the target erasing area, the method further includes: performing an erasure verification on the target erasing area;
  • the step of performing an erase check on the target erase area comprises: performing an erase check on the target erase area according to a preset erase check reference voltage; wherein the erasing The verify reference voltage is less than or equal to the pre-read verify reference voltage.
  • the method further includes: performing a pre-program operation on the target erase area if the pre-program verification fails; After the pre-program operation, the step of performing a pre-program verify on the target erase region is returned.
  • an apparatus for erasing a non-volatile memory further comprising:
  • a read-ahead check module configured to perform a read-ahead check on a target erase area corresponding to the erase command after receiving the erase command;
  • An erase module configured to perform an erase operation on the target erase region when the read-ahead check passes;
  • a pre-programmed verification module configured to perform a pre-programmed verification on the target erase region when the pre-read verify fails;
  • the erase module is further configured to perform an erase operation on the target erase area after the preprogrammed verify is passed.
  • the pre-reading verification module is configured to perform pre-reading verification on the target erasure area according to a pre-reading verification reference voltage set in advance;
  • the pre-programming verification module is specifically configured to perform pre-programming verification on the target erasure area according to a pre-programmed verification reference voltage set in advance;
  • the pre-read verify reference voltage is less than or equal to the pre-programmed verify reference voltage.
  • the target erase area includes a plurality of storage units,
  • the pre-read verification module includes:
  • a voltage verification module configured to separately verify whether a threshold voltage of each memory cell in the target erase region is less than the pre-read verify reference voltage
  • determining configured to determine that the pre-read verification passes when all of the storage unit threshold voltages are less than the pre-read verification reference voltage; otherwise, determining that the pre-read verification fails.
  • the voltage verification module comprises:
  • a detecting module configured to apply a pre-read verify voltage preset to the gate of the memory cell for each memory cell in the target erase region, and detect a drain current of the memory cell
  • a determining module configured to determine that a threshold voltage of the memory cell is less than the pre-read verify reference voltage when a drain current of the memory cell is greater than a pre-read verify reference current set in advance.
  • the device further includes:
  • An erase verifying module configured to perform an erase verify on the target erased region before the erase module performs an erase operation on the target erased region
  • the erasing module is further configured to perform an erasing operation on the target erasing area when the erasure verification fails;
  • the erase verifying module is further configured to perform an erase check on the target erased area after the erasing module performs the erase operation on the target erased area.
  • the erasure verification module is specifically configured to perform erasure verification on the target erasure area according to a preset erasure verification reference voltage;
  • the erase verify reference voltage is less than or equal to the pre-read verify reference voltage.
  • the device further includes:
  • a pre-programming module configured to perform a pre-program operation on the target erase region when the pre-program verify fails
  • the pre-programmed verify module is further configured to perform a pre-program verify on the target erase region after the pre-program module performs the pre-program operation on the target erase region.
  • a computer readable recording medium having recorded thereon a program for executing the method of claim 1.
  • the pre-read check after receiving the erase command, first performing a pre-read check on the target erase region corresponding to the erase command; if the pre-read check passes, performing a wipe on the target erase region In addition to the operation; if the pre-read verify fails, a pre-program verify is performed on the target erase region, and after the pre-program pass is passed, an erase operation is performed on the target erase region.
  • the pre-read check is performed first in the present application before the pre-program check, if the pre-read check passes, the pre-program check process can be skipped and the erase operation can be directly performed, thereby ensuring that before the erase operation When the target erase area is in the fully erased state, the unnecessary pre-programming verification process is no longer performed, the erase time is saved, and the erase process is simpler.
  • FIG. 1 is a flowchart of a method for erasing a nonvolatile memory according to Embodiment 1 of the present application
  • FIG. 2 is a flowchart of a method for erasing a nonvolatile memory according to Embodiment 2 of the present application
  • FIG. 4 is a block diagram showing the structure of an erasing apparatus for a nonvolatile memory according to a third embodiment of the present application.
  • a memory cell is usually a floating gate device with a chargeable memory compared to a general MOS transistor (the MOS transistor is a metal-oxide-semiconductor ( Semiconductor) field effect transistor), in addition to having a source, a drain, a gate, and an additional floating gate that can store chargetama It can be seen that its construction is slightly different from that of a general MOS tube. It has a floating gate that is insulated from other parts for storing charge. For the general design of nonvolatile memory, only The entire block (block) or sector (sector) is deleted and cannot be deleted by a single byte.
  • block block
  • sector sector
  • Typical nonvolatile memories include EPROM (Erasable Programmable Read-Only Memory), EEPROM, and flash memory.
  • EPROM means that the content can be erased by special means and then rewritten.
  • the basic cell (cell) circuit often uses a floating gate avalanche injection MOS circuit. Similar to the MOS circuit, it generally grows two high-concentration P-type regions on the N-type substrate, and respectively extracts the source S and the drain D through ohmic contacts. There is a polysilicon gate floating between the source and the drain in the Si0 2 insulating layer, which is not directly electrically connected to the periphery.
  • This circuit indicates whether the floating gate is charged or not, and the floating gate is charged (such as a negative charge), just below it, a positive conductive channel is induced between the source and the drain, so that the MOS transistor Turned on, which means that 0 is stored. If the floating gate is not charged, no conductive channel is formed, and the MOS transistor is not turned on, that is, 1 is stored.
  • the EEPROM basic memory cell (cell) circuit is similar to EPROM, it is in EPROM
  • a floating gate is further formed on the floating gate of the basic unit circuit, the former being referred to as a first-stage floating gate, and the latter being referred to as a second-stage floating gate.
  • An electrode can be drawn to the second stage floating gate to connect the second stage floating gate to a certain voltage VG. If VG is a positive voltage, a tunneling effect is created between the first floating gate and the drain, causing electrons to be injected into the first floating gate, ie, programmed. If VG is made to be a negative voltage, the electrons of the first stage floating gate will be lost, ie erased. Can be rewritten after erasing.
  • the basic memory cell (cell) circuit of the flash memory is similar to the EEPROM. It is also composed of a double-layer floating gate MOS transistor, but the first gate dielectric is thin. As a tunnel oxide layer, an electrode can be drawn to the second-level floating gate. The second stage floating gate is connected to a certain voltage VG. If VG is a positive voltage, a tunneling effect occurs between the first floating gate and the drain, so that electrons are injected into the first floating gate, that is, program writing; the erasing method is to apply a positive voltage (VB) to the substrate, The tunneling effect between the primary floating gate and the source attracts the negative charge injected into the floating gate to the source.
  • VG is a positive voltage
  • VB positive voltage
  • flash memory also realizes the design of single transistor, which mainly adds a floating gate and a selection gate to the original transistor, and forms a storage electron on the semiconductor whose current is unidirectionally conducted between the source and the drain. Floating shed.
  • the floating gate is covered with a silicon oxide film insulator. Above it is a selection/control gate that controls the conduction current between the source and drain.
  • the data is 0 or 1 depending on whether there is electrons in the floating gate formed on the silicon substrate. There is an electron of 0 and no electron of 1.
  • FIG. 1 a flowchart of a method for erasing a nonvolatile memory according to Embodiment 1 of the present application is shown.
  • the method may specifically include the following steps:
  • Step 101 After receiving the erase command, performing pre-read verification on the target erase region corresponding to the erase command.
  • step 102 If the pre-read check passes, step 102 is performed; if the pre-read check fails, step 103 is performed.
  • the Erase cell has a Pgm cell, which causes a problem of poor convergence of the threshold voltage of the memory cells in the target erase region after the erase operation is completed, and usually performs a pre-programming process to improve the target erase region before performing the erase operation.
  • the convergence of the threshold voltage of the internal memory cell is not limited.
  • the pre-read check is performed on the target erase region corresponding to the erase command, instead of directly A pre-programming process is performed on the target erase area.
  • Step 102 Perform an erase operation on the target erase area.
  • step 101 If the pre-read check passes in step 101, it can be explained that the convergence of the threshold voltage itself of the memory cells in the target erase region is relatively high at this time, so that the pre-programming process can be skipped, directly to the target.
  • the erase region performs an erase operation, and after the erase operation, it can be ensured that the threshold voltage convergence of the memory cells in the target erase region is high.
  • Step 103 Perform a pre-program verification on the target erase area, and perform an erase operation on the target erase area after the pre-program verification is passed.
  • the pre-read check fails in step 101, it can be stated that the storage unit in the target erase region has both the Erase cell and the Pgm cell, so that the target erase region can be pre-programmed. check. If the pre-program verify fails, performing a pre-program operation on the target erase region to program the Erase cell therein as a Pgm cell, thereby ensuring a threshold of a memory cell in the target erase region before the erase operation Convergence of voltage; if the pre-programmed verify pass therefore performs an erase operation on the target erase region.
  • the pre-read check is performed before the pre-programming check is performed. If the pre-read check passes, the pre-program check process may be skipped, and the erase operation may be directly performed, thereby ensuring erasure. In the case where the target erase area is in the full erase state before the operation, the unnecessary pre-programming verification process is not performed, the erase time is saved, and the erase process is simpler.
  • FIG. 2 a method for erasing a nonvolatile memory according to a second embodiment of the present application is shown. Flowchart, the method specifically includes the following steps:
  • Step 201 Receive an erase command.
  • Step 202 Perform pre-read verification on the target erasure area corresponding to the erasure instruction.
  • step 203 is performed; if the pre-read verification is passed, step 205 is performed.
  • the non-volatile memory During normal operation, if the non-volatile memory needs to be erased, it will receive an erase command, which may include information such as the target erase area address, and erase the area according to the target.
  • the address can find the target erase area corresponding to the erase command.
  • the target erase area may be a chip, a block, or a sector.
  • the read-ahead check ( PRE RD ) may be performed on the target erase region corresponding to the erase command.
  • the step 202 may specifically include: performing a pre-reading check on the target erasure area according to a pre-read verification reference voltage set in advance.
  • the step of performing pre-read verification on the target erasure area according to the preset pre-read verification reference voltage may specifically include the following sub-steps: No, less than the pre-reading school Check the reference voltage;
  • Sub-step a2 if the threshold voltages of all the memory cells are less than the pre-read verify reference voltage, it is determined that the pre-read verify passes; otherwise, it is determined that the read-ahead check fails.
  • the erased region can be said to be in a fully erased state), so that the read-ahead check can be determined to pass. If there is a memory cell having a threshold voltage greater than or equal to the pre-read verify reference voltage in the target erase region, it is determined that the read-ahead check fails.
  • the current characteristics of the memory cells in the non-volatile memory are similar to those of the MOS transistors, when the voltage difference between the gate and the source is less than the threshold voltage, the tube is turned off, and there is no current at this time. Therefore, to determine the threshold voltage of a memory cell, it is only necessary to add a certain set voltage to the gate, and then judge the drain.
  • the current can be sized.
  • the above substep al may include the following substeps:
  • Sub-step all, for each memory cell in the target erase region, respectively applying a pre-read verify voltage set in advance at the gate of the memory cell, and detecting a drain current of the memory cell; sub-step al2, If the drain current of the memory cell is greater than a preset pre-read verify reference current, determining that the threshold voltage of the memory cell is less than the pre-read verify reference voltage; if the drain current of the memory cell is less than or equal to a preset The pre-read verifying reference current determines that the threshold voltage of the memory cell is greater than or equal to the pre-read verify reference voltage.
  • FIG. 3 there is shown a schematic structural diagram of a non-volatile memory, which may include 16 memory cells (MN1, MN2 MN3 MN4 MN16) 4 bit lines (BU, BL2 BL3 BL4) And 4 word lines (WL1, WL2 WL3 WL4).
  • the memory cells form an array of memory cells.
  • the gates of the memory cells of the same row in the array are connected to the same word line, and the drains of the memory cells of the same column are connected to the same bit line.
  • the erase operation of the non-volatile memory is performed in blocks, that is, each memory cell in one erase area is erased each time.
  • the structure of the BL2 BL3 BL4) and the four word lines (WL1 WL2 WL3 WL4) is exemplified, but the nonvolatile memory in the embodiment of the present application is not limited to the above structure, and includes the memory cells, the word lines, and The bit line can also be other quantities.
  • the pre-read verify voltages set in advance in the sub-steps can be sequentially applied to the word lines in the target erase area, and then the current on each bit line can be detected.
  • a pre-read verify voltage set in advance is applied to the word line WL1 in the target erase region, which is equivalent to applying a pre-read verify voltage set in advance in the gate of each memory cell in the first row.
  • detecting currents on respective bit lines in the target erase region wherein the current on the bit line BL1 is equivalent to the drain current of the memory cell MN1, and the current on the bit line BL2 is equivalent to the drain current of the memory cell MN2.
  • the current on the bit line BL3 corresponds to the drain current of the memory cell MN3, and the current on the bit line BL4 corresponds to the drain current of the memory cell MN4.
  • Target erase area The processing method of other storage units in the domain is basically the same as the above process, and the embodiments of the present application are not discussed in detail herein. It should be noted that, in the above detection process, the source of each memory cell in the target erase region is grounded, and when a preset pre-read verify voltage is applied on a certain word line, no other word lines are applied. The voltage, that is, the drain of the memory cell that is not connected to the word line to which the pre-read verify voltage is applied is not generated.
  • the values corresponding to different non-volatile memories may be different, and the specific values of the present application are not limited.
  • Step 203 Perform pre-programming verification on the target erasure area.
  • step 204 is performed; if the preprogrammed check passes, step 205 is performed.
  • step 203 may specifically include: performing pre-programming verification on the target erase area according to a preset pre-programmed reference voltage.
  • the step of performing pre-programming verification on the target erasure region according to the preset pre-programmed verification reference voltage may specifically include the following sub-steps: No greater than the pre-programmed school Check the reference voltage;
  • Sub-step b2 if the threshold voltages of all the memory cells are greater than the pre-programmed verify reference voltage, then the pre-programmed verify is determined to pass; otherwise, the pre-program verify is determined to have failed.
  • the purpose of the pre-programmed check is to verify whether the pre-program operation is successful, if the threshold voltages of all the memory cells are greater than the pre-program verify reference voltage, then the pre-program verify can be determined to pass; if the target erases A memory cell having a threshold voltage less than or equal to the pre-programmed verify reference voltage is present in the region, and then the pre-program verify may be determined to have failed.
  • the above substep bl may include the following substeps: Sub-step b11, for each memory cell in the target erase region, respectively, a preset pre-programmed verify voltage is applied to the gate of the memory cell, and the drain current of the memory cell is detected;
  • Sub-step bl2 if the drain current of the memory cell is less than a preset pre-programmed verify reference current, determining that the threshold voltage of the memory cell is greater than the pre-programmed verify reference voltage; if the drain current of the memory cell is greater than Or equal to a pre-programmed verify reference current set in advance, then determining a threshold voltage d of the memory cell at or equal to the pre-programmed verify reference voltage.
  • a preset pre-programmed verify voltage can be sequentially applied to the word line in the target erase region, and then the current on each bit line can be detected.
  • a specific process refer to the related description in the foregoing step 202.
  • the embodiments of the present application are not discussed in detail herein.
  • the pre-programmed verification reference voltage, the pre-programmed verification voltage, and the pre-programmed verification reference current involved in the step 203 those skilled in the art may perform related settings according to actual experience, different non- The numerical values of the volatile memory may be different.
  • the specific numerical values in the embodiments of the present application are not limited.
  • Step 204 Perform a pre-program operation on the target erase area.
  • the pre-program verification fails in step 203, it may be stated that the pre-program operation is unsuccessful, and a pre-program operation may be performed on the target erase region, where the pre-program operation refers to the target erase region.
  • the memory cell is written with a 0 to program the threshold voltages of all memory cells within the target erase region to be greater than the pre-programmed reference voltage.
  • the specific process of the pre-programming operation may include: applying a gate pre-programming voltage to the gates of all the memory cells in the target erasing region, and all the storage in the target erasing region A drain pre-program voltage is applied to the drain of the cell. For example, a voltage of 9V can be applied to the gate and a voltage of 4V can be applied to the drain.
  • a gate pre-programming voltage is applied to the gates of all the memory cells in the target erasing region, and all the storage in the target erasing region
  • a drain pre-program voltage is applied to the drain of the cell.
  • a voltage of 9V can be applied to the gate and a voltage of 4V can be applied to the drain.
  • the specific values vary depending on the process.
  • the step 203 can be returned to perform a pre-program check on the target erase region again.
  • Step 205 Perform an erase check on the target erase area.
  • step 206 is performed; if the erasure verification is passed, then Step 207.
  • step 202 If the pre-read verification passes in step 202, it can be explained that the convergence of the threshold voltage itself of the memory cell in the target erase region is high at this time (for example, the target erase region is in the fully erased state at this time), The pre-program verification process can be skipped to perform an erase verify (EV) directly on the target erase region.
  • step 203 If the pre-program verify passes in step 203, it can be stated that the pre-programmed verify reference voltage is pre-programmed at this time, and the erase verify can also be performed on the target erase region.
  • the step 205 may specifically include: performing an erasure verification on the target erasure area according to a preset erase verify reference voltage.
  • the step of performing erasure verification on the target erasure area according to the preset erasure verification reference voltage may specifically include the following substeps: No less than the erasure correction Check the reference voltage;
  • Sub-step c2 if the threshold voltages of all the memory cells are less than the erase verify reference voltage, it is determined that the erase verify passes; otherwise, it is determined that the erase verify fails.
  • the purpose of the erase verify is to verify whether the erase operation is successful. If the threshold voltages of all the memory cells are less than the erase verify reference voltage, the erase verify can be determined to pass; if the target erases If there is a memory cell having a threshold voltage greater than or equal to the erase verify reference voltage in the region, it may be determined that the erase verify fails.
  • the above substep cl may include the following substeps:
  • Sub-step cl l applying a preset erase verify voltage to the gate of the memory cell for each memory cell in the target erase region, and detecting a drain current of the memory cell; sub-step cl2 If the drain current of the memory cell is greater than a preset erase verify reference current, determining that the threshold voltage of the memory cell is less than the erase verify reference voltage; if the drain current of the memory cell is less than or equal to the advance The set erase verify reference current determines that the threshold voltage of the memory cell is greater than or equal to the erase verify reference voltage.
  • the sub-step cl1 may sequentially apply a preset erase verify voltage on the word line in the target erase region, and then detect the power on each bit line. Stream.
  • the sub-step cl1 may sequentially apply a preset erase verify voltage on the word line in the target erase region, and then detect the power on each bit line. Stream.
  • the values corresponding to different non-volatile memories may be different, and the specific values of the present application are not limited.
  • the pre-read verify reference voltage is greater than or equal to the erase verify reference voltage and less than or equal to the pre-program verify reference voltage.
  • Step 206 Perform an erase operation on the target erase area.
  • step 205 If the erase check fails in step 205, it may be stated that the erase operation is unsuccessful, and an erase operation may be performed on the target erase region, where the erase operation refers to the target erase region.
  • the memory cell is written with a purpose of erasing the threshold voltage of all memory cells in the target erase region to d, and erasing the verify reference voltage.
  • the specific process of the erasing operation may include: applying a gate erase voltage to the gates of all the memory cells in the target erase region, and all the storage in the target erase region A drain erase voltage is applied to the substrate of the cell.
  • a voltage of -9V can be applied to the gate, and a voltage of 4V can be applied to the substrate.
  • the specific values vary depending on the process.
  • step 205 After performing the erase operation, it is returned to step 205 to perform an erase check on the target erase region again.
  • Step 207 ending the erasing operation process.
  • step 205 If the erase check is passed in step 205, it can be stated that the erase operation is successful, so that the erase operation can be ended.
  • step 204 may be performed first, and then step 203 is performed, that is, if the pre-read verification fails in step 202, step 204 may be performed, and after step 204 is performed, step 203 is continued, if step 203 is performed If the program verification fails, the process returns to step 204. If the pre-program verification passes in step 203, step 205 is performed.
  • step 206 may be performed first, and then step 205 is performed, that is, if the pre-read verification fails in step 203, step 206 may be performed, and after step 206 is performed, step 205 is continued, and if step 205 is performed, Except for verification If yes, the process returns to step 206.
  • step 207 is performed.
  • an erasure verification (OVV) may also be performed on the target erasing area.
  • OEV erasure verification
  • Over-erase check refers to adjusting the threshold voltage of the memory cell in the target erase area. The purpose of OEV is to perform a weaker programming on a memory cell that may be over-erased with a threshold below 0V. Its threshold is pushed above 0V.
  • a specific method of operation may be to apply an OEV programming voltage to the gate and drain of the memory cell (eg, 0V may be applied to the gate and 4V may be applied to the drain, depending on the particular process).
  • OEV programming voltage eg, 0V may be applied to the gate and 4V may be applied to the drain, depending on the particular process.
  • the method described in the embodiment of the present application can ensure that the unnecessary erasing verification process is not performed in the case where the target erasing area is in the fully erased state before the erasing operation, the erasing time is saved, and the erasing process is simpler. .
  • FIG. 4 a structural block diagram of an apparatus for erasing a non-volatile memory according to Embodiment 3 of the present application is shown.
  • the apparatus may specifically include the following modules:
  • the read-ahead check module 401 is configured to perform a read-ahead check on the target erase area corresponding to the erase command after receiving the erase command;
  • the erasing module 402 is configured to perform an erasing operation on the target erasing area when the pre-reading verification passes;
  • the pre-programming verification module 403 is configured to perform pre-programming verification on the target erasing area when the pre-reading verification fails;
  • the erasing module is further configured to: after the pre-programmed verification passes, the target erasing area The domain performs an erase operation.
  • the apparatus may further include the following module: a pre-programming module configured to perform a pre-program operation on the target erase area when the pre-program verification fails;
  • the pre-programmed verification module is further configured to perform a pre-programming check on the target erase region after the pre-programming module performs the pre-program operation on the target erase region;
  • An erase verifying module configured to perform an erase verify on the target erased region before the erase module performs an erase operation on the target erased region
  • the erasing module is further configured to perform an erasing operation on the target erasing area when the erasure verification fails;
  • the erase verifying module is further configured to perform an erase verify on the target erased region after the erase module performs the erase operation on the target erase region.
  • the pre-reading verification module is specifically configured to perform pre-reading verification on the target erasure area according to a preset pre-read verification reference voltage
  • the pre-programming verification module is specifically configured to perform pre-programming verification on the target erasure area according to a pre-programmed verification reference voltage set in advance;
  • the erase verifying module is configured to perform an erase check on the target erased area according to a preset erase verify reference voltage
  • the erase verify reference voltage is less than or equal to the pre-read verify reference voltage and greater than or equal to the pre-read verify reference voltage.
  • the pre-read verification module may include the following modules: a voltage verification module configured to separately verify whether a threshold voltage of each memory cell in the target erase region is less than The pre-reading verification reference voltage;
  • determining configured to determine that the pre-read verification passes when all of the storage unit threshold voltages are less than the pre-read verification reference voltage; otherwise, determining that the pre-read verification fails.
  • the voltage verification module includes the following modules:
  • a detecting module configured to apply a pre-read verify voltage preset to the gate of the memory cell for each memory cell in the target erase region, and detect a drain current of the memory cell
  • a determining module configured to determine that a threshold voltage of the memory cell is less than the pre-read verify reference voltage when a drain current of the memory cell is greater than a pre-read verify reference current set in advance.
  • the pre-read check is performed before the pre-programming check is performed. If the pre-read check passes, the pre-program check process may be skipped, and the erase operation may be directly performed, thereby ensuring erasure. In the case where the target erase area is in the full erase state before the operation, the unnecessary pre-programming verification process is not performed, the erase time is saved, and the erase process is simpler.
  • the embodiment of the present application also provides a computer readable recording medium on which the program for the above embodiment is recorded.
  • the computer readable recording medium includes any mechanism for storing or transmitting information in a form readable by a computer (e.g., a computer).
  • a machine readable medium includes a read only memory
  • ROM read only memory
  • RAM random access memory
  • magnetic disk storage media magnetic disk storage media
  • optical storage media flash storage media
  • electrical, optical, acoustic or other forms of propagating signals eg, carrier waves, infrared signals, digital signals, etc.
  • the application can be described in the general context of computer-executable instructions executed by a computer, such as a program module.
  • program modules include routines, programs, objects, components, data structures, and the like that perform particular tasks or implement particular abstract data types.
  • tasks are performed by remote processing devices that are connected through a communication network.
  • program modules can be located in both local and remote computer storage media including storage devices.

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  • Read Only Memory (AREA)

Abstract

申请一种非易失性存储器的擦除方法和装置，以解决目前的擦除操作造成不必要的时间开销，过程较为复杂的问题。其中，方法包括：在接收到擦除指令后，对所述擦除指令对应的目标擦除区域执行预读校验；若所述预读校验通过，则对所述目标擦除区域执行擦除操作；若所述预读校验未通过，则对所述目标擦除区域执行预编程校验，并在所述预编程校验通过后，对所述目标擦除区域执行擦除操作。本申请可以保证在擦除操作之前目标擦除区域处于全擦除状态的情况下，不再执行不必要的预编程校验过程，节省擦除时间，擦除过程更加简单。

Description

一种非易失性存储器的擦除方法和装置 本申请要求在 2014 年 2 月 28 日提交中国专利局、 申请号为 201410073647.7 、发明名称为 "一种非易失性存储器的擦除方法和装置"的 中国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本申请涉及半导体存储器技术领域，特别是涉及一种非易失性存储器的 擦除方法和装置。 背景技术
非易失性存储器是指断电后仍能保持数据， 即断电之后所存储的数据不 会丢失的一种存储器。 EEPROM ( Electrically Erasable Programmable Read-Only Memory, 电可擦可编程只读存储器）和闪存（ Flash Memory )等 均属于非易失性存储器。 非易失性存储器中包括多个存储单元， 通过改变存 储单元的浮栅中的电子数量来存储信息： 在编程过程中， 将电子注入到存储 单元的浮栅后， 存储单元的阈值电压增加， 这时存储单元处于已编程状态； 在擦除过程中， 将浮栅中俘获的电子去除后， 存储单元的阈值电压降低， 这 时存储单元处于已擦除状态。 在编程或擦除完成后， 数据被存储在非易失性 存储器中，此时非易失性存储器的存储单元中一般既有编程单元（ Pgm cell ), 也有擦除单元（Erase cell ), 它们具有不同的阈值电压。
对于非易失性存储器的擦除操作是按块进行的， 即每次对一个目标擦除 区域内的各个存储单元进行擦除操作。 但是， 由于目标擦除区域内可能既有 Erase cell又有 Pgm cell, 而它们在擦除操作前的阈值电压有很大的不同， 如 果直接对目标擦除区域进行擦除操作， 那么擦除操作完成后很难保证目标擦 除区域内存储单元的阈值电压的收敛。
为了解决上述问题， 目前一般的做法是， 在执行擦除操作之前增加预编 程过程： 即首先对目标擦除区域中的 Erase cell进行编程操作， 将其编程为 程操作完成后， 对目标擦除区域执行擦除操作。
通过上述方法， 可以使擦除操作后目标擦除区域内存储单元的阈值电压 分布具有较好的收敛性。 但是， 上述过程会增加整个擦除操作的执行时间； 特别的， 如果在擦除操作之前目标擦除区域内处于全擦除状态（即目标擦除 区域内的存储单元均为 Erase cell ), 则预编程过程仍然会将目标擦除区域内 所有的 Erase cell编程为 Pgm cell, 然后再进行擦除操作， 这样就造成了不必 要的时间开销， 过程较为复杂。 发明内容
本申请提供了一种非易失性存储器的擦除方法和装置， 以解决目前的擦 除操作造成不必要的时间开销， 过程较为复杂的问题。 为了解决上述问题， 本申请公开了一种非易失性存储器的擦除方法， 其 特征在于， 包括：
在接收到擦除指令后，对所述擦除指令对应的目标擦除区域执行预读校 验；
若所述预读校验通过， 则对所述目标擦除区域执行擦除操作； 若所述预读校验未通过， 则对所述目标擦除区域执行预编程校验， 并在 所述预编程校验通过后， 对所述目标擦除区域执行擦除操作。
优选地， 所述对所述擦除指令对应的目标擦除区域执行预读校验的步骤 包括： 依据预先设置的预读校验基准电压对所述目标擦除区域执行预读校 验；
所述对所述目标擦除区域执行预编程校验的步骤包括：依据预先设置的 预编程校验基准电压对所述目标擦除区域执行预编程校验；
其中， 所述预读校验基准电压小于或等于所述预编程校验基准电压。 优选地， 所述目标擦除区域包括多个存储单元，
所述依据预先设置的预读校验基准电压对所述目标擦除区域执行预读 校验的步骤包括： 述预读校验基准电压；
若所有存储单元的阈值电压均小于所述预读校验基准电压，则确定所述 预读校验通过； 否则， 确定所述预读校验未通过。 是否小于所述预读校验基准电压的步骤包括：
针对所述目标擦除区域内的每个存储单元，分别在该存储单元的栅极施 加预先设置的预读校验电压， 并检测该存储单元的漏极电流；
若所述该存储单元的漏极电流大于预先设置的预读校验基准电流， 则确 定该存储单元的阈值电压小于所述预读校验基准电压。
优选地， 在所述对所述目标擦除区域执行擦除操作之前， 还包括： 对所述目标擦除区域执行擦除校验；
若所述擦除校验未通过，则执行所述对所述目标擦除区域执行擦除操作 的步骤；
在执行所述擦除操作之后，返回所述对所述目标擦除区域执行擦除校验 的步骤。
优选地， 所述对所述目标擦除区域执行擦除校验的步骤包括： 依据预先设置的擦除校验基准电压对所述目标擦除区域执行擦除校验； 其中， 所述擦除校验基准电压小于或等于所述预读校验基准电压。 优选地， 在所述对所述目标擦除区域执行预编程校验之后， 还包括： 若所述预编程校验未通过， 则对所述目标擦除区域执行预编程操作； 在执行所述预编程操作之后 ,返回所述对所述目标擦除区域执行预编程 校验的步骤。 根据本申请的另一方面， 还公开了一种非易失性存储器的擦除装置， 其 特征在于， 包括：
预读校验模块， 配置为在接收到擦除指令后， 对所述擦除指令对应的目 标擦除区域执行预读校验；
擦除模块， 配置为在所述预读校验通过时， 对所述目标擦除区域执行擦 除操作； 预编程校验模块， 配置为在所述预读校验未通过时， 对所述目标擦除区 域执行预编程校验；
所述擦除模块， 还配置为在所述预编程校验通过后， 对所述目标擦除区 域执行擦除操作。
优选地， 所述预读校验模块， 具体配置为依据预先设置的预读校验基准 电压对所述目标擦除区域执行预读校验；
所述预编程校验模块，具体配置为依据预先设置的预编程校验基准电压 对所述目标擦除区域执行预编程校验；
其中， 所述预读校验基准电压小于或等于所述预编程校验基准电压。 优选地， 所述目标擦除区域包括多个存储单元，
所述预读校验模块包括：
电压校验模块， 配置为分别校验所述目标擦除区域内的每个存储单元的 阈值电压是否小于所述预读校验基准电压；
确定模块， 配置为在所有存储单元的阈值电压均小于所述预读校验基准 电压时， 确定所述预读校验通过； 否则， 确定所述预读校验未通过。
优选地， 所述电压校验模块包括：
检测模块， 配置为针对所述目标擦除区域内的每个存储单元， 分别在该 存储单元的栅极施加预先设置的预读校验电压， 并检测该存储单元的漏极电 流;
确定模块， 配置为在所述该存储单元的漏极电流大于预先设置的预读校 验基准电流时， 确定该存储单元的阈值电压小于所述预读校验基准电压。
优选地， 所述装置还包括：
擦除校验模块， 配置为在所述擦除模块对所述目标擦除区域执行擦除操 作之前， 对所述目标擦除区域执行擦除校验；
所述擦除模块， 还配置为在所述擦除校验未通过时， 对所述目标擦除区 域执行擦除操作；
所述擦除校验模块，还配置为在所述擦除模块对所述目标擦除区域执行 所述擦除操作之后， 对所述目标擦除区域执行擦除校验。 优选地， 所述擦除校验模块， 具体配置为依据预先设置的擦除校验基准 电压对所述目标擦除区域执行擦除校验；
其中， 所述擦除校验基准电压小于或等于所述预读校验基准电压。
优选地， 所述装置还包括：
预编程模块， 配置为在所述预编程校验未通过时， 对所述目标擦除区域 执行预编程操作；
所述预编程校验模块，还配置为在所述预编程模块对所述目标擦除区域 执行所述预编程操作之后， 对所述目标擦除区域执行预编程校验。 根据本申请的另一方面， 还公开了一种在其上记录有用于执行权利 要求 1所述方法的程序的计算机可读记录介质。 与现有技术相比， 本申请包括以下优点：
本申请中， 在接收到擦除指令后， 首先对所述擦除指令对应的目标擦除 区域执行预读校验； 如果所述预读校验通过， 则对所述目标擦除区域执行擦 除操作；如果所述预读校验未通过，则对所述目标擦除区域执行预编程校验， 并在所述预编程校验通过后， 对所述目标擦除区域执行擦除操作。 由于本申 请中在进行预编程校验之前， 首先进行预读校验， 如果预读校验通过， 则可 以跳过预编程校验过程， 直接执行擦除操作， 从而可以保证在擦除操作之前 目标擦除区域处于全擦除状态的情况下， 不再执行不必要的预编程校验过 程， 节省擦除时间， 擦除过程更加简单。 附图说明
图 1是本申请实施例一的一种非易失性存储器的擦除方法的流程图； 图 2是本申请实施例二的一种非易失性存储器的擦除方法的流程图； 图 3是一种非易失性存储器的结构示意图；
图 4是本申请实施例三的一种非易失性存储器的擦除装置的结构框图。 具体实施方式 为使本申请的上述目的、 特征和优点能够更加明显易懂， 下面结合附图 和具体实施方式对本申请作进一步详细的说明。 随着各种电子装置及嵌入式系统的迅速发展和广泛应用， 如计算机、 个 人数字助理、 移动电话、 数字相机等， 大量需要一种能多次编程， 容量大， 读写、 擦除快捷、 方便、 简单， 外围器件少， 价格低廉的非易失性（在断电 情况下仍能保持所存储的数据信息）的存储器件。 非易失性存储器件就是在 这种背景需求下应运而生的。 一个非易失存储器的核心是存储单元阵列， 一 个存储单元通常是一个拥有可存储电荷的浮栅器件， 相比一般的 MOS 管 ( MOS管是金属（metal ) -氧化物（oxid ) -半导体（semiconductor )场效应 晶体管），它除了拥有一个源极（source ),—个漏极（drain ),—个栅极（gate ) 之外， 还额外拥有一个可存储电荷的浮动栅极（floating gate )„ 可见， 它的 构造和一般的 MOS管略有不同， 多了一个浮动栅极， 该浮动栅极绝缘于其 他部分， 用于存储电荷。 针对非易失存储器的一般设计而言， 只能以整芯片 ( chip ) 整块 ( block )或扇区 ( sector )的形式删除， 而不能被单字节删除。
为使本领域技术人员更好地理解本申请， 首先简单介绍几种非易失存储 器的工作原理。
典型的非易失存储器包括 EPROM ( Erasable Programmable Read-Only Memory, 可擦写可编程只读存储器）、 EEPROM及闪存。 EPROM是指其中 的内容可以通过特殊手段擦去， 然后重新写入。 其基本单元（cell ) 电路常 釆用浮动栅极雪崩注入式 MOS电路。 它与 MOS电路相似， 一般是在 N型 基片上生长出两个高浓度的 P型区，通过欧姆接触分别引出源极 S和漏极 D。 在源极和漏极之间有一个多晶硅栅极浮空在 Si02绝缘层中，与四周无直接电 气联接。 这种电路以浮动栅极是否带电来表示存 1或者 0, 浮动栅极带电后 (譬如负电荷），就在其下面，源极和漏极之间感应出正的导电沟道，使 MOS 管导通， 即表示存入 0。 若浮动栅极不带电， 则不形成导电沟道， MOS管不 导通， 即存入 1。
EEPROM基本存储单元（cell ) 电路与 EPROM相似， 它是在 EPROM 基本单元电路的浮动栅极的上面再生成一个浮动栅极， 前者称为第一级浮动 栅极， 后者称为第二级浮动栅极。 可给第二级浮动栅极引出一个电极， 使第 二级浮动栅极接某一电压 VG。 若 VG为正电压， 第一浮动栅极与漏极之间 产生隧道效应，使电子注入第一浮动栅极， 即编程写入。若使 VG为负电压， 第一级浮动栅极的电子将散失， 即擦除。 擦除后可重新写入。
闪存的基本存储单元（cell ) 电路与 EEPROM类似， 也是由双层浮动栅 极 MOS管组成， 但是第一层栅介质很薄， 作为隧道氧化层， 可给第二级浮 动栅极引出一个电极，使第二级浮动栅极接某一电压 VG。 若 VG为正电压， 第一浮动栅极与漏极之间产生隧道效应， 使电子注入第一浮动栅极 , 即编程 写入； 擦除方法是在衬底加正电压（VB ), 利用第一级浮动栅极与源极之间 的隧道效应， 把注入至浮动栅极的负电荷吸引到源极。 随着半导体技术的改 进， 闪存也实现了单晶体管的设计， 主要就是在原有的晶体管上加入了浮动 栅和选择栅，在源极和漏极之间电流单向传导的半导体上形成贮存电子的浮 动棚。 浮动栅包裹着一层硅氧化膜绝缘体。 它的上面是在源极和漏极之间控 制传导电流的选择 /控制栅。数据是 0或 1取决于在硅底板上形成的浮动栅中 是否有电子。 有电子为 0, 无电子为 1。
下面 ,通过以下各个实施例分别对本申请提出的非易失性存储器的擦除 方法和装置进行详细介绍。 需要说明的是， 以下各个实施例均以闪存为例进 行介绍， 但是， 本申请中并不限定于闪存这一种非易失性存储器。 实施例一：
参照图 1 , 示出了本申请实施例一的一种非易失性存储器的擦除方法的 流程图， 该方法具体可以包括以下步骤：
步骤 101 , 在接收到擦除指令后， 对所述擦除指令对应的目标擦除区域 执行预读校验。
若所述预读校验通过， 则执行步骤 102; 若所述预读校验未通过， 则执 行步骤 103。
在目前的技术中， 为了避免在执行擦除操作之前目标擦除区域内既有 Erase cell又有 Pgm cell , 而导致擦除操作完成之后目标擦除区域内存储单元 的阈值电压的收敛性较差的问题，通常在执行擦除操作之前先执行预编程过 程以提高目标擦除区域内存储单元的阈值电压的收敛性。 但是， 如果目标擦 除区域处于全擦除状态， 则上述的预编程过程将会造成不必要的时间开销。
针对上述问题， 本申请实施例中， 如果非易失性存储器在正常运行过程 中接收到擦除指令， 则首先对所述擦除指令对应的目标擦除区域执行预读校 验， 而并非直接对目标擦除区域执行预编程过程。
步骤 102, 对所述目标擦除区域执行擦除操作。
如果在步骤 101中， 所述预读校验通过， 则可以说明此时目标擦除区域 内存储单元的阈值电压本身的收敛性就比较高， 因此可以跳过预编程过程， 直接对所述目标擦除区域执行擦除操作，在擦除操作后即可以保证目标擦除 区域内存储单元的阈值电压收敛性较高。
步骤 103 , 对所述目标擦除区域执行预编程校验， 并在所述预编程校验 通过后， 对所述目标擦除区域执行擦除操作。
如果在步骤 101中， 所述预读校验未通过， 则可以说明此时目标擦除区 域内的存储单元中既有 Erase cell又有 Pgm cell,因此可以对所述目标擦除区 域执行预编程校验。 如果所述预编程校验未通过， 则对所述目标擦除区域执 行预编程操作， 以将其中的 Erase cell编程为 Pgm cell,从而保证擦除操作之 前目标擦除区域内的存储单元的阈值电压的收敛性； 如果所述预编程校验通 因此对所述目标擦除区域执行擦除操作。
由于本申请实施例中在进行预编程校验之前， 首先进行预读校验， 如果 预读校验通过， 则可以跳过预编程校验过程， 直接执行擦除操作， 从而可以 保证在擦除操作之前目标擦除区域处于全擦除状态的情况下， 不再执行不必 要的预编程校验过程， 节省擦除时间， 擦除过程更加简单。 实施例二：
参照图 2, 示出了本申请实施例二的一种非易失性存储器的擦除方法的 流程图， 该方法具体可以包括以下步骤：
步骤 201 , 接收擦除指令。
步骤 202, 对所述擦除指令对应的目标擦除区域执行预读校验。
若所述预读校验未通过， 则执行步骤 203; 若所述预读校验通过， 则执 行步骤 205。
非易失性存储器在正常运行过程中， 如果需要对其进行擦除操作， 则将 接收到擦除指令， 该擦除指令中可以包括目标擦除区域地址等信息， 根据所 述目标擦除区域地址即可查找到所述擦除指令对应的目标擦除区域。在本申 请实施例中，所述目标擦除区域可以为片（chip )、块（block )或扇区（sector )。
在接收到擦除指令后，首先可以对所述擦除指令对应的目标擦除区域执 行预读校验 ( PRE RD )。 在本申请的一种优选实施例中 , 该步骤 202具体可 以包括：依据预先设置的预读校验基准电压对所述目标擦除区域执行预读校 验。
在本申请的一种优选实施例中，上述依据预先设置的预读校验基准电压 对所述目标擦除区域执行预读校验的步骤具体可以包括以下子步骤： 否小于所述预读校验基准电压；
子步骤 a2, 若所有存储单元的阈值电压均小于所述预读校验基准电压， 则确定所述预读校验通过； 否则， 确定所述预读校验未通过。
如果所有存储单元的阈值电压均小于所述预读校验基准电压，则可以说 标擦除区域处于全擦除状态）， 因此可以确定所述预读校验通过。 如果目标 擦除区域内存在阈值电压大于或等于所述预读校验基准电压的存储单元， 则 确定所述预读校验未通过。
由于非易失性存储器中存储单元的电流特性类似于 MOS管， 当栅极和 源极的电压差小于阈值电压时， 管子关闭， 此时没有电流。 因此判断一个存 储单元的阈值电压， 只需要在栅极上加上某个设定的电压， 然后判断漏极上 的电流大小就可以了。
例如， 上述子步骤 al可以包括以下子步骤：
子步骤 all , 针对所述目标擦除区域内的每个存储单元， 分别在该存储 单元的栅极施加预先设置的预读校验电压， 并检测该存储单元的漏极电流； 子步骤 al2, 若该存储单元的漏极电流大于预先设置的预读校验基准电 流， 则确定该存储单元的阈值电压小于所述预读校验基准电压； 若该存储单 元的漏极电流小于或等于预先设置的预读校验基准电流， 则确定该存储单元 的阈值电压大于或等于所述预读校验基准电压。
参照图 3 , 示出了一种非易失性存储器的结构示意图， 该非易失性存储 器中可以包括 16个存储单元（MN1、 MN2 MN3 MN4 MN16 ) 4 条位线（BU、 BL2 BL3 BL4 ) 以及 4条字线（WL1、 WL2 WL3 WL4 )。 其中， 存储单元组成存储单元阵列， 阵列中同一行的存储单元的栅极连接在 同一条字线上， 同一列的存储单元的漏极连接在同一条位线上。 非易失性存 储器的擦除操作按块进行， 即每次对一个擦除区域内的各个存储单元进行擦 除操作。
需要说明的是， 为节省篇幅， 在图 3所示的非易失性存储器中， 仅以包 括 16个存储单元（ MN1、 MN2、 MN3、 MN4 MN16 ) 4条位线（ BL1、
BL2 BL3 BL4 )、 以及 4条字线 ( WL1 WL2 WL3 WL4 ) 的结构进行 举例说明， 但是本申请实施例中的非易失性存储器并不限定于上述结构， 其 中包括的存储单元、 字线以及位线也可以为其他数量。
如果针对图 3所示的结构， 则上述子步骤 all中即可以依次在目标擦除 区域内的字线上施加预先设置的预读校验电压， 然后再检测每条位线上的电 流。 例如， 首先在目标擦除区域内的字线 WL1上施加预先设置的预读校验 电压， 此时即相当于在第一行中每个存储单元的栅极施加预先设置的预读校 验电压； 然后分别检测目标擦除区域内各条位线上的电流， 其中位线 BL1 上的电流相当于存储单元 MN1的漏极电流， 位线 BL2上的电流相当于存储 单元 MN2的漏极电流， 位线 BL3上的电流相当于存储单元 MN3的漏极电 流， 位线 BL4上的电流相当于存储单元 MN4的漏极电流。 对于目标擦除区 域内其他存储单元的处理方法的与上述过程基本相同， 本申请实施例在此不 再详细论述。 需要说明的是， 在上述检测过程中， 目标擦除区域内各个存储 单元的源极是接地的， 并且在某一条字线上施加预先设置的预读校验电压 时， 其它字线上不施加电压， 即要保证未与施加预先设置的预读校验电压的 字线连接的存储单元的漏极不产生电流。
对于该步骤 202中所涉及到的预读校验基准电压、 预读校验电压、 预读 可， 不同的非易失性存储器对应的数值可能不同， 本申请实施例对具体的数 值并不加以限定。
步骤 203 , 对所述目标擦除区域执行预编程校验。
若所述预编程校验未通过， 则执行步骤 204; 若所述预编程校验通过， 则执行步骤 205。
如果在步骤 202中所述预读校验未通过，则可以说明此时目标擦除区域 内存储单元的阈值电压的收敛性较差， 因此可以通过对所述目标擦除区域执 行预编程校验（PRE— V )过程， 以提高存储单元的阈值电压的收敛性。 在本 申请的一种优选实施例中， 该步骤 203具体可以包括： 依据预先设置的预编 程校验基准电压对所述目标擦除区域执行预编程校验。
在本申请的一种优选实施例中，上述依据预先设置的预编程校验基准电 压对所述目标擦除区域执行预编程校验的步骤具体可以包括以下子步骤： 否大于所述预编程校验基准电压；
子步骤 b2, 若所有存储单元的阈值电压均大于所述预编程校验基准电 压， 则确定所述预编程校验通过； 否则， 确定所述预编程校验未通过。
所述预编程校验的目的是校验预编程操作是否成功，如果所有存储单元 的阈值电压均大于所述预编程校验基准电压， 则可以确定所述预编程校验通 过； 如果目标擦除区域内存在阈值电压小于或等于所述预编程校验基准电压 的存储单元， 则可以确定所述预编程校验未通过。
上述子步骤 bl可以包括以下子步骤： 子步骤 bll , 针对所述目标擦除区域内的每个存储单元， 分别在该存储 单元的栅极施加预先设置的预编程校验电压 , 并检测该存储单元的漏极电 流;
子步骤 bl2, 若该存储单元的漏极电流小于预先设置的预编程校验基准 电流， 则确定该存储单元的阈值电压大于所述预编程校验基准电压； 若该存 储单元的漏极电流大于或等于预先设置的预编程校验基准电流， 则确定该存 储单元的阈值电压 d、于或等于所述预编程校验基准电压。
例如， 针对图 3所示的结构， 上述子步骤 bll中即可以依次在目标擦除 区域内的字线上施加预先设置的预编程校验电压， 然后再检测每条位线上的 电流。 具体过程参照上述步骤 202中的相关描述即可， 本申请实施例在此不 再详细论述。
对于该步骤 203中所涉及到的预编程校验基准电压、 预编程校验电压、 预编程校验基准电流的具体取值， 本领域技术人员根据实际经验进行相关设 定即可， 不同的非易失性存储器对应的数值可能不同， 本申请实施例对具体 的数值并不加以限定。
步骤 204, 对所述目标擦除区域执行预编程操作。
如果步骤 203中所述预编程校验未通过，则可以说明预编程操作未成功， 此时即可对所述目标擦除区域执行预编程操作， 所述预编程操作是指对目标 擦除区域中的存储单元写入 0, 的目的是将目标擦除区域内的所有存储单元 的阈值电压编程到大于预编程校险基准电压。
本申请实施例中， 所述预编程操作的具体过程可以包括： 在所述目标擦 除区域内的所有存储单元的栅极施加栅极预编程电压，在所述目标擦除区域 内的所有存储单元的漏极施加漏极预编程电压。 例如， 可以在栅极施加 9V 的电压， 在漏极施加 4V的电压， 具体数值根据工艺的不同取值不同。
在执行所述预编程操作之后， 即可以返回所述步骤 203 , 再次对所述目 标擦除区域执行预编程校验。
步骤 205 , 对所述目标擦除区域执行擦除校验。
若所述擦除校验未通过， 则执行步骤 206; 若所述擦除校验通过， 则执 行步骤 207。
如果在步骤 202中所述预读校验通过， 则可以说明此时目标擦除区域内 存储单元的阈值电压本身的收敛性较高（例如此时目标擦除区域处于全擦除 状态）， 因此可以跳过预编程校验过程， 直接对所述目标擦除区域执行擦除 校验（EV )。 如果在步骤 203中所述预编程校验通过， 则可以说明此时预编 于预编程校验基准电压， 此时也可以对所述目标擦除区域执行擦除校验。 本 申请实施例中， 该步骤 205具体可以包括： 依据预先设置的擦除校验基准电 压对所述目标擦除区域执行擦除校验。
在本申请的一种优选实施例中，上述依据预先设置的擦除校验基准电压 对所述目标擦除区域执行擦除校验的步骤具体可以包括以下子步骤： 否小于所述擦除校验基准电压；
子步骤 c2, 若所有存储单元的阈值电压均小于所述擦除校验基准电压， 则确定所述擦除校验通过； 否则， 确定所述擦除校验未通过。
所述擦除校验的目的是校验擦除操作是否成功，如果所有存储单元的阈 值电压均小于所述擦除校验基准电压， 则可以确定所述擦除校验通过； 如果 目标擦除区域内存在阈值电压大于或等于所述擦除校验基准电压的存储单 元， 则可以确定所述擦除校验未通过。
上述子步骤 cl可以包括以下子步骤：
子步骤 cl l , 针对所述目标擦除区域内的每个存储单元， 分别在该存储 单元的栅极施加预先设置的擦除校验电压， 并检测该存储单元的漏极电流； 子步骤 cl2, 若该存储单元的漏极电流大于预先设置的擦除校验基准电 流， 则确定该存储单元的阈值电压小于所述擦除校验基准电压； 若该存储单 元的漏极电流小于或等于预先设置的擦除校验基准电流， 则确定该存储单元 的阈值电压大于或等于所述擦除校验基准电压。
例如， 针对图 3所示的结构， 上述子步骤 cl l中即可以依次在目标擦除 区域内的字线上施加预先设置的擦除校验电压， 然后再检测每条位线上的电 流。 具体过程参照上述步骤 202中的相关描述即可， 本申请实施例在此不再 详细论述。
对于该步骤 205中所涉及到的擦除校验基准电压、 擦除校验电压、 擦除 可， 不同的非易失性存储器对应的数值可能不同， 本申请实施例对具体的数 值并不加以限定。
在本申请的一种优选实施例中，所述预读校验基准电压大于或等于所述 擦除校验基准电压， 并且小于或等于所述预编程校验基准电压。
步骤 206, 对所述目标擦除区域执行擦除操作。
如果步骤 205中所述擦除校验未通过， 则可以说明擦除操作未成功， 此 时即可对所述目标擦除区域执行擦除操作， 所述擦除操作是指对目标擦除区 域中的存储单元写入 1 , 目的是将目标擦除区域内的所有存储单元的阈值电 压擦除到 d、于擦除校验基准电压。
本申请实施例中， 所述擦除操作的具体过程可以包括： 在所述目标擦除 区域内的所有存储单元的栅极施加栅极擦除电压，在所述目标擦除区域内的 所有存储单元的衬底施加漏极擦除电压。例如，可以在栅极施加 -9V的电压， 在衬底施加 4V的电压， 具体数值根据工艺的不同取值不同。
在执行所述擦除操作之后， 即可以返回步骤 205 , 再次对所述目标擦除 区域执行擦除校验。
步骤 207, 结束擦除操作过程。
如果步骤 205中所述擦除校验通过， 则可以说明擦除操作成功， 因此可 以结束擦除操作过程。
上述过程中， 也可以先执行步骤 204, 再执行步骤 203 , 即若步骤 202 中预读校验未通过， 则可以执行步骤 204, 在执行完步骤 204之后继续执行 步骤 203 , 若步骤 203中预编程校验未通过， 则返回执行步骤 204, 若步骤 203 中预编程校验通过， 则执行步骤 205。 上述过程中， 也可以先执行步骤 206, 再执行步骤 205 , 即若步骤 203 中预读校验未通过， 则可以执行步骤 206,在执行完步骤 206之后继续执行步骤 205 ,若步骤 205中擦除校验未通 过， 则返回执行步骤 206, 若步骤 205中擦除校验通过， 则执行步骤 207。 另外， 在本申请的一种优选实施例中， 在步骤 206对所述目标擦除区域 执行擦除操作之后， 还可以对所述目标擦除区域执行过擦除校验 ( OEV ), 所述过擦除校验是指调整目标擦除区域中存储单元的阈值电压， 进行 OEV 的目的是对可能存在的 , 被过擦除了的阈值低于 0V的存储单元进行一次较 弱的编程， 将其阈值推到 0V以上。 具体操作的方法可以为在存储单元的栅 极和漏极施加 OEV编程电压（例如， 可以在栅极施加 0V, 漏极施加 4V左 右， 随具体工艺不同而不同）。 对于具体的过擦除校验过程， 本申请实施例 不再详细论述。
本申请实施例所述的方法可以保证在擦除操作之前目标擦除区域处于 全擦除状态的情况下， 不再执行不必要的预编程校验过程， 节省擦除时间， 擦除过程更加简单。
对于前述的各方法实施例， 为了简单描述， 故将其都表述为一系列的动 作组合， 但是本领域技术人员应该知悉， 本申请并不受所描述的动作顺序的 限制， 因为依据本申请， 某些步骤可以釆用其他顺序或者同时进行。 其次， 本领域技术人员也应该知悉， 说明书中所描述的实施例均属于优选实施例， 所涉及的动作和模块并不一定是本申请所必须的。 实施例三：
参照图 4, 示出了本申请实施例三的一种非易失性存储器的擦除装置的 结构框图， 该装置具体可以包括以下模块：
预读校验模块 401 , 配置为在接收到擦除指令后， 对所述擦除指令对应 的目标擦除区域执行预读校验；
擦除模块 402, 配置为在所述预读校验通过时， 对所述目标擦除区域执 行擦除操作；
预编程校验模块 403 , 配置为在所述预读校验未通过时， 对所述目标擦 除区域执行预编程校验；
所述擦除模块， 还配置为在所述预编程校验通过后， 对所述目标擦除区 域执行擦除操作。
在本申请的一种优选实施例中， 所述装置还可以包括以下模块： 预编程模块， 配置为在所述预编程校验未通过时， 对所述目标擦除区域 执行预编程操作；
所述预编程校验模块，还配置为在所述预编程模块对所述目标擦除区域 执行所述预编程操作之后， 对所述目标擦除区域执行预编程校验；
擦除校验模块， 配置为在所述擦除模块对所述目标擦除区域执行擦除操 作之前， 对所述目标擦除区域执行擦除校验；
所述擦除模块， 还配置为在所述擦除校验未通过时， 对所述目标擦除区 域执行擦除操作；
所述擦除校验模块，还配置为在所述擦除模块对所述目标擦除区域执行 所述擦除操作之后， 对所述目标擦除区域执行擦除校验。
其中， 所述预读校验模块， 具体配置为依据预先设置的预读校验基准电 压对所述目标擦除区域执行预读校验；
所述预编程校验模块，具体配置为依据预先设置的预编程校验基准电压 对所述目标擦除区域执行预编程校验；
所述擦除校验模块，具体配置为依据预先设置的擦除校验基准电压对所 述目标擦除区域执行擦除校验；
其中， 所述擦除校验基准电压小于或等于所述预读校验基准电压， 并且 大于或等于所述预读校验基准电压。
在本申请的一种优选实施例中， 所述预读校验模块可以包括以下模块： 电压校验模块， 配置为分别校验所述目标擦除区域内的每个存储单元的 阈值电压是否小于所述预读校验基准电压；
确定模块， 配置为在所有存储单元的阈值电压均小于所述预读校验基准 电压时， 确定所述预读校验通过； 否则， 确定所述预读校验未通过。
所述电压校验模块包括以下模块：
检测模块， 配置为针对所述目标擦除区域内的每个存储单元， 分别在该 存储单元的栅极施加预先设置的预读校验电压， 并检测该存储单元的漏极电 确定模块， 配置为在所述该存储单元的漏极电流大于预先设置的预读校 验基准电流时， 确定该存储单元的阈值电压小于所述预读校验基准电压。
本申请实施例中， 在接收到擦除指令后， 首先对所述擦除指令对应的目 标擦除区域执行预读校验； 如果所述预读校验通过， 则对所述目标擦除区域 执行擦除操作； 如果所述预读校验未通过， 则对所述目标擦除区域执行预编 程校验， 并在所述预编程校验通过后， 对所述目标擦除区域执行擦除操作。 由于本申请实施例中在进行预编程校验之前， 首先进行预读校验， 如果预读 校验通过， 则可以跳过预编程校验过程， 直接执行擦除操作， 从而可以保证 在擦除操作之前目标擦除区域处于全擦除状态的情况下， 不再执行不必要的 预编程校验过程， 节省擦除时间， 擦除过程更加简单。
对于装置实施例而言， 由于其与方法实施例基本相似， 所以描述的比较 简单， 相关之处参见方法实施例的部分说明即可。 本申请实施例还提供了一种在其上记录有用于上述实施例的程序的 计算机可读记录介质。
所述计算机可读记录介质包括用于以计算机（例如计算机） 可读的 形式存储或传送信息的任何机制。 例如， 机器可读介质包括只读存储器
( ROM )、 随机存取存储器 （RAM )、 磁盘存储介质、 光存储介质、 闪速 存储介质、 电、 光、 声或其他形式的传播信号 （例如， 载波、 红外信号、 数字信号等） 等。 本说明书中的各个实施例均釆用递进的方式描述，每个实施例重点说明 的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见 即可。
本申请可以在由计算机执行的计算机可执行指令的一般上下文中描述， 例如程序模块。 一般地， 程序模块包括执行特定任务或实现特定抽象数据类 型的例程、 程序、 对象、 组件、 数据结构等等。 也可以在分布式计算环境中 实践本申请， 在这些分布式计算环境中， 由通过通信网络而被连接的远程处 理设备来执行任务。 在分布式计算环境中， 程序模块可以位于包括存储设备 在内的本地和远程计算机存储介质中。
最后， 还需要说明的是， 在本文中， 诸如第一和第二等之类的关系术语 仅仅用来将一个实体或者操作与另一个实体或操作区分开来， 而不一定要求 或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。 而且， 术 语 "包括"、 "包含" 或者其任何其他变体意在涵盖非排他性的包含， 从而使 得包括一系列要素的过程、 方法、 商品或者设备不仅包括那些要素， 而且还 包括没有明确列出的其他要素， 或者是还包括为这种过程、 方法、 商品或者 设备所固有的要素。 在没有更多限制的情况下， 由语句 "包括一个 ... ... " 限 定的要素， 并不排除在包括所述要素的过程、 方法、 商品或者设备中还存在 另外的相同要素。
以上对本申请所提供的一种非易失性存储器的擦除方法和装置， 进行了 详细介绍， 本文中应用了具体个例对本申请的原理及实施方式进行了阐述， 以上实施例的说明只是用于帮助理解本申请的方法及其核心思想之一； 同 时， 对于本领域的一般技术人员， 依据本申请的思想之一， 在具体实施方式 及应用范围上均会有改变之处， 综上所述， 本说明书内容不应理解为对本申 请的限制。

Claims

权 利 要 求 书
1、 一种非易失性存储器的擦除方法， 其特征在于， 包括：
在接收到擦除指令后，对所述擦除指令对应的目标擦除区域执行预读校 验；
若所述预读校验通过， 则对所述目标擦除区域执行擦除操作； 若所述预读校验未通过， 则对所述目标擦除区域执行预编程校验， 并在 所述预编程校验通过后， 对所述目标擦除区域执行擦除操作。
2、 根据权利要求 1所述的方法， 其特征在于，
所述对所述擦除指令对应的目标擦除区域执行预读校验的步骤包括：依 据预先设置的预读校验基准电压对所述目标擦除区域执行预读校验；
所述对所述目标擦除区域执行预编程校验的步骤包括：依据预先设置的 预编程校验基准电压对所述目标擦除区域执行预编程校验；
其中， 所述预读校验基准电压小于或等于所述预编程校验基准电压。
3、 根据权利要求 2所述的方法， 其特征在于， 所述目标擦除区域包括 多个存储单元，
所述依据预先设置的预读校验基准电压对所述目标擦除区域执行预读 校验的步骤包括： 述预读校验基准电压；
若所有存储单元的阈值电压均小于所述预读校验基准电压，则确定所述 预读校验通过； 否则， 确定所述预读校验未通过。
4、 根据权利要求 3所述的方法， 其特征在于， 所述分别校验所述目标 擦除区域内的每个存储单元的阈值电压是否小于所述预读校验基准电压的 步骤包括：
针对所述目标擦除区域内的每个存储单元，分别在该存储单元的栅极施 加预先设置的预读校验电压， 并检测该存储单元的漏极电流；
若所述该存储单元的漏极电流大于预先设置的预读校验基准电流， 则确 定该存储单元的阈值电压小于所述预读校验基准电压。
5、 根据权利要求 2所述的方法， 其特征在于， 在所述对所述目标擦除 区域执行擦除操作之前， 还包括：
对所述目标擦除区域执行擦除校验；
若所述擦除校验未通过，则执行所述对所述目标擦除区域执行擦除操作 的步骤；
在执行所述擦除操作之后，返回所述对所述目标擦除区域执行擦除校验 的步骤。
6、 根据权利要求 5所述的方法， 其特征在于， 所述对所述目标擦除区 域执行擦除校验的步骤包括：
依据预先设置的擦除校验基准电压对所述目标擦除区域执行擦除校验； 其中， 所述擦除校验基准电压小于或等于所述预读校验基准电压。
7、 根据权利要求 1所述的方法， 其特征在于， 在所述对所述目标擦除 区域执行预编程校验之后， 还包括：
若所述预编程校验未通过， 则对所述目标擦除区域执行预编程操作； 在执行所述预编程操作之后 ,返回所述对所述目标擦除区域执行预编程 校验的步骤。
8、 一种非易失性存储器的擦除装置， 其特征在于， 包括：
预读校验模块， 配置为在接收到擦除指令后， 对所述擦除指令对应的目 标擦除区域执行预读校验；
擦除模块， 配置为在所述预读校验通过时， 对所述目标擦除区域执行擦 除操作；
预编程校验模块， 配置为在所述预读校验未通过时， 对所述目标擦除区 域执行预编程校验；
所述擦除模块， 还配置为在所述预编程校验通过后， 对所述目标擦除区 域执行擦除操作。
9、 根据权利要求 8所述的装置， 其特征在于，
所述预读校验模块，具体配置为依据预先设置的预读校验基准电压对所 述目标擦除区域执行预读校验；
所述预编程校验模块，具体配置为依据预先设置的预编程校验基准电压 对所述目标擦除区域执行预编程校验；
其中， 所述预读校验基准电压小于或等于所述预编程校验基准电压。
10、 根据权利要求 9所述的装置， 其特征在于， 所述目标擦除区域包括 多个存储单元，
所述预读校验模块包括：
电压校验模块， 配置为分别校验所述目标擦除区域内的每个存储单元的 阈值电压是否小于所述预读校验基准电压；
确定模块， 配置为在所有存储单元的阈值电压均小于所述预读校验基准 电压时， 确定所述预读校验通过； 否则， 确定所述预读校验未通过。
11、 根据权利要求 10所述的装置， 其特征在于， 所述电压校验模块包 括：
检测模块， 配置为针对所述目标擦除区域内的每个存储单元， 分别在该 存储单元的栅极施加预先设置的预读校验电压， 并检测该存储单元的漏极电 流;
确定模块， 配置为在所述该存储单元的漏极电流大于预先设置的预读校 验基准电流时， 确定该存储单元的阈值电压小于所述预读校验基准电压。
12、 根据权利要求 9所述的装置， 其特征在于， 还包括：
擦除校验模块， 配置为在所述擦除模块对所述目标擦除区域执行擦除操 作之前， 对所述目标擦除区域执行擦除校验；
所述擦除模块， 还配置为在所述擦除校验未通过时， 对所述目标擦除区 域执行擦除操作；
所述擦除校验模块，还配置为在所述擦除模块对所述目标擦除区域执行 所述擦除操作之后， 对所述目标擦除区域执行擦除校验。
13、 根据权利要求 12所述的装置， 其特征在于， 所述擦除校验模块， 具体配置为依据预先设置的擦除校验基准电压对所述目标擦除区域执行擦 除校验；
其中， 所述擦除校验基准电压小于或等于所述预读校验基准电压。
14、 根据权利要求 8所述的装置， 其特征在于， 还包括： 预编程模块， 配置为在所述预编程校验未通过时， 对所述目标擦除区域 执行预编程操作；
所述预编程校验模块，还配置为在所述预编程模块对所述目标擦除区域 执行所述预编程操作之后， 对所述目标擦除区域执行预编程校验。
15、 一种在其上记录有用于执行权利要求 1 所述方法的程序的计算 机可读记录介质。
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