WO2015115360A1 - 太陽電池 - Google Patents
太陽電池 Download PDFInfo
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- WO2015115360A1 WO2015115360A1 PCT/JP2015/052006 JP2015052006W WO2015115360A1 WO 2015115360 A1 WO2015115360 A1 WO 2015115360A1 JP 2015052006 W JP2015052006 W JP 2015052006W WO 2015115360 A1 WO2015115360 A1 WO 2015115360A1
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- Prior art keywords
- semiconductor layer
- layer
- electrode
- conductivity type
- solar cell
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- 239000004065 semiconductor Substances 0.000 claims abstract description 185
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 230000007423 decrease Effects 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 200
- 238000000034 method Methods 0.000 description 21
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000005530 etching Methods 0.000 description 8
- 238000000926 separation method Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000000969 carrier Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 239000010953 base metal Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000002585 base Substances 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to a solar cell.
- a so-called back junction solar cell in which an n-type semiconductor layer and a p-type semiconductor layer are formed on the back surface of a semiconductor substrate is known (eg, Patent Document 1).
- an insulating layer is generally provided in a boundary region between an n-type semiconductor layer and a p-type semiconductor layer.
- the n-side electrode connected to the n-type semiconductor layer and the p-side electrode connected to the p-type semiconductor layer are also formed above the insulating layer.
- n-side electrode or the p-side electrode is formed by a sputtering method, a CVD method, or the like, there is a problem that cutting or peeling occurs at a step portion due to the side surface of the insulating layer.
- An object of the present invention is to provide a solar cell that can prevent the electrode from being cut or peeled off by an insulating layer.
- the present invention is formed on a first conductive type or second conductive type semiconductor substrate having a light receiving surface and a back surface, a first semiconductor layer having a first conductivity type formed on the back surface, and the back surface.
- a second semiconductor layer having a second conductivity type, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and the first electrode A solar cell comprising a first conductivity type region in which a semiconductor layer is provided and an insulating layer provided in a boundary region of the second conductivity type region in which the second semiconductor layer is provided, wherein the second conductivity type of the insulation layer
- the side surface on the region side has an inclined surface that is inclined so that the thickness decreases as it approaches the second conductivity type region, and the inclined surface in a direction perpendicular to the thickness direction and toward the second conductivity type region In the portion where the inclined surface is not formed Serial is in the range of 10 to 300 times the thickness of the insulating layer.
- the electrode can be prevented from being cut or peeled off by the insulating layer.
- FIG. 1 is a top view which looked at the solar cell of an embodiment from the back side.
- FIG. 2 is a cross-sectional view showing the solar cell of the embodiment, and is a cross-sectional view taken along the line A-A ′ of FIG.
- FIG. 3 is a flowchart showing a manufacturing process of the solar cell of the embodiment.
- FIG. 4 is a cross-sectional view for explaining the method for manufacturing the solar cell of the embodiment.
- FIG. 5 is a cross-sectional view for explaining the method for manufacturing the solar cell of the embodiment.
- FIG. 6 is a cross-sectional view for explaining the method for manufacturing the solar cell of the embodiment.
- Drawing 7 is a sectional view for explaining the manufacturing method of the solar cell of an embodiment.
- FIG. 1 is a top view which looked at the solar cell of an embodiment from the back side.
- FIG. 2 is a cross-sectional view showing the solar cell of the embodiment, and is a cross-sectional view taken along the line A-A ′ of FIG
- FIG. 8 is a cross-sectional view for explaining the method for manufacturing the solar cell of the embodiment.
- FIG. 9 is a cross-sectional view for explaining the method for manufacturing the solar cell of the embodiment.
- FIG. 10 is a cross-sectional view for explaining the method for manufacturing the solar cell of the embodiment.
- FIG. 1 is a plan view of the solar cell of the embodiment as viewed from the back side.
- FIG. 2 is a cross-sectional view showing the solar cell of the embodiment, and is a cross-sectional view taken along the line A-A ′ of FIG.
- the solar cell 1 includes a semiconductor substrate 10n, a first semiconductor layer 20n, a second semiconductor layer 30p, an insulating layer 40, a first electrode 50n, a second electrode 50p, a connection electrode 70n, A connection electrode 70p is provided.
- the semiconductor substrate 10n has a light receiving surface for receiving light and a back surface 12 provided on the side opposite to the light receiving surface.
- the semiconductor substrate 10n generates carriers (electrons and holes) by receiving light on the light receiving surface.
- the semiconductor substrate 10n may be formed of a general semiconductor material including a crystalline semiconductor material such as single crystal Si or polycrystalline Si having n-type or p-type conductivity, or a compound semiconductor material such as GaAs or InP. it can. Minute irregularities may be formed on the light receiving surface and the back surface 12 of the semiconductor substrate 10n.
- a structure for example, an electrode
- the semiconductor substrate 10n can receive light over the entire light receiving surface.
- the light receiving surface may be covered with a passivation layer.
- the passivation layer has a passivation property that suppresses carrier recombination.
- the passivation layer can include, for example, a substantially intrinsic amorphous semiconductor layer formed by adding no dopant or adding a small amount of dopant.
- the semiconductor substrate 10n is of the first conductivity type or the second conductivity type.
- the semiconductor substrate 10n has the first conductivity type will be described. Further, description will be made assuming that the semiconductor substrate 10n is an n-type single crystal silicon substrate. Therefore, in the present embodiment, the first conductivity type is n-type.
- the first semiconductor layer 20n is formed on the back surface 12 of the semiconductor substrate 10n.
- the first semiconductor layer 20n is formed to have a longitudinal direction. This longitudinal direction is defined as a longitudinal direction y.
- the first semiconductor layer 20n has the same first conductivity type as the semiconductor substrate 10n.
- the first semiconductor layer 20n is composed of an n-type amorphous semiconductor layer. According to such a configuration, recombination of carriers at the interface between the back surface 12 of the semiconductor substrate 10n and the first semiconductor layer 20n can be suppressed.
- the second semiconductor layer 30p is formed on the back surface 12 of the semiconductor substrate 10n.
- the second semiconductor layer 30p is formed to have the longitudinal direction y.
- the second semiconductor layer 30p has a second conductivity type different from that of the semiconductor substrate 10n.
- the second semiconductor layer 30p is configured by a p-type amorphous semiconductor layer. For this reason, the junction between the semiconductor substrate 10n and the second semiconductor layer 30p is a pn junction.
- the second semiconductor layer 30p is also formed on the insulating layer 40.
- the first semiconductor layer 20n includes an i-type amorphous semiconductor layer 22i and an n-type amorphous semiconductor layer 25n.
- the i-type amorphous semiconductor layer 22i is formed on the back surface 12 of the semiconductor substrate 10n.
- the n-type amorphous semiconductor layer 25n is formed on the i-type amorphous semiconductor layer 22i. According to such a configuration of the n-type semiconductor substrate 10n, the i-type amorphous semiconductor layer 22i, and the n-type amorphous semiconductor layer 25n, carrier recombination on the back surface of the semiconductor substrate 10n can be further suppressed. it can.
- the second semiconductor layer 30p includes an i-type amorphous semiconductor layer 32i and a p-type amorphous semiconductor layer 35p.
- the i-type amorphous semiconductor layer 32i is formed on the back surface 12 of the semiconductor substrate 10n.
- the p-type amorphous semiconductor layer 35p is formed on the i-type amorphous semiconductor layer 32i. According to such a configuration of the n-type semiconductor substrate 10n, the i-type amorphous semiconductor layer 32i, and the p-type amorphous semiconductor layer 35p, the pn junction characteristics can be improved.
- Each of the i-type amorphous semiconductor layer 22i, the i-type amorphous semiconductor layer 32i, the n-type amorphous semiconductor layer 25n, and the p-type amorphous semiconductor layer 35p may be composed of an amorphous semiconductor containing hydrogen. it can.
- Examples of such an amorphous semiconductor include amorphous silicon, amorphous silicon carbide, and amorphous silicon germanium.
- the amorphous semiconductor layer is not limited to this, and other amorphous semiconductors may be used.
- the i-type amorphous semiconductor layer 22i, the i-type amorphous semiconductor layer 32i, the n-type amorphous semiconductor layer 25n, and the p-type amorphous semiconductor layer 35p are each composed of one kind of amorphous semiconductor. Also good.
- the i-type amorphous semiconductor layer 22i, the i-type amorphous semiconductor layer 32i, the n-type amorphous semiconductor layer 25n, and the p-type amorphous semiconductor layer 35p each include a combination of two or more types of amorphous semiconductors. May be.
- the first semiconductor layers 20n and the second semiconductor layers 30p are alternately arranged.
- This arrangement direction is defined as an arrangement direction x.
- the arrangement direction x and the longitudinal direction y are orthogonal to each other.
- a first conductivity type region Rn in which the first semiconductor layer 20n is provided and a second conductivity type region Rp in which the second semiconductor layer 30p is provided are formed.
- a boundary region R is provided between the first conductivity type region Rn and the second conductivity type region Rp.
- the insulating layer 40 is provided between the end portion 27 of the first semiconductor layer 20n and the end portion 37 of the second semiconductor layer 30p.
- the insulating layer 40 can be formed from aluminum nitride, silicon nitride, silicon oxide, or the like.
- the first electrode 50n is electrically connected to the first semiconductor layer 20n. As shown in FIG. 1, the first electrode 50 n is formed along the longitudinal direction y.
- the first electrode 50n includes a first transparent electrode layer 52n and a first collection electrode 55n.
- the first transparent electrode layer 52n is formed on the first semiconductor layer 20n. Further, it is also formed on the second semiconductor layer 30p formed on the insulating layer 40.
- the first transparent electrode layer 52n is formed of a light-transmitting conductive material.
- ITO indium tin oxide
- tin oxide tin oxide
- zinc oxide zinc oxide
- the first collecting electrode 55n is formed on the first transparent electrode layer 52n.
- the first collecting electrode 55n may be formed by vapor-depositing a resin-type conductive paste using a resin material as a binder and using conductive particles such as silver particles as a filler, or silver by sputtering.
- the second electrode 50p is electrically connected to the second semiconductor layer 30p. As shown in FIG. 1, the second electrode 50 p is formed along the longitudinal direction y.
- the second electrode 50p includes a second transparent electrode layer 52p and a second collection electrode 55p.
- the second transparent electrode layer 52p is formed on the second semiconductor layer 30p.
- the second transparent electrode layer 52p is also formed on the second semiconductor layer 30p formed on the insulating layer 40.
- the second collection electrode 55p is formed on the second transparent electrode layer 52p.
- the second transparent electrode layer 52p and the second collection electrode 55p can be made of the same material as the first transparent electrode layer 52n and the first collection electrode 55n, respectively.
- first transparent electrode layer 52n and the second transparent electrode layer 52p in the first electrode 50n and the second electrode 50p are not necessarily transparent, and may be formed of a material that is not transparent.
- the first electrode 50n and the second electrode 50p collect carriers.
- the first electrode 50n and the second electrode 50p are separated by a separation groove 60 for preventing a short circuit.
- the separation groove 60 is formed along the longitudinal direction y.
- connection electrode 70n is electrically connected to the ends of the plurality of first electrodes 50n.
- the connection electrode 70p is electrically connected to the ends of the plurality of second electrodes 50p.
- the connection electrode 70n and the connection electrode 70p further collect carriers collected by the plurality of first electrodes 50n and the plurality of second electrodes 50p.
- the side surface of the insulating layer 40 on the second conductivity type region Rp side has an inclined surface 40a that is inclined so that the thickness becomes thinner as it approaches the second conductivity type region Rp. ing. Further, the width W of the inclined surface 40a in the direction perpendicular to the thickness direction z and toward the second conductivity type region Rp (arrangement direction x) is 10 of the thickness T of the insulating layer 40 in the portion where the inclined surface 40a is not formed. It is in the range of up to 300 times.
- the second transparent electrode layer 52p is formed thereon by a sputtering method, a CVD method, or the like. When it does, it can suppress that a cutting
- the width W of the inclined surface 40a is in the range of 10 to 300 times the thickness T of the insulating layer 40, preferably in the range of 50 to 200 times, and more preferably in the range of 100 to 200 times. Is within the range. If the width W of the inclined surface 40a is too small, the second transparent electrode layer 52p may be easily cut or peeled off. Further, if the width W of the inclined surface 40a is too large, the insulation resistance may be reduced.
- FIG. 3 is a flowchart for explaining a method for manufacturing the solar cell 1 of the present embodiment.
- 4-10 is a figure for demonstrating the manufacturing method of the solar cell 1 of this embodiment.
- the method for manufacturing the solar cell 1 includes steps S1 to S4.
- Step S1 is a step of forming the first semiconductor layer 20n having the first conductivity type on the back surface 12 of the first conductivity type semiconductor substrate 10n.
- the semiconductor substrate 10n is prepared. In order to remove dirt on the surface of the semiconductor substrate 10n, the semiconductor substrate 10n is etched with an acid or an alkali solution. A texture structure for reducing light reflection is formed on the light receiving surface of the semiconductor substrate 10n. The back surface 12 of the semiconductor substrate 10n is flatter than the light receiving surface.
- An i-type amorphous semiconductor layer 22i is formed on the back surface 12 of the prepared semiconductor substrate 10n.
- An n-type amorphous semiconductor layer 25n is formed on the formed i-type amorphous semiconductor layer 22i.
- the i-type amorphous semiconductor layer 22i and the n-type amorphous semiconductor layer 25n are formed by, for example, chemical vapor deposition (CVD).
- CVD chemical vapor deposition
- Step S2 is a step of forming an insulating layer 40 having insulating properties.
- the insulating layer 40 is formed on the formed first semiconductor layer 20n. Specifically, as shown in FIG. 4, the insulating layer 40 is formed on the n-type amorphous semiconductor layer 25n.
- the insulating layer 40 is formed by, for example, a CVD method.
- Step S3 is a step of forming the second semiconductor layer 30p having the second conductivity type on the back surface 12 of the first conductivity type semiconductor substrate 10n.
- Step S3 includes steps S31 to S33.
- Step S31 is a step of removing the insulating layer 40 formed on the first semiconductor layer 20n.
- an etching paste 41 is applied to a region where the insulating layer 40 is to be removed.
- the etching paste 41 is inclined so that the thickness gradually decreases.
- the insulating layer 40 is removed using the etching paste 41 and the inclined surface 40a is formed on the insulating layer 40, but the present invention is not limited to this.
- the insulating layer 40 may be removed and the inclined surface 40 a may be formed on the insulating layer 40 by a pattern formation method using a resist. Further, the inclined surface 40a may be formed on the insulating layer 40 by other methods.
- Step S32 is a step of removing the first semiconductor layer 20n exposed by removing the insulating layer 40.
- the exposed first semiconductor layer 20n is washed with alkali.
- the semiconductor substrate 10n is exposed as shown in FIG.
- step S32 the insulating layer 40 remaining without being removed serves as a protective layer for protecting the first semiconductor layer 20n.
- Step S33 is a step of forming the second semiconductor layer 30p on the semiconductor substrate 10n exposed by removing the first semiconductor layer 20n.
- An i-type amorphous semiconductor layer 32i is formed on the back surface 12 of the semiconductor substrate 10n.
- a p-type amorphous semiconductor layer 35p is formed on the formed i-type amorphous semiconductor layer 32i.
- the i-type amorphous semiconductor layer 32i and the p-type amorphous semiconductor layer 35p are formed by, for example, a CVD method.
- the second semiconductor layer 30p is formed on the back surface 12. As shown in FIG. 7, in the solar cell 1, the second semiconductor layer 30p is formed over the entire surface. Therefore, the second semiconductor layer 30p is formed not only on the back surface 12 but also on the insulating layer 40.
- Step S4 is a step of forming the first electrode 50n and the second electrode 50p.
- Step S4 includes steps S41 to S44.
- Process S41 is a process of removing the second semiconductor layer 30p and the insulating layer 40.
- a resist is applied to a portion where the second semiconductor layer 30p is to be left by using a photolithography method or a screen printing method.
- the second semiconductor layer 30p portion and the insulating layer 40 portion to which the resist is applied remain.
- the second semiconductor layer 30p portion and the insulating layer 40 portion where the resist is not applied are removed.
- cleaning is performed using hydrogen fluoride (HF).
- HF hydrogen fluoride
- the first semiconductor layer 20n is exposed.
- the second semiconductor layer 30p and the insulating layer 40 may be removed separately.
- the second semiconductor layer 30p and the insulating layer 40 may be removed by a method other than the method using a resist.
- Step S42 is a step of forming the transparent electrode layer 52.
- the transparent electrode layer 52 is formed on the first semiconductor layer 20n and the second semiconductor layer 30p by using a physical vapor deposition method (PVD method). Since the inclined surface 40a is formed in the insulating layer 40, the inclined surface corresponding to the inclined surface 40a is also formed in the second semiconductor layer 30p formed thereon. For this reason, the transparent electrode layer 52 formed on the second semiconductor layer 30p is formed along the inclined surface of the second semiconductor layer 30p. For this reason, it is possible to prevent the transparent electrode layer 52 from being cut or peeled by the side surface of the insulating layer 40.
- PVD method physical vapor deposition method
- a base metal layer serving as a base for the first collection electrode 55n and the second collection electrode 55p is formed using the PVD method.
- Ti and Cu are used as the base metal.
- Step S43 is a step of forming a separation groove 60 for preventing a short circuit.
- the separation groove 60 is formed using a laser. As shown in FIG. 10, by forming the separation groove 60, the transparent electrode layer 52 is separated, and the first transparent electrode layer 52n and the second transparent electrode layer 52p are formed.
- the separation groove 60 is formed using a laser, but the separation groove 60 may be formed using a resist and an etching solution, for example.
- Step S44 is a step of forming the first collection electrode 55n and the second collection electrode 55p.
- the first collection electrode 55n is formed on the first transparent electrode layer 52n and the second collection electrode 55p is formed on the second transparent electrode layer 52p by plating.
- the first collecting electrode 55n and the second collecting electrode 55p may be formed by applying a conductive paste by screen printing and then baking the conductive paste.
- the solar cell 1 shown in FIG. 2 can be manufactured as described above.
- the semiconductor substrate 10n has the first conductivity type, that is, the n-type has been described, but the semiconductor substrate 10n may have the second conductivity type, that is, the p-type.
- the first semiconductor layer 20n is composed of the i-type amorphous semiconductor layer 22i and the n-type amorphous semiconductor layer 25n, but is composed only of the n-type amorphous semiconductor layer 25n. May be.
- the second semiconductor layer 30p may be composed of only the p-type amorphous semiconductor layer 35p.
Abstract
Description
10n…半導体基板
12…裏面
20n…第1半導体層
22i…i型非晶質半導体層
25n…n型非晶質半導体層
27…第1半導体層の端部
30p…第2半導体層
32i…i型非晶質半導体層
35p…p型非晶質半導体層
37…第2半導体層の端部
40…絶縁層
40a…絶縁層の傾斜面
41…エッチングペースト
41a…端部
50n…第1電極
50p…第2電極
52…透明電極層
52n…第1透明電極層
52p…第2透明電極層
55n…第1収集電極
55p…第2収集電極
60…分離溝
70n,70p…接続電極
R…境界領域
Rn…第1導電型領域
Rp…第2導電型領域
Claims (4)
- 受光面と裏面とを有する第1導電型または第2導電型の半導体基板と、
前記裏面上に形成される第1導電型を有する第1半導体層と、
前記裏面上に形成される第2導電型を有する第2半導体層と、
前記第1半導体層と電気的に接続された第1電極と、
前記第2半導体層と電気的に接続された第2電極と、
前記第1半導体層が設けられる第1導電型領域と前記第2半導体層が設けられる第2導電型領域の境界領域に設けられる絶縁層とを備える太陽電池であって、
前記絶縁層の前記第2導電型領域側の側面が、前記第2導電型領域に近づくにつれて厚みが薄くなるように傾斜した傾斜面を有しており、厚み方向に垂直でかつ前記第2導電型領域に向かう方向における前記傾斜面の幅が、前記傾斜面が形成されていない部分における前記絶縁層の厚みの10~300倍の範囲内である、太陽電池。 - 前記第1電極が、第1透明電極層と、前記第1透明電極層の上に形成される第1収集電極層とを有し、前記第2電極が、第2透明電極層と、前記第2透明電極層の上に形成される第2収集電極層とを有する、請求項1に記載の太陽電池。
- 前記境界領域において、前記絶縁層は、前記第1半導体層の上に設けられており、前記絶縁層の上に前記第2半導体層が設けられている、請求項1または2に記載の太陽電池。
- 前記境界領域において、前記第2透明電極層は、前記第2半導体層の上に設けられている、請求項3に記載の太陽電池。
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DE112015000559.5T DE112015000559T5 (de) | 2014-01-29 | 2015-01-26 | Solarzelle |
JP2015559928A JP6447927B2 (ja) | 2014-01-29 | 2015-01-26 | 太陽電池 |
US15/220,394 US10014420B2 (en) | 2014-01-29 | 2016-07-27 | Solar cell |
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WO2012163517A2 (en) * | 2011-05-27 | 2012-12-06 | Renewable Energy Corporation Asa | Solar cell and method for producing same |
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JP5485060B2 (ja) | 2010-07-28 | 2014-05-07 | 三洋電機株式会社 | 太陽電池の製造方法 |
JP2015133341A (ja) * | 2012-04-27 | 2015-07-23 | パナソニック株式会社 | 裏面接合型太陽電池及びその製造方法 |
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JP2003298078A (ja) * | 2002-03-29 | 2003-10-17 | Ebara Corp | 光起電力素子 |
WO2012132655A1 (ja) * | 2011-03-25 | 2012-10-04 | 三洋電機株式会社 | 裏面接合型の光電変換素子及び裏面接合型の光電変換素子の製造方法 |
WO2012163517A2 (en) * | 2011-05-27 | 2012-12-06 | Renewable Energy Corporation Asa | Solar cell and method for producing same |
JP2013120863A (ja) * | 2011-12-08 | 2013-06-17 | Sharp Corp | 太陽電池の製造方法 |
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US10014420B2 (en) | 2018-07-03 |
DE112015000559T5 (de) | 2016-12-15 |
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