WO2015096666A1 - Pcb板的导电孔电性能测试方法及装置 - Google Patents

Pcb板的导电孔电性能测试方法及装置 Download PDF

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Publication number
WO2015096666A1
WO2015096666A1 PCT/CN2014/094349 CN2014094349W WO2015096666A1 WO 2015096666 A1 WO2015096666 A1 WO 2015096666A1 CN 2014094349 W CN2014094349 W CN 2014094349W WO 2015096666 A1 WO2015096666 A1 WO 2015096666A1
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conductive
substrates
hole
conductive pads
line
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PCT/CN2014/094349
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English (en)
French (fr)
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刘洋
刘攀
曾志军
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广州兴森快捷电路科技有限公司
深圳市兴森快捷电路科技股份有限公司
宜兴硅谷电子科技有限公司
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Publication of WO2015096666A1 publication Critical patent/WO2015096666A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2805—Bare printed circuit boards

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  • the invention relates to a comprehensive performance testing method for a PCB board, in particular to a method and a device for testing the electrical conductivity of a conductive hole of a PCB board.
  • the electrical performance is one of the important performances of PCB boards, and electrical performance needs to be tested during PCB board manufacturing and use.
  • the electrical performance affects the quality of the entire PCB.
  • the electrical performance test includes testing the through-holes of the PCB and the conductive properties of the blind vias.
  • the through hole refers to a hole drilled through the PCB board, the side wall of the hole is plated with a copper layer, and the through hole wire is connected with the pattern of the whole PCB board, and the effect of the copper plating layer on the side wall often affects the PCB board.
  • the blind hole is a hole that is drilled into a part of the depth of the PCB.
  • the blind hole is electrically connected to a certain layer of the circuit pattern in the PCB from the surface layer to the PCB board.
  • the sidewall of the hole is also plated with a copper layer. The effect of copper plating on the sidewalls also affects the electrical conductivity of the PCB.
  • each through-hole and blind vias on a pair of PCB boards are often tested with a multimeter. And the number of through holes or blind holes on the PCB board is increasing, it will take a lot of time to do electrical performance testing, wasting human and material resources.
  • the present invention overcomes the defects of the prior art and provides a high-efficiency test method for the electrical conductivity of a conductive hole of a PCB board, which can simultaneously test the electrical conductivity of a plurality of conductive holes.
  • a method for testing the electrical conductivity of a conductive hole of a PCB board comprising the steps of: preparing a PCB board with conductive properties of the conductive hole to be tested, and electrically connecting the two ends of the conductive hole to be tested on the PCB.
  • the conductive connection forms a conductive line in series; the test device is used to test the conduction performance of the conductive line, and it is determined whether the conductive hole on the conductive line is conductive.
  • the two ends of the conductive hole to be tested on the PCB are sequentially electrically connected by a wire.
  • the specific method is: providing two substrates, respectively adding on the two substrates. a conductive pad; wherein an area of the conductive pad on each of the substrates is greater than or equal to an end area of the through hole, a position of the conductive pad on each of the substrates and the through hole on the PCB Corresponding to the position of the distribution; determining a line for connecting all the conductive pads on the substrate; adding wires between the conductive pads of each of the substrates according to the lines; wherein each of the substrates is in the order of the lines One or only two of the three conductive pads are connected by the wires.
  • the wires on the two substrates are spliced to form the line.
  • the conductive hole is a blind hole
  • prepare a PCB board with a conductive property of the blind hole to be tested, and the specific method of electrically connecting the two ends of the blind hole to be tested on the PCB board by wires is: Before laminating a plurality of core plates to form the PCB board, two substrates are provided, and conductive pads are respectively added on the two substrates; wherein an area of the conductive pads on each of the substrates is greater than or equal to the blind holes An end area, a position of the conductive pad on each of the substrates corresponding to a position of the blind hole on the PCB; determining a line for connecting all the conductive pads on the substrate; The wires are respectively added between the conductive pads of each of the substrates; wherein, among the three consecutive conductive pads in the order of the lines on the substrate, and only two of the conductive pads are connected by the wires, When the two substrates are stacked, the wires on the two substrates are spliced to form the wires;
  • the line is in the "S" shape.
  • the number of the conductive pads on each of the substrates is the same as the number of through holes on the PCB.
  • the present invention also provides a through-hole electrical property testing device for a PCB board, comprising two substrates, wherein the two substrates are respectively provided with conductive pads, and the area of the conductive pads on each of the substrates is greater than or equal to the through holes.
  • the end area of the conductive pad on each substrate corresponds to the position of the blind hole on the PCB board, and the conductive pads of each substrate are connected by wires, and the two blocks are When the substrates are stacked, the wires on the two substrates are spliced to form a line.
  • the line is in the "S" shape.
  • one or only two of the plurality of conductive pads on each of the substrates in the order of the lines are connected by the wires.
  • the substrate is provided with a test disc, and the test disc is electrically connected to the line through a wire.
  • the number of the conductive pads on each of the substrates is the same as the number of through holes on the PCB.
  • the conductive holes of the electrical properties to be tested are connected in series to form a line, and the conductive performance of the line is tested by a test instrument.
  • the test result of the test meter When the test result of the test meter is turned on, it indicates that the conductive holes on the tested line can be turned on.
  • the test instrument test result When the test instrument test result is non-conducting, it indicates that the conductive hole is not conductive on the tested line.
  • the method is suitable for batch detecting the conductive performance of the conductive hole of the PCB board, and can quickly find out from the batch PCB board. PCB board with poor conductive properties of conductive holes.
  • the conductive hole electrical property testing method of the invention can simultaneously test the conductive properties of a plurality of conductive holes, and the test efficiency is high.
  • the through hole electrical property testing device of the PCB board of the present invention By adopting the through hole electrical property testing device of the PCB board of the present invention, two substrates are attached to both sides of the PCB board during testing, and the two ends of the through hole to be tested are electrically connected with the wires on the substrate to form a line, and the test is passed.
  • the conductivity of the through-hole can be known by the conductivity of the line.
  • the device can test the conductivity of multiple through-holes at the same time, and the test efficiency is high. It is suitable for the detection of the conductivity of the through-hole of the bulk PCB board, and can quickly find out the conductive performance. Qualified PCB board.
  • FIG. 1 is a schematic structural view of a PCB board having a through hole according to an embodiment of the present invention
  • Figure 3 is a second substrate of an embodiment of the present invention.
  • Figure 4 is a first line of an embodiment of the present invention.
  • Figure 5 is a second line of an embodiment of the present invention.
  • Figure 6 is a third circuit of an embodiment of the present invention.
  • the method for testing the through hole electrical performance of a PCB board according to the present invention comprises the following steps:
  • S101 prepares a PCB board with conductive properties of the conductive holes to be tested, and electrically connects the two ends of the conductive holes to be tested on the PCB board with wires, and the through holes form a conductive line in series;
  • S102 tests the conduction performance of the conductive line by using a test instrument, and determines whether the conductive hole on the conductive line is conductive.
  • the conductive holes of the electrical properties to be tested are connected in series to form a line, and the electrical conductivity of the line is tested by a test instrument.
  • a test instrument For example, two probes of the multimeter can be respectively connected to the two ends of the line, and the test result of the test instrument is guided. When it is over, it means that the conductive holes on the tested line can be turned on.
  • the test result of the test meter is non-conducting, it indicates that the conductive hole is not conductive on the tested line. In this case, the test line can be shortened step by step. To find out the conductive holes that are not conductive on the PCB. This method tests the through-hole method one by one compared with the prior art, which greatly improves the test efficiency.
  • the two ends of the through hole of the electrical property to be tested on the PCB are electrically connected by wires in a specific method:
  • the number of the conductive pads on each of the substrates is the same as the number of through holes on the PCB.
  • the area of the conductive pad on each of the substrates is greater than or equal to the end area of the through hole, and the position of the conductive pad on each of the substrates corresponds to the position of the through hole on the PCB.
  • a line for connecting all of the conductive pads on the substrate is determined.
  • the line is "S" shaped.
  • the line pattern can be made as shown in FIGS. 5 and 6. Adding wires between the conductive pads of each substrate according to the lines, wherein each of the three consecutive conductive pads in the order of the lines on each substrate and only two of the conductive pads are connected by the wires That is, wires are added one by one between adjacent conductive pads on the two substrates in the order of the lines, for example, in the "S" shape of the circuit of the present embodiment, two adjacent ones are first on one of the substrates.
  • Add wires between the conductive pads add wires between the two adjacent conductive pads on the other substrate according to the "S" line, follow the "S" line, and then two adjacent on the other substrate.
  • a wire is added between the conductive pads, so that the two substrates are made as shown in FIGS. 2 and 3.
  • the first substrate and the second substrate when the first substrate and the second substrate are stacked, the wires on the two substrates are spliced to form the "S" line.
  • the idea of fabricating the first substrate and the second substrate can also be performed according to the present invention. First, the circuit patterns of the first substrate and the second substrate are determined, and corresponding film negative films are prepared, and then etched according to the conventional PCB board process. A pattern on a substrate and a second substrate results in a first substrate and a second substrate as shown.
  • the PCB board with the conductive performance of the blind hole is prepared, and the two ends of the blind hole to be tested on the PCB board are electrically connected by wires.
  • the specific method is: providing two substrates, respectively adding conductive pads on the two substrates, in the embodiment, the number of the conductive pads on each substrate and the number of blind holes on the PCB Similarly, the area of the conductive pad on each substrate is greater than or equal to the end area of the blind hole, and the distribution position of the conductive pad on each substrate corresponds to the position of the blind hole on the PCB. . Determining a line for connecting all the conductive pads on the substrate in series. In this embodiment, the line is in an "S" shape.
  • the line may be as shown in FIGS. 5 and 6. .
  • Adding wires between the conductive pads of each substrate according to the circuit in the embodiment, there are only two conductive pads in any three consecutive conductive pads in the order of the lines on each substrate.
  • the wires on the two substrates are spliced to form the wires.
  • the method for testing the electrical properties of the blind via is the same as the method for testing the conductive properties of the via, and the method for testing the via conductivity is to laminate one of the substrates before laminating the plurality of cores to form the PCB.
  • a plurality of core sheets are laminated together to constitute the PCB board.
  • the present invention further provides a through hole electrical property testing device for a PCB board, comprising two substrates, a first substrate 21 and a second substrate 22, and the two substrates are respectively provided with guides.
  • the electric pad 12 has the same number of the conductive pads 12 on each substrate as the number of the through holes 11 on the PCB board 10, and the area of the conductive pads 12 on each of the substrates is greater than or equal to the end of the through holes 11.
  • the distribution position of the conductive pads 12 on each of the substrates corresponds to the distribution position of the through holes 11 on the PCB board 10, and the conductive pads 12 of each substrate are connected by wires 13, which will be When the two substrates are stacked, the wires 13 on the two substrates are spliced to form a line.
  • the line is "S" shaped.
  • any three consecutive conductive pads 12 on each substrate in the order of the lines There are only two conductive pads 12 connected through the wires 13.
  • a test disc is disposed on the substrate, and the test disc is electrically connected to the line through a wire.
  • the through hole electrical property testing device of the PCB board of the present invention By adopting the through hole electrical property testing device of the PCB board of the present invention, two substrates are attached to both sides of the PCB board during testing, and the two ends of the through hole to be tested are electrically connected with the wires on the substrate to form a line, and the test is passed.
  • the conductivity of the through-hole can be known by the conductivity of the line.
  • the device can test the conductivity of a plurality of through-holes at the same time, and can quickly find a PCB with unqualified conductive performance, which has high test efficiency and saves manpower.

Abstract

一种PCB板的导电孔电性能测试方法，包括如下步骤：准备好待测导电孔导电性能的PCB板，将所述PCB板上待测的导电孔两端依次用导线电性连接，所述导电孔串联形成一条导电线路；采用测试仪器测试导电线路的导通性能，判断所述导电线路上的导电孔是否导通。用导线将待测试电性能的导电孔串联形成一条线路，用测试仪器测试该线路的导电性能，当测试仪表测试结果为导通时，则说明被测试线路上的导电孔均能导通，当测试仪表测试结果为不导通时，则说明被测试线路上存在导电孔不导通的情况。该方法测试效率高，节省人力物力。

Description

PCB板的导电孔电性能测试方法及装置 技术领域
本发明涉及一种PCB板的综合性能测试方法，尤其是涉及一种PCB板的导电孔电性能测试方法及装置。
背景技术
随着科技进步，PCB板集成度越来越高，体积越来越小，构成PCB板的芯板层数越来越多，为了满足行业需求，PCB板工艺越来越精密。其中，电气性能是PCB板重要性能之一，在PCB板制作过程及使用过程都需要检测电气性能。电气性能的好坏影响着整块PCB板的质量，电气性能的测试包括对PCB板的通孔以及盲孔导电性能的测试。其中，通孔是指钻穿PCB板的孔，该孔侧壁上被镀上了铜层，通孔电线连接着整块PCB板的图形，侧壁上镀铜层的效果往往影响PCB板的导电性能。盲孔是钻入PCB板部分深度的孔，盲孔电性连接着PCB板中从表层到PCB板内的某层共若干层线路图形，该孔侧壁上也被镀上了铜层，该侧壁上铜层镀的效果同样影响PCB板的导电性能。
在测试PCB板通孔或盲孔的导电性能时，往往逐一对PCB板上的每一个通孔以及盲孔用万用表进行测试。而PCB板上的通孔或者盲孔数量越来越多，就会花费很多时间做电性能测试，浪费人力物力。
发明内容
基于此，本发明在于克服现有技术的缺陷，提供一种高效率的PCB板导电孔电性能测试方法，它能够同时测试出多个导电孔的导电性能。
其技术方案如下：一种PCB板的导电孔电性能测试方法，包括如下步骤：准备好待测导电孔导电性能的PCB板，将所述PCB板上待测的导电孔两端依次用导线电性连接，所述导电孔串联形成一条导电线路；采用测试仪器测试导电线路的导通性能，判断所述导电线路上的导电孔是否导通。
下面对进一步技术方案进行说明：
优选的，当所述导电孔为通孔时,将所述PCB板上待测的导电孔两端依次用导线电性连接具体方法为：提供两块基板,在两块所述基板上分别添加导电焊盘；其中,每块基板上导电焊盘的面积大于或等于所述通孔的端面积，所述导电焊盘在每块基板上的分布位置与所述通孔在所述PCB板上的分布位置相应；确定一条用于将基板上所有导电焊盘串联起来的线路；按照所述线路分别在每块基板的导电焊盘之间添加导线；其中，每块基板上按照该线路顺序的任意连续三个导电焊盘中有且只有两个导电焊盘通过所述导线相连，将两块所述基板叠放起来时，两块所述基板上的导线拼接构成所述线路。
优选的，当所述导电孔为盲孔时,准备好待测盲孔导电性能的PCB板，将所述PCB板上待测的盲孔两端依次用导线电性连接的具体方法为：在层压多块芯板构成所述PCB板之前，提供两块基板,在两块所述基板上分别添加导电焊盘；其中,每块基板上导电焊盘的面积大于或等于所述盲孔的端面积，所述导电焊盘在每块基板上的分布位置与所述盲孔在所述PCB板上的分布位置相应；确定一条用于将基板上所有导电焊盘串联起来的线路；按照所述线路分别在每块基板的导电焊盘之间添加导线；其中，每块基板上按照所述线路顺序的任意连续三个导电焊盘中有且只有两个导电焊盘通过所述导线相连，将两块所述基板叠放起来时，两块所述基板上的导线拼接构成所述线路；将其中一块基板与其它芯板一起层压构成所述PCB板。
优选的，所述线路为“S”形状。
优选的，每块基板上所述导电焊盘的数量与所述PCB板上的通孔数量相同。
本发明还提供一种PCB板的通孔电性能测试装置，包括两块基板，两块所述基板上分别设有导电焊盘,每块基板上导电焊盘的面积大于或等于所述通孔的端面积，所述导电焊盘在每块基板上的分布位置与所述盲孔在所述PCB板上的分布位置相应，每块基板的导电焊盘之间用导线连接，将两块所述基板叠放起来时，两块所述基板上的导线拼接构成一条线路。
优选的，所述线路为“S”形状。
优选的，每块基板上按照所述线路顺序的任意连续三个导电焊盘中有且只有两个导电焊盘通过所述导线相连。
优选的，所述基板上设有测试盘，所述测试盘通过导线与所述线路电性连接。
优选的，每块基板上所述导电焊盘的数量与所述PCB板上的通孔数量相同。
下面对前述技术方案的原理、效果等进行说明：
用导线将待测试电性能的导电孔串联形成一条线路，用测试仪器测试该线路的导电性能，当测试仪表测试结果为导通时，则说明被测试线路上的导电孔均能导通，当测试仪表测试结果为不导通时，则说明被测试线路上存在导电孔不导通的情况，该方法适应于批量检测PCB板导电孔的导电性能，能迅速的从批量的PCB板中找出导电孔导电性能不合格的PCB板。本发明所述导电孔电性能测试方法能够同时测试出多个导电孔的导电性能，测试效率高。通过采用本发明所述PCB板的通孔电性能测试装置，测试时，将两块基板贴在PCB板的两面，待测通孔两端与基板上的导线电性连接构成一条线路，通过测试线路导电性能即可获知通孔的导电性能，该装置能同时将多个通孔的导电性能测试出来，测试效率高，适应于批量PCB板通孔导电性能的检测，能快速找出导电性能不合格的PCB板。
附图说明
图1是本发明实施例具有通孔的PCB板结构示意图；
图2是本发明实施例的第一基板；
图3是本发明实施例的第二基板；
图4是本发明实施例的第一种线路；
图5是本发明实施例的第二种线路；
图6是本发明实施例的第三种线路。
附图标记说明：
10、PCB板，11、通孔，12、导电焊盘，13、导线，21、第一基板，22、第二基板，20、第一种线路，30、第二种线路，40、第三种线路。
具体实施方式
下面对本发明的实施例进行详细说明：
本发明所述一种PCB板的通孔电性能测试方法，包括如下步骤：
S101准备好待测导电孔导电性能的PCB板，将所述PCB板上待测的导电孔两端依次用导线电性连接，所述通孔串联形成一条导电线路；
S102采用测试仪器测试导电线路的导通性能，判断所述导电线路上的导电孔是否导通。
用导线将待测试电性能的导电孔串联形成一条线路，用测试仪器测试该线路的导电性能，例如,可采用万用表的两探针分别接在该线路的两端,当测试仪表测试结果为导通时，则说明被测试线路上的导电孔均能导通,当测试仪表测试结果为不导通时，则说明被测试线路上存在导电孔不导通的情况,此时可以逐步缩短测试线路,找出PCB板上不导通的导电孔,此方法相对于现有技术逐个测试通孔方法,大大提高了测试效率。
在本实施例中，当所述导电孔为通孔时，将所述PCB板上待测电性能的通孔两端依次用导线电性连接具体方法为：
首先,提供两块基板,在两块所述基板上分别添加导电焊盘，导电焊盘用于与PCB板上通孔电性连接。在其中一个实施例中,每块基板上所述导电焊盘的数量与所述PCB板上的通孔的数量相同。每块基板上导电焊盘的面积大于或等于所述通孔的端面积，所述导电焊盘在每块基板上的分布位置与所述通孔在所述PCB板上的分布位置相应。
然后，确定一条用于将基板上所有导电焊盘串联起来的线路，在本实施例中，如图4所示，所述线路为“S”形状。在其中一个实施例中，所述线路图形可以作成如图5和图6所示。按照所述线路分别在每块基板的导电焊盘之间添加导线,其中，每块基板上按照该线路顺序的任意连续三个导电焊盘中有且只有两个导电焊盘通过所述导线相连，即按照线路次序,分别在两块基板上的相邻导电焊盘之间逐一添加导线,例如,在本实施例的“S”形状的线路中，先在其中一块基板上两个相邻的导电焊盘之间添加导线，按照“S”线路，再在另一块基板上两个相邻的导电焊盘之间添加导线，按照“S”线路，接着再在另一基板上两个相邻的导电焊盘之间添加导线，如此，将两块基板制作成如图2和图3所示 的第一基板和第二基板，将第一基板和第二基板叠放起来时，两块基板上的导线拼接构成所述“S”线路。当然，也可以按照本发明制作第一基板和第二基板的思路，先确定好第一基板和第二基板的线路图形，制作出对应的菲林底片，然后按照传统的PCB板工艺分别蚀刻出第一基板和第二基板上的图形，得到如图所示的第一基板和第二基板。
在本实施例中，当所述导电孔为所述盲孔时，准备好待测盲孔导电性能的PCB板，将所述PCB板上待测的盲孔两端依次用导线电性连接的具体方法为：提供两块基板,在两块所述基板上分别添加导电焊盘，在本实施例中,每块基板上所述导电焊盘的数量与所述PCB板上的盲孔的数量相同,每块基板上导电焊盘的面积大于或等于所述盲孔的端面积，所述导电焊盘在每块基板上的分布位置与所述盲孔在所述PCB板上的分布位置相应。确定一条用于将基板上所有导电焊盘串联起来的线路，在本实施例中，所述线路为“S”形状，在其中一个实施例中，所述线路可以如图5和图6所示。按照所述线路分别在每块基板的导电焊盘之间添加导线，在本实施例中，每块基板上按照所述线路顺序的任意连续三个导电焊盘中有且只有两个导电焊盘通过所述导线相连，将两块所述基板叠放起来时，两块所述基板上的导线拼接构成所述线路。测试盲孔电性能的方法与测试通孔导电性能的方法原理相同,与测试通孔导电性能方法不同的是，在层压多块芯板构成所述PCB板之前，将其中一块所述基板与多块芯板一起层压构成所述PCB板。
如图1至图4所示，本发明还提供一种PCB板的通孔电性能测试装置，包括两块基板，第一基板21和第二基板22，两块所述基板上分别设有导电焊盘12,每块基板上所述导电焊盘12的数量与所述PCB板10上的通孔11数量相同,每块基板上导电焊盘12的面积大于或等于所述通孔11的端面积，所述导电焊盘12在每块基板上的分布位置与所述通孔11在所述PCB板10上的分布位置相应，每块基板的导电焊盘12之间用导线13连接，将两块所述基板叠放起来时，两块所述基板上的导线13拼接构成一条线路。在其中一个实施例中，如图4所示，所述线路为“S”形状。
在本实施例中，每块基板上按照所述线路顺序的任意连续三个导电焊盘12 中有且只有两个导电焊盘12通过所述导线13相连。所述基板上设有测试盘，所述测试盘通过导线与所述线路电性连接。
通过采用本发明所述PCB板的通孔电性能测试装置，测试时，将两块基板贴在PCB板的两面，待测通孔两端与基板上的导线电性连接构成一条线路，通过测试线路导电性能即可获知通孔的导电性能，该装置能同时将多个通孔的导电性能测试出来，能快速找出导电性能不合格的PCB板，测试效率高，节省人力。
以上所述实施例仅表达了本发明的具体实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。

Claims (10)

  1. 一种PCB板的导电孔电性能测试方法，其特征在于，包括如下步骤：
    准备好待测导电孔导电性能的PCB板，将所述PCB板上待测的导电孔两端依次用导线电性连接，所述导电孔串联形成一条导电线路；
    采用测试仪器测试导电线路的导通性能，判断所述导电线路上的导电孔是否导通。
  2. 根据权利要求1所述的导电孔电性能测试方法，其特征在于，当所述导电孔为通孔时,将所述PCB板上待测的导电孔两端依次用导线电性连接具体方法为：
    提供两块基板,在两块所述基板上分别添加导电焊盘；其中,每块基板上导电焊盘的面积大于或等于所述通孔的端面积，所述导电焊盘在每块基板上的分布位置与所述通孔在所述PCB板上的分布位置相应；
    确定一条用于将基板上所有导电焊盘串联起来的线路；
    按照所述线路分别在每块基板的导电焊盘之间添加导线；其中，每块基板上按照该线路顺序的任意连续三个导电焊盘中有且只有两个导电焊盘通过所述导线相连，将两块所述基板叠放起来时，两块所述基板上的导线拼接构成所述线路。
  3. 根据权利要求1所述的导电孔电性能测试方法，其特征在于，当所述导电孔为盲孔时,
    准备好待测盲孔导电性能的PCB板，将所述PCB板上待测的盲孔两端依次用导线电性连接的具体方法为：
    在层压多块芯板构成所述PCB板之前，提供两块基板,在两块所述基板上分别添加导电焊盘；其中,每块基板上导电焊盘的面积大于或等于所述盲孔的端面积，所述导电焊盘在每块基板上的分布位置与所述盲孔在所述PCB板上的分布位置相应；
    确定一条用于将基板上所有导电焊盘串联起来的线路；
    按照所述线路分别在每块基板的导电焊盘之间添加导线；其中，每块基板上按照所述线路顺序的任意连续三个导电焊盘中有且只有两个导电焊盘通过所 述导线相连，将两块所述基板叠放起来时，两块所述基板上的导线拼接构成所述线路；
    将其中一块基板与其它芯板一起层压构成所述PCB板。
  4. 根据权利要求2或3所述的导电孔电性能测试方法，其特征在于，所述线路为“S”形状。
  5. 根据权利要求2或3所述的通孔电性能测试装置，其特征在于，每块基板上所述导电焊盘的数量与所述PCB板上的通孔数量相同。
  6. 一种PCB板的通孔电性能测试装置，其特征在于，包括两块基板，两块所述基板上分别设有导电焊盘,每块基板上导电焊盘的面积大于或等于所述通孔的端面积，所述导电焊盘在每块基板上的分布位置与所述盲孔在所述PCB板上的分布位置相应，每块基板的导电焊盘之间用导线连接，将两块所述基板叠放起来时，两块所述基板上的导线拼接构成一条线路。
  7. 根据权利要求6所述的通孔电性能测试装置，其特征在于，所述线路为“S”形状。
  8. 根据权利要求6所述的通孔电性能测试装置，其特征在于，每块基板上按照所述线路顺序的任意连续三个导电焊盘中有且只有两个导电焊盘通过所述导线相连。
  9. 根据权利要求6所述的通孔电性能测试装置，其特征在于，所述基板上设有测试盘，所述测试盘通过导线与所述线路电性连接。
  10. 根据权利要求6所述的通孔电性能测试装置，其特征在于，每块基板上所述导电焊盘的数量与所述PCB板上的通孔数量相同。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105115415A (zh) * 2015-07-21 2015-12-02 胜宏科技（惠州）股份有限公司 一种线路板盲孔深度测试结构及其测试方法
CN105813388A (zh) * 2016-05-04 2016-07-27 上海凯思尔电子有限公司 一种覆铜pcb智能识别装置

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103743991A (zh) * 2013-12-27 2014-04-23 广州兴森快捷电路科技有限公司 Pcb板的导电孔电性能测试方法及装置
CN105527559B (zh) * 2015-11-30 2019-07-02 北大方正集团有限公司 测试线路板、其制作方法、测试方法以及测试系统
CN109029225A (zh) * 2018-10-09 2018-12-18 信丰迅捷兴电路科技有限公司 一种微盲孔镭射成孔质量定期检测方法
WO2022062198A1 (zh) * 2020-09-23 2022-03-31 深圳市大疆创新科技有限公司 堆叠印刷电路板
CN112954889A (zh) * 2021-01-20 2021-06-11 江门崇达电路技术有限公司 一种沉铜工艺测试板及其制作方法
CN113109696B (zh) * 2021-04-12 2023-08-08 万安裕维电子有限公司 一种pcb板导电孔性能测试方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001068819A (ja) * 1999-08-26 2001-03-16 Sharp Corp プリント基板の不良判定方法及びこの判定に用いるマーク
US6462570B1 (en) * 2001-06-06 2002-10-08 Sun Microsystems, Inc. Breakout board using blind vias to eliminate stubs
CN201859193U (zh) * 2010-09-30 2011-06-08 嘉联益科技股份有限公司 用于单一或同步检测通孔及盲孔的测试板
CN103197190A (zh) * 2013-03-11 2013-07-10 昆山苏杭电路板有限公司 万孔板
CN103376402A (zh) * 2013-07-04 2013-10-30 深圳市五株科技股份有限公司 多层电路板钻孔深度测试方法
CN103743991A (zh) * 2013-12-27 2014-04-23 广州兴森快捷电路科技有限公司 Pcb板的导电孔电性能测试方法及装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1553205A (zh) * 2003-06-03 2004-12-08 欣强科技股份有限公司 印刷电路板的电性测试方法
CN102435792B (zh) * 2011-09-28 2013-12-25 东莞生益电子有限公司 Pcb板背钻可靠性测试用附连测试板及其测试方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001068819A (ja) * 1999-08-26 2001-03-16 Sharp Corp プリント基板の不良判定方法及びこの判定に用いるマーク
US6462570B1 (en) * 2001-06-06 2002-10-08 Sun Microsystems, Inc. Breakout board using blind vias to eliminate stubs
CN201859193U (zh) * 2010-09-30 2011-06-08 嘉联益科技股份有限公司 用于单一或同步检测通孔及盲孔的测试板
CN103197190A (zh) * 2013-03-11 2013-07-10 昆山苏杭电路板有限公司 万孔板
CN103376402A (zh) * 2013-07-04 2013-10-30 深圳市五株科技股份有限公司 多层电路板钻孔深度测试方法
CN103743991A (zh) * 2013-12-27 2014-04-23 广州兴森快捷电路科技有限公司 Pcb板的导电孔电性能测试方法及装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105115415A (zh) * 2015-07-21 2015-12-02 胜宏科技（惠州）股份有限公司 一种线路板盲孔深度测试结构及其测试方法
CN105813388A (zh) * 2016-05-04 2016-07-27 上海凯思尔电子有限公司 一种覆铜pcb智能识别装置

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