WO2022062198A1 - 堆叠印刷电路板 - Google Patents

堆叠印刷电路板 Download PDF

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Publication number
WO2022062198A1
WO2022062198A1 PCT/CN2020/135412 CN2020135412W WO2022062198A1 WO 2022062198 A1 WO2022062198 A1 WO 2022062198A1 CN 2020135412 W CN2020135412 W CN 2020135412W WO 2022062198 A1 WO2022062198 A1 WO 2022062198A1
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WO
WIPO (PCT)
Prior art keywords
link
printed circuit
circuit board
solder
solder balls
Prior art date
Application number
PCT/CN2020/135412
Other languages
English (en)
French (fr)
Inventor
张飞
申中国
胡正高
程功
Original Assignee
深圳市大疆创新科技有限公司
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Filing date
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Application filed by 深圳市大疆创新科技有限公司 filed Critical 深圳市大疆创新科技有限公司
Publication of WO2022062198A1 publication Critical patent/WO2022062198A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/52—Testing for short-circuits, leakage current or ground faults
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/54—Testing for continuity
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details

Definitions

  • the present application relates to the technical field of detection link design, and in particular, to a stacked printed circuit board.
  • the traditional printed circuit board (Printed Circuit Board, PCB) stacking design mainly relies on X-ray and other non-destructive methods for short-circuit detection of solder joints.
  • PCB printed Circuit Board
  • the purpose of the present application is to provide a stacked printed circuit board, which can easily detect the open circuit and short circuit problems of the printed circuit board soldering.
  • the stacked printed circuit board includes a first printed circuit board, a second printed circuit board, and a plurality of solder balls connecting the first printed circuit board and the second printed circuit board.
  • the first printed circuit board includes a plurality of first solder joints
  • the second printed circuit board includes a plurality of second solder joints
  • each of the solder balls is soldered to one of the first solder joints and a corresponding one of the solder joints. between the second solder joints to form a first link and a second link that are not electrically connected to each other on the stacked printed circuit board, the solder balls forming the first link and the solder balls forming the second link
  • the solder balls of the road are staggered with each other.
  • the stacked printed circuit board of the present application is provided with two independent first links and second links, so that resistance measurement equipment such as a multimeter can be used to detect soldering open circuit and short circuit problems in the printed circuit board.
  • resistance measurement equipment such as a multimeter
  • the link can also be monitored in real time in the subsequent reliability test, and phenomena such as abnormal resistance caused by solder joint fracture caused by deformation during the test process can be captured in time.
  • FIG. 1 is a schematic diagram of a link of a stacked printed circuit board
  • FIG. 2 is a diagram of a first link formed on a first printed circuit board of the stacked printed circuit boards shown in FIG. 1;
  • FIG. 3 is a diagram of a second link formed on a second printed circuit board of the stacked printed circuit boards shown in FIG. 1;
  • FIG. 4 is a schematic cross-sectional view of a stacked printed circuit board according to an embodiment of the present application.
  • FIG. 5 is a schematic plan view of a link for stacking printed circuit boards according to an embodiment of the present application.
  • FIG. 6 is a schematic plan view of a link for stacking printed circuit boards according to another embodiment of the present application.
  • FIG. 7 is a schematic plan view of a link for stacking printed circuit boards according to another embodiment of the present application.
  • FIG. 8 is a schematic cross-sectional view of the link of the stacked printed circuit board shown in FIG. 7;
  • FIG. 9 is a schematic plan view of a link for stacking printed circuit boards according to still another embodiment of the present application.
  • FIG. 10 is a schematic plan view of a link for stacking printed circuit boards according to still another embodiment of the present application.
  • FIG. 11 is a wiring diagram of a first insulating substrate in a printed circuit board for testing according to an embodiment of the application;
  • FIG. 12 is a wiring diagram on the second insulating substrate in the printed circuit board for testing according to an embodiment of the present application.
  • FIG. 1 discloses a schematic diagram of a link 100 of stacked printed circuit boards
  • FIG. 2 discloses a link diagram formed on a first printed circuit board 11 of the stacked printed circuit boards
  • the stacked printed circuit board includes a first printed circuit board 11 and a second printed circuit board 12 , on which a first link L11 is formed, and on the second printed circuit board 11 is formed a first link L11
  • a second link L12 is formed on the first printed circuit board 12, wherein the first link L11 formed on the first printed circuit board 11 and the second link L12 formed on the second printed circuit board 12 are in a complementary relationship with each other.
  • a serial link 100 is formed on the stacked printed circuit board, that is, a daisy chain.
  • the resistance between IN-OUT as shown in FIG. 1 can detect the open circuit problem of the solder ball 13.
  • the link 100 cannot detect the bridging problem between the solder balls 13 and the solder balls 13 .
  • FIG. 4 shows a schematic cross-sectional view of a stacked printed circuit board 20 according to an embodiment of the present application.
  • the stacked printed circuit board 20 according to an embodiment of the present application includes a first printed circuit board 21 , a second printed circuit board 22 , and a plurality of connection between the first printed circuit board 21 and the second printed circuit board 22 .
  • solder balls 23 so that the first printed circuit board 21 and the second printed circuit board 22 are stacked on top of each other to form a sandwich-like PCB structure.
  • the first printed circuit board 21 includes a plurality of first solder joints 210
  • the second printed circuit board 22 includes a plurality of second solder joints 220 .
  • FIG. 5 discloses a schematic plan view of the link 200 formed on the stacked printed circuit board 20 according to an embodiment of the present application. As shown in FIG. 5 , the solder balls 23 forming the first link 201 and the solder balls 23 forming the second link 202 are arranged in a staggered manner.
  • the so-called staggered arrangement means that there is one solder ball 23 forming the second link 202 between two adjacent solder balls 23 forming the first link 201 , and one solder ball 23 forming the second link 202 between the two adjacent solder balls 23 . There is one solder ball 23 forming the first link 201 therebetween.
  • solder balls 23 forming the first link 201 are arranged in a row with the solder balls 23 forming the second link 202 .
  • solder balls 23 are shown in a single row of four columns in FIG. 5 .
  • the first link 201 and the second link 202 are two independent serial links.
  • the first link 201 and the second link 202 can be used to detect the Whether the solder balls 23 have an open circuit phenomenon can also be detected whether the solder balls 23 in the link 200 have a short circuit phenomenon.
  • the first link 201 and the second link 202 of the present application for the same link, it can be used to detect whether the solder balls 23 forming the link have an open circuit, and the adjacent solder balls of different links can be used to detect whether there is an open circuit.
  • the space between the balls 23 can be used to detect whether the adjacent solder balls 23 are short-circuited.
  • a resistance measuring device such as a multimeter or a datalogger can be used to determine the solder balls 23 in the first link 201 by measuring the resistance of two points IN1-OUT1 in the first link 201, for example, the solder balls No. 1 and No. 3 from the left 23 whether there is an open circuit phenomenon; similarly, by measuring the resistance between the two points IN2-OUT2 in the second link 202, the solder ball 23 in the second link 202 can be judged, such as the No. 2 and No. 4 solder balls from the left 23 Whether there is an open circuit phenomenon.
  • the adjacent solder balls 23 in the first link 201 and the solder balls in the second link 202 can be determined 23, for example, whether there is a short circuit between the solder balls 23 of No. 1 and No. 2 from the left; by measuring the resistance between the IN2 point in the second link 202 and the OUT1 point in the first link 201, it can be judged that the adjacent Whether there is a short circuit between the solder balls 23 in the second link 202 and the solder balls 23 in the first link 201, for example, whether there is a short circuit between the solder balls 23 No. 2 and No.
  • FIG. 6 discloses a schematic plan view of the link 300 formed on the stacked printed circuit board 20 according to another embodiment of the present application.
  • a plurality of independent link groups 301 are formed on the stacked printed circuit board 20 , and each link group 301 includes a first link 201 and a second link 202 .
  • the solder balls 23 forming each link group 301 are arranged in a row.
  • three rows and four columns of solder balls 23 are shown, and in FIG. 6 , it is schematically shown with three link groups 301 as an example.
  • Solder balls 23 in different rows have independent link groups 301 , that is, solder balls 23 in different rows have independent first links 201 and second links 202 respectively.
  • the first link in each link group 301 can be utilized.
  • the circuit 201 and the second link 202 detect the open and short phenomenon of the solder balls 23 in each link group 301, and different link groups 301 can be used to detect whether there is an existence between the solder balls 23 in the different link groups 301 short circuit phenomenon.
  • the detection of the solder balls 23 in the same link group 301 may be similar to the detection of the solder balls 23 shown in FIG. 5 .
  • adjacent solder balls 23 in different link groups 301 can be used to detect whether the adjacent solder balls 23 have a short circuit.
  • a resistance measuring device such as a multimeter or a datalogger can be used to measure the electrical resistance between the IN1 point in the first link 201 of the link group 1 301 and the IN3 point in the first link 201 of the link group 2 301.
  • the resistance can determine whether there is a short circuit between the No. 1 solder ball 23 of the No. 1 link group 301 and the No. 1 solder ball 23 of the No. 2 link group 301;
  • the resistance between the OUT2 point and the OUT2 point in the second link 202 of the No. 2 link group 301 can determine the No. 4 solder ball 23 of the No. 1 link group 301 and the No. 4 solder ball 23 of the No. 2 link group 301 Whether there is a short circuit phenomenon, the detection of other solder balls 23 is deduced by analogy. Therefore, the open-short phenomenon of all the solder balls 23 in the stacked printed circuit board 20 can be easily and easily detected.
  • solder balls 23 mentioned in the present application in the form of a row or a column is relative. Although the solder balls 23 are shown in a completely regular manner such as rows or columns in the description of the present application and the accompanying drawings, in the actual stacked printed circuit board 20 , the first solder joints 210 and the second solder joints 220 And the arrangement between the solder balls 23 may not be arranged in a completely regular row or column.
  • the link of the stacked printed circuit board 20 of the present application is described above by taking an embodiment with four solder balls 23 in one row as an example.
  • the present application is not limited to this, and the creative idea of setting the independent first link 201 and the second link 202 to detect the open and short circuit of the solder balls 23 in the present application can also be applied to the stacked printed circuit board 20 including more solder balls 23 cases.
  • FIG. 7 shows a schematic plan view of the link 400 formed on the stacked printed circuit board according to still another embodiment of the present application
  • FIG. 8 shows a schematic cross-sectional view of the link 400 formed on the stacked printed circuit board shown in FIG. 7
  • the solid line represents the link formed on the first printed circuit board 21
  • the dotted line represents the link formed on the second printed circuit board 22
  • the circle represents the first solder joint 210
  • the second solder joint Schematic illustration of dots 220 and solder balls 23 stacked together.
  • the first link 401 may further include a first sub-link L41 connecting a part of the first solder joints 210 on the first printed circuit board 21 and connecting a part of the first solder joint on the second printed circuit board 22 The second sub-link L42 of the two pads 220 .
  • the first sub-link L41 on the first printed circuit board 21 connects No. 1-3, No. 5-7 ... the first solder joint 210, the second sub-link on the second printed circuit board 22 Road L42 is connected to No. 3-5... the second solder joint 220.
  • the first sub-link L41 on the first printed circuit board 21 is complementary to the second sub-link L42 on the second printed circuit board 22 .
  • the adjacent first sub-links L41 and the second sub-links L42 are electrically connected through the same solder ball 23 .
  • the first sub-link L41 connecting the first pads 210 of Nos. 1-3 is adjacent to the second sub-link L42 connecting the second pads 220 of No. 3-5, and connecting the first pads 1-3
  • the first sub-link L41 of the point 210 and the second sub-link L42 connecting the second pads 220 of Nos. 3-5 are electrically connected to each other by the No. 3 solder ball 23 from the left.
  • the second link 402 may further include a third sub-link L43 connected to another part of the first solder joints 210 on the first printed circuit board 21 and a third sub-link L43 connected to another part of the second solder joints 220 on the second printed circuit board 22 Four sub-links L44.
  • the link 400 of the present application may be formed by a trace design on the first printed circuit board 21 and/or the second printed circuit board 22 .
  • the first sub-link L41 on the first printed circuit board 21 includes a trace formed on the first printed circuit board 21, which is called a first trace; the second sub-link on the second printed circuit board 22
  • the path L42 includes a trace formed on the second printed circuit board 22, which is referred to as a third trace.
  • the third sub-link L43 on the first printed circuit board 21 includes a trace formed on the first printed circuit board 21, which is called a second trace; the fourth sub-link L44 on the second printed circuit board 22
  • the traces formed on the second printed circuit board 22 are called fourth traces.
  • the third sub-link L43 on the first printed circuit board 21 connects No. 2-4, No. 6-8 ... the first solder joint 210
  • the fourth sub-link on the second printed circuit board 22 Road L44 is connected to No. 4-6... the second solder joint 220.
  • the third sub-link L43 on the first printed circuit board 21 is complementary to the fourth sub-link L44 on the second printed circuit board 22 .
  • the adjacent third sub-links L43 and the fourth sub-links L44 are electrically connected through the same solder ball 23 .
  • the third sub-link L43 connecting the first pads 210 of Nos. 2-4 is adjacent to the fourth sub-link L44 connecting the second pads 220 of No. 4-6, and connecting the first pads 2-4
  • the third sub-link L43 of the point 210 and the fourth sub-link L44 connecting the second pads 220 of Nos. 4-6 are electrically connected to each other by the No. 4 solder ball from the left.
  • the link 400 shown in FIG. 8 can be used to detect the open-short phenomenon in a stacked printed circuit board with reference to a similar detection method using the link 400 shown in FIG. 5 .
  • the resistance between the head and tail points IN1-OUT1 of the first link 401 can be used to detect whether the solder balls forming the first link 401 have an open circuit phenomenon
  • the resistance between the head and tail points IN2-OUT2 of the second link 402 can be used to detect whether there is an open circuit phenomenon.
  • two independent first links 401 and second links 402 are respectively designed on the first printed circuit board 21 and the second printed circuit board 22 stacked up and down, so that resistance measurement with a multimeter or the like can be realized.
  • the equipment can detect the soldering open circuit and short circuit in the printed circuit board, and can also monitor the link 400 in real time in the subsequent reliability test, and timely capture the solder joint fracture caused by deformation during the test process. Caused by abnormal resistance and other phenomena.
  • the stacked printed circuit boards described in the above embodiments of the present application can be applied to the field of consumer electronic products requiring high integration.
  • the stacked printed circuit boards described in the above embodiments of the present application may include test boards corresponding to function boards used in electronic products such as movable platforms for unmanned aerial vehicles, action cameras or toys.
  • FIG. 9 illustrates a schematic diagram of a link 500 of stacked printed circuit boards according to yet another embodiment of the present application.
  • a plurality of independent link groups 501 are formed on the stacked printed circuit board, and each link group 501 includes the first link 401 and the second link 402.
  • the solder balls forming each link group 501 are arranged in a row.
  • FIG. 9 it is schematically shown with four link groups 501 as an example.
  • the link 500 shown in FIG. 9 can be used to detect the open-short phenomenon in the stacked printed circuit board with reference to a similar detection method using the link 300 shown in FIG. 6 . Therefore, it is not repeated here.
  • each row of solder balls can be independently detected, so that the number of rows where the problem solder balls are located can be quickly located.
  • the present application may correspondingly set multiple independent link groups.
  • the present application is not limited to this.
  • the heads and tails of multiple rows of solder balls may also be connected together to form only one link 600 including the first link 601 and the second link 602 as a whole, thereby It can quickly determine whether there is an open circuit phenomenon in the link through the detection of the resistance between the beginning and end points of the same link, such as IN1-OUT1 or IN2-OUT2, which can greatly reduce the number of test points.
  • FIG. 11 shows a wiring diagram of the first insulating substrate 71 in the printed circuit board for testing according to an embodiment of the present application.
  • the printed circuit board for testing includes a first insulating substrate 71 and a plurality of first pads 710 formed on the surface of the first insulating substrate 71 .
  • the printed circuit board for testing further includes at least one first wiring group G1 formed on the first insulating substrate 71 .
  • Each first wire group G1 includes a first wire G11 and a second wire G12 that are not electrically connected to each other.
  • the first trace G11 may be used to form a part of the first link
  • the second trace G12 may be used to form a part of the second link
  • the first trace G11 and the second trace G12 are respectively electrically connected to different first traces.
  • the first pads 710 connected to the first trace G11 and the first pads 710 connected to the second trace G12 are arranged in a staggered manner.
  • FIG. 11 shows the complete two first wiring groups G1.
  • the first wire G11 is electrically connected to the first solder joints 710 No. 1 and No. 3 from the left
  • the second wire G12 is electrically connected to the No. 2 from the left. No. 4 and No.
  • first solder joints 710 For the first wire group G1 No. 2 from the left shown in FIG. 11 , the first wire G11 is electrically connected to the first pads 710 No. 5 and No. 7 from the left, and the second wire G12 is electrically connected to the No. 6 from the left. No. 8 and No. 8 first solder joints 710.
  • FIG. 12 discloses a wiring diagram on the second insulating substrate 72 in the printed circuit board for testing according to an embodiment of the present application.
  • the printed circuit board for testing further includes a second insulating substrate 72 , a plurality of second solder joints 720 formed on the surface of the second insulating substrate 72 , forming a second insulating substrate At least one second wiring group G2 on the surface of 72, and a plurality of solder balls (not shown) connecting the first insulating substrate 71 and the second insulating substrate 72 together.
  • Each second wire group G2 includes a third wire G21 and a fourth wire G22 that are not electrically connected to each other.
  • the third trace G21 can be used to form another part of the first link
  • the fourth trace G22 can be used to form another part of the second link
  • the third trace G21 and the fourth trace G22 are electrically connected to different
  • the second pads 720, and the second pads 720 connected to the third trace G21 and the second pads 720 connected to the fourth trace G22 are alternately arranged.
  • a complete second wire group G2 is shown in FIG. 12 .
  • the third wire G21 is electrically connected to the second pads 720 No. 3 and No. 5 from the left
  • the fourth wire G22 is electrically connected to the No. 4 from the left. No. 6 and No. 6 second solder joints 720.
  • Each solder ball is soldered between a first solder joint 710 and a corresponding second solder joint 720 so that the first wiring G11 on the first insulating substrate 71 and the third wiring G21 on the second insulating substrate 72
  • the electrical connection forms the first link as described above, and the second wire G12 on the first insulating substrate 71 and the fourth wire G22 on the second insulating substrate 72 are electrically connected to form the second wire as described above. link.
  • the first trace G11 on the first insulating substrate 71 is complementary to the third trace G21 on the second insulating substrate 72, and the first trace G11 on the first insulating substrate 71 is complementary.
  • the second trace G12 is complementary to the fourth trace G22 on the second insulating substrate 72 .
  • the printed circuit board for testing of the present application can use the design of the traces formed on the insulating substrate to conveniently and simply realize the detection of the open circuit and short circuit problems in solder ball welding.

Abstract

一种堆叠印刷电路板（20）。该堆叠印刷电路板（20）应用于无人飞行器，其包括第一印刷电路板（21）、第二印刷电路板（22）及连接第一印刷电路板（21）和第二印刷电路板（22）的多个焊球（23）。第一印刷电路板（21）包括多个第一焊点（210），第二印刷电路板（22）包括多个第二焊点（220），每个焊球（23）焊接于一个第一焊点（210）与对应的一个第二焊点（220）之间，以在堆叠印刷电路板（20）上形成互不电连接的第一链路（201）和第二链路（202），形成第一链路（201）的焊球（23）与形成第二链路（202）的焊球（23）之间相互交错排布。能够方便地检测出印刷电路板焊接的开路及短路问题。

Description

堆叠印刷电路板 技术领域
本申请涉及检测链路设计技术领域，尤其涉及一种堆叠印刷电路板。
背景技术
传统的印刷电路板(Printed Circuit Board，PCB)堆叠设计主要依靠X-ray等无损手段进行焊点的短路检测。然而，因为X-ray的局限性很难观测到开路的异常现象，而且，X-ray的检测方式无法实时测试，无法实时检出PCB堆叠结构在可靠性过程中焊点的短时间开路问题。
发明内容
本申请的目的在于提供一种堆叠印刷电路板，能够方便地检测出印刷电路板焊接的开路及短路问题。
本申请的一个方面提供一种堆叠印刷电路板。所述堆叠印刷电路板包括第一印刷电路板、第二印刷电路板及连接所述第一印刷电路板和所述第二印刷电路板的多个焊球。所述第一印刷电路板包括多个第一焊点，所述第二印刷电路板包括多个第二焊点，每个所述焊球焊接于一个所述第一焊点与对应的一个所述第二焊点之间，以在所述堆叠印刷电路板上形成互不电连接的第一链路和第二链路，形成所述第一链路的焊球与形成所述第二链路的焊球之间相互交错排布。
本申请的堆叠印刷电路板通过设置两条独立的第一链路和第二链路，从而能够实现用万用表等电阻测量设备即可检测印刷电路板中的焊接开路及短路问题。并且，在后续的可靠性测试中也可以对链路进行实时监测，及时地捕捉到在测试过程中因为形变导致的焊点断裂而导致的电阻异常等现象。
附图说明
图1为一种堆叠印刷电路板的链路示意图；
图2为在图1所示的堆叠印刷电路板中的第一印刷电路板上形成的第一链路图；
图3为在图1所示的堆叠印刷电路板中的第二印刷电路板上形成的第二链路图；
图4为本申请一个实施例的堆叠印刷电路板的截面示意图；
图5为本申请一个实施例的堆叠印刷电路板的链路的平面示意图；
图6为本申请另一个实施例的堆叠印刷电路板的链路的平面示意图；
图7为本申请另一个实施例的堆叠印刷电路板的链路的平面示意图；
图8为图7所示的堆叠印刷电路板的链路的截面示意图；
图9为本申请又一个实施例的堆叠印刷电路板的链路的平面示意图；
图10为本申请再一个实施例的堆叠印刷电路板的链路的平面示意图；
图11为本申请一个实施例的测试用印刷电路板中的第一绝缘基板的走线图；
图12为本申请一个实施例的测试用印刷电路板中的第二绝缘基板上的走线图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。除非另作定义，本申请使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“多个”或者“若干”表示两个及两个以上。除非另行指出，“前部”、“后部”、“下部”和/或“上部”等类似词语只是为了便于说明，而并非限于一个位置或者一种空间定向。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。在本申请说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能 组合。
下面结合附图，对本申请的各个实施例进行详细说明。在不冲突的情况下，下述的实施例及实施方式中的特征可以相互组合。
图1揭示了一种堆叠印刷电路板的链路100示意图，图2揭示了在该堆叠印刷电路板中的第一印刷电路板11上形成的链路图，及图3揭示了在该堆叠印刷电路板中的第二印刷电路板12上形成的链路图。如图1至图3所示，该堆叠印刷电路板包括第一印刷电路板11和第二印刷电路板12，在第一印刷电路板11上形成第一链路L11，在第二印刷电路板12上形成第二链路L12，其中，在第一印刷电路板11上形成的第一链路L11与第二印刷电路板12上形成的第二链路L12互为互补关系，从而，在第一印刷电路板11和第二印刷电路板12通过多个焊球13电性堆叠在一起时，在堆叠印刷电路板上形成一条串联的链路100，即一条菊花链路。通过检测该链路100的首尾，如图1中所示的IN-OUT之间的电阻可以检测出焊球13的开路问题。然而，该链路100却无法检测焊球13与焊球13之间的桥接问题。
有鉴于此，本申请提出了一种改进的技术解决方案。
图4揭示了本申请一个实施例的堆叠印刷电路板20的截面示意图。如图4所示，本申请一个实施例的堆叠印刷电路板20包括第一印刷电路板21、第二印刷电路板22以及连接第一印刷电路板21和第二印刷电路板22之间的多个焊球23，从而将第一印刷电路板21和第二印刷电路板22上下堆叠在一起形成类似三明治PCB结构。第一印刷电路板21包括多个第一焊点210，第二印刷电路板22包括多个第二焊点220。
每个焊球23焊接于一个第一焊点210与对应的一个第二焊点220之间，以在由第一印刷电路板21和第二印刷电路板22构成的堆叠印刷电路板20上形成互不电连接的第一链路201和第二链路202。图5揭示了本申请一个实施例的堆叠印刷电路板20上形成的链路200的平面示意图。如图5所示，形成第一链路201的焊球23与形成第二链路202的焊球23之间相互交错排布。所谓交错排布是指形成第一链路201的相邻两个焊球23之间具有形成第二链路202的一个焊球23，形成第二链路202的相邻两个焊球23之间具有形成第一链路201的一个焊球23。
在图5所示的实施例中，形成第一链路201的焊球23与形成第二链路202的焊球23排列成一排。例如，在图5中以单排四列焊球23被示出。第一链路201和第二链路202为两个独立的串联链路。
在本申请的该堆叠印刷电路板20中，通过设置两个独立的第一链路201和第二链路202，利用第一链路201和第二链路202既可以检测链路200中的焊球23是否有开路的现象，也可以检测链路200中的焊球23是否有短路的现象。具体地，在本申请的第一链路201和第二链路202中，对于同一链路，可以用来检测形成该链路的焊球23是否存在开路情况，而不同链路的相邻焊球23之间可以用来检测该相邻焊球23是否存在短路情况。
例如，可以利用万用表或者datalogger等电阻测量设备通过测量第一链路201中的IN1-OUT1两点的电阻可以判断第一链路201中的焊球23，例如左起1号和3号焊球23是否有开路现象；同样地，通过测量第二链路202中的IN2-OUT2两点之间的电阻可以判断第二链路202中的焊球23，例如左起2号和4号焊球23是否有开路现象。通过测量第一链路201中的IN1点和第二链路202中的IN2点之间的电阻可以判断相邻的第一链路201中的焊球23与第二链路202中的焊球23，例如左起1号和2号焊球23之间是否有短路现象；通过测量第二链路202中的IN2点和第一链路201中的OUT1点之间的电阻可以判断相邻的第二链路202中的焊球23与第一链路201中的焊球23，例如左起2号和3号焊球23之间是否有短路现象；同样地，通过测量第一链路201中的OUT1点和第二链路202中的OUT2点之间的电阻可以判断相邻的第一链路201中的焊球23与第二链路202中的焊球23，例如左起3号和4号焊球23之间是否有短路现象。从而，可以方便容易地检测出堆叠印刷电路板20中的所有焊球23的开短路现象。
图6揭示了本申请另一个实施例的堆叠印刷电路板20上形成的链路300的平面示意图。如图6所示，在堆叠印刷电路板20上形成多个独立的链路组301，每个链路组301包括第一链路201和第二链路202。形成每一链路组301的焊球23排列成一排。例如，在图6中以三排四列焊球23被示出，图6中以具有三个链路组301为例被示意性示出。
不同排的焊球23具有独立的链路组301，即不同排的焊球23分别具有独立的第一链路201和第二链路202。
在本申请的该堆叠印刷电路板20中，通过设置多个独立的包括第一链路201和第二链路202的链路组301，既可以利用每一链路组301中的第一链路201和第二链路202检测每一链路组301中的焊球23的开短路现象，又可以利用不同的链路组301来检测不同链路组301中的焊球23之间是否存在短路现象。
具体地，对于同一链路组301中的焊球23的检测，可以与图5所示的焊球23的 检测相类似。在图6中对于不同排的焊球23来说，不同链路组301中的相邻焊球23之间可以用来检测该相邻焊球23是否存在短路现象。
例如，可以利用万用表或者datalogger等电阻测量设备通过测量上述1号链路组301的第一链路201中的IN1点与2号链路组301的第一链路201中的IN3点之间的电阻可以判断1号链路组301的1号焊球23与2号链路组301的1号焊球23是否有短路现象；通过测量上述1号链路组301的第二链路202中的OUT2点与2号链路组301的第二链路202中的OUT2点之间的电阻可以判断1号链路组301的4号焊球23与2号链路组301的4号焊球23是否有短路现象，其他焊球23的检测以此类推。从而，可以方便容易地检测出堆叠印刷电路板20中的所有焊球23的开短路现象。
需要说明的是，在本申请中所提到的焊球23以排或列等形式排列均是相对而言。在本申请的说明书及其附图中虽然焊球23以排或列等完全规整的方式被示出，然而，在实际的堆叠印刷电路板20中，第一焊点210、第二焊点220以及焊球23之间的排布可能并非以完全规整的行或列的形式排布。
以上是以一排具有四个焊球23的实施例为例来描述本申请的堆叠印刷电路板20的链路的。然而，本申请并不局限于此，本申请设置独立的第一链路201和第二链路202来检测焊球23开短路的创作思路同样可以适用于堆叠印刷电路板20包括更多焊球23的情况。
图7揭示了本申请又一个实施例的堆叠印刷电路板上形成的链路400的平面示意图，图8揭示了图7所示的堆叠印刷电路板上形成的链路400的截面示意图。在图7和图8中，实线表示在第一印刷电路板21上形成的链路，虚线表示在第二印刷电路板22上形成的链路，圆圈表示第一焊点210、第二焊点220及焊球23三者堆叠在一起的示意。如图7和8所示，第一链路401可以进一步包括连接第一印刷电路板21上的一部分第一焊点210的第一子链路L41和连接第二印刷电路板22上的一部分第二焊点220的第二子链路L42。
例如，从左边起算，第一印刷电路板21上的第一子链路L41连接1―3号、5―7号……第一焊点210，第二印刷电路板22上的第二子链路L42连接3―5号……第二焊点220。第一印刷电路板21上的第一子链路L41与第二印刷电路板22上的第二子链路L42互补。相邻的第一子链路L41与第二子链路L42通过同一个焊球23电连接。例如，连接1―3号第一焊点210的第一子链路L41与连接3―5号第二焊点220的第二子链路L42相邻，并且，连接1―3号第一焊点210的第一子链路L41与连接3―5号第二焊点 220的第二子链路L42通过左起第3号焊球23彼此电连接。
第二链路402可以进一步包括连接第一印刷电路板21上的另一部分第一焊点210的第三子链路L43和连接第二印刷电路板22上的另一部分第二焊点220的第四子链路L44。
在一些实施例中，本申请的链路400可以由第一印刷电路板21和/或第二印刷电路板22上的走线设计形成。例如，第一印刷电路板21上的第一子链路L41包括形成于第一印刷电路板21上的走线，称之为第一走线；第二印刷电路板22上的第二子链路L42包括形成于第二印刷电路板22上的走线，称之为第三走线。第一印刷电路板21上的第三子链路L43包括形成于第一印刷电路板21上的走线，称之为第二走线；第二印刷电路板22上的第四子链路L44包括形成于第二印刷电路板22上的走线，称之为第四走线。
例如，从左边起算，第一印刷电路板21上的第三子链路L43连接2―4号、6―8号……第一焊点210，第二印刷电路板22上的第四子链路L44连接4―6号……第二焊点220。第一印刷电路板21上的第三子链路L43与第二印刷电路板22上的第四子链路L44互补。相邻的第三子链路L43与第四子链路L44通过同一个焊球23电连接。例如，连接2―4号第一焊点210的第三子链路L43与连接4―6号第二焊点220的第四子链路L44相邻，并且，连接2―4号第一焊点210的第三子链路L43与连接4―6号第二焊点220的第四子链路L44通过左起第4号焊球彼此电连接。
可以参照利用图5所示的链路400的类似检测方式，来利用图8所示的链路400来检测堆叠印刷电路板中的开短路现象。例如，可以利用第一链路401的首尾点IN1-OUT1点之间的电阻来检测形成第一链路401中的焊球是否存在开路现象，利用第二链路402的首尾点IN2-OUT2之间的电阻来检测形成第二链路402中的焊球是否存在开路现象，利用相邻的第一链路401中的IN1点与第二链路402中的IN2之间的电阻检测来检测第一链路401与第二链路402中相邻的焊球之间是否存在短路现象，对于其他焊球的检测以此类推，在此不再赘述。
因此，本申请通过在上下堆叠的第一印刷电路板21和第二印刷电路板22上分别设计出两条独立的第一链路401和第二链路402，从而能够实现用万用表等电阻测量设备即可检测印刷电路板中的焊接开路及短路问题，并且，在后续的可靠性测试中也可以对链路400进行实时监测，及时地捕捉到在测试过程中因为形变导致的焊点断裂而导致的电阻异常等现象。
本申请上面各个实施例所述的堆叠印刷电路板可以应用于高集成度要求的消费类电子产品领域。例如，在一个实施例中，本申请上面各个实施例所述的堆叠印刷电路板可以包括例如无人飞行器的可移动平台、运动相机或玩具等电子产品所用功能板对应的测试板。
图9揭示了本申请再一个实施例的堆叠印刷电路板的链路500示意图。与图7和图8所示的链路400所不同的是，在图9中，在堆叠印刷电路板上形成多个独立的链路组501，每个链路组501包括第一链路401和第二链路402。形成每一链路组501的焊球排列成一排。在图9中以具有四个链路组501为例被示意性示出。
可以参照利用图6所示的链路300的类似检测方式，来利用图9所示的链路500来检测堆叠印刷电路板中的开短路现象。故，在此不再赘述。
针对多排焊球，通过设置多个独立的链路组501，从而可以针对每排焊球进行独立检测，从而可以快速定位出发生问题的焊球所在的排数。
对于多排焊球来说，本申请可以对应地设置多个独立的链路组。然而，本申请并不局限于此。在本申请的其他实施例中，如图10所示，也可以将多排焊球的首尾连接在一起而整体仅形成一个包括第一链路601和第二链路602的链路600，从而可以通过同一链路的首尾点，例如IN1-OUT1或IN2-OUT2之间电阻的检测快速判断出该链路是否存在开路现象，从而可以大大减少测试点数。
本申请还提供了一种测试用印刷电路板。图11揭示了本申请一个实施例的测试用印刷电路板中的第一绝缘基板71的走线图。如图11所示，该测试用印刷电路板包括第一绝缘基板71及形成于第一绝缘基板71的表面上的多个第一焊点710。该测试用印刷电路板还包括形成于第一绝缘基板71上的至少一个第一走线组G1。每个第一走线组G1包括互不电连接的第一走线G11和第二走线G12。第一走线G11可以用来形成第一链路的一部分，第二走线G12可以用来形成第二链路的一部分，第一走线G11和第二走线G12分别电连接不同的第一焊点710。并且，连接第一走线G11的第一焊点710和连接第二走线G12的第一焊点710之间相互交错排布。例如，图11中示出完整的两个第一走线组G1。对于图11中所示的左起1号第一走线组G1来说，第一走线G11电连接左起1号和3号第一焊点710，第二走线G12电连接左起2号和4号第一焊点710。对于图11中所示的左起2号第一走线组G1来说，第一走线G11电连接左起5号和7号第一焊点710，第二走线G12电连接左起6号和8号第一焊点710。
图12揭示了本申请一个实施例的测试用印刷电路板中的第二绝缘基板72上的走线图。如图12所示，在一些实施例中，该测试用印刷电路板还包括第二绝缘基板72、形成于第二绝缘基板72的表面上的多个第二焊点720、形成第二绝缘基板72的表面上的至少一个第二走线组G2、以及将第一绝缘基板71和第二绝缘基板72连接在一起的多个焊球(未图示)。每个第二走线组G2包括互不电连接的第三走线G21和第四走线G22。第三走线G21可以用来形成第一链路的另一部分，第四走线G22可以用来形成第二链路的另一部分，第三走线G21和第四走线G22分别电连接不同的第二焊点720，并且，连接第三走线G21的第二焊点720和连接第四走线G22的第二焊点720之间相互交错排布。例如，图12中示出完整的一个第二走线组G2。对于图12中所示的左起1号第二走线组G2来说，第三走线G21电连接左起3号和5号第二焊点720，第四走线G22电连接左起4号和6号第二焊点720。
每个焊球焊接于一个第一焊点710与对应的一个第二焊点720之间以使第一绝缘基板71上的第一走线G11和第二绝缘基板72上的第三走线G21电连接形成如上面所述的第一链路，并且，第一绝缘基板71上的第二走线G12和第二绝缘基板72上的第四走线G22电连接形成如上面所述的第二链路。
结合参照图11和图12所示，在一些实施例中，第一绝缘基板71上的第一走线G11与第二绝缘基板72上的第三走线G21互补，第一绝缘基板71上的第二走线G12与第二绝缘基板72上的第四走线G22互补。
本申请的测试用印刷电路板可以利用绝缘基板上形成的走线设计能够方便简单地实现焊球焊接中出现的开路和短路问题的检测。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。

Claims (10)

  1. 一种堆叠印刷电路板，应用于无人飞行器，其特征在于，包括：
    第一印刷电路板，包括多个第一焊点；
    第二印刷电路板，包括多个第二焊点；以及
    多个焊球，连接所述第一印刷电路板和所述第二印刷电路板，
    其中，每个所述焊球焊接于一个所述第一焊点与对应的一个所述第二焊点之间，以在所述堆叠印刷电路板上形成互不电连接的第一链路和第二链路，形成所述第一链路的焊球与形成所述第二链路的焊球之间相互交错排布。
  2. 如权利要求1所述的堆叠印刷电路板，其特征在于，形成所述第一链路的焊球与形成所述第二链路的焊球排列成一排。
  3. 如权利要求1所述的堆叠印刷电路板，其特征在于，所述第一链路和所述第二链路为两个独立的串联链路。
  4. 如权利要求3所述的堆叠印刷电路板，其特征在于，所述第一链路包括连接所述第一印刷电路板上的一部分所述第一焊点的第一子链路和连接所述第二印刷电路板上的一部分所述第二焊点的第二子链路。
  5. 如权利要求4所述的堆叠印刷电路板，其特征在于，所述第一子链路与所述第二子链路互补。
  6. 如权利要求5所述的堆叠印刷电路板，其特征在于，相邻的所述第一子链路与所述第二子链路通过同一个所述焊球电连接。
  7. 如权利要求3所述的堆叠印刷电路板，其特征在于，所述第二链路包括连接所述第一印刷电路板上的另一部分所述第一焊点的第三子链路和连接所述第二印刷电路板上的另一部分所述第二焊点的第四子链路。
  8. 如权利要求7所述的堆叠印刷电路板，其特征在于，所述第三子链路与所述第四子链路互补。
  9. 如权利要求8所述的堆叠印刷电路板，其特征在于，相邻的所述第三子链路与所述第四子链路通过同一个所述焊球电连接。
  10. 如权利要求3所述的堆叠印刷电路板，其特征在于，在所述第一链路和所述第二链路中，同一链路用于检测形成该链路的焊球是否存在开路情况，不同链路的相邻焊球之间用于检测该相邻焊球是否存在短路情况。
PCT/CN2020/135412 2020-09-23 2020-12-10 堆叠印刷电路板 WO2022062198A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101515018A (zh) * 2008-02-22 2009-08-26 纬创资通股份有限公司 电路检测回路及制造使用方法
CN103743991A (zh) * 2013-12-27 2014-04-23 广州兴森快捷电路科技有限公司 Pcb板的导电孔电性能测试方法及装置
CN107450009A (zh) * 2016-05-31 2017-12-08 展讯通信（上海）有限公司 一种集成电路测试装置及采用其测试焊点的方法
CN109029225A (zh) * 2018-10-09 2018-12-18 信丰迅捷兴电路科技有限公司 一种微盲孔镭射成孔质量定期检测方法
US20200103295A1 (en) * 2018-09-28 2020-04-02 Intel Corporation Integrated strain gauges to evaluate printed circuit board integrity during operation

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101515018A (zh) * 2008-02-22 2009-08-26 纬创资通股份有限公司 电路检测回路及制造使用方法
CN103743991A (zh) * 2013-12-27 2014-04-23 广州兴森快捷电路科技有限公司 Pcb板的导电孔电性能测试方法及装置
CN107450009A (zh) * 2016-05-31 2017-12-08 展讯通信（上海）有限公司 一种集成电路测试装置及采用其测试焊点的方法
US20200103295A1 (en) * 2018-09-28 2020-04-02 Intel Corporation Integrated strain gauges to evaluate printed circuit board integrity during operation
CN109029225A (zh) * 2018-10-09 2018-12-18 信丰迅捷兴电路科技有限公司 一种微盲孔镭射成孔质量定期检测方法

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