201142317 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種檢測方法，特別是指一種檢測印 刷電路板（PCB)中各個焊塾之間的線路連接情況的電路檢測 方法。 【先前技術】 隨著科技進步，印刷電路板（Printed Circuit Board， PCB)的技術不斷精進且種類繁多，例如··單層電路板、多 層電路板（Multilayer PCB)及高密度連接電路板（High201142317 VI. Description of the Invention: [Technical Field] The present invention relates to a detecting method, and more particularly to a circuit detecting method for detecting a line connection between respective soldering pads in a printed circuit board (PCB). [Prior Art] With the advancement of technology, the technology of Printed Circuit Board (PCB) has been continuously improved and varied, such as single-layer boards, multilayer PCBs, and high-density connection boards (High).
Density Interconnection，HDI PCB)等，但同時也增加了其 中線路測試的困難度》 習知針對印刷電路板中各個焊墊之間線路開路（〇pen)/ 短路（short)的測試技術’主要有兩種：菊鍵型（Daisy chain) 及梳形圖案型（Comb Pattern)。 菊鏈型的測試技術主要是將印刷電路板中所有的焊墊 相互串接’並在頭尾兩端分別拉出一測試點（test pacj)，以檢 測其中的電流變化，若在測試點量測不到電流，則表示焊 塾之間的線路有發生開路的現象，如此將可進行後續的處 理與改善。但是，此種測試技術將只能檢測出線路之間的 開路現象，並無法檢測出線路之間的短路現象，如此檢測 結果的可靠度將大打折扣。 梳形圖案型的測試技術主要是如圖1所示，將印刷電 路板900中所有的焊墊以梳形的圖案相互交錯的連接，其 中在五個線路交界處分別拉出一測試點910，以檢測各測試 201142317 點的電流變化，若在測試點9】〇量測到有電流變化，則表 示焊墊之間的線路有發生短路的現象，如此將可進行後續 的處理與改善。同樣的，此種測試技術將只能檢測出線路 之間的短路現象，並無法檢測出線路之間的開路現象，且 右當中某一條測試路徑92〇的終端發生開路（〇pen)現象時 (如圖2所不），測試技術將無法檢測出該測試路徑92〇與旁 邊的測試路徑930所發生的短路（sh〇rt)現象。 【發明内容】 癱 因此本發明之目的，即在提供一種可以同時檢測出 印刷電路板之開路（open)及短路（sh〇rt)現象的電路檢測方 法。 於是，本發明電路檢測方法，係應用於檢測一待測電 路板’該電路檢測方法包含以下步驟： (A)置備一測試電路板，該測試電路板包含多數焊墊組 及多數個測試點，該等測試點分別連接每一焊墊組兩端的 焊墊’以形成一測試路徑； 籲 （B)將该等測試路徑通以電流，並檢測該等測試路徑是 否有電流通過，以判斷各該測試路徑是否發生開路異常現 象；及 (C)將任一測試點及其他任一與該測試點在不同測試路 徑的測試點與一測試電源電連接，並檢測該二測試點是否 有電流通過，以判斷各該測試路徑是否發生短路異常現 象。 較佳地，步驟（B)係將每一測試路徑的測試點與測試電 201142317 源電連接，並檢測各該測試路徑是否有電流通過。 較佳地，步驟（B)係將相隔一條的各該測試路徑相互串 接形成該另一測試路徑，再將該另一測試路徑的該二位於 末端的測試點與測試電源連接’以檢測該二測試點是否有 電流通過。 較佳地，步驟（C)係將至少部分該等測試路徑透過該等 測試點連接而形成另二各自獨立的測試路徑，並將該二測 試路徑各取一測試點與測試電源連接，以檢測該二測試點 是否有電流通過。 本發明之功效在於，透過本發明電路檢測方法能夠同 時檢測出印刷電路板中各個焊墊之間開路及短路的線路。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之一個較佳實施例的詳細說明中，將可 清楚的呈現。 參閱圖3及圖4，圖3為本發明電路檢測方法之較佳實 施例’ a亥電路檢測方法係應用於如圖4所示之一待測電路 板100，用以針對該待測電路板丨00進行線路的檢測。在本 貫施例中，β亥待測電路板loo係為一高密度連接（High Density Interconnection，HDI)電路板，當然也可以是多層 板（Multilayer PCB)或是軟性電路板等，不以此為限。 在本實施例中’待測電路板1〇〇包含一電路板本體 10，及6又於該電路板本體1 〇的多數焊塾組6〇與多數個測 試點（test pad)30 ’其中每一焊墊組60中具有多數個焊塾 201142317 (pad)20 〇 ' 本實施例之焊墊組60的數量共有8組，而每一焊塾組 60中具有8個焊墊20，且該等焊墊20係以一 8x8的矩陣 排列，但不以此為限’且在該矩陣中，每一行中的8個焊 墊20係為一組焊墊組60且彼此透過金屬線相互串接。為 了方便以下描述，如圖5所示’從左到右的每一行焊塾2〇 分別標示為八、&、：6、13、（：、（：、〇及（1，且在每一行焊塾 20令從上到下的焊墊20分別標示為i〜8，。 # 特別說明的是，焊墊20的數量及排列方式可以根據不 同的使用需求而改變，且在圖5中各個焊墊20是呈現在同 一平面上以方便說明，實際上連接各個焊墊2〇之間的線路 可能位於電路板本體1〇中的不同層，配合參閱圖6，以 al〜a8來說明，第三個焊墊a3及第四個焊墊a4之間，與第 七個焊墊a7及第八個焊墊a8之間係透過第三層金屬線連 接，而第一個焊墊al及第二個焊墊a2之間，與第五個焊墊 a5及第六個焊墊a6之間係透過第二層金屬線連接，而電流 • 流過的路徑係以虛線所示。 測試點30係用以檢測各個焊墊2〇之間線路的連接情 況，且其數量在本實施例中共有16個，係分別連接於該矩 陣中每一焊墊組60頭尾兩端的焊墊2〇,也就是該矩陣中第 一列的焊墊20與第八列的焊墊2〇會分別連接一個測試點 3〇，使得每一焊墊組60中的八個焊墊2〇及二個測試點3〇 相互串接形成一獨立的測試路徑，即圖5中所示 L1(A0 〜A9)、L2(a0 〜a9)、L3(B0 〜B9)、L4(b0 〜b9)、 201142317 L8(d0〜d9)的八條測 L5(C0〜C9)、L6(c0〜c9)、L7(D0〜D9)及 試路徑》 接者參關3,以下料細說明本實施例之電路 法係如何檢測各個焊塾2G ^的線路是否出現開路⑽ 或紐路（short)的現象。其中，步驟sl〇是針對該待測電 1〇〇進行開路測試(量測高阻值變化)，即檢測各個焊墊加之 間的線路是否發生開路情況，而步驟S2G則是針對該待= 電路板100進行短路測試（量測低阻值變化）。 ' 步驟S10 ’將每一條測試路徑（L1〜L8)的測試點扣與一 測試電源40(如圖7所示）電連接形成一迴路，以檢測每^條 測試路徑是否有電流通過，若所有測試路徑皆有電流通 過，則表示該等载路財各個焊墊2G之間的線路並無開 路情況，即開路檢測通過則接著執行步驟S2〇 ;若其中有任 條測忒路徑無電流通過，則表示該（等）測試路徑中各個焊 塾20之間的線路有開路情況，如此將進行後續的分析（如微 切片等）與修補（步驟S30)。 參閱圖7，以測試路徑L1來說明，測試電源4〇係電連 接於測試路徑L1的測試點A〇及A9，以形成一開路測試迴 路I ’並且量測測試點A0及A9是否有電流通過，若有則 表示通過開路檢測（即測試路徑L1中的線路無開路現象）， 而其他的測試路徑（L2〜L8)皆以同樣的方式檢測是否有開路 情況，故不多加贅述。 此外’為了增加檢測效率，步驟Si〇還可以先將相隔 一條的測試路徑相互串接（即奇數條接奇數條及偶數條接偶 201142317 數條）’之後再檢測串接後的測試路 處所指的「串接」係透過連接測試路:；：電流通過。此 成’參閱圖8，以串接奇數停 、Ά點30來完 τ ㈣料路_卩職路徑L1、Density Interconnection, HDI PCB), etc., but also increased the difficulty of the line test." There are two main test techniques for the circuit open (short) / short between the pads in the printed circuit board. Species: Daisy chain and Comb Pattern. The daisy-chain test technology mainly connects all the solder pads in the printed circuit board to each other' and pulls a test point (test pacj) at both ends of the head and tail to detect the current change, if at the test point If the current is not detected, it means that there is an open circuit on the line between the welding dies, which will enable subsequent processing and improvement. However, this test technique will only detect the open circuit between the lines and will not detect the short circuit between the lines, so the reliability of the test results will be greatly reduced. The test pattern of the comb pattern is mainly as shown in FIG. 1 , and all the pads in the printed circuit board 900 are connected to each other in a comb pattern, wherein a test point 910 is respectively pulled out at the intersection of the five lines. In order to detect the current change of each test at 201142317 point, if there is a current change at the test point 9], it means that there is a short circuit between the pads, so that subsequent processing and improvement can be performed. Similarly, this kind of test technology will only detect the short circuit between the lines, and can not detect the open circuit between the lines, and when the terminal of one of the right test paths 92〇 is open (〇pen) phenomenon ( As shown in Figure 2, the test technique will not be able to detect the short circuit (sh〇rt) phenomenon that occurs between the test path 92〇 and the adjacent test path 930. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a circuit detecting method capable of simultaneously detecting an open circuit and a short circuit (short) phenomenon of a printed circuit board. Therefore, the circuit detection method of the present invention is applied to detecting a circuit board to be tested. The circuit detection method includes the following steps: (A) providing a test circuit board including a plurality of pad groups and a plurality of test points. The test points are respectively connected to the pads at both ends of each pad group to form a test path; (B) the test paths are connected with current, and the test paths are detected to have current passing, so as to determine the respective Whether the test path has an open circuit abnormality; and (C) electrically connecting any one of the test points and any test point of the test point at a different test path to a test power source, and detecting whether the two test points have current passing, To determine whether each test path has a short circuit abnormality. Preferably, step (B) electrically connects the test points of each test path with the test power 201142317 source, and detects whether each test path has current passing through. Preferably, in step (B), the test paths are separated from each other to form the other test path, and the two test points at the end of the other test path are connected to the test power source to detect the At the second test point, there is current passing. Preferably, in step (C), at least some of the test paths are connected through the test points to form two separate test paths, and each test path is connected to the test power source to detect Whether there is current passing through the two test points. The effect of the present invention is that the circuit detection method of the present invention can simultaneously detect open and short circuits between the pads in the printed circuit board. The above and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. Referring to FIG. 3 and FIG. 4, FIG. 3 is a schematic diagram of a circuit detection method according to a preferred embodiment of the present invention. The method for detecting a circuit is applied to a circuit board 100 to be tested as shown in FIG. 4, and is used for the circuit board to be tested.丨00 performs line detection. In the present embodiment, the βH test board loo is a High Density Interconnection (HDI) circuit board, and of course, it may be a Multilayer PCB or a flexible circuit board. Limited. In the present embodiment, the circuit board 1 to be tested includes a circuit board body 10, and 6 of the plurality of soldering holes 6 of the circuit board body 1 and a plurality of test pads 30' each. There is a plurality of soldering pads 201142317 (pad) 20 〇 in a pad group 60. The number of pad groups 60 of the present embodiment has 8 groups, and each pad group 60 has 8 pads 20, and these The pads 20 are arranged in an 8x8 matrix, but are not limited thereto, and in the matrix, the eight pads 20 in each row are a set of pad groups 60 and are connected to each other through metal wires. For the convenience of the following description, as shown in FIG. 5, each row of solder joints 2 from left to right is marked as eight, &,: 6, 13, (:, (:, 〇, and (1, and in each row). The soldering pads 20 are used to mark the solder pads 20 from top to bottom as i~8, respectively. # Specifically, the number and arrangement of the solder pads 20 can be changed according to different use requirements, and the soldering is performed in FIG. The pads 20 are presented on the same plane for convenience of explanation. Actually, the lines connecting the pads 2 〇 may be located in different layers of the circuit board body 1 ,, with reference to FIG. 6 , illustrated by a1 to a8, and third. Between the pad a3 and the fourth pad a4, and the seventh pad a7 and the eighth pad a8 are connected through the third layer of metal wires, and the first pad a and the second Between the pads a2, and the fifth pad a5 and the sixth pad a6 are connected through the second layer of metal wires, and the path through which the current flows is indicated by a broken line. Detecting the connection of the wires between the pads 2, and the number of the pads is 16 in the embodiment, which are respectively connected to the matrix. The pads 2 at the ends of each of the pad groups 60, that is, the pads 20 of the first column in the matrix and the pads 2 of the eighth column are respectively connected to a test point 3〇, so that each pad The eight pads 2〇 and the two test points 3〇 in the group 60 are connected in series to form an independent test path, that is, L1 (A0 to A9), L2 (a0 to a9), and L3 (B0) shown in FIG. ~B9), L4 (b0 to b9), 201142317 L8 (d0~d9), eight tests L5 (C0~C9), L6 (c0~c9), L7 (D0~D9) and test path" 3, the following is a detailed description of how the circuit method of the present embodiment detects whether there is an open circuit (10) or a short circuit in the line of each solder 塾 2G ^, wherein step s1〇 is performed for the power to be tested. The open circuit test (measuring the high resistance value change), that is, detecting whether the circuit between the pads is open, and the step S2G is performing a short circuit test (measuring the low resistance value) for the circuit board 100 to be tested. Step S10' electrically connecting each test path (L1~L8) to a test power source 40 (shown in FIG. 7) to form a loop to detect whether each test path has If the current passes, if all the test paths have current passing, it means that there is no open circuit between the 2G pads of each of the load pads, that is, the open circuit detection is passed, and then step S2 is performed; if any one of them is tested If there is no current passing through the path, it means that there is an open circuit in the line between each soldering iron 20 in the (equal) test path, so that subsequent analysis (such as micro-slice, etc.) and repair (step S30) will be performed. Test path L1 indicates that test power supply 4 is electrically connected to test points A 〇 and A9 of test path L1 to form an open circuit test circuit I ' and measure whether test currents A0 and A9 have current passing, if any By open circuit detection (that is, the circuit in the test path L1 has no open circuit phenomenon), and other test paths (L2 to L8) detect whether there is an open circuit in the same manner, so no more details are added. In addition, in order to increase the detection efficiency, the step Si〇 can also first connect the test paths that are separated by one another (that is, the odd-numbered strips are connected to the odd-numbered strips and the even-numbered strips are connected to the 201142317 strips), and then the test roads after the tandem connection are detected. The "serial connection" is through the connection test path:;: current is passed. This is shown in Figure 8. The odd-numbered stop and the Ά point 30 are completed in series. τ (4) Feed path _ 卩 路径 path L1
L3、L5及L7)來說，其中是 K路位U 接、測試點B9與測試點〇連接tA〇與測試點-連 連接，之後再將兩端的測試點A9^；=CG與測試點 連接而形成-開路賴迴路„ ,並且4+ 9與測試電源4〇 、峪II，並且針對測試點Α9及D〇 進行量測是否有電流通過，若有，For L3, L5 and L7), where is the K-way U connection, the test point B9 and the test point 〇 connection tA〇 and the test point-connection, and then the test points A9^;=CG at both ends are connected to the test point And form a - open circuit „, and 4+ 9 and test power supply 4〇, 峪II, and measure the test point Α9 and D〇 whether there is current, if any,
有則表示所有奇數條浪丨4 路徑中各個焊塾20之間的後拉^ 114 φ 的線路並無開路情況，如此將只須 要檢測兩次（奇數條及偶數條各一 、 „ 人）可大幅降低測試時 間0 而當進行步驟S20時，練—測試點（例如：測試點B9) 及其他任—與該測試點B9纟不同測試路徑的測試點（例 如·測試點b〇)與測試電源40電連接，如圖9所示，並檢 測二測試點B9及b0是否有電流通過。由於測試點B9所在 的測試路徑u與測試點b0所在的測試路徑l4係屬於不同 的測試路徑’因此在測試點則及b〇與測試電源4〇相連接 後，理論上在測試路徑L3及測試路徑L4上不會有電流通 過，^在測試點B9與測試點b〇上不會量測到電流因 此，右有電流通過，則表示測試點B9所在的測試路徑U 及測式點b〇所在的測試路役L4之間有發生短路情況，如 圖9中&路區塊5Q所示’亦將進行後續的分析與修補（步驟 S3〇)。若並無電流通過測試路徑L3及測試路徑L4，則測試 釔束，表不待測電路板1〇〇上所有焊墊2〇之間的線路皆正 201142317 常。特別說明的是，圖9中短路區塊50同樣可以透過測試 點B0及b9，或是測試點B0及b0，或是測試點B9及⑽而 被檢測出，不以本實施例為限。 此外，在步驟S20中還可以先將至少部分的測試路徑 透過其中測試點30的連接而形成另二各自獨立的測試路 徑，並將該二測試路徑各取一測試點3〇與該測試電源4〇 連接以檢測該一測試點3 0是否有電流通過。參閱圖1 〇， 其t是將測試路徑L1及測試路徑L2透過測試點A〇及測試 點a〇而連接’測試路徑L3及測試路徑L4透過測試點B0 及測試點b〇而連接，並且將測試點A9及測試點b9與測試 電源40連接，同樣可以利用檢測電流而判斷出二測試路徑 之間是否發生短路現象。 —綜上所述，本發明電路檢測方法藉由在待測電路板1〇< 上每一組焊墊組60兩端的焊墊2〇各連接一測試點3〇，^ 適當地連接該等測試點30 待測電路板1 〇〇中各個焊墊 達成本發明之目的。 而形成不同的測試迴路，以檢測 20之間的線路情況，故確實能In some cases, there is no open circuit for the post-pull 114 φ line between each of the odd-welded four paths in the odd-wave 4 path, so that it only needs to be detected twice (odd and even, „人) Substantially reduce test time 0. When performing step S20, practice - test point (for example: test point B9) and other test points (for example, test point b〇) and test power supply with different test paths from the test point B9纟40 electrical connection, as shown in Figure 9, and check whether the two test points B9 and b0 have current passing. Because the test path u where the test point B9 is located and the test path l4 where the test point b0 is located belong to different test paths' After the test point and b〇 are connected to the test power supply 4〇, theoretically no current will pass through the test path L3 and the test path L4, and the current will not be measured at the test point B9 and the test point b〇. If there is current passing right, it means that there is a short circuit between the test path U where the test point B9 is located and the test road L4 where the test point b is located, as shown in the & road block 5Q in Figure 9 Perform subsequent analysis and repair (step S 3〇). If there is no current passing the test path L3 and the test path L4, the test beam is bundled, and the line between all the pads 2〇 on the circuit board 1待 of the board to be tested is positive 201142317. The short-circuit block 50 in FIG. 9 can also be detected through the test points B0 and b9, or the test points B0 and b0, or the test points B9 and (10), not limited to this embodiment. Furthermore, in step S20 The at least part of the test path may be first formed through the connection of the test point 30 to form two separate test paths, and each of the two test paths is taken from a test point 3〇 to be connected to the test power source 4〇 to detect the test path. Whether there is current passing through a test point 30. Referring to Figure 1, t, t is to connect test path L1 and test path L2 through test point A〇 and test point a〇 and connect 'test path L3 and test path L4 through test point B0. And the test point b〇 is connected, and the test point A9 and the test point b9 are connected to the test power source 40, and the detection current can also be used to determine whether a short circuit phenomenon occurs between the two test paths. - In summary, the circuit of the present invention Detection method On the circuit board to be tested, the solder pads 2 at each end of each group of pad pads 60 are connected to a test point 3〇, ^ are properly connected to the test points 30, and each soldering in the circuit board 1 to be tested The pad achieves the purpose of the present invention. Different test circuits are formed to detect the line condition between 20, so it is indeed possible
惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍’即大凡依本發明中請專利 範圍及發明說明内容所作之簡單的等效變化與修飾，皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 說明習知梳形圖案型測試技術的線 圖1是一配線圖 路連接方式； 10 201142317 圖2是—示意圖，說明梳形圖案型的測試技術在其中 某條測试路徑的終端發生開路現象時，將無法檢測出兮 測試路徑與旁邊的測試路徑所發生的短路現象； ^ 包◊圖3疋—流程圖，說明本發明電路檢測方法之較佳實 圖4疋—電路不意圖，說明本實施例之待測電路板， 其中/、有一電路板本體、以8χ8矩陣排列的64個焊墊，及 16個測試點；However, the above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto. All remain within the scope of the invention patent. [Simple diagram of the diagram] The line diagram 1 of the conventional comb pattern test technique is a wiring diagram connection method; 10 201142317 Fig. 2 is a schematic diagram illustrating a comb pattern type test technique in which one test path When the terminal has an open circuit, it will not be able to detect the short circuit phenomenon that occurs between the test path and the test path next to it; ^ Figure 3疋—flow chart showing the better actual circuit of the circuit detection method of the present invention. It is not intended to describe the circuit board to be tested of this embodiment, wherein /, there is a circuit board body, 64 pads arranged in a matrix of 8 χ 8 , and 16 test points;
圖5是-電路示意圖，說明各個焊#、測試點及測試 路徑的標示； 圖疋 4面圖，說明測試路徑L2中各個焊塾實際的 線路連接情況； _圖7疋一電路示意圖，說明測試電源電連接於測試路 徑L1的測試點Α〇及Aq &…丄 次A9而形成一開路測試迴路I ; 圖8是一電路矛咅固 坪下思圖’說明測試路徑LI、L3、L5及 L7相互串接的線路連接情況； 圖9是一電路示音闰 丁恩圖，說明測試電源4〇電連接於測試 點B9及測試點b0的線路連接情況；及 圖10是一電路千立η '、‘思圖’說明測試路徑L1與測試路徑 L2，及測試路徑L3與 丹則试路徑L4的線路連接情況。 201142317 【主要元件符號說明】 100 . ……待測電路板 •測5式 10... ……電路板本體 A1 〜A 8 · · •焊墊 20·.. ……焊墊 B1 〜Β8·. •焊墊 30... ......測試點 Cl 〜C8·· •焊墊 40··· ......測5式電源 D1 〜D 8 · · •焊墊 50··· ......短路£塊 al〜a8… •焊墊 60··· ......焊墊組 b1〜b8… •焊墊 A0、 BO、CO、D0 c1〜c8… •焊墊 ......測5式點 dl 〜d8·.· -焊墊 A9、B9、C9、D9Figure 5 is a schematic diagram of the circuit, showing the indication of each solder #, test point and test path; Figure 4 is a side view showing the actual line connection of each solder fillet in the test path L2; _ Figure 7 疋 a circuit diagram illustrating the test The power supply is electrically connected to the test point of the test path L1 and the Aq &... times A9 to form an open circuit test circuit I; Fig. 8 is a circuit of the spear 咅 ping down the diagram 'describe the test paths LI, L3, L5 and L7 is connected in series with each other; FIG. 9 is a circuit diagram showing the circuit connection of the test power supply 4〇 electrically connected to the test point B9 and the test point b0; and FIG. 10 is a circuit 千立η ', 'Thinking' illustrates the test path L1 and test path L2, and the test line L3 and Dan test path L4 line connection. 201142317 [Explanation of main component symbols] 100 . . . The circuit board to be tested • Test 5 type 10... ...... Board body A1 ~ A 8 · · • Solder pad 20·........ Solder pad B1 ~ Β • Solder pad 30... ...... Test point Cl ~ C8 · · • Pad 40 · · · ... Test 5 type power supply D1 ~ D 8 · · • Solder pad 50··· ...... Short circuit £ block a~a8... • Solder pad 60··· ... pad group b1~b8... • Pad A0, BO, CO, D0 c1~c8... • Pad ......Measure 5 points dl ~d8·.· - pads A9, B9, C9, D9
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