WO2015090004A1 - 阵列基板及其制备方法 - Google Patents

阵列基板及其制备方法 Download PDF

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Publication number
WO2015090004A1
WO2015090004A1 PCT/CN2014/078543 CN2014078543W WO2015090004A1 WO 2015090004 A1 WO2015090004 A1 WO 2015090004A1 CN 2014078543 W CN2014078543 W CN 2014078543W WO 2015090004 A1 WO2015090004 A1 WO 2015090004A1
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WIPO (PCT)
Prior art keywords
lead
array substrate
gate
forming
patterning process
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Ceased
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PCT/CN2014/078543
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English (en)
French (fr)
Inventor
胡海琛
郤玉生
刘家荣
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US14/406,950 priority Critical patent/US9502441B2/en
Publication of WO2015090004A1 publication Critical patent/WO2015090004A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • Embodiments of the present invention relate to an array substrate and a method of fabricating the same. Background technique
  • TFT Thin Film Transistor
  • LCDs Thin Film Transistor
  • TFT array substrate and color film substrate A lead pad (Lead PAD) region is provided on the periphery of the box portion. The main function of the Lead PAD region is to add test signals for electrical property detection during the preparation of the array substrate.
  • the preparation process of the array substrate is divided into: forming a gate metal layer, the gate metal layer including a gate electrode and a gate line; forming a gate insulating layer and an amorphous silicon semiconductor layer; forming a source/drain metal layer, a source/drain metal layer The source electrode, the drain electrode and the data line are included; a passivation layer is formed; and a pixel electrode is formed.
  • An embodiment of the present invention provides an array substrate, including:
  • both ends of the signal line disconnection position are electrically connected through the connection lead.
  • a connection lead is disposed in an adjacent layer of the signal line, and both ends of the signal line disconnection position are connected by the connection lead, thereby avoiding the problem that the metal after the array substrate is cut is easily corroded.
  • the signal line includes a gate line
  • the connection lead includes a first lead; wherein the first lead is formed on the substrate, and the gate line is located on the first lead upper layer.
  • the first lead and the gate line are disposed on two adjacent layers, thereby achieving direct contact between the first lead and the gate line, thereby avoiding the use of the via process, thereby reducing process complexity.
  • the signal line further includes a data line
  • the connection lead further includes a second lead
  • the array substrate structure further includes a gate insulating layer, the second lead is formed on the gate insulating layer, and the data line is located on an upper layer of the second lead.
  • the second lead and the data line are disposed on two adjacent layers, thereby achieving direct contact between the second lead and the data line, thereby avoiding the use of the via process, thereby reducing process complexity.
  • the signal line includes a gate line
  • the connection lead includes a first lead
  • the array substrate structure further includes a gate insulating layer
  • the first lead is formed on the gate insulating layer
  • the gate line is located on an upper layer of the first lead.
  • the first lead and the gate line are disposed on two adjacent layers, thereby achieving direct contact between the first lead and the gate line, thereby avoiding the use of the via process, thereby reducing process complexity.
  • the signal line further includes a data line
  • the connection lead further includes a second lead
  • the second lead is formed on the substrate, the data line is located on an upper layer of the second lead, and the gate insulating layer is formed on the data line.
  • the second lead and the data line are disposed on two adjacent layers, thereby achieving direct contact between the second lead and the data line, thereby avoiding the use of the via process, thereby reducing process complexity.
  • a plurality of common electrodes are further included, and the first lead and the common electrode are disposed in the same layer.
  • the first lead is disposed in the same layer as the common electrode to reduce the preparation process and reduce the cost.
  • connection leads is a conductive oxide, for example, indium tin oxide, indium oxide or aluminum oxide.
  • the connecting leads are made of an inert material to improve corrosion resistance.
  • connection lead formed by an inert material is disposed on an adjacent layer of the gate line or/and the data line, and both ends of the gate line or/and the disconnected position of the data line are connected by the connection lead, thereby avoiding The metal after the array substrate is cut is susceptible to corrosion.
  • Embodiments of the present invention provide a method for preparing an array substrate, including:
  • a first metal thin film is formed, and a gate electrode and a plurality of gate lines are formed by a patterning process, the gate lines being disconnected at a dicing area of the substrate, and electrically connected through the first leads.
  • the preparation method further includes:
  • Forming a second metal thin film forming a source electrode, a drain electrode, and a plurality of data lines by a patterning process, the data lines being disconnected at a dicing area of the substrate, and electrically connected through the second lead;
  • Forming an active layer film forming an active layer by a patterning process
  • a passivation layer film is formed, and a passivation layer is formed by a patterning process.
  • connection lead formed by an inert material is disposed on an adjacent layer of the gate line or/and the data line, and both ends of the gate line or/and the disconnected position of the data line are connected by the connection lead, thereby avoiding The metal after the array substrate is cut is susceptible to corrosion.
  • Embodiments of the present invention provide a method for preparing an array substrate, including:
  • Forming a second conductive film forming a plurality of second leads and a plurality of pixel electrodes by a patterning process; forming a second metal film, forming a source electrode, a drain electrode, and a plurality of data lines by a patterning process, wherein the data lines are on the substrate
  • the cutting area is broken and electrically connected through the second lead.
  • the preparation method further includes:
  • Forming an active layer film forming an active layer by a patterning process
  • first conductive film Forming a first conductive film, forming a plurality of first leads and a plurality of common electrodes by a patterning process; forming a first metal film, forming a gate electrode and a plurality of gate lines by a patterning process, the gate lines being on the substrate The cutting area is broken and electrically connected through the first lead;
  • a passivation layer film is formed, and a passivation layer is formed by a patterning process.
  • the material of at least one of the first lead and the second lead is a conductive oxide.
  • the beneficial effects of the embodiments of the present invention are as follows: a connection lead formed by an inert material is disposed on an adjacent layer of the gate line or/and the data line, and both ends of the gate line or/and the disconnected position of the data line are connected by the connection lead, thereby avoiding The metal after the array substrate is cut is susceptible to corrosion.
  • 1 is a top plan view showing the structure of the gate line of the array substrate in the Lead PAD region;
  • Figure 2 is a cross-sectional view of the portion A-A of Figure 1;
  • 3 is a top plan view showing the structure of the data line of the array substrate in the Lead PAD region;
  • Figure 4 is a cross-sectional view of the portion A-A of Figure 3;
  • FIG. 5 is a top plan view showing the structure of a gate line of an array substrate in a lead PAD region according to an embodiment of the present invention
  • Figure 6 is a cross-sectional view of the portion A-A of Figure 5;
  • FIG. 7 is a cross-sectional view showing an array substrate according to an embodiment of the present invention, which is connected at both ends of a gate line disconnection position in a Lead PAD region;
  • FIG. 8 is a top plan view showing the structure of a data line of an array substrate in a lead PAD region according to an embodiment of the present invention.
  • Figure 9 is a cross-sectional view of the portion A-A of Figure 8.
  • FIG. 10 is a cross-sectional view showing an array substrate according to an embodiment of the present invention, which is connected at both ends of a data line disconnection position of a Lead PAD region.
  • FIG. 1 and FIG. 2 are schematic diagrams showing a design structure of a Lead PAD region corresponding to a gate line of a TFT array substrate and a cross-sectional view thereof at an AA portion.
  • the gate line Lead PAD structure includes: a substrate 1, a gate line 2, at least one via 8 (only one via 8 is shown in FIG. 1), and a test pad 9, wherein Mark 12 is indicated as the array substrate cut.
  • a gate insulating layer 3 is overlaid on the gate line 2
  • a passivation layer 5 is overlaid on each of the above portions. Test pad 9 through the grid
  • the via holes 8 of the pole insulating layer 3 and the passivation layer 5 are connected to the gate line 2.
  • FIG. 1 and FIG. 2 are schematic diagrams showing a design structure of a Lead PAD region corresponding to a gate line of a TFT array substrate and a cross-sectional view thereof at an AA portion.
  • the gate line Lead PAD structure includes: a substrate 1, a gate line 2,
  • the design structure of the Lead PAD region corresponding to the data line of the current mainstream array substrate and the cross-sectional view thereof at the AA portion are shown.
  • the data line Lead PAD structure includes: a substrate 1, a data line 4, at least one via 10 (only one via 10 is shown in FIG. 3), and a test pad 11, wherein reference numeral 13 Indicated as the array substrate cut.
  • the data line 4 is disposed between the gate insulating layer 3 and the passivation layer 5, and the passivation layer 5 covers the above portions.
  • the test pad 11 is connected to the data line 4 through the via 10 of the passivation layer 5.
  • An embodiment of the present invention provides an array substrate, including:
  • connecting leads are disposed on adjacent layers of the signal lines, the connecting leads correspond to the positions of the disconnections of the signal lines, and are in direct contact with the signal lines;
  • both ends of the signal line disconnection position are electrically connected by a connection lead.
  • connecting leads are disposed in adjacent layers of the signal lines, and both ends of the signal line disconnecting position are connected by the connecting leads, thereby avoiding the problem that the metal after the cutting of the array substrate is easily corroded.
  • the signal line includes a gate line
  • the connection lead includes a first lead; wherein the first lead is formed on the substrate, and the gate line is located on the upper layer of the first lead.
  • This structure is generally used in an array substrate of a bottom gate type structure in which a gate line is broken at a substrate cutting region, and both ends of the gate line are electrically connected through a first lead.
  • the first lead and the gate line are disposed on two adjacent layers, thereby achieving direct contact between the first lead and the gate line, thereby avoiding the use of the via process, thereby reducing process complexity.
  • the signal line further includes a data line
  • the connection lead further includes a second lead
  • the array substrate structure further includes a gate insulating layer
  • the second lead is formed on the gate insulating layer
  • the data line is located on the upper layer of the second lead .
  • the structure is also used in an array substrate of a bottom gate type structure in which a data line is disconnected at a substrate cutting region, and both ends of the data line are electrically connected by a second lead.
  • the second lead and the data line are disposed on two adjacent layers, thereby achieving direct contact between the second lead and the data line, thereby avoiding the use of the via process, thereby reducing process complexity.
  • the array substrate further includes a plurality of common electrodes, and the first lead and the common electrode are disposed in the same layer.
  • the first lead is disposed in the same layer as the common electrode to reduce the preparation process and reduce the cost. of course, Not all of the array substrate structure is suitable for the first lead and the common electrode are disposed in the same layer.
  • the bottom gate type array substrate structure provided in this embodiment is only an exemplary solution, and the first lead can also be set by an independent process to adapt to various arrays. Substrate architecture.
  • the signal line includes a gate line
  • the connection lead includes a first lead
  • the array substrate structure further includes a gate insulating layer, the first lead is formed on the gate insulating layer, and the gate line is located on the upper layer of the first lead.
  • This structure is generally used in an array substrate of a top gate type structure in which a gate line is broken at a substrate cutting region, and both ends of the gate line are electrically connected by a first lead.
  • the first lead and the gate line are disposed on two adjacent layers, thereby achieving direct contact between the first lead and the gate line, thereby avoiding the use of the via process, thereby reducing process complexity and reducing resistance.
  • the signal line further includes a data line
  • the connection lead further includes a second lead; wherein the second lead is formed on the substrate, the data line is located on the upper layer of the second lead, and the gate insulating layer is formed on the data line .
  • the structure is also used in an array substrate of a top gate type structure in which a data line is disconnected in a substrate cutting region, and both ends of the data line being disconnected are electrically connected through a second lead.
  • the second lead and the data line are disposed on two adjacent layers, thereby achieving direct contact between the second lead and the data line, thereby avoiding the use of the via process, thereby reducing process complexity and reducing resistance.
  • the array substrate of the above embodiment is exemplified by a bottom gate type and a top gate type gate line and a data line, respectively.
  • the architecture of the array substrate in this embodiment is only for the purpose of illustrating the present invention, and the present invention is equally applicable to other array substrates, and is not limited thereto.
  • the array substrate provided by the present invention does not mean an array substrate for display, but an array substrate structure in which a plurality of display array substrates are formed on one substrate and not cut.
  • the material of the connecting lead is indium tin oxide, indium oxide or aluminum oxide.
  • the connecting leads are made of an inert material to improve corrosion resistance.
  • connection lead formed by an inert material is disposed on an adjacent layer of the gate line or/and the data line, and both ends of the gate line or/and the disconnected position of the data line are connected by the connection lead, thereby avoiding The metal after the array substrate is cut is susceptible to corrosion.
  • FIG. 5 shows a schematic top view of a gate line structure of the array substrate in a lead pad (Lead PAD) region.
  • FIG. 5 only shows the array substrate.
  • Multi-layered gate line 2, via 8 and test pad 9, the gate line 2 is in the array
  • the cut 12 of the substrate is broken.
  • FIG. 6 is a schematic cross-sectional view showing the AA position shown in FIG. 5, including a substrate 1, and a gate line 2 over the substrate 1, a gate insulating layer 3 over the gate line 2, a passivation layer 5; At least one end of the off position of the pole line 2 is connected to the test pad 9 through the via 8; between the gate line 2 and the substrate 1, the first lead 6 is disposed, and both ends of the off position of the gate line 2 pass through the first The lead wires 6 are connected.
  • the first lead 6 shown in Fig. 6 is disposed at the position where the corresponding gate line 2 is turned off, and is capable of connecting both ends of the position where the gate line 2 is turned off.
  • the joint Since the both ends of the off position of the gate line 2 are connected by the first lead 6 which is in direct contact with the gate line 2, the joint has a small resistance.
  • the first lead 6 may be disposed under all of the gate lines 2.
  • FIG. 7 a schematic cross-sectional view showing the ends of the gate line 2 at the disconnected position is shown.
  • the meanings of the respective reference numerals are the same as those of FIGS. 5 and 6, and FIG. 7 clearly shows that the gate line 2 is broken. Both ends of the open position, and the both ends are connected by the first lead 6.
  • FIG. 8 is a top view of the data line structure of the lead substrate in the lead pad (Lead PAD) region. For clarity of the drawing, FIG. 8 only shows the data line 4, the via 10 and the test lining of the multilayer structure of the array substrate. Pad 11, the data line 4 is broken at the cut 13 of the array substrate.
  • Figure 9 is a cross-sectional view showing the AA position shown in Figure 8, including the substrate 1, and the gate insulating layer 3 over the substrate 1, the data line 4 over the gate insulating layer 3, above the data line 4.
  • the second lead 7 shown in Fig. 9 is disposed at the position where the corresponding data line 4 is disconnected, and is capable of connecting the disconnected position of the data line 4.
  • the joint Since the both ends of the disconnected position of the data line 4 are connected by the second lead 7 which is in direct contact with the data line 4, the joint has a small resistance. It is also possible to provide the second lead 7 below all the data lines 4 except for the position where the corresponding data line 4 is disconnected. Referring to FIG. 10, a schematic cross-sectional view of the ends of the data line 4 at the disconnected position is connected. The meanings of the reference numerals are the same as those of FIGS. 8 and 9. The two ends of the data line 4 are connected by the second lead 7 at the disconnected position. together.
  • the gate lines 2 as shown in FIG. 6 are connected by the first ITO lead 6 at the off position, or may have only the structure shown in FIG.
  • the structure in which the data line 4 is connected by the second lead 7 at the disconnection position may also have a structure in which the gate line 2 as shown in FIG. 6 is connected by the first ITO lead 6 at the disconnected position, and FIG. 9 Shown The data line 4 is connected by the second lead 7 at the disconnected position.
  • the gate line 2 may be a single layer or a composite layer structure composed of one or any combination of aluminum, chromium, tungsten, tantalum, molybdenum, and aluminum nickel.
  • the data line 4 may be a single layer or a composite layer structure composed of one or any combination of aluminum, chromium, tungsten, tantalum, molybdenum, and aluminum nickel.
  • the material of the gate insulating layer 3 may be silicon nitride, silicon dioxide or aluminum oxide.
  • the material of the passivation layer 5 may be silicon nitride, silicon dioxide or aluminum oxide.
  • the material of the first lead 6 may be a conductive oxide such as indium tin oxide, indium oxide or aluminum oxide.
  • the material of the second lead 7 may be a conductive oxide such as indium tin oxide, indium oxide or alumina.
  • the array substrate further includes a gate electrode disposed in the same layer as the gate line 2, a source electrode and a drain electrode disposed in the same layer as the data line, and a pixel electrode on the passivation layer, and the like.
  • a gate electrode disposed in the same layer as the gate line 2
  • a source electrode and a drain electrode disposed in the same layer as the data line
  • a pixel electrode on the passivation layer and the like.
  • connection lead formed by an inert material is disposed on an adjacent layer of the gate line or/and the data line, and both ends of the gate line or/and the disconnected position of the data line are connected by the connection lead, thereby avoiding The metal after the array substrate is cut is susceptible to corrosion.
  • Embodiments of the present invention provide a method for preparing an array substrate, including:
  • a first conductive film is formed on the substrate, and a plurality of first leads and a plurality of common electrodes are formed by a patterning process.
  • a first metal thin film is formed, and a gate electrode and a plurality of gate lines are formed by a patterning process, the gate lines being disconnected at a dicing area of the substrate, and electrically connected through the first leads.
  • a second metal thin film Forming a second metal thin film, forming a source electrode, a drain electrode, and a plurality of data lines by a patterning process, the data lines being disconnected at a dicing area of the substrate, and electrically connected by the second lead; forming an active layer film Forming an active layer by a patterning process;
  • a passivation layer film is formed, and a passivation layer is formed by a patterning process.
  • connection lead formed by an inert material is disposed on an adjacent layer of the gate line or/and the data line, and both ends of the gate line or/and the disconnected position of the data line are connected by the connection lead, thereby avoiding The metal after the array substrate is cut is susceptible to corrosion.
  • Embodiments of the present invention provide a method for preparing an array substrate, including:
  • Forming a second conductive film forming a plurality of second leads and a plurality of pixel electrodes by a patterning process; Forming a second metal thin film, forming a source electrode, a drain electrode, and a plurality of data lines by a patterning process, the data lines being disconnected at a dicing area of the substrate, and electrically connected through the second lead;
  • Forming an active layer film forming an active layer by a patterning process
  • first conductive film Forming a first conductive film, forming a plurality of first leads and a plurality of common electrodes by a patterning process; forming a first metal film, forming a gate electrode and a plurality of gate lines by a patterning process, the gate lines being on the substrate The cutting area is broken and electrically connected through the first lead;
  • a passivation layer film is formed, and a passivation layer is formed by a patterning process.
  • the patterning process in the embodiments of the present invention generally includes: photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • a photoresist positive
  • the photoresist layer is exposed; after development, the photoresist in the exposed region is removed to expose the first metal film, and the photoresist in the unexposed region remains; the first metal film is etched, and the first metal film in the exposed region is engraved Etched, the first metal film of the unexposed area is not etched due to photoresist protection; the remaining photoresist is stripped to form a pattern including the gate electrode and the plurality of gate lines.
  • connection lead formed by an inert material is disposed on an adjacent layer of the gate line or/and the data line, and both ends of the gate line or/and the disconnected position of the data line are connected by the connection lead, thereby avoiding The metal after the array substrate is cut is susceptible to corrosion.
  • the array substrate in the embodiment of the present invention can be used as an array substrate of a TFT-LCD, or can be applied to a display device such as an organic light emitting diode (OLED) or an electronic paper, or can be applied to an electronic device such as an X-ray detector.
  • a display device such as an organic light emitting diode (OLED) or an electronic paper
  • OLED organic light emitting diode
  • X-ray detector an X-ray detector

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  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)
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Abstract

一种阵列基板及其制备方法。该阵列基板包括：一基板（1）；金属层形成的多条信号线（2，4），所述信号线（2，4）在所述基板（1）的切割区域（12，13）断开；多条连接引线（6，7），所述连接引线（6，7）设置于所述信号线（2，4）的相邻层，与所述信号线（2，4）的断开处（12，13）的位置对应，且与所述信号线（2，4）直接接触；其中，所述信号（2，4）线断开位置的两端通过所述连接引线（6，7）电连接。在栅极线（2）或/和数据线（3）的相邻层设置惰性材料形成的连接引线（6，7），栅极线（2）或/和数据线（3）断开位置的两端通过该连接引线（6，7）连接，避免上述阵列基板切割后的金属容易被腐蚀的问题。

Description

阵列基板及其制备方法 技术领域
本发明的实施例涉及一种阵列基板及其制备方法。 背景技术
在平板显示技术中， 薄膜晶体管（Thin Film Transistor, TFT )液晶显示 器（Liquid Crystal Display, LCD )具有功耗低、 制造成本相对较低和无辐射 的特点， 因此在平板显示器市场占据了主导地位。 TFT阵列基板和彩膜基板 对盒部分的外围， 设置引线衬垫（Lead PAD ) 区域。 Lead PAD区域的主要 作用是在阵列基板制备过程中， 加入测试信号进行电学特性检测。
通常阵列基板的制备工艺步骤分为： 形成栅金属层， 栅金属层包括栅极 和栅极线； 形成栅极绝缘层和非晶硅半导体层； 形成源漏极金属层， 源漏极 金属层包括源电极、 漏电极及数据线； 形成钝化层； 形成像素电极。
上述工艺由于在 Lead PAD 区域釆用一体的无间断引线设计结构， 在阵 列基板进行切割工艺时， 会对金属层及绝缘层造成破坏， 产生细小裂纹， 因 此在使用过程中随着水蒸汽等的渗透， 会出现栅金属层和源漏金属层的金属 被腐蚀的现象。 发明内容
本发明实施例提供一种阵列基板， 包括：
基板；
金属层形成的多条信号线， 所述信号线在所述基板的切割区域断开； 多条连接引线， 所述连接引线设置于所述信号线的相邻层， 所述连接引 线与所述信号线的断开处的位置对应， 且与所述信号线直接接触；
其中， 所述信号线断开位置的两端通过所述连接引线电连接。
本发明实施例中， 在信号线的相邻层设置连接引线， 信号线断开位置的 两端通过该连接引线连接， 避免上述阵列基板切割后的金属容易被腐蚀的问 题。 在一个示例中， 所述信号线包括栅极线， 所述连接引线包括第一引线； 其中， 所述第一引线形成于所述基板之上， 所述栅极线位于所述第一引 线的上层。 本实施例中， 第一引线和栅极线设置于相邻的两层， 从而实现第 一引线和栅极线直接接触， 避免釆用过孔工艺， 从而减少工艺复杂度。
在一个示例中， 所述信号线还包括数据线， 所述连接引线还包括第二引 线；
所述阵列基板结构还包括栅极绝缘层， 所述第二引线形成于所述栅极绝 缘层之上， 所述数据线位于所述第二引线的上层。 本实施例中， 第二引线和 数据线设置于相邻的两层， 从而实现第二引线和数据线线直接接触， 避免釆 用过孔工艺， 从而减少工艺复杂度。
在一个示例中， 所述信号线包括栅极线， 所述连接引线包括第一引线； 所述阵列基板结构还包括栅极绝缘层， 所述第一引线形成于所述栅极绝 缘层之上， 所述栅极线位于所述第一引线的上层。 本实施例中， 第一引线和 栅极线设置于相邻的两层， 从而实现第一引线和栅极线直接接触， 避免釆用 过孔工艺， 从而减少工艺复杂度。
在一个示例中， 所述信号线还包括数据线， 所述连接引线还包括第二引 线；
其中， 所述第二引线形成于所述基板之上， 所述数据线位于所述第二引 线的上层， 所述栅极绝缘层形成于所述数据线之上。 本实施例中， 第二引线 和数据线设置于相邻的两层， 从而实现第二引线和数据线线直接接触， 避免 釆用过孔工艺， 从而减少工艺复杂度。
在一个示例中， 还包括多个公共电极， 所述第一引线和所述公共电极同 层设置。 本实施例中， 第一引线与公共电极同层设置， 以减少制备工序和降 低成本。
在一个示例中， 所述连接引线的材料为导电氧化物， 例如， 氧化铟锡、 氧化铟辞或氧化铝辞。 本实施例中， 连接引线釆用惰性的材料制备， 以提高 耐腐蚀性能。
本发明实施例有益效果如下：在栅极线或 /和数据线的相邻层设置惰性材 料形成的连接引线， 栅极线或 /和数据线断开位置的两端通过该连接引线连 接， 避免上述阵列基板切割后的金属容易被腐蚀的问题。 本发明实施例提供一种阵列基板的制备方法， 包括：
在基板上形成第一导电薄膜， 通过构图工艺形成多条第一引线和多个公 共电极；
形成第一金属薄膜， 通过构图工艺形成栅电极和多条栅极线， 所述栅极 线在所述基板的切割区域断开， 并通过所述第一引线电连接。
在一个示例中， 该制备方法还包括：
形成栅极绝缘层；
形成第二导电薄膜， 通过构图工艺形成多条第二引线；
形成第二金属薄膜， 通过构图工艺形成源电极、 漏电极和多条数据线， 所述数据线在所述基板的切割区域断开， 并通过所述第二引线电连接；
形成有源层薄膜， 通过构图工艺形成有源层；
形成钝化层薄膜， 通过构图工艺形成钝化层。
本发明实施例有益效果如下：在栅极线或 /和数据线的相邻层设置惰性材 料形成的连接引线， 栅极线或 /和数据线断开位置的两端通过该连接引线连 接， 避免上述阵列基板切割后的金属容易被腐蚀的问题。
本发明实施例提供一种阵列基板的制备方法， 包括：
形成第二导电薄膜， 通过构图工艺形成多条第二引线和多个像素电极； 形成第二金属薄膜， 通过构图工艺形成源电极、 漏电极和多条数据线， 所述数据线在所述基板的切割区域断开， 并通过所述第二引线电连接。
在一个示例中， 该制备方法还包括：
形成有源层薄膜， 通过构图工艺形成有源层；
形成栅极绝缘层薄膜， 通过构图工艺形成栅极绝缘层；
形成第一导电薄膜， 通过构图工艺形成多条第一引线和多个公共电极； 形成第一金属薄膜， 通过构图工艺形成栅电极和多条栅极线， 所述栅极 线在所述基板的切割区域断开， 并通过所述第一引线电连接；
形成钝化层薄膜， 通过构图工艺形成钝化层。
在一个示例中，上述第一引线和第二引线至少之一的材料为导电氧化物。 本发明实施例有益效果如下：在栅极线或 /和数据线的相邻层设置惰性材 料形成的连接引线， 栅极线或 /和数据线断开位置的两端通过该连接引线连 接， 避免上述阵列基板切割后的金属容易被腐蚀的问题。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为阵列基板在 Lead PAD区域栅极线的结构俯视示意图；
图 2为图 1中 A-A部分横截面示意图；
图 3为阵列基板在 Lead PAD区域数据线的结构俯视示意图；
图 4为图 3中 A-A部分横截面示意图；
图 5本发明实施例提供的一种阵列基板在 Lead PAD区域栅极线的结构 俯视示意图；
图 6为图 5中 A-A部分横截面示意图；
图 7本发明实施例提供的一种阵列基板在示出在 Lead PAD区域栅极线 断开位置处两端连接在一起的截面示意图；
图 8本发明实施例提供的一种阵列基板在 Lead PAD区域数据线的结构 俯视示意图；
图 9为图 8中 A-A部分横截面示意图；
图 10本发明实施例提供的一种阵列基板在示出在 Lead PAD区域数据线 断开位置处两端连接在一起的截面示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
图 1 、图 2是 TFT阵列基板的栅极线所对应的 Lead PAD区域的设计结 构及其在 A-A部位的截面示意图。 如图 1所示， 该栅极线 Lead PAD 结构包 括:基板 1、 一栅极线 2、 至少一个过孔 8 (图 1中只示出一个过孔 8 )和测试 衬垫 9， 其中附图标记 12指示为阵列基板切割处。 如图 2 所示， 栅极绝缘 层 3覆盖在栅极线 2上， 钝化层 5覆盖在上述各部分上。 测试衬垫 9通过栅 极绝缘层 3和钝化层 5 的过孔 8 与栅极线 2相连接。如图 3 、 图 4， 是目前 主流的阵列基板的数据线所对应的 Lead PAD区域的设计结构及其在 A-A部 位的截面示意图。 如图 3所示， 该数据线 Lead PAD 结构包括:基板 1、 一数 据线 4、 至少一个过孔 10 (图 3中只示出一个过孔 10 )和测试衬垫 11， 其中 附图标记 13 指示为阵列基板切割处。 如图 4 所示， 数据线 4设置于栅极绝 缘层 3和钝化层 5之间，钝化层 5覆盖在上述各部分上。测试衬垫 11通过钝 化层 5 的过孔 10与数据线 4相连接。
本发明实施例提供一种阵列基板， 包括：
一基板；
金属层形成的多条信号线， 信号线在基板的切割区域断开；
多条连接引线， 连接引线设置于信号线的相邻层， 连接引线与信号线的 断开处的位置对应， 且与信号线直接接触；
其中， 信号线断开位置的两端通过连接引线电连接。
本发明实施例中， 在信号线的相邻层设置连接引线， 信号线断开位置的 两端通过该连接引线连接， 避免上述阵列基板切割后的金属容易被腐蚀的问 题。
以信号线为栅极线或 /和数据线为例进行描述如下：
例如： 信号线包括栅极线， 连接引线包括第一引线； 其中， 第一引线形 成于基板之上， 栅极线位于第一引线的上层。 该结构通常用于底栅型结构的 阵列基板中， 栅极线在基板切割区域断开， 栅极线断开的两端通过第一引线 电连接。 本实施例中， 第一引线和栅极线设置于相邻的两层， 从而实现第一 引线和栅极线直接接触， 避免釆用过孔工艺， 从而减少工艺复杂度。
在一个示例中， 信号线还包括数据线， 连接引线还包括第二引线； 阵列 基板结构还包括栅极绝缘层， 第二引线形成于栅极绝缘层之上， 数据线位于 第二引线的上层。 该结构同样用于底栅型结构的阵列基板中， 数据线在基板 切割区域断开， 数据线断开的两端通过第二引线电连接。 本实施例中， 第二 引线和数据线设置于相邻的两层， 从而实现第二引线和数据线线直接接触， 避免釆用过孔工艺， 从而减少工艺复杂度。
本实施例中， 该阵列基板还包括多个公共电极， 第一引线和公共电极同 层设置。 第一引线与公共电极同层设置， 以减少制备工序和降低成本。 当然， 并非全部的阵列基板架构适合第一引线与公共电极同层设置， 本实施例提供 的底栅型的阵列基板架构只是一个示例的方案， 第一引线也可以通过独立工 艺设置， 以适应各种阵列基板架构。
又例如： 信号线包括栅极线， 连接引线包括第一引线； 阵列基板结构还 包括栅极绝缘层， 第一引线形成于栅极绝缘层之上， 栅极线位于第一引线的 上层。 该结构通常用于顶栅型结构的阵列基板中， 栅极线在基板切割区域断 开， 栅极线断开的两端通过第一引线电连接。 本实施例中， 第一引线和栅极 线设置于相邻的两层， 从而实现第一引线和栅极线直接接触， 避免釆用过孔 工艺， 从而减少工艺复杂度， 也减少了电阻。
在一个示例中，信号线还包括数据线， 连接引线还包括第二引线； 其中， 第二引线形成于基板之上， 数据线位于第二引线的上层， 栅极绝缘层形成于 数据线之上。 该结构同样用于顶栅型结构的阵列基板中， 数据线在基板切割 区域断开， 数据线断开的两端通过第二引线电连接。 本实施例中， 第二引线 和数据线设置于相邻的两层， 从而实现第二引线和数据线线直接接触， 避免 釆用过孔工艺， 从而减少工艺复杂度， 也减少了电阻。
上述实施例的阵列基板分别以底栅型和顶栅型的栅极线和数据线为例进 行说明。 当然， 本实施例中的阵列基板的架构只是为了说明本发明， 本发明 同样适用于其他的阵列基板， 并非以此为限。 同时， 应当说明的是， 本发明 提供的阵列基板并非指一个显示用阵列基板， 而是多个显示用阵列基板形成 于一个衬底基板上且未割时的阵列基板结构。
例如， 连接引线的材质为氧化铟锡、 氧化铟辞或氧化铝辞。 本实施例中， 连接引线釆用惰性的材料制备， 以提高耐腐蚀性能。
本发明实施例有益效果如下：在栅极线或 /和数据线的相邻层设置惰性材 料形成的连接引线， 栅极线或 /和数据线断开位置的两端通过该连接引线连 接， 避免上述阵列基板切割后的金属容易被腐蚀的问题。
为了便于理解， 结合附图对信号线为栅极线或数据线时的阵列基板结构 进行说明：
参见图 5， 本发明实施例提供一种阵列基板， 图 5示出了该阵列基板在 引线衬垫（Lead PAD )区域栅极线结构俯视示意图， 为了示图清晰， 图 5仅 示出阵列基板多层结构的栅极线 2、过孔 8和测试衬垫 9，该栅极线 2在阵列 基板的切割处 12断开。
图 6示出了在图 5所示 A-A位置的截面示意图， 包括基板 1， 以及基板 1之上的栅极线 2， 栅极线 2之上的栅极绝缘层 3、 钝化层 5; 栅极线 2断开 位置的至少一端通过过孔 8与测试衬垫 9连接； 在栅极线 2与基板 1之间， 设置第一引线 6，栅极线 2断开位置的两端通过第一引线 6连接。 例如， 图 6 所示第一引线 6设置于对应栅极线 2断开位置处， 能够连接栅极线 2断开位 置的两端。 由于是通过与栅极线 2直接接触的第一引线 6使栅极线 2的断开 位置的两端连接， 因此连接处具有较小的电阻。 当然除了对应栅极线 2断开 位置处之外， 也可以在全部栅极线 2的下方设置第一引线 6。
参见图 7， 示出了栅极线 2断开位置处两端连接在一起的截面示意图， 各附图标记的含义与图 5和图 6相同， 图 7清晰的示出了栅极线 2断开位置 的两端， 以及通过第一引线 6连接该两端。
参见图 8示出了该阵列基板在引线衬垫（Lead PAD )区域数据线结构俯 视示意图， 为了示图清晰， 图 8仅示出阵列基板多层结构的数据线 4、 过孔 10和测试衬垫 11， 该数据线 4在阵列基板的切割处 13处断开。
图 9示出了在图 8所示 A-A位置的截面示意图， 包括基板 1， 以及基板 1之上的栅极绝缘层 3、 栅极绝缘层 3之上的数据线 4， 数据线 4之上的钝化 层 5; 数据线 4断开位置的至少一端通过过孔 10与测试衬垫 11连接； 在数 据线 4与栅极绝缘层 3之间， 设置第二引线 7， 数据线 4断开位置的两端通 过第二引线 7连接。 例如， 图 9所示第二引线 7设置于对应数据线 4断开位 置处， 能够连接数据线 4断开位置。 由于是通过与数据线 4直接接触的第二 引线 7使数据线 4的断开位置的两端连接， 因此连接处具有较小的电阻。 当 然除了对应数据线 4断开位置处之外， 也可以在全部数据线 4的下方设置第 二引线 7。 参见图 10， 数据线 4断开位置处两端连接在一起的截面示意图， 各附图标记的含义与图 8和图 9相同， 数据线 4断开位置处两端通过第二引 线 7连接在一起。
需要说明的是， 对于同一阵列基板而言， 可以仅具有如图 6所示的栅极 线 2在断开位置处由第一 ITO引线 6连接的结构，也可以仅具有如图 9所示 的数据线 4在断开位置处由第二引线 7连接的结构， 也可以同时具有如图 6 所示的栅极线 2在断开位置处由第一 ITO引线 6连接的结构， 和如图 9所示 的数据线 4在断开位置处由第二引线 7连接的结构。
上述实施例中， 栅极线 2可以为铝、 铬、 钨、 钽、 钼和铝镍中之一或任 意组合构成的单层或复合层结构。 数据线 4可以为铝、 铬、 钨、 钽、 钼和铝 镍中之一或任意组合构成的单层或复合层结构。 栅极绝缘层 3的材料可以为 氮化硅、 二氧化硅或氧化铝。 钝化层 5的材料可以为氮化硅、 二氧化硅或氧 化铝。 第一引线 6的材料可以为导电氧化物， 例如， 氧化铟锡、 氧化铟辞或 氧化铝辞。 第二引线 7的材料可以为导电氧化物， 例如， 氧化铟锡、 氧化铟 辞或氧化铝辞。
当然， 本领域技术人员应该了解， 阵列基板还包括与栅极线 2同层设置 的栅电极、 与数据线同层设置的源电极和漏电极、 以及钝化层之上的像素电 极等等， 为了便于本发明实施例阵列基板的描述， 在此不再详细说明。
本发明实施例有益效果如下：在栅极线或 /和数据线的相邻层设置惰性材 料形成的连接引线， 栅极线或 /和数据线断开位置的两端通过该连接引线连 接， 避免上述阵列基板切割后的金属容易被腐蚀的问题。
本发明实施例提供一种阵列基板的制备方法， 包括：
在基板上形成第一导电薄膜， 通过构图工艺形成多条第一引线和多个公 共电极。
形成第一金属薄膜， 通过构图工艺形成栅电极和多条栅极线， 所述栅极 线在所述基板的切割区域断开， 并通过所述第一引线电连接。
形成栅极绝缘层；
形成第二导电薄膜， 通过构图工艺形成多条第二引线；
形成第二金属薄膜， 通过构图工艺形成源电极、 漏电极和多条数据线， 所述数据线在所述基板的切割区域断开， 并通过所述第二引线电连接； 形成有源层薄膜， 通过构图工艺形成有源层；
形成钝化层薄膜， 通过构图工艺形成钝化层。
本发明实施例有益效果如下：在栅极线或 /和数据线的相邻层设置惰性材 料形成的连接引线， 栅极线或 /和数据线断开位置的两端通过该连接引线连 接， 避免上述阵列基板切割后的金属容易被腐蚀的问题。
本发明实施例提供一种阵列基板的制备方法， 包括：
形成第二导电薄膜， 通过构图工艺形成多条第二引线和多个像素电极； 形成第二金属薄膜， 通过构图工艺形成源电极、 漏电极和多条数据线， 所述数据线在所述基板的切割区域断开， 并通过所述第二引线电连接；
形成有源层薄膜， 通过构图工艺形成有源层；
形成栅极绝缘层薄膜， 通过构图工艺形成栅极绝缘层；
形成第一导电薄膜， 通过构图工艺形成多条第一引线和多个公共电极； 形成第一金属薄膜， 通过构图工艺形成栅电极和多条栅极线， 所述栅极 线在所述基板的切割区域断开， 并通过所述第一引线电连接；
形成钝化层薄膜， 通过构图工艺形成钝化层。
本发明实施例中的构图工艺通常包括： 光刻胶涂敷、 曝光、 显影、 刻蚀、 光刻胶剥离等工艺。以通过构图工艺形成栅电极和多条栅极线为例进行说明， 在第一金属薄膜上涂覆光刻胶（正性）形成覆盖第一金属薄膜的光刻胶层； 利用掩模板对光刻胶层进行曝光； 显影后， 曝光区域的光刻胶被去除而暴露 出第一金属薄膜， 未曝光区域的光刻胶保留； 刻蚀第一金属薄膜， 曝光区域 的第一金属薄膜被刻蚀掉， 未曝光区域的第一金属薄膜由于光刻胶保护未被 刻蚀； 剥离剩余的光刻胶， 形成包括栅电极和多条栅极线的图形。
本发明实施例有益效果如下：在栅极线或 /和数据线的相邻层设置惰性材 料形成的连接引线， 栅极线或 /和数据线断开位置的两端通过该连接引线连 接， 避免上述阵列基板切割后的金属容易被腐蚀的问题。
本发明实施例中的阵列基板可以作为 TFT-LCD的阵列基板， 也可以应 用在有机发光二极管 （OLED ) 、 电子纸等显示装置中， 也可以应用在 X射 线探测器等电子装置。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。
本申请要求于 2013年 12月 18日递交的中国专利申请第 201310701251.8 号的优先权， 在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims

权利要求书
1、 一种阵列基板， 包括：
基板；
金属层形成的多条信号线， 所述信号线在所述基板的切割区域断开； 多条连接引线， 所述连接引线设置于所述信号线的相邻层， 所述连接引 线与所述信号线的断开处的位置对应， 且与所述信号线直接接触；
其中， 所述信号线断开位置的两端通过所述连接引线电连接。
2、 如权利要求 1所述的阵列基板， 其中， 所述信号线包括栅极线， 所述 连接引线包括第一引线；
其中， 所述第一引线形成于所述基板之上， 所述栅极线位于所述第一引 线的上层。
3、 如权利要求 2所述的阵列基板， 其中， 所述信号线还包括数据线， 所 述连接引线还包括第二引线；
所述阵列基板结构还包括栅极绝缘层， 所述第二引线形成于所述栅极绝 缘层之上， 所述数据线位于所述第二引线的上层。
4、 如权利要求 1所述的阵列基板， 其中， 所述信号线包括栅极线， 所述 连接引线包括第一引线；
所述阵列基板结构还包括栅极绝缘层， 所述第一引线形成于所述栅极绝 缘层之上， 所述栅极线位于所述第一引线的上层。
5、 如权利要求 4所述的阵列基板， 其中， 所述信号线还包括数据线， 所 述连接引线还包括第二引线；
其中， 所述第二引线形成于所述基板之上， 所述数据线位于所述第二引 线的上层， 所述栅极绝缘层形成于所述数据线之上。
6、 如权利要求 2或 4所述的阵列基板， 其中， 还包括多个公共电极， 所 述第一引线和所述公共电极同层设置。
7、如权利要求 1所述的阵列基板， 其中， 所述连接引线的材料为导电氧 化物。
8、如权利要求 7所述的阵列基板， 其中， 所述连接引线的材料为氧化铟 锡、 氧化铟辞或氧化铝辞。
9、 一种阵列基板的制备方法， 包括：
在基板上形成第一导电薄膜， 通过构图工艺形成多条第一引线和多个公 共电极；
形成第一金属薄膜， 通过构图工艺形成栅电极和多条栅极线， 所述栅极 线在所述基板的切割区域断开， 并通过所述第一引线电连接。
10、 如权利要求 9所述的制备方法， 还包括：
形成栅极绝缘层；
形成第二导电薄膜， 通过构图工艺形成多条第二引线；
形成第二金属薄膜， 通过构图工艺形成源电极、 漏电极和多条数据线， 所述数据线在所述基板的切割区域断开， 并通过所述第二引线电连接； 形成有源层薄膜， 通过构图工艺形成有源层；
形成钝化层薄膜， 通过构图工艺形成钝化层。
11、 根据权利要求 10所述的制备方法， 其中，
所述第一引线和所述第二引线至少之一的材料为导电氧化物。
12、 一种阵列基板的制备方法， 包括：
形成第二导电薄膜， 通过构图工艺形成多条第二引线和多个像素电极； 形成第二金属薄膜， 通过构图工艺形成源电极、 漏电极和多条数据线， 所述数据线在所述基板的切割区域断开， 并通过所述第二引线电连接。
13、 如权利要求 12所述的制备方法， 还包括：
形成有源层薄膜， 通过构图工艺形成有源层；
形成栅极绝缘层薄膜， 通过构图工艺形成栅极绝缘层；
形成第一导电薄膜， 通过构图工艺形成多条第一引线和多个公共电极； 形成第一金属薄膜， 通过构图工艺形成栅电极和多条栅极线， 所述栅极 线在所述基板的切割区域断开， 并通过所述第一引线电连接；
形成钝化层薄膜， 通过构图工艺形成钝化层。
14、 根据权利要求 13所述的制备方法， 其中，
所述第一引线和所述第二引线至少之一的材料为导电氧化物。
PCT/CN2014/078543 2013-12-18 2014-05-27 阵列基板及其制备方法 Ceased WO2015090004A1 (zh)

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