WO2018137441A1 - 阵列基板及其制备方法、显示面板 - Google Patents

阵列基板及其制备方法、显示面板 Download PDF

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Publication number
WO2018137441A1
WO2018137441A1 PCT/CN2017/116952 CN2017116952W WO2018137441A1 WO 2018137441 A1 WO2018137441 A1 WO 2018137441A1 CN 2017116952 W CN2017116952 W CN 2017116952W WO 2018137441 A1 WO2018137441 A1 WO 2018137441A1
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Prior art keywords
electrode layer
layer
contact pad
reflective pixel
source
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PCT/CN2017/116952
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English (en)
French (fr)
Inventor
苏磊
张正东
周刚
杨小飞
代科
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/063,885 priority Critical patent/US11171160B2/en
Publication of WO2018137441A1 publication Critical patent/WO2018137441A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80518—Reflective anodes, e.g. ITO combined with thick metallic layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • At least one embodiment of the present disclosure is directed to an array substrate, a method of fabricating the same, and a display panel.
  • the display panel prepared by the total reflection array substrate may not require a backlight during the display process, and the light incident incident in the external environment may be reflected for image display by preparing, for example, a metal reflective pixel electrode layer on the surface of the array substrate, thereby realizing the display panel. Lightweight, low weight and low power consumption.
  • At least one embodiment of the present disclosure provides a method for fabricating an array substrate, comprising: providing a substrate including a display region and a lead region located at a periphery of the display region; forming a contact pad in the lead region Forming a source/drain electrode layer on the base substrate in the display region; depositing a connection electrode layer film on the substrate substrate and patterning the same in the lead region Forming a connection electrode on the substrate, leaving a first photoresist layer covering the connection electrode for performing a patterning process; depositing a reflective pixel electrode layer film on the substrate substrate and patterning the same to Forming a reflective pixel electrode layer in the display region and removing the reflective pixel electrode layer film in the lead region to expose the first photoresist layer; removing the reflective pixel electrode layer for the reflective pixel
  • the electrode layer film is patterned with a second photoresist layer and the first photoresist layer in the lead region; wherein the reflective pixel electrode layer is electrically connected to the source/drain electrode layer, the connection
  • the preparation method provided by at least one embodiment of the present disclosure may further include: forming a passivation layer on the source/drain electrode layer on the base substrate, and then patterning the passivation layer to be in the Forming a first via located in the display region in the passivation layer, and forming the a second via hole in the lead region; wherein the source drain electrode layer and the reflective pixel electrode layer are electrically connected through the first via hole, and the connection electrode and the contact pad pass through the second via hole Electrical connection.
  • the preparation method provided by at least one embodiment of the present disclosure may further include: forming a signal line in the lead region when forming a source/drain electrode layer on the gate electrode layer in the display region; A third via hole is formed in the passivation layer, and the connection electrode is electrically connected to the signal line through the third via hole.
  • the signal line is formed to be electrically connected to the contact pad through the connection electrode.
  • the signal line is formed as at least one of a gate line, a data line, a common electrode line, a power line, a ground line, a frame start scan line, and a reset line.
  • the preparation method provided by at least one embodiment of the present disclosure may further include: forming a gate insulating layer over the contact pad, the source/drain electrode layer being formed on the gate insulating layer; in the passivation Forming the second via hole, further forming a fourth via hole exposing the contact pad in the gate insulating layer, the connection electrode passing through the second via hole and the fourth via hole and the The contact pads are electrically connected.
  • the preparation method provided by at least one embodiment of the present disclosure may further include: forming an active layer on the gate insulating layer, and then forming the source/drain electrode layer on the active layer.
  • the preparation method provided by at least one embodiment of the present disclosure may further include: forming a gate electrode layer on the base substrate in the display region, and forming the gate electrode layer and the contact pad by one patterning process.
  • At least one embodiment of the present disclosure provides an array substrate, including: a substrate substrate including a display region and a lead region located at a periphery of the display region; a source/drain electrode layer on the substrate substrate of the display region; a pixel electrode layer located in the display region and located above the source/drain electrode layer; a contact pad located in the lead region; a connection electrode located in the lead region, the connection electrode being located above the contact pad
  • the reflective pixel electrode layer is electrically connected to the source/drain electrode layer
  • the connection electrode is at least partially electrically connected to the contact pad
  • the reflective pixel electrode layer and the connection electrode are formed of different materials.
  • the material of the connection electrode may include a transparent conductive material.
  • a gate electrode layer is further disposed on the substrate of the display region.
  • the array substrate provided by at least one embodiment of the present disclosure may further include a passivation layer disposed on the base substrate, wherein a portion of the passivation layer located in the display region is located on the reflective pixel electrode layer and Between the source and drain electrode layers, a portion of the passivation layer located in the lead region is located between the connection electrode and the contact pad.
  • a first via hole may be disposed in the passivation layer in the display region, and the source/drain electrode layer and the reflective pixel electrode layer pass through a first via electrical connection, a second via is disposed in the passivation layer in the lead region, the connection electrode is formed on the passivation layer, and through the second via The contact pads are electrically connected.
  • the array substrate provided by at least one embodiment of the present disclosure may further include a signal line disposed between the passivation layer and the substrate substrate in the lead region, wherein the lead in the lead region A third via hole is disposed in the passivation layer, and the connection electrode is electrically connected to the signal line through the third via hole.
  • the source/drain electrode layer and the signal line may be disposed in the same layer.
  • the array substrate provided by at least one embodiment of the present disclosure may further include a gate insulating layer disposed on the substrate substrate, wherein the gate insulating layer in the display region is disposed on the gate electrode layer and Between the source and drain electrode layers, the gate insulating layer in the lead region is disposed between the contact pad and the signal line.
  • a fourth via hole is disposed in the gate insulating layer in the lead region, the fourth via hole exposing the contact pad and The second via is in communication, and the connection electrode is electrically connected to the contact pad through the second via and the fourth via.
  • a gate electrode layer is further disposed on the substrate substrate of the display region, and the gate electrode layer is disposed in the same layer as the contact pad.
  • At least one embodiment of the present disclosure provides a display panel that can include any of the array substrates described above.
  • 1a is a schematic cross-sectional structural view of an array substrate display area according to an embodiment of the present disclosure
  • FIG. 1b is a schematic cross-sectional structural view of a lead substrate of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a flowchart of a method for preparing an array substrate according to an embodiment of the present disclosure
  • 3a, 4a, 5a, 6a, 7a, 8a, 9a, 10a, and 11a are schematic cross-sectional structural views of a display region in the method for fabricating the array substrate shown in Fig. 2;
  • 3b, 4b, 5b, 6b, 7b, 8b, 9b, 10b, and 11b are cross-sectional structural views of the lead region in the method of fabricating the array substrate shown in Fig. 2.
  • a preparation process of a total reflection substrate requires six mask processes to sequentially prepare a gate electrode, an active layer, a source/drain electrode layer, a via hole, an ITO layer, and a metal reflective pixel electrode layer.
  • the etching solution penetrates the ITO layer during the etching of the metal layer in the peripheral region and, for example, other components at the via holes in the peripheral region (for example) The signal line in the peripheral area) causes corrosion.
  • the method of preparing a total reflection display substrate Too many steps and high preparation costs.
  • At least one embodiment of the present disclosure provides an array substrate, a method of fabricating the same, and a display panel.
  • the array substrate includes: a substrate substrate including a display region and a lead region located at a periphery of the display region; a source/drain electrode layer and a reflective pixel electrode layer sequentially disposed on the substrate substrate of the display region; and a substrate sequentially disposed on the lead region a contact pad and a connection electrode on the substrate; the reflective pixel electrode layer is electrically connected to the source/drain electrode layer, the connection electrode is at least partially electrically connected to the contact pad, and the reflective pixel electrode layer and the connection electrode are formed of different materials.
  • the reflective pixel electrode layer can combine the function of the pixel electrode and the reflection electrode, and the connection electrode can lead the contact pads located in different layers or connect the contact pads and the signal lines located in different layers for signal transmission.
  • connection electrode may be a conductive connection line.
  • the electrically conductive connection lines may form a bridge between, for example, elements located in different layers, such as signal lines and contact pads.
  • a gate electrode layer is further disposed on a substrate of the display region.
  • the gate electrode layer and the contact pad may be separately disposed; in other embodiments, the gate electrode layer and the contact pad may be configured in the same layer (refer to the following implementation of the present disclosure. The corresponding content in the example).
  • the arrangement of the above two is not related to the technical solution of the embodiment of the present disclosure. Therefore, in order to facilitate the explanation of the technical solutions of the present disclosure, in the following embodiments of the present disclosure, the description is made by taking the gate electrode layer and the contact pad as the same layer.
  • An embodiment of the present disclosure provides an array substrate.
  • FIG. 1 is a schematic cross-sectional view of a display area of an array substrate according to an embodiment of the present disclosure
  • FIG. 1b is a cross section of a lead substrate of an array substrate according to an embodiment of the present disclosure
  • the display region portion of the array substrate includes a base substrate 100, a source/drain electrode layer 131, and a reflective pixel electrode layer 180.
  • the reflective pixel electrode layer 180 is electrically connected to the source/drain electrode layer 131, and the reflective pixel electrode layer 180 functions as a pixel electrode in the display region, and also has a reflection function.
  • the reflective pixel electrode layer 180 can reflect the incident light in the environment, thereby emitting the reflected light from the corresponding pixel region of the reflective pixel electrode layer 180 to realize image display.
  • a device such as a display panel including the array substrate may not need to additionally provide, for example, a light source device or the like that provides a backlight.
  • the lead portion portion of the array substrate includes a base substrate 100, a contact pad 112, a signal line 132, and a connection electrode 160, and the connection electrode 160 is electrically connected to a signal line 132 (for example, a data line).
  • the connection electrode 160 can connect the contact pads 112 and the signal lines 132 at different layers, for example, the connection electrodes 160 can also be electrically connected to the driver.
  • the array substrate may further include a gate electrode layer 111 on the base substrate 100 in the display region.
  • the gate electrode layer 111 and the source/drain electrode layer 131 belong to a thin film transistor as a switching element or a driving element in a sub-pixel unit in the display region, the gate electrode layer 111 corresponds to the gate of the thin film transistor, and the source/drain electrode layer 131 corresponds to Source or drain.
  • the gate is electrically connected or integrally formed, for example, with a gate line; and one of the source and the drain of the thin film transistor that is not electrically connected to the reflective pixel electrode layer 180 may be electrically connected to the data line or the like.
  • connection electrode 160 may connect the contact pads 112 and the signal lines 132 at different layers, however, embodiments of the present disclosure are not limited thereto, and the contact pads 112 are not electrically connected to the signal lines 132 located at different layers in the lead regions.
  • the connection is electrically connected to other signal lines (for example, gate lines) located in the same layer, and then electrically connected to, for example, a driver through the connection electrode 160.
  • the signal line is formed as at least one of a gate line, a data line, a common electrode line, a power line, a ground line, a frame start scan line, and a reset line.
  • the type of the signal line is not limited as long as the signal line needs to be electrically connected to the contact pad through, for example, a connection electrode.
  • connection electrode 160 and the reflective pixel electrode layer 180 may be formed of different materials, for example, the connection electrode 160 may be formed before the pixel electrode layer 180 is reflected, that is, First, the connection electrode 160 is formed by, for example, a patterning process, and the reflective pixel electrode layer 180 is formed by a patterning process.
  • the connection electrode 160 is formed, for example, by a patterning process, the photoresist layer (for example, the first photoresist layer, not shown) overlying the connection electrode 160 is not removed.
  • the reflective pixel electrode layer 180 is formed by a patterning process, the position where the connection electrode 160 communicates with the contact pad 112 or the signal line 132 is covered with the first photoresist layer.
  • the etching solution for etching the reflective pixel electrode layer 180 does not pass through the connection electrode 160 to the contact pad 112 in the lead region due to the presence of the first photoresist layer.
  • signal line 132 causes corrosion to protect circuit connections in the lead regions.
  • the material for preparing the reflective pixel electrode layer 180 is not limited.
  • the material for preparing the reflective pixel electrode layer 180 may include aluminum, silver, gold, chromium, or molybdenum.
  • a reflective conductive material may be included in the array substrate provided by at least one embodiment of the present disclosure.
  • the material for preparing the reflective pixel electrode layer 180 may also include a conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium oxide, and dope the metal material having a reflective function in the above material.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • gallium oxide dope the metal material having a reflective function in the above material.
  • the pair of connection electrodes 160 The preparation material is not limited, and for example, the preparation material of the connection electrode 160 may include a transparent conductive material.
  • the material for connecting the electrodes may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide, gallium zinc oxide, zinc oxide, indium oxide, aluminum zinc oxide or carbon nanotubes.
  • the embodiment of the present disclosure does not limit the arrangement relationship between the gate electrode layer 111 and the contact pad 112.
  • the gate electrode layer 111 and the contact pad 112 may be, for example, in the same layer structure. For example, both may be patterned by depositing a gate electrode layer film on the substrate substrate 100. The process is simultaneously formed, which simplifies the preparation process of the array substrate and reduces the cost.
  • the gate electrode layer 111 and the contact pads 112 may also be separately formed by different fabrication processes, that is, the contact pads 112 may be separately provided.
  • the specific arrangement of the contact pads 112 is not limited.
  • the specific structure of the contact pads, the connection electrodes, and the signal lines in the array substrate is not limited, as long as the contact pads are connected to other structures such as signal lines by using the connection electrodes.
  • the portion of the signal line that is located in the display area and the portion that is located in the lead area may be located in different layers. For example, as shown in FIG. 1a and FIG. 1b, taking the signal line 132 as a gate line as an example, a portion of the gate line in the display area (not shown) may be integrally formed with the gate electrode layer 111, in the display area.
  • the gate line is connected to the gate electrode layer 111, and the other end may be provided as a contact pad 112, and the connection electrode 160 may connect the gate lines of different layers.
  • the contact pad can be connected to the signal line in the display area to realize the transfer of the signal line in the display area and the signal line 132 in the lead area, and the contact pad can be used as a part of the signal line in the display area. It can also be used as a separate structure to connect with signal lines in the display area, and embodiments of the present disclosure are not limited herein.
  • the specific positions of the contact pads and the connection electrodes in the array substrate are not limited.
  • the position at which the contact pad and the connection electrode are disposed can be selected according to the type of the signal line.
  • the signal line is a gate line, and the contact pad can be used as a part of the signal line in the display area, that is, the contact pad can be disposed in the same layer as the gate electrode.
  • the signal line is a data line, and the contact pad can be used as a part of the signal line in the display area, that is, the contact pad can be disposed in the same layer as the source/drain motor layer.
  • the preparation material of the gate electrode layer or the contact pad may include copper (Cu), copper-molybdenum alloy (Cu/Mo), Cu-Ti alloy, Cu/Mo/Ti, Cu/Mo/W, Cu/Mo/Nb, etc.; gate electrode layer or The material of the contact pad may also be a chromium-based metal, for example, chromium-molybdenum alloy (Cr/Mo), chrome-titanium alloy (Cr/Ti), chromium-molybdenum-titanium alloy (Cr/Mo/Ti), etc.; gate electrode layer or contact pad The material can also be aluminum or aluminum alloy.
  • the embodiment of the present disclosure does not limit the arrangement relationship between the signal line 132 and the source/drain electrode layer 131.
  • the source/drain electrode layer 131 and the signal line 132 may be configured in the same layer structure, for example, by depositing a source/drain electrode layer film on the substrate substrate. The formation process is simultaneously formed by the patterning process, which simplifies the preparation process of the array substrate and reduces the cost.
  • the signal line 132 and the source/drain electrode layer 131 may also be separately formed by different fabrication processes.
  • the embodiment of the present disclosure does not limit the specific structure of the signal line 132 and the source/drain electrode layer 131.
  • the material of the source/drain electrode layer 131 or the signal line 132 may be a metal material, and may be a single layer or a multilayer structure.
  • the source/drain electrode layer 131 or the signal line 132 may be a single-layer aluminum structure or a single-layer molybdenum structure. Or a three-layer structure in which a layer of aluminum is sandwiched between two layers of molybdenum.
  • a passivation layer 140 disposed on the base substrate 100 is further included.
  • the passivation layer 140 in the display region is partially located between the reflective pixel electrode layer 180 and the source/drain electrode layer 131.
  • the passivation layer 140 in the lead region is partially located between the connection electrode 160 and the contact pad 112.
  • the embodiment of the present disclosure does not limit the specific structure and preparation material of the passivation layer 140.
  • the passivation layer 140 may be a single layer or a multilayer composite structure including at least one of silicon nitride (SiNx) and silicon oxide (SiOx).
  • a first via 151, a source/drain electrode layer 161 and a reflective pixel electrode layer 180 are disposed in the passivation layer 140 in the display region. Electrically connected through the first via 151.
  • the reflective pixel electrode layer 180 can be connected to the drain of the source/drain electrode layer 161, for example, such that the reflective pixel electrode layer 180 can serve as a pixel electrode; the reflective pixel electrode layer 180 can also reflect light, so that, for example, light in the environment can be reflected. Used for reflective display.
  • a second via hole 152 is disposed in the passivation layer 140 in the lead region, and the connection electrode 160 and the contact pad 112 pass through the second pass.
  • the holes 152 are electrically connected.
  • the embodiment of the present disclosure does not limit the specific positional relationship between the connection electrode 160 and the contact pad 112, as long as the connection electrode 160 and the contact pad 112 can pass through the second
  • the via 152 is connected.
  • the connection electrode 160 and the contact pad 112 may be disposed to at least partially overlap, and a second via hole 152 is provided in a region of the passivation layer 140 corresponding to the overlap portion.
  • a third via 153 may be disposed in the passivation layer 140 in the lead region, and the connection electrode 160 and the signal line 132 pass through the third.
  • the vias 153 are electrically connected.
  • a gate insulating layer 120 is further disposed on the substrate substrate 100, and the gate insulating layer 120 located in the display region is partially disposed on Between the source/drain electrode layer 131 and the gate electrode layer 111, a portion of the gate insulating layer 120 located in the lead region is disposed between the signal line 132 and the contact pad 112.
  • the material for preparing the gate insulating layer 120 may include, for example, one or a combination of silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), and other suitable materials.
  • An active layer (not shown) of the thin film transistor is formed, for example, on the gate insulating layer 120, and the source/drain electrode layer 131 is electrically connected to the active layer.
  • the active layer may be amorphous silicon, polysilicon, or an oxide semiconductor. Layers, etc.
  • a fourth via 154 is disposed in the gate insulating layer 120 in the lead region, and the fourth via 154 is exposed.
  • the pad 112 is in communication with the second via 152.
  • the connection electrode 160 can be electrically connected to the contact pad 112 through the second via 152 and the fourth via 154.
  • At least one embodiment of the present disclosure provides a method for fabricating an array substrate, the method comprising: providing a substrate including a display region and a lead region located at a periphery of the display region; forming a contact pad in the lead region; Forming a source/drain electrode layer on the base substrate; depositing a connection electrode layer film on the base substrate and patterning the same to form a connection electrode on the base substrate in the lead region, remaining on the connection electrode a first photoresist layer for performing a patterning process; depositing a reflective pixel electrode layer film on the base substrate and patterning the same to form a reflective pixel electrode layer in the display region and removing the reflective pixel electrode layer film in the lead region Exposing the first photoresist layer; removing the second photoresist layer on the reflective pixel electrode layer for patterning the reflective pixel electrode layer film and the first photoresist layer in the lead region; wherein the reflective pixel electrode The layer is electrically connected to the source/drain electrode layer, and the connection electrode is at
  • the method of fabricating the array substrate in at least one embodiment of the present disclosure may include the following process:
  • S1 providing a base substrate including a display area and a lead area located at a periphery of the display area.
  • the gate electrode layer may be formed on the base substrate of the display region.
  • the gate electrode layer may also be formed simultaneously with the contact pad, that is, the gate electrode layer and the contact pad are disposed in the same layer and may be prepared from the same material layer;
  • the source/drain electrode layer may be formed simultaneously with the signal line, that is, the source/drain electrode layer.
  • the signal lines can be arranged in the same layer and can be prepared from the same material layer.
  • connection electrode layer film depositing a connection electrode layer film on the base substrate and patterning the same to form a connection electrode on the base substrate in the lead region, and retaining the first photoresist covering the connection electrode for patterning process
  • the layer does not require a removal or stripping process of the first photoresist layer, ie, the process steps of removing the first photoresist layer are omitted.
  • S4 depositing a reflective pixel electrode layer film on the base substrate and patterning the same to form a reflective pixel electrode layer in the display region and removing the reflective pixel electrode layer film in the lead region to expose the first photoresist layer.
  • the reflective pixel electrode layer is electrically coupled to the source and drain electrode layers, and the connection electrode is at least partially electrically coupled to the contact pads.
  • the preparation method provided by at least one embodiment of the present disclosure may further include: forming a gate electrode layer on the substrate in the display region.
  • the gate electrode layer and the contact pad may be formed in the same layer. This process has been explained in the flow shown in FIG. 2 of the above embodiment, and will not be described herein.
  • the preparation method provided by at least one embodiment of the present disclosure may further include: forming a passivation layer on the source/drain electrode layer on the base substrate, and then patterning the passivation layer to be in the passivation layer in the display region. Forming a first via hole, wherein the source/drain electrode layer and the reflective pixel electrode layer are electrically connected through the first via hole, and a second via hole is formed in the passivation layer in the lead region, and the connection electrode and the contact pad pass The second via is electrically connected.
  • the preparation method provided by at least one embodiment of the present disclosure may further include: forming a signal line in the lead region when forming a source/drain electrode layer on the gate electrode layer in the display region; forming a passivation layer in the lead region The third via hole, the connection electrode is electrically connected to the signal line through the third via hole.
  • the preparation method provided by at least one embodiment of the present disclosure may further include: forming a third via hole in the passivation layer, and the connection electrode is electrically connected to the contact pad through the third via hole.
  • the preparation method provided by at least one embodiment of the present disclosure may further include: forming a gate insulating layer over the gate electrode layer and the contact pad, the source/drain electrode layer being formed on the gate insulating layer; forming a second pass in the passivation At the time of the hole, a fourth via hole exposing the contact pad may also be formed in the gate insulating layer.
  • the second via and the fourth via are in communication with each other.
  • the preparation method provided by at least one embodiment of the present disclosure may further include: forming an active layer on the gate insulating layer, and then forming a source/drain electrode layer on the active layer.
  • one example of at least one embodiment of the present disclosure provides a method of fabricating an array substrate, such as FIG. 3a, FIG. 4a, FIG. 5a, FIG. 6a, FIG. 7a, FIG. 8a, FIG. 9a, FIG. 10a, FIG. 3b, FIG. 4b, FIG. 5b, FIG. 6b, FIG. 7b, FIG. 8b, FIG. 9b, FIG. 10b, and FIG. 11b are schematic cross-sectional structural views of the array substrate manufacturing method of the present example shown in FIG.
  • FIG. 3a, 4a, 5a, 6a, 7a, 8a, 9a, 10a, and 11a are schematic cross-sectional structures of the display region in the method for fabricating the array substrate shown in Fig. 2;
  • Fig. 3b, Fig. 4b 5b, 6b, 7b, 8b, 9b, 10b, and 11b are schematic cross-sectional views of the lead region in the method for fabricating the array substrate shown in Fig. 2.
  • the method of preparing the array substrate shown in this example is a process after the completion of the preparation of the passivation layer.
  • a gate electrode layer 111, a gate insulating layer 120, a source/drain electrode layer 131, and a passivation layer 140 are sequentially formed on the base substrate 100 of the display region; as shown in FIG. 3b, the lining in the lead region is shown in FIG. 3b.
  • a contact pad 112, a gate insulating layer 120, a signal line 132, and a passivation layer 140 are sequentially formed on the base substrate 100.
  • the base substrate 100 may be a glass substrate.
  • the contact pad 112 may be disposed, for example, in the same layer as the gate electrode layer 111 and formed by the same patterning process; the signal line 132 may be disposed, for example, in the same layer as the source/drain electrode layer 131 and formed by the same patterning process.
  • an exemplary preparation method for forming a partial structure in a thin film transistor can be packaged And forming a gate electrode film on the substrate, and performing a patterning process on the gate electrode film to form a gate electrode layer in the display region, and forming a contact pad in the lead region.
  • a gate insulating layer is deposited on the base substrate on which the gate electrode layer is formed.
  • An active layer film is deposited on the gate insulating layer and patterned to form an active layer.
  • the material for preparing the active layer may include metal oxides such as amorphous silicon, polycrystalline silicon, indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), gallium zinc oxide (GZO), and the like.
  • a source/drain electrode layer film is deposited on the base substrate on which the active layer is formed and patterned to form a source/drain electrode layer in the display region, and a signal line is formed in the lead region.
  • a passivation layer is deposited on the substrate substrate on which the active drain electrode layer and the signal line are formed.
  • a first via 151 is formed by a patterning process in the passivation layer 140 on the base substrate 100 in the display region; as shown in FIG. 4b, blunt on the substrate substrate 100 in the lead region
  • the second via 152 and the third via 153 are formed in the layer 140 by a patterning process.
  • the first via 151, the second via 152, and the third via 153 may be formed by the same patterning process.
  • the gate insulating layer 120 in the lead region forms a fourth via 154 at the second via 152, and the fourth via 154 is in communication with the second via 152.
  • the second via 152 and the fourth via 154 expose the contact pads 112.
  • the second via 152 and the fourth via 154 may be simultaneously formed by, for example, one patterning process; for example, the second via 152 and the fourth via 154 may also be formed separately, that is, after the gate insulating layer 120 is formed.
  • a fourth via 154 is formed therein to expose the contact pad 112, and then a passivation layer 153 is formed to form a second via 152 in communication with the fourth via 154 therein.
  • the patterning process may be, for example, a photolithographic patterning process, which may include, for example, coating a photoresist layer on a structural layer that needs to be patterned, and exposing the photoresist layer using a mask.
  • the exposed photoresist layer is developed to obtain a photoresist pattern, the structural layer is etched using a photoresist pattern, and then the photoresist pattern is optionally removed.
  • connection electrode layer film 161 is deposited on the base substrate 100 in the display region; as shown in FIG. 5b, a connection electrode layer film 161 is deposited on the substrate substrate 100 in the lead region.
  • the connection electrode layer film 161 is electrically connected to the signal line through the third via 153; the connection electrode layer film 161 is electrically connected to the contact pad 112 through the second via 152.
  • the connection electrode layer film 161 may be electrically connected to the contact pad 112 through the second via hole 152 and the fourth via hole 154.
  • a first photoresist layer 170 is coated on the connection electrode layer film 161 of the display region; and a first photoresist layer 170 is coated on the connection electrode layer film 161 of the lead region.
  • connection electrode layer film 161 in the display region and the lead region is subjected to a patterning process to form the connection electrode 160 in the lead region.
  • a process of exposure, development, etching, etc. is performed to remove the connection electrode layer film 161 and the first photoresist layer 170 in the display region, and the first photoresist layer 170 remains on the connection electrode 160 in the lead region, that is, no need
  • a cleaning process is performed on the first photoresist layer 170 after the patterning process.
  • a reflective pixel electrode layer film 181 is deposited on the base substrate 100 in the display region and the lead region.
  • the reflective pixel electrode layer film 181 in the display region and the source/drain electrode layer 131 are electrically connected through the first via hole 151.
  • a second photoresist layer 190 is deposited on the reflective pixel electrode layer film 181 in the display region and the lead region.
  • the reflective pixel electrode layer film 181 in the display region and the lead region is subjected to a patterning process to form the reflective pixel electrode layer 180 in the display region, and the reflective pixel electrode layer film in the lead region.
  • 181 is, for example, etched away.
  • the etching solution does not enter the second via hole and The third via hole does not cause corrosion to the contact pad or signal line.
  • the second photoresist layer in the display region and the first photoresist layer in the lead region are removed.
  • the first photoresist layer and the second photoresist layer are collectively removed by a cleaning process, which simplifies the preparation process while protecting the signal lines of the array substrate.
  • the process steps in the display region and the lead region may be performed simultaneously, for example, in depositing a film connecting the electrode layers, on the substrate substrate of the display region and the lead region.
  • the connection electrode layer film is deposited.
  • the patterning process of the connection electrode layer film is performed by simultaneously patterning the connection electrode layer film in the display area and the lead area.
  • At least one embodiment of the present disclosure provides a display panel including the array substrate of any of the above embodiments.
  • the display panel is a liquid crystal display panel including an array substrate and a counter substrate which are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color filter substrate.
  • the reflective pixel electrode layer of each pixel unit of the array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the type of liquid crystal panel may include TN type (Twisted Nematic) The display panel, the VA type (Vertical Alignment) display panel, or the IPS type (In-Plane Switching) display panel, etc., the embodiments of the present disclosure are not limited herein.
  • TN type Transmission Nematic
  • VA type Vertical Alignment
  • IPS type In-Plane Switching
  • Still another example of the display panel is an electronic paper display panel in which an electronic ink layer is formed on the array substrate, and a reflective pixel electrode layer of each pixel unit is moved as a charged microparticle for applying the driving electronic ink to perform a display operation. Voltage.
  • Embodiments of the present disclosure provide an array substrate, a method of fabricating the same, a display panel, and have at least one of the following beneficial effects:
  • At least one embodiment of the present disclosure provides an array substrate, a method for fabricating the same, and a display panel.
  • the reflective pixel electrode layer in the display region of the array substrate has both a function of a pixel electrode and a reflection, and the reflectance of the light is improved.
  • connection electrode in the lead region is still covered with the first photoresist layer, thereby preventing use for preparing the reflective pixel. Corrosion of the electrode layer passes through the connection electrode to cause corrosion to the contact pad or signal line.
  • the first photoresist layer for preparing the connection electrode in the lead region is removed together with the second photoresist layer for preparing the reflective pixel electrode layer in the display region, This can eliminate the need to separately clean the first photoresist layer cleaning process, reducing costs.

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Abstract

一种阵列基板及其制备方法、显示面板，该制备方法包括：提供包括显示区和位于显示区外围的引线区的衬底基板(100)，在引线区中形成连接电极(160)的过程中保留用于对其进行构图工艺的第一光刻胶层(170)，然后在衬底基板(100)上沉积反射像素电极层薄膜(181)并对其进行构图工艺以在显示区中形成反射像素电极层(180)且在引线区内去除反射像素电极层薄膜(181)以暴露出第一光刻胶层(170)，然后去除反射像素电极层(180)上用于对反射像素电极层薄膜(181)进行构图的第二光刻胶层(190)和引线区内的第一光刻胶层(170)。上述制备方法可以简化阵列基板的制备工艺并且避免构件被腐蚀。

Description

阵列基板及其制备方法、显示面板
本申请要求于2017年1月25日递交的中国专利申请第201710061083.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开至少一个实施例涉及一种阵列基板及其制备方法、显示面板。
背景技术
由全反射阵列基板制备的显示面板在显示过程可不需要背光，通过在阵列基板的表面上制备例如金属反射像素电极层可以将外界环境中入射的光线进行反射以进行图像显示，从而可以实现显示面板的轻薄化、低重量和低功耗等。
发明内容
本公开至少一实施例提供一种阵列基板的制备方法，包括：提供衬底基板，所述衬底基板包括显示区和位于所述显示区外围的引线区；在所述引线区内形成接触垫；在所述显示区内于所述衬底基板上形成源漏电极层；在所述衬底基板上沉积连接电极层薄膜并对其进行构图工艺以在所述引线区中的所述衬底基板上形成连接电极，保留覆盖于所述连接电极上的用以进行构图工艺的第一光刻胶层；在所述衬底基板沉积反射像素电极层薄膜并对其进行构图工艺以在所述显示区中形成反射像素电极层且在所述引线区内去除所述反射像素电极层薄膜以暴露出所述第一光刻胶层；去除所述反射像素电极层上用于对所述反射像素电极层薄膜进行构图的第二光刻胶层和所述引线区内的所述第一光刻胶层；其中，所述反射像素电极层与所述源漏电极层电连接，所述连接电极至少部分与所述接触垫电连接。
例如，本公开至少一实施例提供的制备方法还可以包括：在所述衬底基板上的所述源漏电极层上形成钝化层，然后对所述钝化层进行构图，以在在所述钝化层中形成位于所述显示区内的第一过孔，以及形成位于所述 引线区中的第二过孔；其中，所述源漏电极层与所述反射像素电极层通过所述第一过孔电连接，所述连接电极与所述接触垫通过所述第二过孔电连接。
例如，本公开至少一实施例提供的制备方法还可以包括：在所述显示区内于所述栅电极层上形成源漏电极层时，在所述引线区内形成信号线；在所述引线区内于所述钝化层中形成第三过孔，所述连接电极通过所述第三过孔与所述信号线电连接。
例如，在本公开至少一实施例提供的制备方法中，所述信号线形成为通过所述连接电极与所述接触垫电连接。
例如，在本公开至少一实施例提供的制备方法中，所述信号线形成为栅线、数据线、公共电极线、电源线、接地线、帧开始扫描线和复位线中的至少一种。
例如，本公开至少一实施例提供的制备方法还可以包括：在所述接触垫之上形成栅绝缘层，所述源漏电极层形成在所述栅绝缘层之上；在所述钝化中形成所述第二过孔时，还在所述栅绝缘层中形成暴露所述接触垫的第四过孔，所述连接电极通过所述第二过孔和所述第四过孔与所述接触垫电连接。
例如，本公开至少一实施例提供的制备方法还可以包括：在所述栅绝缘层上形成有源层，然后在所述有源层上形成所述源漏电极层。
例如，本公开至少一实施例提供的制备方法还可以包括：在所述显示区中的衬底基板上形成栅电极层，并且通过一次构图工艺形成所述栅电极层和所述接触垫。
本公开的至少一实施例提供一种阵列基板，包括：衬底基板，包括显示区和位于所述显示区外围的引线区；源漏电极层，位于所述显示区的衬底基板上；反射像素电极层，位于所述显示区，且位于所述源漏电极层之上；接触垫，位于所述引线区；连接电极，位于所述引线区，所述连接电极位于所述接触垫之上；其中，所述反射像素电极层与所述源漏电极层电连接，所述连接电极至少部分与所述接触垫电连接，且所述反射像素电极层和所述连接电极由不同的材料形成。
例如，在本公开至少一实施例提供的阵列基板中，所述连接电极的材料可以包括透明导电材料。
例如，在本公开至少一实施例提供的阵列基板中，所述显示区的衬底基板上还设置有栅电极层。
例如，本公开至少一实施例提供的阵列基板还可以包括设置于所述衬底基板上的钝化层，其中，所述钝化层位于所述显示区的部分位于所述反射像素电极层和所述源漏电极层之间，所述钝化层位于所述引线区的部分位于所述连接电极和所述接触垫之间。
例如，在本公开至少一实施例提供的阵列基板中，所述显示区中的所述钝化层中可以设置有第一过孔，所述源漏电极层与所述反射像素电极层通过所述第一过孔电连接，所述引线区中的所述钝化层中设置有第二过孔，所述连接电极形成于所述钝化层之上，并且通过所述第二过孔与所述接触垫电连接。
例如，本公开至少一实施例提供的阵列基板还可以包括在所述引线区中设置于所述钝化层和所述衬底基板之间的信号线，其中，所述引线区中的所述钝化层中设置有第三过孔，所述连接电极通过所述第三过孔与所述信号线电连接。
例如，在本公开至少一实施例提供的阵列基板中，所述源漏电极层与所述信号线可以为同层设置。
例如，本公开至少一实施例提供的阵列基板还可以包括设置于所述衬底基板上的栅绝缘层，其中，所述显示区中的所述栅绝缘层设置于所述栅电极层和所述源漏电极层之间，所述引线区中的所述栅绝缘层设置于所述接触垫和所述信号线之间。
例如，在本公开至少一实施例提供的阵列基板中，在所述引线区中的所述栅绝缘层中设置有第四过孔，所述第四过孔暴露所述接触垫并与所述第二过孔连通，所述连接电极通过所述第二过孔和所述第四过孔与所述接触垫电连接。
例如，在本公开至少一实施例提供的阵列基板中，所述显示区的衬底基板上还设置有栅电极层，并且所述栅电极层与所述接触垫同层设置。
本公开至少一实施例提供一种显示面板可以包括上述任一的阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1a为本公开一实施例提供的阵列基板显示区的横截面结构示意图；
图1b为本公开一实施例提供的阵列基板引线区的横截面结构示意图；
图2为本公开一实施例提供的阵列基板制备方法流程图；
[根据细则91更正 23.01.2018]　
图3a、图4a、图5a、图6a、图7a、图8a、图9a、图10a、图11a为图2所示的阵列基板制备方法中显示区的横截面结构示意图；以及
[根据细则91更正 23.01.2018]　
图3b、图4b、图5b、图6b、图7b、图8b、图9b、图10b、图11b为图2所示的阵列基板制备方法中引线区的横截面结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
一种全反射基板的制备过程需要六次掩膜工艺，依次制备栅电极、有源层、源漏电极层、过孔、ITO层和金属反射像素电极层。在形成金属反射像素电极层的过程中，因ITO的致密性不够，在外围区域中刻蚀金属层的过程中腐蚀液会透过ITO层并对例如外围区域中过孔处的其他部件(例如外围区域中的信号线)造成腐蚀。并且，该制备全反射显示基板的方法 的步骤过多，制备成本高。
本公开的至少一个实施例提供了一种阵列基板及其制备方法、显示面板。该阵列基板包括：衬底基板，包括显示区和位于显示区外围的引线区；依次设置于显示区的衬底基板上的源漏电极层和反射像素电极层；依次设置于引线区的衬底基板上的接触垫和连接电极；反射像素电极层与源漏电极层电连接，连接电极至少部分与接触垫电连接，且反射像素电极层和连接电极由不同的材料形成。反射像素电极层可以兼具像素电极和反射的功能，连接电极可将位于不同层的接触垫引出，或将位于不同层的接触垫和信号线连通以进行信号的传输。
需要说明的是，连接电极可以为导电连接线。该导电连接线可以在例如位于不同层的元件例如信号线和接触垫之间形成桥接。
例如，在本公开的实施例中，显示区的衬底基板上还设置有栅电极层。需要说明的是，在一些实施例中，栅电极层和接触垫可以为单独设置；在另一些实施例中，栅电极层和接触垫可以为同层设置的结构(具体参考下述本公开实施例中的相应内容)。上述两者的设置方式与本公开实施例的技术方案无关，所以为便于解释本公开技术方案，在本公开下述实施例中，以栅电极层和接触垫为同层设置为例进行说明。本公开的一实施例提供了一种阵列基板，图1a为本公开一实施例提供的阵列基板显示区的横截面结构示意图；图1b为本公开一实施例提供的阵列基板引线区的横截面结构示意图。
例如，如图1a所示，阵列基板的显示区部分包括衬底基板100、源漏电极层131和反射像素电极层180。反射像素电极层180与源漏电极层131电连接，反射像素电极层180在显示区中充当像素电极作用同时，还具有反射功能。反射像素电极层180可以将环境中入射的光线进行反射，从而将反射光线从反射像素电极层180对应的像素区域中射出，以实现图像显示。如此，包括本阵列基板的例如显示面板等器件可不需要再额外设置例如提供背光的光源设备等。
例如，如图1b所示，阵列基板的引线区部分包括衬底基板100、接触垫112、信号线132和连接电极160，连接电极160与信号线132(例如数据线)电连接。连接电极160可以将位于不同层的接触垫112和信号线132连通，例如连接电极160还可以与驱动器电连接。
例如，在本公开至少一个实施例中，阵列基板还可以包括位于显示区中的衬底基板100上的栅电极层111。栅电极层111和源漏电极层131属于显示区中的子像素单元中作为开关元件或驱动元件的薄膜晶体管，栅电极层111对应于薄膜晶体管的栅极，而源漏电极层131则对应于源极或漏极。该栅极例如与栅线电连接或一体形成；并且，该薄膜晶体管的源极和漏极中不与反射像素电极层180电连接的一个，可以与数据线等电连接。
在图1b中，连接电极160可以将位于不同层的接触垫112和信号线132连通，然而本公开的实施例不限于此，在引线区中接触垫112不是与位于不同层的信号线132电连接，而是与位于同一层的其他信号线(例如栅线)电连接，再通过连接电极160与例如驱动器电连接。
例如，在本公开至少一个实施例中，信号线形成为栅线、数据线、公共电极线、电源线、接地线、帧开始扫描线和复位线中的至少一种。本公开至少一个实施例中对信号线的类型不做限制，只要该信号线需要通过例如连接电极与接触垫电连接即可。
例如，在本公开至少一个实施例中，如图1a和1b所示，连接电极160和反射像素电极层180可以由不同的材料形成，例如连接电极160可以在反射像素电极层180之前形成，即先例如通过构图工艺形成连接电极160再通过构图工艺形成反射像素电极层180。在例如通过构图工艺形成连接电极160时，不清除连接电极160上覆盖的光刻胶层(例如为第一光刻胶层，图中未示出)。之后通过构图工艺形成反射像素电极层180时，连接电极160与接触垫112或信号线132连通处的位置上覆盖有第一光刻胶层。在反射像素电极层180形成过程中，由于第一光刻胶层的存在，在引线区中，用于对反射像素电极层180进行刻蚀的腐蚀液不会透过连接电极160对接触垫112或信号线132造成腐蚀，从而对引线区中的电路连通进行保护。
例如，在本公开至少一个实施例提供的阵列基板中，对反射像素电极层180的制备材料不做限制，例如反射像素电极层180的制备材料可以包括铝、银、金、铬或钼等具有反射作用的导电材料。例如，反射像素电极层180的制备材料也可以包括氧化铟锡(ITO)、氧化铟锌(IZO)或者氧化铟镓等导电材料，并且在上述材料中掺杂具有反射功能的金属材料颗粒。
例如，在本公开至少一个实施例提供的阵列基板中，对连接电极160 的制备材料不做限制，例如连接电极160的制备材料可以包括透明导电材料。例如连接电极的材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓、氧化镓锌、氧化锌、氧化铟、氧化铝锌或碳纳米管等。
本公开的实施例对栅电极层111和接触垫112之间的设置关系不做限制。例如，在本公开至少一个实施例所提供的阵列基板中，栅电极层111与接触垫112例如可以为同层结构，例如两者可以通过在衬底基板100上沉积栅电极层薄膜后通过构图工艺同时形成，如此可以简化阵列基板的制备工艺流程，降低成本。例如，在本公开至少一个实施例中，栅电极层111和接触垫112也可以通过不同的制备工艺分别形成，即接触垫112可以单独设置。在本公开至少一个实施例中，对接触垫112的具体设置方式不做限制。
需要说明的是，在本公开至少一个实施例中，对接触垫、连接电极和信号线在阵列基板中的具体化结构不做限制，只要接触垫利用连接电极与其它结构例如信号线连接即可。例如，在本公开至少一个实施例中，信号线的位于显示区的部分和位于引线区的部分可以位于不同层。示例性的，如图1a和图1b所示，以信号线132为栅线为例，栅线在显示区的部分(图中未示出)可以与栅电极层111一体形成，显示区中的栅线的一端与栅电极层111连接，另一端可以设置为接触垫112，连接电极160可以将不同层的栅线连接。如此，可以简化阵列基板的制备工艺，降低成本。需要说明的是，接触垫可以与显示区中的信号线连接，以实现显示区中的信号线与引线区中的信号线132的转接，接触垫可以作为显示区中的信号线的一部分，也可以作为独立结构以与显示区中的信号线连接，本公开的实施例在此不做限制。
需要说明的是，在本公开至少一个实施例中，对接触垫和连接电极在阵列基板中的具体设置位置不做限制。例如，接触垫和连接电极的设置位置可以根据信号线的类型进行选择。例如，信号线为栅线，接触垫可以作为显示区中的信号线的一部分，即接触垫可以与栅电极同层设置。再例如，信号线为数据线，接触垫可以作为显示区中的信号线的一部分，即接触垫可以与源漏电机层同层设置。
本公开的实施例对栅电极层111和接触垫112的制备材料不做限制。例如，栅电极层或接触垫的制备材料可以包括铜(Cu)、铜钼合金(Cu/Mo)、 铜钛合金(Cu/Ti)、铜钼钛合金(Cu/Mo/Ti)、铜钼钨合金(Cu/Mo/W)、铜钼铌合金(Cu/Mo/Nb)等；栅电极层或接触垫的材料也可以为铬基金属，例如，铬钼合金(Cr/Mo)、铬钛合金(Cr/Ti)、铬钼钛合金(Cr/Mo/Ti)等；栅电极层或接触垫的材料还可以为铝或铝合金等。
本公开的实施例对信号线132和源漏电极层131之间的设置关系不做限制。例如，在本公开至少一个实施例所提供的阵列基板中，源漏电极层131与信号线132例如可以配置为同层结构，例如两者可以通过在衬底基板上沉积源漏电极层薄膜后通过构图工艺同时形成，如此可以简化阵列基板的制备工艺流程，降低成本。例如，在本公开至少一个实施例中，信号线132和源漏电极层131也可以通过不同的制备工艺分别形成。
本公开的实施例对信号线132和源漏电极层131具体化结构不做限制。例如，源漏电极层131或信号线132的制备材料可以为金属材料，可以为单层或多层结构，例如，源漏电极层131或信号线132可以为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构等。
例如，在本公开至少一个实施例提供的阵列基板中，如图1a和图1b所示，还包括设置在衬底基板100上的钝化层140。例如如图1a所示，在显示区中的钝化层140部分位于反射像素电极层180和源漏电极层131之间。例如如图1b所示，在引线区中的钝化层140部分位于连接电极160和接触垫112之间。本公开的实施例对钝化层140的具体化结构及制备材料不做限制。例如，钝化层140可以为包括氮化硅(SiNx)和氧化硅(SiOx)等中的至少一种材料构成的单层或多层复合结构。
例如，在本公开至少一个实施例所提供的阵列基板中，如图1a所示，显示区中的钝化层140中设置有第一过孔151，源漏电极层161与反射像素电极层180通过第一过孔151电连接。反射像素电极层180例如可以连通至源漏电极层161的漏极，如此反射像素电极层180可以作为像素电极；反射像素电极层180还可以反射光线，从而可以对例如环境中的光线进行反射，用于进行反射显示。
例如，在本公开至少一个实施例所提供的阵列基板中，如图1b所示，引线区中的钝化层140中设置有第二过孔152，连接电极160与接触垫112通过第二过孔152电连接。本公开的实施例对连接电极160与接触垫112的具体位置关系不做限制，只要连接电极160与接触垫112可以通过第二 过孔152连通即可。例如，在垂直于衬底基板100所在面的方向上，连接电极160与接触垫112可以设置为至少部分重叠，在钝化层140的与该重叠部分相对应的区域设置第二过孔152。
例如，在本公开至少一个实施例所提供的阵列基板中，如图1b所示，引线区中的钝化层140中可以设置有第三过孔153，连接电极160与信号线132通过第三过孔153电连接。连接电极160与信号线132之间的位置关系可以参考前述实施例中对连接电极160与接触垫112之间位置关系的相关说明，本公开的实施例在此不做赘述。
例如，在本公开至少一个实施例所提供的阵列基板中，如图1a和图1b所示，衬底基板100上还设置有栅绝缘层120，位于显示区中的栅绝缘层120部分设置于源漏电极层131和栅电极层111之间，位于引线区中的栅绝缘层120部分设置于信号线132和接触垫112之间。栅绝缘层120的制备材料例如可以包括氮化硅(SiNx)、氧化硅(SiOx)、氧化铝(Al2O3)、氮化铝(AlN)和其他适合的材料等的一种或组合。薄膜晶体管的有源层(未示出)例如形成在栅绝缘层120上，源漏电极层131与该有源层电连接，例如，该有源层可以为非晶硅、多晶硅、氧化物半导体层等。
例如，在本公开至少一个实施例所提供的阵列基板中，如图1a和图1b所示，在引线区中的栅绝缘层120中设置有第四过孔154，第四过孔154暴露接触垫112并与第二过孔152连通。如此，连接电极160可以通过第二过孔152和第四过孔154与接触垫112电连接。
本公开至少一实施例提供了一种阵列基板的制备方法，该方法包括:提供衬底基板，衬底基板包括显示区和位于显示区外围的引线区；在引线区内形成接触垫；在显示区内于衬底基板上形成源漏电极层；在衬底基板上沉积连接电极层薄膜并对其进行构图工艺以在引线区中的衬底基板上形成连接电极，保留覆盖于连接电极上的用以进行构图工艺的第一光刻胶层；在衬底基板沉积反射像素电极层薄膜并对其进行构图工艺以在显示区中形成反射像素电极层且在引线区内去除反射像素电极层薄膜以暴露出第一光刻胶层；去除反射像素电极层上用于对反射像素电极层薄膜进行构图的第二光刻胶层和引线区内的第一光刻胶层；其中，反射像素电极层与源漏电极层电连接，连接电极至少部分与接触垫电连接。例如，反射像素电极层上用于对反射像素电极层薄膜进行构图的第二光刻胶层和引线区内的第一 光刻胶层可以同时去除。
图2为本公开一实施例提供的阵列基板制备方法流程图。例如如图2所示，本公开至少一个实施例中的阵列基板的制备方法可以包括下述过程：
S1：提供衬底基板，该衬底基板包括显示区和位于显示区外围的引线区。
S2：在引线区的衬底基板上形成接触垫，在显示区的衬底基板上形成源漏电极层。
例如，在本实施例提供的制备方法中，还可以在显示区的衬底基板上形成栅电极层。例如，栅电极层还可以与接触垫同时形成，即栅电极层和接触垫同层设置并且可以由同一个材料层制备得到；源漏电极层例如可以与信号线同时形成，即源漏电极层和信号线可以同层设置并且可以由同一个材料层制备得到。
S3：在衬底基板上沉积连接电极层薄膜并对其进行构图工艺以在引线区中的衬底基板上形成连接电极，保留覆盖于连接电极上的用以进行构图工艺的第一光刻胶层；不需要对第一光刻胶层进行去除或剥离工艺，即省去去除第一光刻胶层的工艺步骤。
S4：在衬底基板沉积反射像素电极层薄膜并对其进行构图工艺以在显示区中形成反射像素电极层且在引线区内去除反射像素电极层薄膜以暴露出第一光刻胶层。
S5：例如同时去除反射像素电极层上用于对反射像素电极层薄膜进行构图的第二光刻胶层和引线区内的第一光刻胶层。
在例如图2所示的实施例中，反射像素电极层与源漏电极层电连接，连接电极至少部分与接触垫电连接。
例如，本公开至少一个实施例提供的制备方法还可以包括：在显示区中的衬底基板上形成栅电极层。例如，在本公开实施例提供的制备方法中，栅电极层和所述接触垫可以为同层形成。该过程在上述实施例的如图2所示的流程中已做解释，在此不做赘述。
例如，本公开至少一个实施例提供的制备方法还可以包括：在衬底基板上在源漏电极层上形成钝化层，然后对钝化层进行构图，以在显示区内于钝化层中形成第一过孔，其中，源漏电极层与反射像素电极层通过第一过孔电连接，在引线区中在钝化层中形成第二过孔，连接电极与接触垫通 过第二过孔电连接。
例如，本公开至少一个实施例提供的制备方法还可以包括：在显示区内于栅电极层上形成源漏电极层时，在引线区内形成信号线；在引线区内于钝化层中形成第三过孔，连接电极通过第三过孔与信号线电连接。
例如，本公开至少一个实施例提供的制备方法还可以包括：在钝化层中形成第三过孔，连接电极通过第三过孔与接触垫电连接。
例如，本公开至少一个实施例提供的制备方法还可以包括：在栅电极层和接触垫之上形成栅绝缘层，源漏电极层形成在栅绝缘层之上；在钝化中形成第二过孔时，还可以在栅绝缘层中形成暴露接触垫的第四过孔。第二过孔与第四过孔彼此相通。
例如，本公开至少一个实施例提供的制备方法还可以包括：在栅绝缘层上形成有源层，然后在有源层上形成源漏电极层。
需要说明的是，由本公开上述实施例中的制备方法得到的阵列基板的具体化结构可以参考前述实施例(关于阵列基板的实施例)中的相关内容，本公开的实施例在此不做赘述。
[根据细则91更正 23.01.2018]　
为便于理解，本公开至少一个实施例中的一个示例提供了阵列基板的制备方法，图3a、图4a、图5a、图6a、图7a、图8a、图9a、图10a、图11a和图3b、图4b、图5b、图6b、图7b、图8b、图9b、图10b、图11b为图2所示本示例中阵列基板制备方法中的横截面结构示意图。图3a、图4a、图5a、图6a、图7a、图8a、图9a、图10a、图11a为图2所示的阵列基板制备方法中显示区的横截面结构示意图；图3b、图4b、图5b、图6b、图7b、图8b、图9b、图10b、图11b为图2所示的阵列基板制备方法中引线区的横截面结构示意图。
需要说明的是，在本公开实施例提供的下述示例中，除本公开描述的结构及其制备工艺和过程之外，其他的结构及其制备工艺和过程可以采用当前的阵列基板制备工艺流程。为便于解释本公开的技术方案，本示例中所示阵列基板的制备方法为完成制备钝化层之后的过程。
如图3a所示，在显示区的衬底基板100上依次形成栅电极层111、栅绝缘层120、源漏电极层131和钝化层140；如图3b所示，在引线区中的衬底基板100上依次形成接触垫112、栅绝缘层120、信号线132和钝化层140。例如，该衬底基板100可以为玻璃基板。接触垫112例如可以与栅电极层111同层设置且由同一构图工艺形成；信号线132例如可以与源漏电极层131同层设置且由同一构图工艺形成。
例如，形成薄膜晶体管中的部分结构的一种示范性的制备方法可以包 括：在衬底上沉积一层栅电极薄膜，通过对该栅电极薄膜进行构图工艺处理以在显示区中形成栅电极层，在引线区中形成接触垫。在形成有栅电极层的衬底基板上沉积一层栅绝缘层。在栅绝缘层上沉积一层有源层薄膜，并对其进行构图工艺处理以形成有源层。例如，制备该有源层的材料可以包括非晶硅、多晶硅、氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化镓锌(GZO)等金属氧化物等。
在形成有有源层的衬底基板上沉积一层源漏电极层薄膜并对其进行构图工艺以在显示区形成源漏电极层，在引线区形成信号线。在形成有源漏电极层和信号线的衬底基板上沉积一层钝化层。
如图4a所示，在显示区中的衬底基板100上的钝化层140中通过构图工艺形成第一过孔151；如图4b所示，在引线区中的衬底基板100上的钝化层140中通过构图工艺形成第二过孔152和第三过孔153。第一过孔151、第二过孔152和第三过孔153可以通过同一构图工艺形成。
例如，引线区中的栅绝缘层120在第二过孔152处形成第四过孔154，第四过孔154与第二过孔152相连通。第二过孔152和第四过孔154暴露接触垫112。需要说明的是，第二过孔152和第四过孔154例如可以通过一次构图工艺同时形成；例如第二过孔152和第四过孔154也可以分别形成，即形成栅绝缘层120后在其中形成第四过孔154以暴露接触垫112，然后形成钝化层153后在其中形成与第四过孔154连通的第二过孔152。
在本公开至少一个实施例中，构图工艺例如可以为光刻构图工艺，其例如可以包括：在需要被构图的结构层上涂覆光刻胶层，使用掩膜板对光刻胶层进行曝光，对曝光的光刻胶层进行显影以得到光刻胶图案，使用光刻胶图案对结构层进行蚀刻，然后可选地去除光刻胶图案。
如图5a所示，在显示区中的衬底基板100上沉积一层连接电极层薄膜161；如图5b所示，在引线区中的衬底基板100上沉积一层连接电极层薄膜161。连接电极层薄膜161通过第三过孔153与信号线电连接；连接电极层薄膜161通过第二过孔152与接触垫112电连接。例如，在形成有第四过孔154的情况下，连接电极层薄膜161可以通过第二过孔152和第四过孔154与接触垫112电连接。
如图6a所示，在显示区的连接电极层薄膜161上涂覆一层第一光刻胶层170；在引线区的连接电极层薄膜161上涂覆一层第一光刻胶层170。
如图7a和图7b所示，对显示区和引线区中的连接电极层薄膜161进行构图工艺处理以在引线区中形成连接电极160。例如进行曝光、显影、刻蚀等工艺，去除显示区中的连接电极层薄膜161和第一光刻胶层170，引线区中的连接电极160上保留第一光刻胶层170，即不需对构图工艺之后的第一光刻胶层170进行清除工艺。
如图8a和图8b所示，在显示区和引线区中的衬底基板100上沉积一层反射像素电极层薄膜181。显示区中的反射像素电极层薄膜181与源漏电极层131通过第一过孔151电连接。
如图9a和图9b所示，在显示区和引线区中的反射像素电极层薄膜181上沉积一层第二光刻胶层190。
如图10a和图10b所示，对显示区和引线区中的反射像素电极层薄膜181进行构图工艺处理以在显示区中形成反射像素电极层180，而在引线区中的反射像素电极层薄膜181被例如刻蚀掉。
在对反射像素电极层薄膜181进行例如刻蚀的过程中，因为第二过孔和第三过孔处的连接电极上覆盖有第一光刻胶层，腐蚀液不会进入第二过孔和第三过孔中，从而不会对接触垫或信号线造成腐蚀。
如图11a和图11b所示，清除掉显示区中的第二光刻胶层和引线区中的第一光刻胶层。第一光刻胶层和第二光刻胶层通过一道清洗工艺共同清除，在保护阵列基板信号线连通的同时简化了其制备工艺。
需要说明的是，在本公开至少一个实施例中，显示区和引线区中的工艺步骤可以同时进行，例如，沉积连接电极层薄膜的过程中，可以在显示区和引线区的衬底基板上同时沉积连接电极层薄膜，同样的，对连接电极层薄膜进行构图工艺，则为在显示区和引线区中同时对连接电极层薄膜进行构图工艺处理。
本公开至少一实施例提供一种显示面板，包括上述实施例中任一的阵列基板。
该显示面板的一个示例为液晶显示面板，包括阵列基板和对置基板，二者彼此对置以形成液晶盒，在液晶盒中填充有液晶材料。该对置基板例如为彩膜基板。阵列基板的每个像素单元的反射像素电极层用于施加电场对液晶材料的旋转的程度进行控制从而进行显示操作。
例如，液晶面板的类型可以包括TN型(Twisted Nematic，扭曲向列 型)显示面板、VA型(Vertical Alignment)显示面板或者IPS型(In-Plane Switching，平面转换)显示面板等，本公开的实施例在此不做限制。
该显示面板的再一个示例为电子纸显示面板，其中，阵列基板上形成有电子墨水层，每个像素单元的反射像素电极层作为用于施加驱动电子墨水中的带电微颗粒移动以进行显示操作的电压。
本公开的实施例提供一种阵列基板及其制备方法、显示面板，并且具有以下至少一项有益效果：
(1)本公开至少一个实施例提供一种阵列基板及其制备方法、显示面板，阵列基板的显示区中的反射像素电极层兼具像素电极和反射的功能，提高了光的反射率。
(2)在本公开至少一个实施例中，在显示区中形成反射像素电极层的过程中，在引线区中的连接电极上仍覆盖有第一光刻胶层，从而防止用于制备反射像素电极层的腐蚀液透过连接电极对接触垫或信号线造成的腐蚀。
(3)在本公开至少一个实施例中，用于制备引线区中连接电极的第一光刻胶层与用于制备显示区中的反射像素电极层的第二光刻胶层一同清除，由此可以省去一道单独清除第一光刻胶层的清洗工艺，降低成本。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (18)

  1. 一种阵列基板的制备方法，包括：
    提供衬底基板，所述衬底基板包括显示区和位于所述显示区外围的引线区；
    在所述引线区内形成接触垫；
    在所述显示区内于所述衬底基板上形成源漏电极层；
    在所述衬底基板上沉积连接电极层薄膜并对其进行构图工艺以在所述引线区中的所述衬底基板上形成连接电极，保留覆盖于所述连接电极上的用以进行构图工艺的第一光刻胶层；
    在所述衬底基板沉积反射像素电极层薄膜并对其进行构图工艺以在所述显示区中形成反射像素电极层且在所述引线区内去除所述反射像素电极层薄膜以暴露出所述第一光刻胶层；
    去除所述反射像素电极层上用于对所述反射像素电极层薄膜进行构图的第二光刻胶层和所述引线区内的所述第一光刻胶层；
    其中，所述反射像素电极层与所述源漏电极层电连接，所述连接电极至少部分与所述接触垫电连接。
  2. 根据权利要求1所述的制备方法，还包括：
    在所述衬底基板上的所述源漏电极层上形成钝化层，然后对所述钝化层进行构图，以在所述钝化层中形成位于在所述显示区内的第一过孔，以及形成位于所述引线区中的第二过孔；
    其中，所述源漏电极层与所述反射像素电极层通过所述第一过孔电连接，所述连接电极与所述接触垫通过所述第二过孔电连接。
  3. 根据权利要求2所述的制备方法，还包括：
    在所述显示区内于所述栅电极层上形成源漏电极层时，在所述引线区内形成信号线；
    在所述引线区内于所述钝化层中形成第三过孔，所述连接电极通过所述第三过孔与所述信号线电连接。
  4. 根据权利要求3所述的制备方法，其中，所述信号线形成为通过所述连接电极与所述接触垫电连接。
  5. 根据权利要求3或4所述的制备方法，其中，
    所述信号线形成为栅线、数据线、公共电极线、电源线、接地线、帧开始扫描线和复位线中的至少一种。
  6. 根据权利要求4或5所述的制备方法，还包括：在所述接触垫之上形成栅绝缘层，所述源漏电极层形成在所述栅绝缘层之上；
    在所述钝化中形成所述第二过孔时，还在所述栅绝缘层中形成暴露所述接触垫的第四过孔，所述连接电极通过所述第二过孔和所述第四过孔与所述接触垫电连接。
  7. 根据权利要求6所述的制备方法，还包括：在所述栅绝缘层上形成有源层，然后在所述有源层上形成所述源漏电极层。
  8. 根据权利要求1-7中任一项所述的制备方法，还包括：在所述显示区中的衬底基板上形成栅电极层，并且通过一次构图工艺形成所述栅电极层和所述接触垫。
  9. 一种阵列基板，包括：
    衬底基板，包括显示区和位于所述显示区外围的引线区；
    源漏电极层，位于所述显示区的衬底基板上；
    反射像素电极层，位于所述显示区，且位于所述源漏电极层之上；
    接触垫，位于所述引线区；
    连接电极，位于所述引线区，所述连接电极位于所述接触垫之上；
    其中，所述反射像素电极层与所述源漏电极层电连接，所述连接电极至少部分与所述接触垫电连接，且所述反射像素电极层和所述连接电极由不同的材料形成。
  10. 根据权利要求9所述的阵列基板，其中，所述连接电极的材料包括透明导电材料。
  11. 根据权利要求9或10所述的阵列基板，还包括设置于所述衬底基板上的钝化层，
    其中，所述钝化层位于所述显示区的部分位于所述反射像素电极层和所述源漏电极层之间，所述钝化层位于所述引线区的部分位于所述连接电极和所述接触垫之间。
  12. 根据权利要求11所述的阵列基板，其中，
    所述显示区中的所述钝化层中设置有第一过孔，所述源漏电极层与所述反射像素电极层通过所述第一过孔电连接，并且
    所述引线区中的所述钝化层中设置有第二过孔，所述连接电极形成于所述钝化层之上，并且通过所述第二过孔与所述接触垫电连接。
  13. 根据权利要求11或12所述的阵列基板，还包括在所述引线区中设置于所述钝化层和所述衬底基板之间的信号线，
    其中，所述引线区中的所述钝化层中设置有第三过孔，所述连接电极通过所述第三过孔与所述信号线电连接。
  14. 根据权利要求13所述的阵列基板，其中，所述源漏电极层与所述信号线同层设置。
  15. 根据权利要求13或14所述的阵列基板，还包括设置于所述衬底基板上的栅绝缘层，
    其中，所述显示区中的所述栅绝缘层设置于所述栅电极层和所述源漏电极层之间，所述引线区中的所述栅绝缘层设置于所述接触垫和所述信号线之间。
  16. 根据权利要求15所述的阵列基板，其中，在所述引线区中的所述栅绝缘层中设置有第四过孔，所述第四过孔暴露所述接触垫并与所述第二过孔连通，所述连接电极通过所述第二过孔和所述第四过孔与所述接触垫电连接。
  17. 根据权利要求9-16中任一项所述的阵列基板，其中，所述显示区的所述衬底基板上还设置有栅电极层，并且所述栅电极层与所述接触垫同层设置。
  18. 一种显示面板，包括权利要求9-17中任一项所述的阵列基板。
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